Multilayer micro-space power panel and manufacturing method thereof

Abstract

The invention discloses a multilayer micro-space power panel and a manufacturing method thereof, and belongs to the technical field of power panels. The multi-layer micro-space power panel comprises a substrate, a dielectric layer, an inner copper layer, a surface copper layer and an inner conduction copper layer. The substrate is provided with a through groove. The dielectric layer comprises a first dielectric layer and a second dielectric layer which are arranged on the two opposite sides of the substrate, and the first dielectric layer is provided with at least one through hole. The inner copper layer is arranged between the first dielectric layer and the second dielectric layer in a stacked mode and fills the through groove. The surface copper layer comprises a first surface copper layer arranged on the surface, deviating from the inner copper layer, of the first dielectric layer and a second surface copper layer arranged on the surface, deviating from the inner copper layer, of the second dielectric layer. The inner conduction copper layer is arranged in the through hole and is electrically connected with the inner copper layer and the first surface copper layer. According to the invention, the ultra-thick copper heat dissipation layer is obtained by utilizing the longitudinal space superposition of the power panel structure to the maximum extent, and the heat dissipation capability of the power panel structure is remarkably improved.

Description

Technical Field

[0001] This application relates to the technical field of power supply boards, and particularly to a multi-layer micro-space power supply board and a manufacturing method thereof. Background Art

[0002] With the advent of the big data era, the market demand for PMIC (Power Management Integrated Circuit) is becoming increasingly widespread. The problem of heat generation caused by high-speed operation has attracted more and more attention. Subject to the requirement of an increasingly smaller space layout, the heat dissipation problem is more prominent. To address the micro-space heat dissipation problem, ultra-thick copper is often used for heat dissipation.

[0003] However, in the process of manufacturing an inner layer buried with ultra-thick copper foil to achieve efficient heat dissipation, when the copper foil thickness reaches or exceeds 0.210 mm, due to the significantly reduced etching efficiency of copper, it becomes extremely difficult to fabricate the pattern of the ultra-thick copper. This not only prolongs the processing time but also increases the uncertainty and cost during the manufacturing process. Moreover, during the lamination process, the inner layer pattern gap of the ultra-thick copper is prone to poor filling. This poor filling will result in the inability to achieve cross-layer conduction between layers, seriously affecting the electrical performance and reliability of the circuit board. Summary of the Invention

[0004] The purpose of this application is to provide a multi-layer micro-space power supply board and a manufacturing method thereof, which are used to solve the problem that it is difficult to manufacture an inner layer of ultra-thick copper foil in the prior art.

[0005] To solve the above technical problems, this application is implemented by adopting the following technical solutions:

[0006] Provide a first copper layer, a substrate, and a second copper layer that are sequentially stacked;

[0007] A first blind via is formed on the substrate and the first copper layer, and the opening of the first blind via is located on the first copper layer;

[0008] A third copper layer is provided to cover the surface of the second copper layer, the inside of the first blind via, and the surface of the first copper layer, so as to form an inner layer copper layer integrated with the second copper layer and the first copper layer;

[0009] Graphically electroplate the inner layer copper layer;

[0010] A first dielectric layer and a second dielectric layer are respectively arranged on the opposite two surfaces of the inner layer copper layer. A fourth copper layer is arranged on the side of the first dielectric layer facing away from the inner layer copper layer, and a fifth copper layer is arranged on the side of the second dielectric layer facing away from the inner layer copper layer;

[0011] A first blind hole is formed on the first dielectric layer and the fourth copper layer, and the opening of the first blind hole is located on the fourth copper layer;

[0012] An inner layer conduction copper layer is disposed in the first blind hole, a sixth copper layer is disposed on a surface of the fourth copper layer facing away from the first dielectric layer, and a seventh copper layer is disposed on a surface of the fifth copper layer facing away from the second dielectric layer;

[0013] Wherein, the sixth copper layer and the fourth copper layer are integrally formed into a first surface layer copper layer, the seventh copper layer and the second copper layer are integrally formed into a second surface layer copper layer, and the first surface layer copper layer is electrically connected to the inner layer copper layer through the inner layer conduction copper layer;

[0014] Pattern the first surface layer copper layer and the second surface layer copper layer.

[0015] Optionally, the step of disposing a third copper layer covering the surface of the second copper layer, the inside of the first blind groove, and the surface of the first copper layer includes:

[0016] Clean the first blind groove;

[0017] Perform electroless copper plating in the first blind groove;

[0018] Electroplate copper to form a third copper layer, and grind the surface of the third copper layer.

[0019] Optionally, the step of pattern electroplating the inner layer copper layer includes:

[0020] Dispose a dry film on the non-electroplated area of the inner layer copper layer;

[0021] Electroplate the inner layer copper layer with copper and tin in sequence;

[0022] Perform film removal, etching, and tin stripping in sequence;

[0023] Dispose a resin isolation layer on the exposed surface of the inner layer copper layer;

[0024] Grind and remove the resin isolation layer on the electroplated side of the inner layer copper layer.

[0025] Optionally, after disposing the fifth copper layer on a surface of the second dielectric layer facing away from the inner layer copper layer, and before disposing the inner layer conduction copper layer in the first blind hole, further includes:

[0026] Form at least one first through hole on the fourth copper layer, the first dielectric layer, the inner layer copper layer, the second dielectric layer, and the fifth copper layer;

[0027] Dispose a first insulating layer in the first through hole;

[0028] Form a second through hole in the first insulating layer.

[0029] Optionally, a through-layer conductive copper layer is provided in the second through-hole; the steps of providing a through-layer conductive copper layer in the second through-hole, providing an inner-layer conductive copper layer in the first blind hole, providing a sixth copper layer on the surface of the fourth copper layer facing away from the first dielectric layer, and providing a seventh copper layer on the surface of the fifth copper layer facing away from the second dielectric layer include: electroplating copper to form a third through-hole on the first surface copper layer, the through-layer conductive copper layer, and the second surface copper layer by electroplating copper.

[0030] Optionally, a second insulating layer is provided in the third through-hole;

[0031] Copper is backfilled on the side of the first surface copper layer facing away from the first dielectric layer and on the side of the second surface copper layer facing away from the second dielectric layer.

[0032] On the other hand, the present application provides a multi-layer micro-space power board, including: a substrate, with a through-groove opened on the substrate;

[0033] A dielectric layer, including a first dielectric layer and a second dielectric layer provided on opposite sides of the substrate, with at least one through-hole provided on the first dielectric layer;

[0034] An inner-layer copper layer, stacked between the first dielectric layer and the second dielectric layer and filling the through-groove;

[0035] A surface copper layer, including a first surface copper layer provided on the surface of the first dielectric layer facing away from the inner-layer copper layer and a second surface copper layer provided on the surface of the second dielectric layer facing away from the inner-layer copper layer;

[0036] An inner-layer conductive copper layer, provided in the through-hole and electrically connected to the inner-layer copper layer and the first surface copper layer.

[0037] In this solution, a through-groove is provided on the substrate, and the through-groove is filled with the inner-layer copper layer, so that an ultra-thick copper heat dissipation layer is formed between the first dielectric layer and the second dielectric layer. This solution maximally utilizes the longitudinal space of the power board structure to stack an ultra-thick copper heat dissipation layer, significantly improving the heat dissipation capacity of the power board structure, helping to reduce the working temperature of the power board, and improving its stability and reliability.

[0038] Optionally, at least one buried hole is formed in the first surface copper layer, the first dielectric layer, the inner-layer copper layer, the second dielectric layer, and the second surface copper layer. Both ends of the buried hole are located in the first surface copper layer and the second surface copper layer respectively. A first insulating layer, a through-layer conductive copper layer, and a second insulating layer are sequentially nested in the buried hole, and the through-layer conductive copper layer is electrically connected to the first surface copper layer and the second surface copper layer.

[0039] In this solution, buried vias are set to form conduction channels in the first surface copper layer, the first dielectric layer, the inner copper layer, the second dielectric layer, and the second surface copper layer. An insulating layer is provided in the buried via to isolate the inner copper layer, and a cross-layer conduction copper layer is provided in the insulating layer to achieve conduction between the first surface copper layer and the second surface copper layer, thus meeting the conduction requirements across the inner copper layer. The design of the cross-layer conduction copper layer makes the power supply board more flexible in layout and routing, meets the design requirements of complex circuits, and can effectively reduce the overall unit graphic size of the power supply board structure.

[0040] Optionally, a resin isolation layer is provided between the first dielectric layer and the second dielectric layer, and the resin isolation layer covers both side surfaces of the inner copper layer. The resin isolation layer improves the electrical isolation performance and structural stability of the power supply board, reducing the risk of failures caused by short circuits, signal interference, or structural looseness.

[0041] Optionally, unit graphic cutting channels are provided on the substrate.

[0042] Beneficial effects

[0043] In this application, a first blind via is formed on the substrate and the first copper layer, and then copper is filled in the first blind via. Subsequently, on this basis, pattern selective electroplating of copper is further used for targeted thickening to obtain an inner copper layer with a super-thick copper feature. The surface flatness of the inner copper layer obtained in this way (the height difference between the inner copper layer and the substrate) can be reduced by 2 / 3 compared with the existing process. This makes it more convenient to fill the resin at the position of the unit graphic cutting channel before laminating the inner copper layer, avoiding the occurrence of bubbles, voids and other defects in the resin filling of the super-thick copper gap before lamination in the prior art. Moreover, using pattern selective electroplating of copper for thickening saves the cost of electroplating copper compared with the whole-board electroplating of super-thick copper.

[0044] In this application, buried vias are set to form conduction channels in the first surface copper layer, the first dielectric layer, the inner copper layer, the second dielectric layer, and the second surface copper layer. An insulating layer is provided in the buried via to isolate the inner copper layer, and a cross-layer conduction copper layer is provided in the insulating layer to achieve conduction between the first surface copper layer and the second surface copper layer, thus meeting the conduction requirements across the inner copper layer. The surface wiring space is saved to the greatest extent, and the inner-layer heat dissipation super-thick copper space is utilized to the greatest extent. The unit graphic size can be reduced by more than 20% under the premise of the same heat dissipation, and finally the overall cost reduction advantage is achieved. Description of the drawings

[0045] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0046] Figure 1 is a schematic diagram of the overall structure of the multi-layer micro-space power board provided by the present application;

[0047] Figure 2 is a schematic diagram of the process flow of the manufacturing method of the multi-layer micro-space power board in Embodiment 1 provided by the present application;

[0048] Figure 3 is a schematic diagram of the process flow of the manufacturing method of the multi-layer micro-space power board in Embodiment 2 provided by the present application;

[0049] Figure 4 is a schematic diagram of the structures of the first copper layer, the substrate, and the second copper layer in the manufacturing method of the multi-layer micro-space power board in Embodiment 1 provided by the present application;

[0050] Figure 5 is a schematic diagram of the structure for forming the first blind via in the manufacturing method of the multi-layer micro-space power board in Embodiment 1 provided by the present application;

[0051] Figure 6 is a schematic diagram of the structure for forming the third copper layer in the manufacturing method of the multi-layer micro-space power board in Embodiment 1 provided by the present application;

[0052] Figure 7 is a schematic diagram of the grinding structure of the third copper layer in the manufacturing method of the multi-layer micro-space power board in Embodiment 1 provided by the present application;

[0053] Figure 8 is a schematic diagram of the structure for setting the dry film in the graphic electroplating in the manufacturing method of the multi-layer micro-space power board in Embodiment 1 provided by the present application;

[0054] Figure 9 is a schematic diagram of the structure for electroplating copper and tin in the graphic electroplating in the manufacturing method of the multi-layer micro-space power board in Embodiment 1 provided by the present application;

[0055] Figure 10 is a schematic diagram of the structure for removing the film, etching, and stripping tin in the graphic electroplating in the manufacturing method of the multi-layer micro-space power board in Embodiment 1 provided by the present application;

[0056] Figure 11 is a schematic diagram of the structure for setting the resin isolation layer in the manufacturing method of the multi-layer micro-space power board in Embodiment 1 provided by the present application;

[0057] Figure 12 It is a schematic structural diagram of grinding and removing the resin isolation layer on the electroplated side of the inner copper layer in the manufacturing method of the multi-layer micro-space power supply board of Embodiment 1 provided by this application;

[0058] Figure 13 It is a schematic structural diagram of setting the first dielectric layer, the second dielectric layer, the fourth copper layer, and the fifth copper layer in the manufacturing method of the multi-layer micro-space power supply board of Embodiment 1 provided by this application;

[0059] Figure 14 It is a schematic structural diagram of forming the first through hole in the manufacturing method of the multi-layer micro-space power supply board of Embodiment 2 provided by this application;

[0060] Figure 15 It is a schematic structural diagram of setting the first insulating layer in the manufacturing method of the multi-layer micro-space power supply board of Embodiment 2 provided by this application;

[0061] Figure 16 It is a schematic structural diagram of forming the second through hole in the manufacturing method of the multi-layer micro-space power supply board of Embodiment 2 provided by this application;

[0062] Figure 17 It is a schematic structural diagram of forming the first blind hole in the manufacturing method of the multi-layer micro-space power supply board of Embodiment 1 provided by this application;

[0063] Figure 18 It is a schematic structural diagram of forming the cross-layer conductive copper layer, the inner-layer conductive copper layer, the sixth copper layer, the seventh copper layer, and the third through hole in the manufacturing method of the multi-layer micro-space power supply board of Embodiment 1 provided by this application;

[0064] Figure 19 It is a schematic structural diagram of setting the second insulating layer in the manufacturing method of the multi-layer micro-space power supply board of Embodiment 2 provided by this application;

[0065] Figure 20 It is a schematic structural diagram of reverse copper plating in the manufacturing method of the multi-layer micro-space power supply board of Embodiment 2 provided by this application;

[0066] Figure 21 It is a schematic structural diagram of forming the outer layer circuit in the manufacturing method of the multi-layer micro-space power supply board of Embodiment 1 provided by this application.

[0067] Explanation of the reference numerals: 100-substrate; 110-through groove; 120-unit graphic cutting road; 210-first dielectric layer; 220-second dielectric layer; 300-inner copper layer; 310-first copper layer; 320-second copper layer; 330-third copper layer; 331-dry film; 332-tin; 410-first surface copper layer; 411-fourth copper layer; 412-sixth copper layer; 420-second surface copper layer; 421-fifth copper layer; 422-seventh copper layer; 500-inner conductive copper layer; 610-first insulating layer; 620-cross-layer conductive copper layer; 630-second insulating layer; 640-first through hole; 650-second through hole; 660-third through hole; 700-resin isolation layer; 800-first blind groove; 900-first blind hole. DETAILED DESCRIPTION

[0068] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present disclosure / application, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present application and its application or use.

[0069] Example 1

[0070] This embodiment introduces a method for manufacturing a multi-layer micro-space power board. Figure 2 The method for manufacturing the multi-layer micro-space power board in this embodiment includes:

[0071] S100: providing a first copper layer 310, a substrate 100 and a second copper layer 320 which are stacked in sequence.

[0072] refer to Figure 4 , providing a first copper layer 310, a substrate 100 and a second copper layer 320 stacked in sequence. The substrate 100 is located between the first copper layer 310 and the second copper layer 320. The thickness of the substrate 100 is ≤ 0.1 mm. In addition, a unit graphic cutting path is provided on the substrate 100. S200: A first blind groove 800 is formed on the substrate 100 and the first copper layer 310, and the opening of the first blind groove 800 is located on the first copper layer 310.

[0073] refer to Figure 5, a first blind via 800 is formed on the substrate 100 and the first copper layer 310, and the opening of the first blind via 800 is located on the first copper layer 310. Specifically, first, a laser window is opened on the first copper layer 310. Then, the substrate is laser grooved along the window opening position of the first copper layer 310, so as to obtain the first blind via 800 with the opening located on the first copper layer 310. It should be noted that the first blind via 800 should be set avoiding the unit pattern cutting track, so that no additional etching process is required to remove the copper on the unit pattern cutting track during subsequent cutting of the unit pattern. By making a groove reservation at the unit pattern cutting track position, the problem of low efficiency caused by directly etching the ultra-thick copper layer is avoided, and the problems of low etching factor and low pattern accuracy in the ultra-thick copper etching process are also avoided.

[0074] S300: Set a third copper layer 330 covering the surface of the second copper layer 320, the inside of the first blind via 800 and the surface of the first copper layer 310, so as to form an inner copper layer 300 integrated with the second copper layer 320 and the first copper layer 310.

[0075] Reference Figure 6 , set a third copper layer 330 covering the surface of the second copper layer 320, the inside of the first blind via 800 and the surface of the first copper layer 310. The third copper layer 330 can be combined with the second copper layer 320 and the first copper layer 310 by electroplating, chemical deposition or other means to form an integrated inner copper layer 300.

[0076] As an optional implementation manner, the step of setting the third copper layer 330 covering the surface of the second copper layer 320, the inside of the first blind via 800 and the surface of the first copper layer 310 includes:

[0077] S301: Clean the first blind via 800;

[0078] Remove the slag in the first blind via 800 to ensure that the inside of the first blind via is clean without impurities.

[0079] S302: Conduct electroless copper plating in the first blind via 800;

[0080] Adopt chemical deposition technology to deposit a thin layer of chemical copper on the inner wall of the first blind via 800. This layer of chemical copper is usually called the "seed layer". Electroless copper plating can provide a uniform conductive substrate for electroplated copper and enhance the bonding force between copper layers.

[0081] S303: Electroplate copper to form the third copper layer 330, and grind the surface of the third copper layer 330.

[0082] Form the third copper layer 330 covering the surface of the second copper layer 320, the inside of the blind via and the surface of the first copper layer 310 by electroplating copper. Reference Figure 7, after electroplating, the surface of the third copper layer 330 is polished to remove burrs, protrusions and uneven parts on the surface, so that the surface of the copper layer reaches the required flatness and smoothness.

[0083] S400: Pattern electroplate the inner copper layer 300 to increase the copper thickness.

[0084] Reference Figures 8 to 12 , in this embodiment, the steps of pattern electroplating the inner copper layer 300 include:

[0085] S401: A dry film 331 is set on the non-electroplated area of the inner copper layer 300.

[0086] Before electroplating, first, a dry film 331 is set on the non-electroplated area of the inner copper layer 300. The dry film 331 is a photosensitive resin material, and a pattern can be formed through exposure and development processes to protect the underlying copper layer from being eroded by the electroplating solution. Select the corresponding thickness of the dry film 331 according to actual needs. It should be noted that the maximum thickness of the dry film 331 should not exceed 0.200 mm.

[0087] S402: The inner copper layer 300 is electroplated with copper and tin 332 in sequence.

[0088] After setting the dry film 331, first, copper electroplating is carried out in the electroplating solution to increase the thickness of the copper layer. Subsequently, tin 332 electroplating is carried out.

[0089] S403: Remove the film, etch, and strip tin 332 in sequence.

[0090] After electroplating, the dry film 331 needs to be removed. Then, the etching process is carried out, and chemical or physical methods are used to remove the copper layer that is not protected by electroplating to form the required circuit pattern. Finally, the tin 332 layer is stripped off, leaving the copper layer that has been electroplated and etched.

[0091] S404: A resin isolation layer 700 is set on the exposed surface of the inner copper layer 300.

[0092] S405: Grind and remove the resin isolation layer 700 on the electroplated side of the inner copper layer 300.

[0093] Through the above steps, the resin isolation layer 700 covers both sides of the inner copper layer 300. The electrical isolation performance of the inner copper layer 300 is improved.

[0094] Copper thickening of the inner copper layer 300 is carried out by pattern electroplating. While increasing the thickness of the inner copper layer 300, the firmness of the structure of the inner copper layer 300 is not damaged, ensuring that the inner copper layer 300 is taken as a whole and avoiding problems such as poor conduction. In this embodiment, the thickness of the inner copper layer 300 obtained through the above steps is greater than 0.34 mm, and the depression of the obtained inner copper layer 300 (the height difference between the inner copper layer and the substrate) is less than 0.005 mm.

[0095] In this embodiment, the first blind via 800 is electroplated and ground after electroplating, and then pattern selective electroplating of copper is used to thicken the copper, obtaining an inner copper layer 300 with a larger thickness. This not only solves the problem that it is not easy to fill the resin in the ultra-thick copper gap, but also avoids the waste generated by the whole-board electroplating of thick copper. In addition, during the manufacturing process of the ultra-thick copper PCB, due to the large thickness of the copper layer, it is difficult to ensure the accuracy of the lines and the surface quality by direct etching. In this embodiment, through blind via electroplating and pattern selective electroplating of copper, the thickening position and thickness of the copper layer are precisely controlled, thereby reducing the etching difficulty and improving the accuracy of the lines and the surface quality.

[0096] S500: The first dielectric layer 210 and the second dielectric layer 220 are respectively arranged on the two opposite surfaces of the inner copper layer 300, and the fourth copper layer 411 is arranged on the surface of the first dielectric layer 210 facing away from the inner copper layer 300, and the fifth copper layer 421 is arranged on the surface of the second dielectric layer 220 facing away from the inner copper layer 300.

[0097] Reference Figure 13 , first, the first dielectric layer 210 and the second dielectric layer 220 are respectively laminated on the two opposite surfaces of the inner copper layer 300. Then, the fourth copper layer 411 is laminated on the surface of the first dielectric layer 210 facing away from the inner copper layer 300, and the fifth copper layer 421 is laminated on the surface of the second dielectric layer 220 facing away from the inner copper layer 300. Electrical insulation between the fourth copper layer 411 and the fifth copper layer 421 and the inner copper layer 300 is achieved through the isolation of the first dielectric layer 210 and the second dielectric layer 220.

[0098] S600: The first blind hole 900 is formed on the first dielectric layer 210 and the fourth copper layer 411, and the opening of the first blind hole 900 is located on the fourth copper layer 411.

[0099] Reference Figure 17 , the first blind hole 900 is formed on the first dielectric layer 210 and the fourth copper layer 411, and the opening of the first blind hole 900 is located on the fourth copper layer 411. Specifically, first, laser window opening is performed on the fourth copper layer 411. Then, laser drilling is performed at the laser window opening position on the fourth copper layer 411, thereby obtaining the first blind hole 900 with an opening located on the fourth copper layer 411.

[0100] S700: An inner layer conductive copper layer 500 is disposed in the first blind hole 900, a sixth copper layer 412 is disposed on the side of the fourth copper layer 411 facing away from the first dielectric layer 210, and a seventh copper layer 422 is disposed on the side of the fifth copper layer 421 facing away from the second dielectric layer 220.

[0101] Among them, the sixth copper layer 412 and the fourth copper layer 411 are integrally formed into a first surface copper layer 410, the seventh copper layer 422 and the second copper layer 320 are integrally formed into a second surface copper layer 420, and the first surface copper layer 410 is electrically connected to the inner layer copper layer 300 through the inner layer conductive copper layer 500.

[0102] Reference Figure 18 , in this embodiment, the inner layer conductive copper layer 500 is disposed in the first blind hole 900, the sixth copper layer 412 is disposed on the side of the fourth copper layer 411 facing away from the first dielectric layer 210, and the seventh copper layer 422 is disposed on the side of the fifth copper layer 421 facing away from the second dielectric layer 220 are realized by electroplating copper. The first surface copper layer 410 is electrically connected to the inner layer copper layer 300 through the inner layer conductive copper layer 500 to realize electrical connection between multiple layers. The inner layer copper layer 300, the inner layer conductive copper layer 500, and the first surface copper layer 410 form an ultra-thick copper heat dissipation layer, significantly improving the heat dissipation capacity of the power supply board structure, helping to reduce the working temperature of the power supply board, and improving its stability and reliability.

[0103] S800: Pattern the first surface copper layer 410 and the second surface copper layer 420.

[0104] Reference Figure 21 , pattern the first surface copper layer 410 and the second surface copper layer 420 according to actual requirements to form the outer layer circuit of the multi-layer micro-space power supply board. The following is an optional patterning method. First, a layer of photoresist is evenly coated on the surfaces of the first surface copper layer 410 and the second surface copper layer 420. Using a lithography machine or a step exposure machine, the copper layer coated with photoresist is exposed through a mask plate. The pattern on the mask plate determines the final circuit layout of the circuit board. During the exposure process, light passes through the transparent part of the mask plate and irradiates the photoresist, causing a chemical reaction. After exposure, the circuit board is placed in a developer to dissolve the exposed area of the photoresist, thereby forming the required pattern on the surface of the copper layer. Use methods such as chemical etching solution or plasma etching to remove the part of the copper layer not covered by the photoresist. The etching solution will react with the copper not covered by the photoresist and will not attack the copper layer protected by the photoresist. After etching, only the area covered by the photoresist remains on the copper layer, thereby forming the outer layer circuit of the multi-layer micro-space power supply board. After etching is completed, use a stripping solution or plasma stripping and other methods to remove the remaining photoresist to expose the complete outer layer circuit. Finally, the circuit board is cleaned to remove residual etching solution, stripping solution and other impurities.

[0105] S900: Conductive solder mask treatment for the outer layer circuit.

[0106] Conductive solder mask treatment is performed on the outer layer circuit to protect the circuit from external environmental erosion and the risk of short circuits. The following is an optional conductive solder mask treatment method. First, the oxide layer, oil stains, and other impurities on the surface of the outer layer circuit are removed to ensure that the conductive solder mask ink can firmly adhere to the copper layer. Among them, common cleaning methods include using chemical cleaning agents, ultrasonic cleaning, etc. Then, select a suitable conductive solder mask ink according to the actual application scenario and requirements. Use screen printing, electrostatic spraying, curtain coating, or roller printing to evenly coat the conductive solder mask ink on the surface of the outer layer circuit. Place the outer layer circuit coated with the conductive solder mask ink in an oven for pre-baking treatment to volatilize the solvent in the ink and form a smooth and non-sticky coating state. Then, use a lithography machine or an exposure machine to transfer the image to the conductive solder mask ink through a negative film (or direct laser imaging). During exposure, ultraviolet light irradiates the ink, causing a photochemical reaction to harden and firmly adhere to the copper layer. Then, place the exposed PCB in a developer solution to wash away the unhardened ink. The developer solution usually uses a weak alkaline solution such as sodium carbonate. Finally, place the developed PCB in an oven for post-baking treatment. The purpose of post-baking is to completely cure the ink and enhance its solder resistance, wear resistance, and chemical corrosion resistance.

[0107] Embodiment 2

[0108] Based on the same inventive concept as Embodiment 1, refer to Figure 3 , this embodiment is used to achieve cross-layer conduction between the first surface copper layer 410 and the second surface copper layer 420 on the basis of the manufacturing method of Embodiment 1. Specifically, it is achieved through the following methods.

[0109] First, after setting the fifth copper layer 421 on the side of the second dielectric layer 220 facing away from the inner copper layer 300 in this embodiment, and before setting the inner layer conductive copper layer 500 in the blind hole, it further includes:

[0110] S510: Form at least one first through hole 640 on the fourth copper layer 411, the first dielectric layer 210, the inner copper layer 300, the second dielectric layer 220, and the fifth copper layer 421.

[0111] Refer to Figure 14 , in this embodiment, at least one first through hole 640 is formed on the fourth copper layer 411, the first dielectric layer 210, the inner copper layer 300, the second dielectric layer 220, and the fifth copper layer 421 by mechanical drilling. The first through hole 640 penetrates the fourth copper layer 411, the first dielectric layer 210, the inner copper layer 300, the second dielectric layer 220, and the fifth copper layer 421, providing a physical channel for crossing the inner copper layer 300.

[0112] S520: A first insulating layer 610 is disposed within the first through-hole 640.

[0113] Reference Figure 15 , resin plug the first through-hole 640 to form the first insulating layer 610, and grind the first insulating layer 610 at both ends of the first through-hole 640 to be flat.

[0114] S530: A second through-hole 650 is formed within the first insulating layer 610.

[0115] Reference Figure 16 , mechanically drill a hole within the first insulating layer 610 to form the second through-hole 650, thereby realizing the formation of a conductive channel within the first insulating layer 610, and enabling the first insulating layer 610 to isolate the inner copper layer 300.

[0116] S710: A cross-layer conducting copper layer 620 is disposed within the second through-hole 650.

[0117] Reference Figure 18 , during the process of forming the inner-layer conducting copper layer 500 within the blind hole, forming the sixth copper layer 412 on the side of the fourth copper layer 411 facing away from the first dielectric layer 210, and forming the seventh copper layer 422 on the side of the fifth copper layer 421 facing away from the second dielectric layer 220 by electroplating copper, a cross-layer conducting copper layer 620 can be formed within the second through-hole 650. In addition, through the through-hole electroplating copper process with a high aspect ratio, a third through-hole 660 can also be formed on the first surface copper layer 410, the cross-layer conducting copper layer 620, and the second surface copper layer 420. In this embodiment, the isolation of the inner copper layer 300 and the conduction between the first surface copper layer 410 and the second surface copper layer 420 are both achieved within the first through-hole 640, which can effectively reduce the size of the overall unit pattern.

[0118] S720: A second insulating layer 630 is disposed within the third through-hole 660, and copper is backfilled on the side of the first surface copper layer 410 facing away from the first dielectric layer 210 and on the side of the second surface copper layer 420 facing away from the second dielectric layer 220. Reference Figure 19 And Figure 20 , the backfilled copper not only covers the third through-hole 660, but also further increases the copper thickness of the first surface copper layer 410 and the second surface copper layer 420.

[0119] Embodiment 3

[0120] This embodiment introduces a multi-layer micro-space power supply board. Reference Figure 1, the multi-layer micro-space power board in this embodiment includes: a substrate 100, a dielectric layer, an inner copper layer 300, a surface copper layer, and an inner conduction copper layer 500. Among them, a through groove 110 is formed on the substrate 100 by laser. The dielectric layer includes a first dielectric layer 210 and a second dielectric layer 220 disposed on opposite sides of the substrate 100, and at least one through hole is provided on the first dielectric layer 210. The inner copper layer 300 is stacked between the first dielectric layer 210 and the second dielectric layer 220 and fills the through groove 110. Further, a resin isolation layer 700 is provided between the first dielectric layer 210 and the second dielectric layer 220, and the resin isolation layer 700 covers both side surfaces of the inner copper layer 300. The resin isolation layer 700 improves the electrical isolation performance and structural stability of the power board, and reduces the risk of failures caused by short circuits, signal interference, or structural looseness. The surface copper layer is subjected to solder mask treatment, including a first surface copper layer 410 disposed on the side of the first dielectric layer 210 facing away from the inner copper layer 300 and a second surface copper layer 420 disposed on the side of the second dielectric layer 220 facing away from the inner copper layer 300. The inner conduction copper layer 500 is disposed in the through hole and is electrically connected to the inner copper layer 300 and the first surface copper layer 410. In this embodiment, the thickness of the inner copper layer 300 is greater than 0.34 mm.

[0121] In this embodiment, by providing the through groove 110 on the substrate 100 and filling the through groove 110 with the inner copper layer 300, a relatively thick copper heat dissipation layer is formed between the first dielectric layer 210 and the second dielectric layer 220. By providing a through hole in the first dielectric layer 210 and disposing the inner conduction copper layer 500 in the through hole, an ultra-thick copper heat dissipation layer composed of the inner copper layer 300, the inner conduction copper layer 500, and the first surface copper layer 410 is formed. The ultra-thick copper heat dissipation layer is obtained by maximizing the use of the longitudinal space of the power board structure, significantly improving the heat dissipation capacity of the power board structure, helping to reduce the working temperature of the power board, and improving its stability and reliability.

[0122] In this embodiment, unit pattern cutting channels 120 are provided on the substrate 100.

[0123] Embodiment 4

[0124] Based on the same inventive concept as the said Embodiment 3, refer to Figure 1, this embodiment is used to achieve the cross-layer conduction of the multi-layer micro-space power board to meet the design requirements of complex circuits. Specifically, in this embodiment, at least one buried via is formed on the first surface copper layer 410, the first dielectric layer 210, the inner copper layer 300, the second dielectric layer 220, and the second surface copper layer 420. Both ends of the buried via are located in the first surface copper layer 410 and the second surface copper layer 420 respectively. A first insulating layer 610, a cross-layer conduction copper layer 620, and a second insulating layer 630 are sequentially nested in the buried via. The cross-layer conduction copper layer 620 is electrically connected to the first surface copper layer 410 and the second surface copper layer 420.

[0125] In this embodiment, by setting the buried via, a conduction channel is formed in the first surface copper layer 410, the first dielectric layer 210, the inner copper layer 300, the second dielectric layer 220, and the second surface copper layer 420. The inner copper layer 300 is isolated by setting the first insulating layer 610 in the buried via, and the conduction between the first surface copper layer and the second surface copper layer 420 is achieved by setting the cross-layer conduction copper layer 620 in the first insulating layer 610, so as to meet the conduction requirement across the inner copper layer 300. The design of the cross-layer conduction copper layer 620 makes the power board more flexible in layout and wiring, meets the design requirements of complex circuits, can save the surface wiring space to the greatest extent, and make the best use of the inner layer heat dissipation ultra-thick copper space. It can reduce the unit pattern size by more than 20% under the premise of the same heat dissipation, and finally achieve the overall cost reduction advantage.

[0126] The above is only the preferred embodiment of the present application. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present disclosure / the present application, several improvements and deformations can still be made, and these improvements and deformations should also be regarded as the protection scope of the present disclosure / the present application.

Claims

1. A manufacturing method of a multi-layer micro-space power supply board, characterized in that Comprising the following steps: Providing a first copper layer, a substrate, and a second copper layer that are sequentially stacked; Forming a first blind via on the substrate and the first copper layer, with the opening of the first blind via located on the first copper layer; Providing a third copper layer covering the surface of the second copper layer, the interior of the first blind via, and the surface of the first copper layer to form an inner copper layer integrated with the second copper layer and the first copper layer; Graphically electroplating the inner copper layer; Respectively providing a first dielectric layer and a second dielectric layer on the opposite two surfaces of the inner copper layer, providing a fourth copper layer on the side of the first dielectric layer facing away from the inner copper layer, and providing a fifth copper layer on the side of the second dielectric layer facing away from the inner copper layer; Forming a first blind hole on the first dielectric layer and the fourth copper layer, with the opening of the first blind hole located on the fourth copper layer; Providing an inner conduction copper layer in the first blind hole, providing a sixth copper layer on the side of the fourth copper layer facing away from the first dielectric layer, and providing a seventh copper layer on the side of the fifth copper layer facing away from the second dielectric layer; Wherein, the sixth copper layer and the fourth copper layer are integrally formed into a first surface copper layer, the seventh copper layer and the second copper layer are integrally formed into a second surface copper layer, and the first surface copper layer is electrically connected to the inner copper layer through the inner conduction copper layer; Patterning the first surface copper layer and the second surface copper layer.

2. The manufacturing method of the multi-layer micro-space power supply board according to claim 1, wherein The step of providing a third copper layer covering the surface of the second copper layer, the interior of the first blind via, and the surface of the first copper layer includes: Cleaning the first blind via; Chemically depositing copper in the first blind via; Electroplating copper to form the third copper layer and grinding the surface of the third copper layer.

3. The manufacturing method of the multi-layer micro-space power supply board according to claim 1, characterized in that, The step of graphically electroplating the inner copper layer includes: Providing a dry film on the non-electroplated area of the inner copper layer; Sequentially electroplating copper and tin on the inner copper layer; Performing film removal, etching, and tin stripping in sequence; Providing a resin isolation layer on the exposed surface of the inner copper layer; Grinding to remove the resin isolation layer on the electroplated side of the inner copper layer.

4. The manufacturing method of the multi-layer micro-space power supply board according to claim 1, characterized in that, After providing a fifth copper layer on the side of the second dielectric layer facing away from the inner copper layer and before providing an inner conduction copper layer in the first blind hole, it further includes: Forming at least one first through hole on the fourth copper layer, the first dielectric layer, the inner copper layer, the second dielectric layer, and the fifth copper layer; Providing a first insulating layer in the first through hole; Forming a second through hole in the first insulating layer.

5. The manufacturing method of the multi-layer micro-space power supply board according to claim 4, characterized in that, The step of providing a cross-layer conduction copper layer in the second through hole, providing an inner conduction copper layer in the first blind hole, providing a sixth copper layer on the side of the fourth copper layer facing away from the first dielectric layer, and providing a seventh copper layer on the side of the fifth copper layer facing away from the second dielectric layer includes: electroplating copper to form a third through hole on the first surface copper layer, the cross-layer conduction copper layer, and the second surface copper layer through electroplating copper.

6. The manufacturing method of the multi-layer micro-space power supply board according to claim 5, characterized in that, Providing a second insulating layer in the third through hole; Redepositing copper on the side of the first surface copper layer facing away from the first dielectric layer and on the side of the second surface copper layer facing away from the second dielectric layer.

7. A multi-layer micro-space power supply board, characterized in that, Including: A substrate, with a through groove formed on the substrate; A dielectric layer, including a first dielectric layer and a second dielectric layer provided on opposite sides of the substrate, and at least one through hole provided on the first dielectric layer; The inner copper layer is stacked between the first dielectric layer and the second dielectric layer and fills the through groove; The surface copper layer includes a first surface copper layer disposed on a surface of the first dielectric layer facing away from the inner copper layer and a second surface copper layer disposed on a surface of the second dielectric layer facing away from the inner copper layer; The inner conductive copper layer is disposed in the through hole and is electrically connected to the inner copper layer and the first surface copper layer.

8. The multi-layer micro-space power supply board according to claim 7, wherein, At least one buried via is formed in the first surface copper layer, the first dielectric layer, the inner copper layer, the second dielectric layer, and the second surface copper layer. Two ends of the buried via are respectively located in the first surface copper layer and the second surface copper layer. A first insulating layer, a cross-layer conductive copper layer, and a second insulating layer are sequentially nested in the buried via. The cross-layer conductive copper layer is electrically connected to the first surface copper layer and the second surface copper layer.

9. The multi-layer micro-space power supply board according to claim 8, characterized in that, A resin isolation layer is provided between the first dielectric layer and the second dielectric layer. The resin isolation layer covers both side surfaces of the inner copper layer.

10. The multi-layer micro-space power supply board according to claim 7, characterized in that, Unit pattern cutting channels are provided on the substrate.

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