Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and the semiconductor device comprises a plurality of transistors which are distributed in different layers and are stacked in a direction perpendicular to a substrate; the word lines penetrate through different layers and extend in the direction perpendicular to the substrate; the transistor comprises a first electrode, a second electrode, a semiconductor layer and a contact layer, the semiconductor layer surrounds the side wall of the word line, the semiconductor layer is arranged between the contact layer and the word line, a first groove and a second groove are formed in the semiconductor layer, and the opening directions of the first groove and the second groove deviate from the word line. The first grooves and the second grooves are formed in the side walls of the word lines at intervals, the contact layers are distributed on the bottom walls and the side walls of the first grooves and the second grooves, the first grooves are filled with the first electrodes, and the second grooves are filled with the second electrodes. According to the scheme provided by the embodiment, the contact area of the semiconductor layer with the first electrode and the second electrode is large, the gate control capability is good, the contact resistance is small, the contact layer can protect the semiconductor layer in the manufacturing process, and the stability of the device is improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present application provides a semiconductor device and a manufacturing method thereof, and an electronic device, which simplifies the process and reduces contact resistance.

[0006] An embodiment of the present application provides a semiconductor device, including:

[0007] Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate;

[0008] A word line, passing through the transistors of different layers and extending in a direction perpendicular to the substrate;

[0009] The transistor includes: a first electrode, a second electrode, a semiconductor layer and a contact layer, the semiconductor layer surrounds the side wall of the word line, and the semiconductor layer is arranged between the contact layer and the word line, the semiconductor layer is formed with a first groove and a second groove with an opening direction away from the word line, the first groove and the second groove are spaced apart on the side wall of the word line, the contact layer is distributed on the bottom wall of the first groove and two side walls parallel to the substrate, and distributed on the bottom wall of the second groove and two side walls parallel to the substrate, the first electrode fills the first groove with the contact layer, and the second electrode fills the second groove with the contact layer.

[0010] In some embodiments, the semiconductor layer and the contact layer in the first groove overlap, and the semiconductor layer and the contact layer in the second groove overlap.

[0011] In some embodiments, the semiconductor layers of multiple transistors located at the same position in different layers are arranged at intervals, and the contact layers of multiple transistors located at the same position in different layers are arranged at intervals.

[0012] In some embodiments, the first electrode is disposed in the first groove, and the second electrode is disposed in the second groove; the first electrode extends in a direction parallel to the substrate, and the second electrode extends in a direction parallel to the substrate.

[0013] In some embodiments, the word line is located in a vertical word line hole, and the cross-sectional shapes and sizes of the word lines are the same; the region of the semiconductor layer between the first electrode and the second electrode only includes the region extending along the sidewall of the word line; the regions of the semiconductor layer in contact with the first electrode and the second electrode include the region extending along the sidewall of the word line and the region extending in a direction parallel to the substrate.

[0014] In some embodiments, multiple transistors in the same layer are arranged in an array in a first direction and a second direction, and the semiconductor device further includes: multiple bit lines extending in the second direction and distributed in different layers, and each bit line is connected to the second electrodes of the transistors in the same column distributed in the second direction in the same layer through a first connecting sub-electrode.

[0015] In some embodiments, the first connecting sub-electrode is connected to the semiconductor layer on the end face of the second groove and, to the contact layer located at the opening of the second groove.

[0016] In some embodiments, the semiconductor device further includes: a capacitor disposed on a side of the first electrode facing away from the word line; the capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode extends in a direction parallel to the substrate, the first capacitor electrode includes a first end face facing the word line and a second end face facing away from the word line, and a side surface connecting the first end face and the second end face, and the second capacitor electrode wraps the side surface of the first capacitor electrode whose distance from the first end face is greater than or equal to a preset distance; the first end face of the first capacitor electrode is connected to the first electrode through a second connecting sub-electrode.

[0017] In some embodiments, the second connecting sub-electrode is connected to the semiconductor layer on the end face of the first groove and, to the contact layer located at the opening of the first groove.

[0018] In some embodiments, the semiconductor device further includes: an isolation layer disposed between word lines adjacent in a second direction, penetrating different layers and extending along a direction perpendicular to the substrate, the isolation layer including at least one of silicon oxyfluoride, silicon oxycarbide, and fluorinated amorphous carbon film, and in a plane parallel to the second direction and perpendicular to the substrate, a positive projection of the isolation layer overlaps a positive projection of the word line.

[0019] In some embodiments, the isolation layer is connected to a semiconductor layer in a region between the first groove and the second groove distributed on sidewalls of the word line.

[0020] Embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including:

[0021] Providing a substrate, and sequentially and alternately depositing an insulating thin film and a sacrificial layer thin film on the substrate to form a stacked structure including alternately arranged insulating layers and sacrificial layers;

[0022] Forming a hole penetrating the stacked structure in a direction perpendicular to the substrate, and forming a gate insulating layer covering an inner wall of the hole and a word line filling the hole in the hole;

[0023] Forming a plurality of first trenches penetrating the stacked structure and extending in a first direction, the plurality of first trenches being spaced apart in the first direction and a second direction, the hole being located between the first trenches adjacent in the second direction and sidewalls of the first trenches not exposing the gate insulating layer, etching the sacrificial layer through the first trenches to expose an annular gate insulating layer, and simultaneously forming an annular lateral groove with adjacent insulating layers as sidewalls and the sidewall of the gate insulating layer as a bottom wall, sequentially depositing a semiconductor thin film, a contact layer thin film, and a first conductive thin film in the annular lateral groove and the first trenches, and filling the annular lateral groove with the first conductive thin film, etching and removing the first conductive thin film, the contact layer thin film, and the semiconductor thin film covering ends of each insulating layer in the first trenches, and retaining the first conductive thin film, the contact layer thin film, and the semiconductor thin film in the annular lateral groove;

[0024] Etching the first conductive thin film, the contact layer thin film, and the semiconductor thin film in the annular lateral groove to respectively form a semiconductor layer, a contact layer, a first electrode, and a second electrode, the semiconductor layer surrounding a sidewall of the word line, the semiconductor layer forming a first groove and a second groove with an opening direction facing away from the word line, the first groove and the second groove being distributed in the first direction on the sidewall of the word line, the first electrode filling the first groove, and the second electrode filling the second groove.

[0025] In some embodiments, etching the first conductive film, the contact layer film, and the semiconductor film in the annular transverse groove includes:

[0026] forming a second trench and a third trench in the first trench that penetrate the stack structure and are distributed in the first direction and spaced from each other, performing lateral etching through the second trench to expose a side wall of the semiconductor layer disposed on the first side of the word line away from the word line, etching and removing the side wall of the semiconductor layer disposed on the first side of the word line away from the word line and the side wall of the contact layer disposed on the first side of the word line away from the word line, exposing the first electrode, and performing lateral etching through the third trench to expose a portion of the contact layer disposed on the second side of the word line that is parallel to the substrate and faces the surface of the first conductive film, etching and removing the exposed area of the contact layer and the semiconductor layer connected to the exposed area of the contact layer;

[0027] A fourth trench is formed penetrating the stacked structure, wherein the sidewall of the fourth trench distributed along the second direction exposes the semiconductor layer, and on a plane perpendicular to the substrate and parallel to the first direction, the orthographic projection of the word line falls within the orthographic projection of the fourth trench.

[0028] In some embodiments, when the first conductive film, the contact layer film, and the semiconductor film in the annular transverse groove are etched, a bit line extending along the second direction is also formed;

[0029] After etching the first conductive film, the contact layer film and the semiconductor film in the annular lateral groove, it also includes: depositing a second conductive film, etching and removing the second conductive film located in the second groove and the third groove to form a second connecting sub-electrode connected to the end face of the first electrode away from the word line, and a first connecting sub-electrode located between the second electrode and the bit line and connected to the second electrode and the bit line.

[0030] In some embodiments, the method further includes: forming an isolation layer filling the fourth trench, the isolation layer including at least one of silicon oxyfluoride, silicon oxycarbide, and a fluorinated amorphous carbon film.

[0031] An embodiment of the present disclosure provides an electronic device, comprising any of the semiconductor devices described above, or a semiconductor device formed by any of the semiconductor device manufacturing methods described above.

[0032] This application includes a semiconductor device, a manufacturing method thereof, and an electronic device. The semiconductor device includes: a plurality of transistors stacked along a direction perpendicular to a substrate in different layers; word lines extending along the direction perpendicular to the substrate through the transistors in different layers; the transistors include: a first electrode, a second electrode, a semiconductor layer, and a contact layer. The semiconductor layer surrounds the sidewalls of the word lines, the semiconductor layer is disposed between the contact layer and the word lines, the semiconductor layer is formed with a first groove and a second groove with an opening direction facing away from the word lines, the first groove and the second groove are spaced apart on the sidewalls of the word lines, the contact layer is distributed on the bottom wall and two sidewalls parallel to the substrate of the first groove, and on the bottom wall and two sidewalls parallel to the substrate of the second groove. The first electrode fills the first groove provided with the contact layer, and the second electrode fills the second groove provided with the contact layer. The solution provided in this embodiment has a larger contact area, better gate control ability, smaller contact resistance compared with the solution where the semiconductor layer only contacts one sidewall of the first electrode and the second electrode, and the contact layer can protect the semiconductor layer during the manufacturing process, improving the film quality of the semiconductor layer and the device performance.

[0033] Other features and advantages of this application will be described in the subsequent description, and part of them will become obvious from the description, or will be understood by implementing this application. Other advantages of this application can be achieved and obtained through the solutions described in the description and the drawings.

[0034] Other aspects can be understood after reading and understanding the drawings and the detailed description. Description of the Drawings

[0035] The drawings are used to provide an understanding of the technical solutions of this application, and constitute a part of the description. Together with the embodiments of this application, they are used to explain the technical solutions of this application and do not constitute a limitation to the technical solutions of this application.

[0036] Figure 1A A plan view of a semiconductor device provided for an exemplary embodiment; Figure 1B For Figure 1A schematic view in the aa' direction in Figure 1C For Figure 1A schematic view in the bb' direction in Figure 1D For Figure 1A schematic view in the cc' direction in Figure 1E For Figure 1A schematic view in the dd' direction in

[0037] Figure 2 A cross-sectional view along the aa' direction after forming a stacked structure provided for an exemplary embodiment;

[0038] Figure 3A The mask pattern used to form the first hole provided for an exemplary embodiment; Figure 3B A cross-sectional view along the aa' direction after the first hole is formed, Figure 3C A cross-sectional view along the bb' direction, Figure 3D A cross-sectional view along the cc' direction, Figure 3E A cross-sectional view along the dd' direction;

[0039] Figure 4A A cross-sectional view along the aa' direction after the gate insulating layer and the word line are formed provided for an exemplary embodiment, Figure 4B A cross-sectional view along the bb' direction, Figure 4C A cross-sectional view along the cc' direction, Figure 4D A cross-sectional view along the dd' direction;

[0040] Figure 5A The mask pattern used to form the first trench provided for an exemplary embodiment; Figure 5B A cross-sectional view along the aa' direction after the first trench is formed, Figure 5C A cross-sectional view along the bb' direction, Figure 5D A cross-sectional view along the cc' direction, Figure 5E A cross-sectional view along the dd' direction;

[0041] Figure 6A A cross-sectional view along the aa' direction after the support layer is formed provided for an exemplary embodiment, Figure 6B A cross-sectional view along the bb' direction, Figure 6C A cross-sectional view along the cc' direction, Figure 6D A cross-sectional view along the dd' direction.

[0042] Figure 7A The mask pattern used to form the second trench provided for an exemplary embodiment; Figure 7B A cross-sectional view along the aa' direction after the second trench is formed, Figure 7C A cross-sectional view along the bb' direction, Figure 7D A cross-sectional view along the cc' direction, Figure 7E A cross-sectional view along the dd' direction;

[0043] Figure 8A A cross-sectional view along the aa' direction after the sacrificial layer in the capacitor region is etched provided for an exemplary embodiment, Figure 8B A cross-sectional view along the bb' direction, Figure 8C A cross-sectional view along the cc' direction, Figure 8D A cross-sectional view along the dd' direction;

[0044] Figure 9A A cross-sectional view along the aa' direction after the first conductive layer is formed provided for an exemplary embodiment, Figure 9BIt is a cross-sectional view along the bb' direction. Figure 9C It is a cross-sectional view along the cc' direction. Figure 9D It is a cross-sectional view along the dd' direction.

[0045] Figure 10A It is a mask pattern used to form the third trench provided for an exemplary embodiment. Figure 10B It is a cross-sectional view along the aa' direction after forming the third trench. Figure 10C It is a cross-sectional view along the bb' direction. Figure 10D It is a cross-sectional view along the cc' direction. Figure 10E It is a cross-sectional view along the dd' direction.

[0046] Figure 11A It is a cross-sectional view along the aa' direction after etching the first insulating layer in the capacitor region provided for an exemplary embodiment. Figure 11B It is a cross-sectional view along the bb' direction. Figure 11C It is a cross-sectional view along the cc' direction. Figure 11D It is a cross-sectional view along the dd' direction.

[0047] Figure 12A It is a cross-sectional view along the aa' direction after forming the dielectric layer and the second capacitor electrode provided for an exemplary embodiment. Figure 12B It is a cross-sectional view along the bb' direction. Figure 12C It is a cross-sectional view along the cc' direction. Figure 12D It is a cross-sectional view along the dd' direction.

[0048] Figure 13A It is a mask pattern used to form the fourth trench provided for an exemplary embodiment. Figure 13B It is a cross-sectional view along the aa' direction after forming the fourth trench. Figure 13C It is a cross-sectional view along the bb' direction. Figure 13D It is a cross-sectional view along the cc' direction. Figure 13E It is a cross-sectional view along the dd' direction.

[0049] Figure 14A It is a cross-sectional view along the aa' direction after forming the third lateral groove provided for an exemplary embodiment. Figure 14B It is a cross-sectional view along the bb' direction. Figure 14C It is a cross-sectional view along the cc' direction. Figure 14D It is a cross-sectional view along the dd' direction.

[0050] Figure 15A It is a cross-sectional view along the aa' direction after forming the semiconductor layer and the contact layer provided for an exemplary embodiment. Figure 15B It is a cross-sectional view along the bb' direction. Figure 15C It is a cross-sectional view along the cc' direction. Figure 15D It is a cross-sectional view along the dd' direction.

[0051] Figure 16A Cross-sectional view along the aa' direction after forming the second conductive layer provided for an exemplary embodiment Figure 16B Cross-sectional view along the bb' direction Figure 16C Cross-sectional view along the cc' direction Figure 16D Cross-sectional view along the dd' direction

[0052] Figure 17A Cross-sectional view along the aa' direction after exposing the fourth trench provided for an exemplary embodiment Figure 17B Cross-sectional view along the bb' direction Figure 17C Cross-sectional view along the cc' direction Figure 17D Cross-sectional view along the dd' direction

[0053] Figure 18A Cross-sectional view along the aa' direction after forming the seventh insulating layer provided for an exemplary embodiment Figure 18B Cross-sectional view along the bb' direction Figure 18C Cross-sectional view along the cc' direction Figure 18D Cross-sectional view along the dd' direction

[0054] Figure 19A Mask pattern used to form the fifth trench and the sixth trench provided for an exemplary embodiment Figure 19B Cross-sectional view along the aa' direction after forming the fifth trench and the sixth trench Figure 19C Cross-sectional view along the bb' direction Figure 19D Cross-sectional view along the cc' direction Figure 19E Cross-sectional view along the dd' direction

[0055] Figure 20A Cross-sectional view along the aa' direction after laterally etching the first conductive layer and the second conductive layer provided for an exemplary embodiment Figure 20B Cross-sectional view along the bb' direction

[0056] Figure 21A Cross-sectional view along the aa' direction after etching the semiconductor layer and the contact layer provided for an exemplary embodiment Figure 21B Cross-sectional view along the bb' direction

[0057] Figure 22A Cross-sectional view along the aa' direction after forming the first connection sub-electrode and the second connection sub-electrode provided for an exemplary embodiment Figure 22B Cross-sectional view along the bb' direction

[0058] Figure 23 Cross-sectional view along the bb' direction after exposing the fifth trench and the sixth trench provided for an exemplary embodiment

[0059] Figure 24 Cross-sectional view along the bb' direction after forming the ninth insulating layer provided for an exemplary embodiment;

[0060] Figure 25A Mask pattern used for forming the seventh trench provided for an exemplary embodiment; Figure 25B Cross-sectional view along the bb' direction after forming the seventh trench, Figure 25C Cross-sectional view along the cc' direction. Detailed implementation manners

[0061] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Without conflict, the embodiments of the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0062] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should have the ordinary meaning understood by those of ordinary skill in the field to which the present disclosure belongs.

[0063] The embodiments of the present disclosure do not necessarily limit the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0064] The ordinal numbers such as "first", "second", "third", etc. in the present disclosure are set to avoid confusion of components and do not represent any order, quantity or importance.

[0065] In the present disclosure, for convenience, terms indicating orientation or positional relationship such as "middle part", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of components with reference to the drawings, which are only for facilitating the description of this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present disclosure. The positional relationship of the components is appropriately changed according to the directions describing the components. Therefore, it is not limited to the terms described in the disclosure and can be appropriately replaced according to the situation.

[0066] In the present disclosure, unless otherwise clearly specified and limited, the terms "install", "connect", "couple" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be directly connected, or indirectly connected through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific situations.

[0067] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to the region through which current mainly flows.

[0068] In the present disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, etc., the functions of the "source electrode" and the "drain electrode" may sometimes be swapped. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be swapped with each other.

[0069] In the present disclosure, "connection" includes cases where components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0070] In the present disclosure, "parallel" means approximately parallel or almost parallel. For example, a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus, it also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular. For example, a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus, it also includes a state where the angle is 85° or more and 95° or less.

[0071] In the embodiments of the present disclosure, "the positive projection of B is within the range of the positive projection of A" means that the boundary of the positive projection of B falls within the boundary of the positive projection of A, or the boundary of the positive projection of A overlaps with the boundary of the positive projection of B.

[0072] Figure 1A Schematic diagram of a semiconductor device provided for an exemplary embodiment Figure 1B is a cross-sectional view along the Figure 1A aa' direction in Figure 1C is a cross-sectional view along the Figure 1A bb' direction in Figure 1D is a cross-sectional view along the Figure 1A cc' direction in Figure 1E is a cross-sectional view along the Figure 1A dd' direction in. As Figures 1A to 1EAs shown in the figure, embodiments of the present disclosure provide a semiconductor device, which may include a multi-layer memory cell array vertically stacked on a substrate 1 and a plurality of word lines 40. Each layer of the memory cell array may include a plurality of memory cells and a plurality of bit lines 30, and the plurality of memory cells may be arrayed and distributed along a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1.

[0073] The word lines 40 may extend along a direction perpendicular to the substrate 1. Memory cells at the same position in different layers share one word line 40.

[0074] The bit lines 30 may be conductive lines extending along the second direction Y. The plurality of bit lines 30 in the memory cell array of the same layer may be spaced apart from each other, and the plurality of bit lines 30 may be spaced apart and distributed along the first direction X. The bit lines 30 of the memory cell arrays of different layers may be stacked on the substrate 1, and the bit lines 30 at the same position in different layers are spaced apart from each other.

[0075] The memory cell may be a 1T or 2T memory cell (such as a 2T0C or 2T1C memory cell) or other multi-transistor memory cells.

[0076] Taking the 1T1C memory cell as an example, the memory cell includes a transistor and a capacitor connected to the transistor. The transistor and the capacitor of the same memory cell may be distributed along the first direction X. The transistor may include a gate electrode 26, a first electrode 51, a second electrode 52, a semiconductor layer 23, and a contact layer 25. The gate electrode 26 may be a part of the word line 40, and the gate electrodes 26 of the transistors at the same position in different layers may be different regions of the same word line 40. The capacitor may include a first capacitor electrode 41 and a second capacitor electrode 42. The first electrode 51 may be connected to the first capacitor electrode 41 of the capacitor through a second connecting sub-electrode 62.

[0077] The second electrode 52 may be connected to the bit line 30 through a first connecting sub-electrode 61. The second electrodes 52 of the transistors of the memory cells in the same column of the same memory cell array may be connected to the same bit line 30. That is, the second electrodes 52 of the transistors in the same column distributed along the second direction Y are connected to form a bit line 30 extending along the second direction Y.

[0078] The second electrodes 52 of the transistors of adjacent two columns of memory cells in the same layer may be connected to the same bit line 30.

[0079] Next, a semiconductor device including a plurality of vertically stacked transistors at the same position will be taken as an example for illustration. And taking the memory cell as 1T1C as an example for illustration.

[0080] As Figures 1A to 1E shown in the figure, embodiments of the present disclosure provide a semiconductor device, including:

[0081] Multiple transistors are stacked along the direction perpendicular to the substrate 1 in different layers; it can be understood that multiple transistors are stacked in a column of vertical memory cells in the direction perpendicular to the substrate 1 and are insulated from each other in the direction perpendicular to the substrate 1.

[0082] The word line 40 extends along the direction perpendicular to the substrate 1 through the transistors in the different layers; one word line 40 is connected to the multiple transistors.

[0083] The transistor includes: a first electrode 51, a second electrode 52, a semiconductor layer 23, and a contact layer 25. The semiconductor layer 23 surrounds the side wall of the word line 40, and the semiconductor layer 23 is disposed between the contact layer 25 and the word line 40; the semiconductor layer 23 is formed with a first groove and a second groove with the opening direction facing away from the word line 40. The first groove and the second groove are spaced apart on the side wall of the word line 40. The contact layer 25 is distributed on the bottom wall of the first groove and two side walls parallel to the substrate 1, and is distributed on the bottom wall of the second groove and two side walls parallel to the substrate 1. The first electrode 51 fills the first groove provided with the contact layer 25, and the second electrode 52 fills the second groove provided with the contact layer 25. The contact layer 25 distributed in the first groove is disconnected from the contact layer 25 distributed in the second groove.

[0084] The solution provided in this embodiment has a larger contact area, better gate control ability, smaller contact resistance compared with the solution where the semiconductor layer only contacts one side wall of the first electrode and the second electrode. Moreover, the contact layer can protect the semiconductor layer during the manufacturing process, improving the film quality of the semiconductor layer, improving the device performance, and this solution does not require large-area etching of the semiconductor layer on the side wall, etc., reducing the process difficulty.

[0085] In some embodiments, the contact layer material is a material that can reduce the barrier thickness between the semiconductor layer and the first electrode and the second electrode. The solution provided in this embodiment can reduce the barrier thickness between the semiconductor layer and the first electrode and the second electrode by the contact layer, thereby reducing the contact resistance between the semiconductor layer and the first electrode and the second electrode. For example, the contact layer can be ITO, but the embodiments of the present disclosure are not limited thereto, and other materials that can reduce the barrier thickness can be used.

[0086] In some embodiments, the semiconductor layer 23 and the contact layer 25 in the first groove overlap, and the semiconductor layer 23 and the contact layer 25 in the second groove overlap. And the contact layer 25 in the first groove covers the semiconductor layer 23, and the contact layer 25 in the second groove covers the semiconductor layer 23.

[0087] In some embodiments, the semiconductor layers 23 of multiple transistors located at the same position in different layers may be spaced apart, that is, the contact layers 25 of multiple transistors located at the same position in different layers may be spaced apart, and the spaced-apart setting means physically disconnected. The solution provided in this embodiment can eliminate the parasitic MOS between layers and reduce leakage.

[0088] In some embodiments, the first groove may include a bottom wall extending in a direction perpendicular to the substrate 1 and two side walls extending in a direction parallel to the substrate 1, and the second groove may include a bottom wall extending in a direction perpendicular to the substrate 1 and two side walls extending in a direction parallel to the substrate 1.

[0089] In some embodiments, the first groove and the second groove may be distributed along the first direction X.

[0090] In some embodiments, the first electrode 51 may be disposed in the first groove.

[0091] In some embodiments, the first electrode 51 may extend in a direction parallel to the substrate 1.

[0092] In some embodiments, the second electrode 52 may be disposed in the second groove.

[0093] In some embodiments, the second electrode 52 may extend in a direction parallel to the substrate 1.

[0094] In some embodiments, the word line 40 may be located in a vertical (i.e., extending in a direction perpendicular to the substrate 1) word line hole, and the cross-sectional shape and size (section along a direction parallel to the substrate 1) of the word line 40 may be the same; the region of the semiconductor layer 23 located between the first electrode 51 and the second electrode 52 only includes the region extending along the side wall of the word line 40; the regions where the semiconductor layer 23 contacts the first electrode 51 and the second electrode 52 include the region extending along the side wall of the word line 40 and the region extending in a direction parallel to the substrate 1.

[0095] In some embodiments, the semiconductor layer 23 may also be distributed on the surface of the bit line 30 close to the substrate 1 and on the surface facing away from the substrate 1, and the contact layer 25 may also be distributed on the surface of the bit line 30 close to the substrate 1 and on the surface facing away from the substrate 1, and the semiconductor layer 23 is disposed on the side of the contact layer 25 facing away from the bit line 30. The semiconductor layer 23 distributed on the surface of the bit line 30 is physically disconnected from the semiconductor layer 23 surrounding the sidewall of the word line 40, and the contact layer 25 distributed on the surface of the bit line 30 is physically disconnected from the contact layer 25 surrounding the sidewall of the word line 40. In another exemplary embodiment, the semiconductor layer 23 and the contact layer 25 distributed on the surface of the bit line close to the substrate 1 and on the surface facing away from the substrate 1 may be removed.

[0096] In some embodiments, the first connecting sub-electrode 61 may be connected to the semiconductor layer 23 on the end face of the second groove, and further, to the contact layer 25 located at the opening of the second groove. Connecting to the contact layer 25 at the opening may be connecting to the surface of the contact layer 25 facing the opening direction of the second groove. That is, the first connecting sub-electrode 61 may be disposed at the opening of the second groove to close the second groove.

[0097] In some embodiments, the transistor may further include a gate insulating layer 24 surrounding the sidewall of the word line 40, and the gate insulating layer 24 is disposed between the semiconductor layer 23 and the word line 40. That is, the semiconductor layer 23 also surrounds the sidewall of the gate insulating layer 24.

[0098] In some embodiments, the gate insulating layers 24 of the transistors at the same position in different layers may be connected to form an integral structure. This solution can form the gate insulating layers 24 of multiple transistors through one process, simplifying the process.

[0099] In some embodiments, the semiconductor device may further include:

[0100] An insulating layer and a conductive layer alternately distributed in sequence along the direction perpendicular to the substrate 1, and the first electrode 51 and the second electrode 52 are disposed on the conductive layer;

[0101] A first hole penetrating each of the insulating layer and the conductive layer, and a gate insulating layer 24 and a word line 40 are sequentially distributed from the outside to the inside in the first hole. The solution provided in this embodiment can form the gate insulating layers 24 and the word lines 40 of multiple transistors through one process, simplifying the process.

[0102] In some embodiments, the diameter of the first sub-hole corresponding to the conductive layer of the first hole may be the same as or substantially the same as the diameter of the second sub-hole corresponding to the insulating layer. That is, a via hole can be formed by one etching, without setting different hole diameters for the conductive layer and the insulating layer.

[0103] In some embodiments, the first capacitive electrode 41 may extend in a direction parallel to the substrate 1, for example, extend along the first direction X.

[0104] In some embodiments, the first capacitive electrode 41 may include a first end face facing the word line 40, a second end face facing away from the word line 40, and a side surface connecting the first end face and the second end face. The second capacitive electrode 42 wraps the side surface of the first capacitive electrode 41 whose distance from the first end face is greater than or equal to a preset distance. That is, the second capacitive electrode 42 does not wrap the side surface close to the first end face (the side surface whose distance from the first end face is less than or equal to the preset distance). The first end face of the first capacitive electrode 41 is connected to the first electrode 51 through the second connecting sub-electrode 62. That is, the second connecting sub-electrode 62 is disposed between the first end face of the first capacitive electrode 41 and the side wall of the first electrode 51 facing away from the word line 40, and connects the first end face of the first capacitive electrode 41 and the side wall of the first electrode 51 facing away from the word line 40.

[0105] In some embodiments, the second connecting sub-electrode 62 is connected to the semiconductor layer 23 on the end face of the first groove, and is connected to the contact layer 25 at the opening of the first groove. The connection to the contact layer 25 at the opening may be a connection to the surface of the contact layer 25 facing the opening direction of the first groove. That is, the second connecting sub-electrode 62 may be formed at the opening of the first groove to close the first groove.

[0106] In some embodiments, the semiconductor device may further include: a connecting electrode 44 extending in a direction perpendicular to the substrate, and the connecting electrode 44 wraps the second capacitive electrodes 42 of the capacitors in the same column of different layers. The connecting electrode 44 may be a planar electrode extending over the entire surface.

[0107] In some embodiments, the semiconductor device may further include: an isolation layer 19 disposed between word lines 40 adjacent to each other along the second direction Y and extending in a direction perpendicular to the substrate 1 through different layers. In a plane parallel to the first direction X and perpendicular to the substrate 1, the orthographic projection of the isolation layer 19 may overlap with the orthographic projection of the word line 40.

[0108] In some embodiments, the isolation layer 19 may include at least one of silicon oxyfluoride, silicon oxycarbide, and fluorinated amorphous carbon film. Compared with using silicon dioxide or the like for isolation, the isolation layer 19 using the materials of this embodiment can reduce the parasitic capacitance between the word lines 40.

[0109] In some embodiments, on a plane parallel to the first direction X and perpendicular to the substrate 1, the orthographic projection of the word line 40 falls within the orthographic projection of the isolation layer 19. That is, the adjacent word lines 40 are isolated by the isolation layer 19, minimizing the parasitic capacitance as much as possible.

[0110] In some embodiments, the isolation layer 19 may be connected to the semiconductor layer 23 in a region between the first groove and the second groove distributed on the sidewall of the word line 40. Refer to Figure 1D , the isolation layer 19 is connected to the semiconductor layer 23.

[0111] In some embodiments, the isolation layer 19 may be connected to the bit line 30. As Figure 1C shown. However, the embodiments of the present disclosure are not limited thereto, and the isolation layer 19 may not be connected to the bit line 30.

[0112] In some embodiments, the semiconductor device may further include: a support layer 45 extending in a direction perpendicular to the substrate 1, a sacrificial layer 10 connected to the second end face of the first capacitor electrode 41, and the support layer 45 wrapping the sacrificial layer 10. The support layer 45 forms a plate-shaped film layer extending in a direction perpendicular to the substrate 1, which can be formed before manufacturing the capacitor and provides support for the subsequent manufacturing process of forming the capacitor. The support layer 45 wrapping the sacrificial layer 10 can enhance the support performance during the manufacturing process of the capacitor.

[0113] Other insulating materials, such as silicon dioxide, silicon nitride, etc., may also be filled between the memory cells.

[0114] The technical solution of this embodiment will be further described below through the manufacturing process of the semiconductor device in this embodiment. The "lithography process" mentioned in this embodiment includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist, which are mature manufacturing processes in the related art. The "photolithography process" mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition. Coating can use known coating processes, and etching can use known methods, which will not be specifically limited here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a lithography process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a lithography process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process or the photolithography process contains at least one "pattern".

[0115] In an exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0116] 1) Sequentially deposit a first insulating thin film and a sacrificial layer thin film on the substrate 1 to form a stacked structure, the stacked structure includes a plurality of alternately arranged first insulating layers 9 and sacrificial layers 10, as Figure 2 shown, wherein, Figure 2 is a cross-sectional view along the aa' direction after forming the stacked structure provided by an exemplary embodiment. The cross-sectional views in the bb' direction, cc' direction, and dd' direction are similar to the aa' direction and are omitted here.

[0117] The positive projections of the first insulating layer 9 and the sacrificial layer 10 overlap in the direction parallel to the substrate 1.

[0118] In some embodiments, the first insulating thin film may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2), etc.

[0119] In some embodiments, the sacrificial layer thin film may be an insulating material having an etching selectivity ratio with the first insulating thin film, including but not limited to silicon nitride (SiN).

[0120] Figure 2 The stacked structure shown in includes four first insulating layers 9 and three sacrificial layers 10, which is only an example. In other embodiments, the stacked structure may include more or fewer first insulating layers 9 and sacrificial layers 10.

[0121] 2) Form a first hole K1;

[0122] A second insulating film is deposited on the substrate 1 forming the foregoing structure to form a second insulating layer 11; the second insulating layer 11 covers the stacked structure;

[0123] The stacked structure is etched to form a plurality of first holes K1 penetrating through the stacked structure (etching stops on the substrate 1), and the aperture sizes of the first holes K1 in different layers are substantially the same, as Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D and Figure 3E shown, wherein, Figure 3A is a mask pattern used to form the first hole K1 provided for an exemplary embodiment; Figure 3B is a cross-sectional view along the aa' direction after the first hole K1 is formed, Figure 3C is a cross-sectional view along the bb' direction, Figure 3D is a cross-sectional view along the cc' direction, Figure 3E is a cross-sectional view along the dd' direction. The plurality of first holes K1 are arranged in an array in a first direction X and a second direction Y, and word lines 40 are formed in the first holes K1 subsequently.

[0124] In some embodiments, the first holes K1 can be formed by dry etching.

[0125] In some embodiments, the orthographic projection of the first hole K1 parallel to the substrate 1 can be, for example, square. However, it is not limited thereto and can be other shapes.

[0126] In some embodiments, the second insulating film can be an insulating material having an etching selectivity ratio with the first insulating film, including but not limited to silicon nitride (SiN).

[0127] 3) Form a gate insulating layer 24 and word lines 40;

[0128] A gate insulating film and a gate electrode film are sequentially deposited on the substrate 1 forming the foregoing structure, and a gate insulating layer 24 and word lines 40 are formed in the first holes K1. The gate insulating layer 24 covers the bottom wall and side walls of the first holes K1, and the word lines 40 fill the first holes K1 in which the gate insulating layer 24 is formed, as Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D shown, wherein, Figure 4A is a cross-sectional view along the aa' direction after the gate insulating layer 24 and word lines 40 are formed provided for an exemplary embodiment, Figure 4B is a cross-sectional view along the bb' direction, Figure 4C is a cross-sectional view along the cc' direction, Figure 4D is a cross-sectional view along the dd' direction.

[0129] In an exemplary embodiment of the present disclosure, the material of the gate insulating layer 24 may include one or more layers of High-K dielectric materials, such as dielectric materials with a dielectric constant K≥3.9. In some embodiments, it may include oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, it may include, but is not limited to, at least one of the following: high-K materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2).

[0130] In some embodiments, the gate electrode film may be one or more of the following different types of materials:

[0131] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing these metals mentioned above;

[0132] Or, it may be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), etc.; for example, conductive metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0133] Or, it may be doped polysilicon, silicon, germanium, silicon germanium, etc. that are conductive.

[0134] 4) Form a first trench T1;

[0135] Etch the stacked structure from the top layer to the bottom layer, remove the stacked structure located in the support area 100, and form a first trench T1; the first trench T1 extends along the second direction Y;

[0136] Laterally etch the sacrificial layer 10 by a preset length through the first trench T1, so that the first trench T1 forms a lateral groove in the sacrificial layer 10, and this lateral groove can enhance the support performance of the support layer 45 formed in the first trench T1 subsequently, as Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E shown, where, Figure 5A is the mask pattern used to form the first trench T1 provided for an exemplary embodiment; Figure 5B is the cross-sectional view along the aa' direction after forming the first trench T1, Figure 5C is the cross-sectional view along the bb' direction, Figure 5D is the cross-sectional view along the cc' direction, Figure 5E is the cross-sectional view along the dd' direction. Figure 5AIn it, the area where the substrate 1 is located is schematically shown by a dashed-line box.

[0137] 5) Form a support layer 45;

[0138] Deposit a support layer thin film in the first trench T1 to form a support layer 45, and the support layer 45 fills the first trench T1;

[0139] Grind the support layer 45 to make the support layer 45 flush with the second insulating layer 11, as shown in Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D wherein, Figure 6A is a cross-sectional view along the aa' direction after forming the support layer 45 provided for an exemplary embodiment, Figure 6B is a cross-sectional view along the bb' direction, Figure 6C is a cross-sectional view along the cc' direction, Figure 6D is a cross-sectional view along the dd' direction.

[0140] In an exemplary embodiment, the support layer thin film may be an insulating material having an etching selectivity ratio with respect to the first insulating thin film, the second insulating thin film, and the sacrificial layer thin film, such as silicon oxynitride (SiON).

[0141] The support layer 45 can provide support when forming a capacitor in a subsequent step.

[0142] 6) Form a second trench T2;

[0143] Deposit a third insulating thin film to form a third insulating layer 12, and the third insulating layer 12 covers the gate insulating layer 24, the word line 40, and the second insulating layer 11. The third insulating layer 12 can protect the word line 40 during an etching process in a subsequent step;

[0144] Etch the stacked structure from the top layer to the bottom layer to form a second trench T2 penetrating the stacked structure; as shown in Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D and Figure 7E wherein, Figure 7A is a mask pattern used to form the second trench T2 provided for an exemplary embodiment; Figure 7B is a cross-sectional view along the aa' direction after forming the second trench T2, Figure 7C is a cross-sectional view along the bb' direction, Figure 7D is a cross-sectional view along the cc' direction, Figure 7EIt is a cross-sectional view along the dd' direction. Among them, the second trench T2 extends along the second direction Y, and the second trench T2 can define the first capacitive electrode 41, that is, the area where the first capacitive electrode 41 is located is between the second trenches T2 adjacent along the second direction Y.

[0145] The side walls of the second trench T2 expose the end faces of the first insulating layer 9 and the sacrificial layer 10, and do not expose the gate insulating layer in the first hole K1. The first insulating layer 9 and the sacrificial layer 10 are divided into multiple groups by the second trench T2, and each group of the first insulating layer 9 and the sacrificial layer 10 includes upper and lower main surfaces and side walls approximately perpendicular to the substrate 1, and this side wall is the end face.

[0146] In some embodiments, the third insulating thin film may be an insulating material having an etching selectivity ratio with the first insulating thin film, including but not limited to silicon nitride (SiN).

[0147] 7) Etch the sacrificial layer 10 in the capacitive region;

[0148] Etch the sacrificial layer 10 laterally through the second trench T2 to remove the first sacrificial layer 10 located in the capacitive region, and form a first lateral groove A1, as Figure 8A , Figure 8B , Figure 8C , Figure 8D shown, where Figure 8A is a cross-sectional view along the aa' direction after etching the sacrificial layer 10 in the capacitive region provided by an exemplary embodiment, Figure 8B is a cross-sectional view along the bb' direction, Figure 8C is a cross-sectional view along the cc' direction, Figure 8D is a cross-sectional view along the dd' direction. Subsequently, the first capacitive electrode 41 can be formed in the first lateral groove A1.

[0149] 8) Form the first conductive layer 41a;

[0150] Deposit a first conductive thin film on the substrate 1 with the aforementioned structure to form the first conductive layer 41a. The first conductive layer 41a fills the second trench T2 and also fills the first lateral groove A1; as Figure 9A , Figure 9B , Figure 9C , Figure 9D shown, where Figure 9A is a cross-sectional view along the aa' direction after forming the first conductive layer 41a provided by an exemplary embodiment, Figure 9B is a cross-sectional view along the bb' direction, Figure 9C is a cross-sectional view along the cc' direction, Figure 9D is a cross-sectional view along the dd' direction. Subsequently, the first conductive layer 41a can form the first capacitive electrode 41. That is, the first conductive layer 41a includes the first capacitive electrodes 41 of multiple transistors.

[0151] In some embodiments, the first conductive thin film may be the following conductive materials:

[0152] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing these metals mentioned above;

[0153] Or, it may be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO) and other conductive metal oxide materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other conductive metal nitride materials;

[0154] Or, it may be doped polysilicon, silicon, germanium, silicon germanium, etc. that are conductive.

[0155] Subsequently, the materials of the fourth conductive thin film and the fifth conductive thin film are similar to those of the first conductive thin film, and will not be elaborated here.

[0156] 9) Form the third trench T3;

[0157] Deposit a fourth insulating thin film to form a fourth insulating layer 13, and the fourth insulating layer 13 covers the third insulating layer 12 and the first conductive layer 41a. The fourth insulating layer 13 can protect the first conductive layer 41a during the etching process in subsequent steps;

[0158] Etch the stacked structure from the top layer to the bottom layer to form a third trench T3 that penetrates the stacked structure; as shown in Figure 10A , 、, Figure 10B , 、, Figure 10C , 、, Figure 10D , and Figure 10E , where Figure 10A is the mask pattern used to form the third trench T3 provided for an exemplary embodiment; Figure 10B is the cross-sectional view along the aa' direction after forming the third trench T3, Figure 10C is the cross-sectional view along the bb' direction, Figure 10D is the cross-sectional view along the cc' direction, and Figure 10E is the cross-sectional view along the dd' direction. The third trench T3 is a part of the second trench T2. The length of the third trench T3 along the first direction X is less than the length of the second trench T2 along the first direction X, and the width of the third trench T3 along the second direction Y is the same as the width of the second trench T2 along the second direction Y. Along the second direction Y, one side wall of the third trench T3 is the support layer 45, and the other side wall is the first conductive layer 41a.

[0159] ​​​​​​​By forming the third trench T3, the first capacitive electrodes 41 of capacitors at the same position in different layers can be disconnected, and the first capacitive electrodes 41 of adjacent capacitors in the same layer can be disconnected.

[0160] In some embodiments, the fourth insulating film may be an insulating material having an etching selectivity ratio with respect to the first insulating film, including but not limited to silicon nitride (SiN).

[0161] 10) Etch the first insulating layer 9 in the capacitive region;

[0162] By laterally etching the first insulating layer 9 along the second direction Y through the third trench T3, a second lateral groove A2 is formed to expose a partial side surface of the first capacitive electrode 41, that is, the side surface whose distance from the first end face is greater than or equal to a preset distance, facilitating the subsequent formation of the dielectric layer 43 and the second capacitive electrode 42, as Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 11D shown, wherein, Figure 11A is a cross-sectional view along the aa' direction after etching the first insulating layer 9 in the capacitive region provided for an exemplary embodiment, Figure 11B is a cross-sectional view along the bb' direction, Figure 11C is a cross-sectional view along the cc' direction, Figure 11D is a cross-sectional view along the dd' direction.

[0163] 11) Form the dielectric layer 43, the second capacitive electrode 42, and the connection electrode 44;

[0164] In the substrate 1 having the above structure, a dielectric film and a conductor material are sequentially deposited to form the dielectric layer 43 and the second capacitive electrode 42, and the dielectric layer 43 wraps the exposed region of the first capacitive electrode 41; that is, the dielectric layer 43 wraps the side surface of the first capacitive electrode 41 whose distance from the first end face is greater than the preset distance. The dielectric layer 43 also covers the side wall of the first insulating layer 9 facing the support layer 45.

[0165] Deposit a second conductive film to form a connection electrode 44 that covers the second capacitive electrode 42 and fills the third trench T3 and the second lateral groove A2; the connection electrode 44 is connected to the second capacitive electrode 42, and the connection electrode 44 can be grounded, thereby realizing the grounding of the capacitor.

[0166] Etch and remove the dielectric layer 43, the second capacitive electrode 42, and the connection electrode 44 located on the side of the fourth insulating layer 13 away from the substrate, so that the connection electrode 44 is flush with the fourth insulating layer 13, as Figure 12A 、 Figure 12B 、 Figure 12C and Figure 12D shown, wherein,Figure 12A Cross-sectional view along the aa' direction after forming the dielectric layer 43 and the second capacitor electrode 42 provided for an exemplary embodiment Figure 12B Cross-sectional view along the bb' direction Figure 12C Cross-sectional view along the cc' direction Figure 12D Cross-sectional view along the dd' direction

[0167] In some embodiments, the dielectric thin film and the conductor material may be deposited by Atomic Layer Deposition (ALD).

[0168] In some embodiments, the dielectric thin film may be a High-K dielectric material, that is, a dielectric material with a dielectric constant K≥3.9. In some embodiments, it may include one or more oxides such as hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0169] In some embodiments, the conductor material includes but is not limited to at least one of the following or a combination thereof:

[0170] Metal or alloy, for example, containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc., and may be a metal alloy containing these metals mentioned above;

[0171] Or, it may be metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other metal oxide conductive materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.

[0172] In some embodiments, the second conductive thin film includes but is not limited to metal, metal alloy, polysilicon, silicon-doped conductive layer, metal oxide conductive layer, such as polysilicon-silicon germanium (Poly-SiGe), etc.

[0173] 12) Form the fourth trench T4;

[0174] Deposit a fifth insulating film to form a fifth insulating layer 14, where the fifth insulating layer 14 covers the fourth insulating layer 13, the connecting electrode 44, and the second capacitor electrode 42, and the dielectric layer 43. The fifth insulating layer 14 can protect the connecting electrode 44 and the second capacitor electrode 42 during the etching process in subsequent steps.

[0175] Etch the stacked structure from the top layer to the bottom layer to form a fourth trench T4 that penetrates the stacked structure; as Figure 13A 、 Figure 13B 、 Figure 13C 、 Figure 13D and Figure 13E shown, where Figure 13A is the mask pattern used to form the fourth trench T4 provided for an exemplary embodiment; Figure 13B is a cross-sectional view along the aa' direction after forming the fourth trench T4, Figure 13C is a cross-sectional view along the bb' direction, Figure 13D is a cross-sectional view along the cc' direction, Figure 13E is a cross-sectional view along the dd' direction. The fourth trench T4 can extend along the first direction X, and the transistor regions are located between the fourth trenches T4 adjacent to each other along the second direction Y. That is, the fourth trench T4 defines the region where the transistor is located. The sidewalls of the fourth trench T4 do not expose the gate insulating layer 24.

[0176] In some embodiments, the fifth insulating film can be an insulating material that has an etching selectivity ratio with the first insulating film, including but not limited to silicon nitride (SiN).

[0177] 13) Form a third lateral groove A3;

[0178] Etch away the film layer of the topmost first insulating layer 9 away from the substrate 1 side, and laterally etch the sacrificial layer 10 through the fourth trench T4 to expose all of the gate insulating layer 24 wrapped by the sacrificial layer 10 and the two opposite main surfaces of the two first insulating layers 9 adjacent to the sacrificial layer 10, forming a third lateral groove A3 between the first insulating layers 9. At this time, except for the sacrificial layer 10 in contact with the support layer 45, the sacrificial layer 10 in the remaining regions has been removed, as Figure 14A 、 Figure 14B 、 Figure 14C and Figure 14D shown, where Figure 14A is a cross-sectional view along the aa' direction after forming the third lateral groove A3 provided for an exemplary embodiment, Figure 14B is a cross-sectional view along the bb' direction, Figure 14C is a cross-sectional view along the cc' direction, Figure 14DIt is a cross-sectional view along the dd' direction. The third lateral groove A3 is an annular lateral groove. The horizontal extension of the annular lateral groove surrounds the exposed gate insulating layer 24 in a circle. It can be seen that in the aa' direction, the gate insulating layer 24 is formed as the bottom wall, and the bottom wall extends approximately perpendicular to the substrate, and the main surfaces (horizontally extended surfaces) of two adjacent layers of the first insulating layer 9 are used as the side walls of the groove. In the cc' direction, the first insulating layer 9 and the gate insulating layer 24 form a groove with the gate insulating layer 24 as the bottom wall and the main surfaces of two adjacent layers of the first insulating layer 9 as the side walls.

[0179] 14) Form the semiconductor layer 23 and the contact layer 25;

[0180] On the substrate 1 with the aforementioned structure formed, a semiconductor thin film and a third conductive thin film are sequentially deposited in the second trench and the annular lateral groove to form the semiconductor layer 23 and the contact layer 25, as shown in Figure 15A , Figure 15B , Figure 15C and Figure 15D shown, wherein, Figure 15A is a cross-sectional view along the aa' direction after the semiconductor layer 23 and the contact layer 25 are formed provided by an exemplary embodiment, Figure 15B is a cross-sectional view along the bb' direction, Figure 15C is a cross-sectional view along the cc' direction, Figure 15D is a cross-sectional view along the dd' direction.

[0181] Both the semiconductor layer 23 and the contact layer 25 in the annular lateral groove are annular structures. The semiconductor layer 23 and the contact layer 25 in the second trench connect the semiconductor layer 23 and the contact layer 25 between the stacked memory cells, and need to be disconnected subsequently.

[0182] The third conductive thin film can reduce the contact barrier thickness between the semiconductor layer 23 and the first electrode 51 and the second electrode 52, thereby reducing the contact resistance between the semiconductor layer 23 and the first electrode 51 and the second electrode 52, and the third conductive thin film can act as a barrier layer to prevent impurities in the first electrode 51 and the second electrode 52 from damaging the semiconductor layer 23 when the first electrode 51 and the second electrode 52 are formed subsequently. For example, when the first electrode 51 or the second electrode 52 is tungsten (W), it can prevent the fluorine element in tungsten from damaging the semiconductor layer 23.

[0183] In the exemplary embodiment of the present disclosure, the material of the semiconductor layer 23 can be silicon or polysilicon and other materials with a band gap less than 2 eV, or it can be a wide band gap material, such as a metal oxide material with a band gap greater than 2 eV.

[0184] For example, the material of the metal oxide semiconductor layer or the channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, and other materials. Of course, it is not excluded that the metal oxide contains compounds of other elements, such as elements N, Si, etc.; nor is it excluded that there are other minor doping elements.

[0185] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxide nitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc. As long as the leakage current of the transistor can meet the requirements, it can be adjusted according to the actual situation specifically.

[0186] These materials have a relatively wide bandgap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of the dynamic memory.

[0187] The above materials of the metal oxide semiconductor layer or the channel only emphasize the element type of the material, not the atomic ratio in the material and the film quality of the material.

[0188] In some embodiments, the third conductive thin film may be ITO. However, it is not limited thereto, and other materials that can reduce the barrier thickness may be used.

[0189] 15) Form the second conductive layer 30a;

[0190] Deposit a fourth conductive thin film on the substrate 1 with the aforementioned structure to form the second conductive layer 30a, as shown in Figure 16A 、 Figure 16B 、 Figure 16C and Figure 16D shown, where Figure 16AA cross-sectional view along the aa' direction after forming the second conductive layer 30a provided for an exemplary embodiment. Figure 16B A cross-sectional view along the bb' direction. Figure 16C A cross-sectional view along the cc' direction. Figure 16D A cross-sectional view along the dd' direction. The fourth conductive thin film fills the fourth trench T4 and the third lateral groove A3.

[0191] Subsequently, the second conductive layer 30a can form the bit line 30 and the first electrode 51.

[0192] 16) Expose the fourth trench T4;

[0193] Deposit a sixth insulating thin film to form a sixth insulating layer 15. The sixth insulating layer 15 covers the fourth insulating layer 13, the connection electrode 44, the second capacitor electrode 42, and the dielectric layer 43. The sixth insulating layer 15 can protect the connection electrode 44, the second capacitor electrode 42, the word line 40, etc. during the etching process in subsequent steps.

[0194] Using Figure 13A the mask shown, etch and remove the second conductive layer 30a in the fourth trench T4 to expose the fourth trench T4, as shown in Figure 17A , Figure 17B , Figure 17C and Figure 17D shown, where Figure 17A A cross-sectional view along the aa' direction after exposing the fourth trench T4 provided for an exemplary embodiment. Figure 17B A cross-sectional view along the bb' direction. Figure 17C A cross-sectional view along the cc' direction. Figure 17D A cross-sectional view along the dd' direction.

[0195] It can be seen that the first conductive layer 41a is disconnected at different layers, the second conductive layer 30a is disconnected at different layers, and the semiconductor layer 23 and the contact layer 25 at different layers are disconnected.

[0196] In some embodiments, the sixth insulating thin film can be a material having an etching selectivity ratio with the first insulating thin film, such as SiN, etc.

[0197] 17) Form a seventh insulating layer 16;

[0198] Deposit a seventh insulating thin film on the substrate 1 having the above structure to form a seventh insulating layer 16. The seventh insulating layer 16 fills the fourth trench T4. The seventh insulating layer 16 isolates the word line 40 distributed along the second direction Y, as shown in Figure 18A , Figure 18B , Figure 18C and Figure 18D shown, whereFigure 18A A cross-sectional view along the aa' direction after forming the seventh insulating layer 16 provided for an exemplary embodiment, Figure 18B is a cross-sectional view along the bb' direction, Figure 18C is a cross-sectional view along the cc' direction, Figure 18D is a cross-sectional view along the dd' direction.

[0199] In some embodiments, the seventh insulating film may be a material having an etching selectivity ratio with respect to the sixth insulating film, such as SiO2 or the like.

[0200] 18) Form the fifth trench T5 and the sixth trench T6;

[0201] Deposit an eighth insulating film to form an eighth insulating layer 17; the eighth insulating layer 17 covers the sixth insulating layer 15 and the seventh insulating layer 16;

[0202] Etch the stacked structure from the top layer to the bottom layer to form the fifth trench T5 and the sixth trench T6 passing through the stacked structure; as Figure 19A , Figure 19B , Figure 19C , 19D and Figure 19E shown, wherein, Figure 19A is a mask pattern used to form the fifth trench T5 and the sixth trench T6 provided for an exemplary embodiment; Figure 19B is a cross-sectional view along the aa' direction after forming the fifth trench T5 and the sixth trench T6, Figure 19C is a cross-sectional view along the bb' direction, Figure 19D is a cross-sectional view along the cc' direction, Figure 19E is a cross-sectional view along the dd' direction.

[0203] Along the first direction X, the fifth trench T5 and the sixth trench T6 are respectively located on both sides of the word line 40, the fifth trench T5 may be a part of the fourth trench T4, and the fifth trench T5 does not expose the dielectric layer 43. The side walls of the sixth trench T6 distributed along the first direction X do not expose the second conductive layer 30a, that is, there is a certain distance between the sixth trench T6 and the second conductive layer 30a along the first direction X.

[0204] In some embodiments, the eighth insulating film may be a material having an etching selectivity ratio with respect to the first insulating film, such as SiN or the like.

[0205] 19) Laterally etch the first conductive layer 41a and the second conductive layer 30a;

[0206] Etch the first conductive layer 41a transversely along the second direction Y through the fifth groove T5 to form a fourth transverse groove A4, where the fourth transverse groove A4 exposes the side wall of the semiconductor layer 23 facing the first capacitive electrode 41; etch the second conductive layer 30a transversely along the second direction Y through the sixth groove T6 to form a fifth transverse groove A5, where the fifth transverse groove A5 exposes a part of the contact layer 25 parallel to the substrate 1 and facing the surface of the second conductive layer 30a, as Figure 20A and Figure 20B shown, where Figure 20A FIG. Figure 20A is a cross-sectional view along the aa' direction after transversely etching the first conductive layer 41a and the second conductive layer 30a provided for an exemplary embodiment, Figure 20B and FIG. Figure 20B is a cross-sectional view along the bb' direction. Cross-sectional views in the cc' and dd' directions refer to the cross-sectional views in the corresponding directions in step 18 and are omitted here.

[0207] 20) Etch the semiconductor layer 23 and the contact layer 25;

[0208] Etch the semiconductor layer 23 and the contact layer 25 through the fourth transverse groove A4 to expose the side wall of the first electrode 51 facing away from the word line 40; etch the semiconductor layer 23 and the contact layer 25 through the fifth transverse groove A5, such that the semiconductor layers 23 of transistors adjacent along the first direction X are disconnected, the contact layers 25 of transistors adjacent along the first direction X are disconnected, and also such that the semiconductor layers 23 of transistors adjacent along the second direction Y are disconnected, and the contact layers 25 of transistors adjacent along the second direction Y are disconnected, as Figure 21A and Figure 21B shown, where Figure 21A FIG. Figure 21A is a cross-sectional view along the aa' direction after etching the semiconductor layer 23 and the contact layer 25 provided for an exemplary embodiment, Figure 21B and FIG. Figure 21B is a cross-sectional view along the bb' direction. Cross-sectional views in the cc' and dd' directions refer to the cross-sectional views in the corresponding directions in step 18 and are omitted here.

[0209] 21) Form a first connecting sub-electrode 61 and a second connecting sub-electrode 62;

[0210] Deposit a fifth conductive thin film on the substrate 1 on which the structure is formed to form a first connecting sub-electrode 61 filling the fourth transverse groove A4 and the fifth groove T5, and to form a second connecting sub-electrode 62 filling the fifth transverse groove A5 and the sixth groove T6. The first connecting sub-electrode 61 connects the first capacitive electrode 41 and the first electrode 51, and connects the first electrodes 51 of transistors adjacent along the second direction Y together; the second connecting sub-electrode 62 connects the second electrode 52 to the bit line 30 and connects bit lines 30 of different layers, as Figure 22A andFigure 22B as shown, wherein, [[ID FIG. is a cross-sectional view along the aa' direction after forming the first connection sub-electrode 61 and the second connection sub-electrode 62 provided for an exemplary embodiment, ​ FIG. is a cross-sectional view along the bb' direction. Cross-sectional views in the cc' and dd' directions refer to the cross-sectional views in the corresponding directions in step 18 and are omitted here.

[0211] 22) Expose the fifth trench T5 and the sixth trench T6;

[0212] Etch and remove the first connection sub-electrode 61 in the fifth trench T5 and the second connection sub-electrode 62 in the sixth trench T6 to expose the fifth trench T5 and the sixth trench T6, as ​ shown, wherein, ​ FIG. is a cross-sectional view along the bb' direction after exposing the fifth trench T5 and the sixth trench T6 provided for an exemplary embodiment. The cross-sectional view in the aa' direction refers to ​ , and the cross-sectional views in the cc' and dd' directions refer to the cross-sectional views in the corresponding directions in step 18 and are omitted here. In this step, the first electrodes 51 of transistors adjacent along the second direction Y can be disconnected, and the first electrodes 51 of transistors in different layers can be disconnected, and the bit lines 30 in different layers can be disconnected.

[0213] 23) Form the ninth insulating layer 18;

[0214] Deposit a ninth insulating thin film on the substrate 1 having the aforementioned structure to form the ninth insulating layer 18 filling the fifth trench T5 and the sixth trench T6, as ​ shown, ​ FIG. is a cross-sectional view along the bb' direction after forming the ninth insulating layer 18 provided for an exemplary embodiment. The cross-sectional view in the aa' direction refers to ​ , and the cross-sectional views in the cc' and dd' directions refer to the cross-sectional views in the corresponding directions in step 18 and are omitted here.

[0215] In some embodiments, the ninth insulating thin film may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxides such as silicon dioxide (SiO2), etc.

[0216] 24) Form the seventh trench T7;

[0217] Etch the stacked structure from the top layer to the bottom layer to form a plurality of seventh trenches T7 penetrating the stacked structure. The plurality of seventh trenches T7 are located between adjacent transistors. The seventh trench T7 exposes the sidewalls of the semiconductor layer 23 of the transistor facing the side of the transistor adjacent along the second direction Y, and may expose the sidewalls of the second conductive layer 30a facing the word line 40 and located between adjacent transistors, as​ , ​ and Figure 25C as shown, where Figure 25A is a photomask pattern used to form the seventh trench T7 provided for an exemplary embodiment; Figure 25B is a cross-sectional view along the bb' direction after the seventh trench T7 is formed, Figure 25C is a cross-sectional view along the cc' direction. For the cross-sectional view in the aa' direction, refer to Figure 22A , and for the cross-sectional view in the dd' direction, refer to the cross-sectional view in the corresponding direction in step 18, which is omitted here. Along the first direction X, the size of the seventh trench T7 can be greater than the size of the word line 40 along the first direction X, that is, in a plane perpendicular to the substrate 1 and parallel to the first direction X, the orthographic projection of the word line 40 falls within the orthographic projection of the seventh trench T7, so that the isolation layer 19 formed in the seventh trench T7 subsequently isolates the word lines 40 adjacent in the second direction Y. By forming the seventh trench T7, the second conductive layer 30a and the contact layer 25 in the groove formed by the semiconductor layer 23 in the cc' direction can be removed, so that the contact layer 25 connected to the first electrode 51 and the contact layer 25 connected to the second electrode 52 are disconnected, that is, the contact layer 25 forms two independent parts, one part is connected to the first electrode 51, and the other part is connected to the second electrode 52. In addition, it is convenient to form the isolation layer 19 in the seventh trench T7 to isolate the word lines 40.

[0218] The seventh trench T7 is approximately located between the word lines 40 of two transistors, and its width in the first direction X is approximately equal to the width of the word line 40. The longitudinally extending seventh trench T7 can be formed by dry etching, and then the seventh insulating layer 16, the second conductive layer 30a, and the contact layer 25 are removed by wet etching to expose the semiconductor layer 23. At this time, the contact layer 25 between the first electrode 51 and the second electrode 52 of the transistor is disconnected, avoiding short circuit between the first electrode 51 and the second electrode 52 when the contact layer 25 is a conductive material.

[0219] When the contact layer 25 is a non-conductive material, it is only necessary to ensure insulation between the first electrode 51 and the second electrode 52, and it is not necessary to remove the contact layer 25. At this time, the contact layer 25 also plays a role in protecting the semiconductor layer 23 from process effects.

[0220] 25) Form the isolation layer 19;

[0221] Deposit a tenth insulating film on the substrate 1 having the aforementioned structure to form the isolation layer 19 filling the seventh trench T7, as Figure 1C and Figure 1D shown.

[0222] In some embodiments, the isolation layer 19 may be a low-K dielectric layer, such as silicon oxyfluoride (SiOF) / silicon oxycarbide (SiOC) / amorphous carbon fluoride film (a-C:F), etc. Compared with the case where silicon dioxide is used in the seventh trench T7, the isolation layer 19 can reduce the parasitic capacitance between adjacent word lines 40 along the second direction Y. However, the embodiments of the present disclosure are not limited thereto, and the isolation layer 19 may be other low-K dielectric layers, such as silicon dioxide, etc.

[0223] Subsequently, an insulating thin film covering the previously formed memory array may be deposited to protect the memory array.

[0224] Embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including:

[0225] Providing a substrate, and sequentially and alternately depositing an insulating thin film and a sacrificial layer thin film on the substrate to form a stacked structure including alternately arranged insulating layers and sacrificial layers;

[0226] Forming holes penetrating the stacked structure in a direction perpendicular to the substrate, and forming a gate insulating layer covering the inner walls of the holes and word lines filling the holes in the holes;

[0227] Forming a plurality of first trenches penetrating the stacked structure and extending along a first direction, the plurality of first trenches being spaced apart along the first direction and a second direction, the holes being located between the first trenches adjacent along the second direction and the side walls of the first trenches not exposing the gate insulating layer, etching the sacrificial layer through the first trenches to expose an annular gate insulating layer, and simultaneously forming an annular lateral groove with adjacent insulating layers as side walls and the side walls of the gate insulating layer as bottom walls, sequentially depositing a semiconductor thin film, a contact layer thin film, and a first conductive thin film in the annular lateral groove and the first trenches, and the first conductive thin film filling the annular lateral groove, etching and removing the first conductive thin film, the contact layer thin film, and the semiconductor thin film covering the ends of the insulating layers in the first trenches, and retaining the first conductive thin film, the contact layer thin film, and the semiconductor thin film in the annular lateral groove;

[0228] Etching the first conductive thin film, the contact layer thin film, and the semiconductor thin film in the annular lateral groove to respectively form a semiconductor layer, a contact layer, a first electrode, and a second electrode, the semiconductor layer surrounding the side walls of the word lines, the semiconductor layer forming a first groove and a second groove with the opening directions facing away from the word lines, the first groove and the second groove being distributed along the first direction on the side walls of the word lines, the first electrode filling the first groove, and the second electrode filling the second groove.

[0229] In some embodiments, etching the first conductive film, the contact layer film, and the semiconductor film in the annular transverse groove includes:

[0230] forming a second trench and a third trench in the first trench that penetrate the stack structure and are distributed in the first direction and spaced from each other, performing lateral etching through the second trench to expose a side wall of the semiconductor layer disposed on the first side of the word line away from the word line, etching and removing the side wall of the semiconductor layer disposed on the first side of the word line away from the word line and the side wall of the contact layer disposed on the first side of the word line away from the word line, exposing the first electrode, and performing lateral etching through the third trench to expose a portion of the contact layer disposed on the second side of the word line that is parallel to the substrate and faces the surface of the first conductive film, etching and removing the exposed area of the contact layer and the semiconductor layer connected to the exposed area of the contact layer;

[0231] A fourth trench is formed penetrating the stacked structure, wherein the sidewall of the fourth trench distributed along the second direction exposes the semiconductor layer, and on a plane perpendicular to the substrate and parallel to the first direction, the orthographic projection of the word line falls within the orthographic projection of the fourth trench.

[0232] In some embodiments, when the first conductive film, the contact layer film, and the semiconductor film in the annular transverse groove are etched, a bit line extending along the second direction is also formed;

[0233] After etching the first conductive film, the contact layer film and the semiconductor film in the annular lateral groove, it also includes: depositing a second conductive film, etching and removing the second conductive film located in the second groove and the third groove to form a second connecting sub-electrode connected to the end face of the first electrode away from the word line, and a first connecting sub-electrode located between the second electrode and the bit line and connected to the second electrode and the bit line.

[0234] In some embodiments, the method further includes: forming an isolation layer filling the fourth trench, the isolation layer including at least one of silicon oxyfluoride, silicon oxycarbide, and a fluorinated amorphous carbon film.

[0235] The present disclosure also provides an electronic device, including the semiconductor device described in any of the above embodiments, or a semiconductor device formed by the method for manufacturing the semiconductor device described in any of the above embodiments. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0236] Although the embodiments disclosed in the present invention are as above, the content described is only the embodiments adopted for the convenience of understanding the present invention and is not intended to limit the present invention. Any person skilled in the art within the scope of the present invention may make any modifications and changes in the form of implementation and details without departing from the spirit and scope disclosed in the present invention. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A plurality of transistors, stacked along a direction perpendicular to the substrate and distributed in different layers; Word lines, extending along a direction perpendicular to the substrate and passing through the transistors in different layers; The transistor includes: a first electrode, a second electrode, a semiconductor layer, and a contact layer. The semiconductor layer surrounds the sidewall of the word line, and the semiconductor layer is disposed between the contact layer and the word line. The semiconductor layer is formed with a first groove and a second groove with an opening direction away from the word line. The first groove and the second groove are spaced apart on the sidewall of the word line. The contact layer is distributed on the bottom wall of the first groove and two sidewalls parallel to the substrate, and is distributed on the bottom wall of the second groove and two sidewalls parallel to the substrate. The first electrode fills the first groove provided with the contact layer, and the second electrode fills the second groove provided with the contact layer.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor layer and the contact layer in the first groove overlap, and the semiconductor layer and the contact layer in the second groove overlap.

3. The semiconductor device according to claim 1, wherein, The semiconductor layers of a plurality of transistors at the same position in different layers are spaced apart, and the contact layers of a plurality of transistors at the same position in different layers are spaced apart.

4. The semiconductor device according to claim 1, wherein, The first electrode is disposed in the first groove, and the second electrode is disposed in the second groove; the first electrode extends along a direction parallel to the substrate, and the second electrode extends along a direction parallel to the substrate.

5. The semiconductor device according to claim 1, wherein The word line is located in a vertical word line hole, and the cross-sectional shape and size of the word line are the same; the region of the semiconductor layer between the first electrode and the second electrode only includes the region extending along the sidewall of the word line; the region where the semiconductor layer contacts the first electrode and the second electrode includes the region extending along the sidewall of the word line and the region extending along a direction parallel to the substrate.

6. The semiconductor device according to claim 1, wherein A plurality of transistors in the same layer are arrayed in a first direction and a second direction. The semiconductor device further includes: a plurality of bit lines extending in the second direction and distributed in different layers. Each bit line is connected to the second electrodes of the transistors in the same column distributed in the second direction in the same layer through a first connecting sub-electrode.

7. The semiconductor device according to claim 6, wherein, The first connecting sub-electrode is connected to the semiconductor layer at the end face of the second groove, and is connected to the contact layer at the opening of the second groove.

8. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: a capacitor disposed on the side of the first electrode away from the word line; the capacitor includes a first capacitor electrode and a second capacitor electrode. The first capacitor electrode extends along a direction parallel to the substrate. The first capacitor electrode includes a first end face facing the word line, a second end face away from the word line, and a side surface connecting the first end face and the second end face. The second capacitor electrode wraps the side surface of the first capacitor electrode whose distance from the first end face is greater than or equal to a preset distance; the first end face of the first capacitor electrode is connected to the first electrode through a second connecting sub-electrode.

9. The semiconductor device according to claim 8, wherein, The second connecting sub-electrode is connected to the semiconductor layer at the end face of the first groove, and is connected to the contact layer at the opening of the first groove.

10. The semiconductor device according to claim 6, characterized in that, The semiconductor device also includes: an isolation layer arranged between word lines adjacent along the second direction and extending through the different layers in a direction perpendicular to the substrate, the isolation layer including at least one of silicon oxyfluoride, silicon oxycarbide, and a fluorinated amorphous carbon film, and on a plane parallel to the second direction and perpendicular to the substrate, an orthographic projection of the isolation layer overlaps with an orthographic projection of the word line.

11. The semiconductor device according to claim 10, wherein, The isolation layer is connected to the semiconductor layer distributed in the area between the first groove and the second groove on the side wall of the word line.

12. A method for manufacturing a semiconductor device, characterized in that include: Providing a substrate, on which insulating thin films and sacrificial thin films are alternately deposited in sequence to form a stacked structure including insulating layers and sacrificial layers alternately arranged; forming a hole penetrating the stacked structure in a direction perpendicular to the substrate, and forming a gate insulating layer covering an inner wall of the hole and a word line filling the hole in the hole; A plurality of first grooves are formed which penetrate the stack structure and extend along the first direction, the plurality of first grooves are spaced apart along the first direction and the second direction, the holes are located between the first grooves adjacent to each other along the second direction and the sidewalls of the first grooves do not expose the gate insulating layer, the sacrificial layer is removed by etching the first grooves to expose the annular gate insulating layer, and an annular transverse groove is formed with the adjacent insulating layer as the sidewall and the sidewall of the gate insulating layer as the bottom wall, a semiconductor film, a contact layer film and a first conductive film are sequentially deposited in the annular transverse groove and the first groove, and the first conductive film fills the annular transverse groove, the first conductive film, the contact layer film and the semiconductor film covering the ends of each insulating layer in the first groove are etched away, and the first conductive film, the contact layer film and the semiconductor film in the annular transverse groove are retained; The first conductive film, the contact layer film, and the semiconductor film in the annular lateral groove are etched to form a semiconductor layer, a contact layer, a first electrode, and a second electrode, respectively. The semiconductor layer surrounds the side wall of the word line, and the semiconductor layer forms a first groove and a second groove with an opening direction away from the word line. The first groove and the second groove are distributed along a first direction on the side wall of the word line. The first electrode fills the first groove, and the second electrode fills the second groove.

13. The manufacturing method of the semiconductor device according to claim 12, characterized in that, Etching the first conductive film, the contact layer film, and the semiconductor film in the annular transverse groove includes: forming a second trench and a third trench in the first trench that penetrate the stack structure and are distributed in the first direction and spaced from each other, performing lateral etching through the second trench to expose a side wall of the semiconductor layer disposed on the first side of the word line away from the word line, etching and removing the side wall of the semiconductor layer disposed on the first side of the word line away from the word line and the side wall of the contact layer disposed on the first side of the word line away from the word line, exposing the first electrode, and performing lateral etching through the third trench to expose a portion of the contact layer disposed on the second side of the word line that is parallel to the substrate and faces the surface of the first conductive film, etching and removing the exposed area of the contact layer and the semiconductor layer connected to the exposed area of the contact layer; A fourth trench is formed penetrating the stacked structure, wherein the sidewall of the fourth trench distributed along the second direction exposes the semiconductor layer, and on a plane perpendicular to the substrate and parallel to the first direction, the orthographic projection of the word line falls within the orthographic projection of the fourth trench.

14. The manufacturing method of the semiconductor device according to claim 13, characterized in that, When the first conductive film, the contact layer film, and the semiconductor film in the annular transverse groove are etched, a bit line extending along the second direction is also formed; After etching the first conductive film, the contact layer film and the semiconductor film in the annular lateral groove, it also includes: depositing a second conductive film, etching and removing the second conductive film located in the second groove and the third groove to form a second connecting sub-electrode connected to the end face of the first electrode away from the word line, and a first connecting sub-electrode located between the second electrode and the bit line and connected to the second electrode and the bit line.

15. The manufacturing method of the semiconductor device according to claim 14, wherein, The method further includes: forming an isolation layer filling the fourth trench, the isolation layer including at least one of silicon oxyfluoride, silicon oxycarbide, and a fluorinated amorphous carbon film.

16. An electronic device, characterized in that, A semiconductor device comprising the semiconductor device according to any one of claims 1 to 11, or a semiconductor device formed by the method for manufacturing a semiconductor device according to any one of claims 12 to 15.

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