Semiconductor device structure and preparation method thereof

Abstract

The invention relates to a semiconductor device structure and a preparation method thereof. The semiconductor device structure comprises a substrate, a stacking structure located on the substrate and at least one through hole penetrating through the stacking structure, and a word line structure and a channel layer are arranged in the through hole. Wherein the stacked structure comprises a plurality of interlayer dielectric layers which are arranged at intervals along a first direction perpendicular to the substrate; the word line structure comprises a main body part and a plurality of branch parts, and the main body part is integrally connected with each branch part; wherein the main body part extends along a first direction; the branch parts are arranged at intervals along the first direction and extend along a second direction and a third direction parallel to the substrate, and the second direction intersects with the third direction; the channel layer is located between the adjacent interlayer dielectric layers and surrounds the side wall of the word line structure. According to the semiconductor device structure, formation of a parasitic transistor can be avoided, so that the device performance can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device structure and a method for manufacturing the same. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are increasingly shrinking, and the types and quantities of devices included in a single chip are increasing accordingly. As a result, any minor differences in the process production may affect the device performance.

[0003] In the related art, metal oxide semiconductor materials are usually used as the channel materials of devices. However, metal oxide semiconductor materials are also deposited on the surfaces of the interlayer dielectric layers of each layer, which may cause the upper and lower two transistors to be interconnected through the metal oxide semiconductor materials on the surfaces of the interlayer dielectric layers, thereby forming parasitic transistors, and the parasitic transistors will cause the performance of the devices to decline. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor device structure and a method for manufacturing the same for the problem of parasitic transistors in the prior art.

[0005] In a first aspect, the present invention provides a semiconductor device structure, including:

[0006] A substrate and a stacked structure located on the substrate, at least one through hole penetrating the stacked structure, and a word line structure and a channel layer are arranged in the through hole; wherein,

[0007] The stacked structure includes multiple interlayer dielectric layers arranged at intervals in a first direction perpendicular to the substrate;

[0008] The word line structure includes a main body portion and multiple branch portions, and the main body portion is integrally connected to each branch portion; wherein, the main body portion extends in the first direction; each branch portion is arranged at intervals in the first direction, and extends in a second direction and a third direction parallel to the substrate, and the second direction intersects with the third direction;

[0009] The channel layer is located between adjacent interlayer dielectric layers and surrounds the side walls of the word line structure.

[0010] The above semiconductor device structure includes: a substrate and a stacked structure located on the substrate, at least one through hole penetrating the stacked structure, and a word line structure and a channel layer are disposed in the through hole; wherein, the stacked structure includes multiple interlayer dielectric layers arranged at intervals in a first direction perpendicular to the substrate; the word line structure includes a main body portion and multiple branch portions, and the main body portion is integrally connected to each branch portion; wherein, the main body portion extends in the first direction; each branch portion is arranged at intervals in the first direction, and extends in a second direction and a third direction parallel to the substrate, and the second direction intersects the third direction; the channel layer is located between adjacent interlayer dielectric layers and surrounds the side walls of the word line structure. Since the channel layer is disconnected between adjacent interlayer dielectric layers, that is, the channel layer does not cover the side surfaces of each interlayer dielectric layer along the third direction, parasitic transistors can be avoided, and thus the device performance can be improved.

[0011] In some embodiments, the stacked structure further includes multiple conductive layers, the conductive layers are located between adjacent interlayer dielectric layers, and the channel layer covers the surfaces of the conductive layers and is disconnected between adjacent conductive layers.

[0012] In some embodiments, each conductive layer includes:

[0013] A first extension portion extending in the second direction, and the first extension portion serves as a bit line;

[0014] Multiple second extension portions are located on opposite sides of the first extension portion along the third direction, and are located on the side of the word line structure away from the first extension portion; each second extension portion extends in the third direction, and multiple second extension portions on the same side of the first extension portion are arranged at intervals in the second direction;

[0015] The number of the through holes is multiple, and the multiple through holes are respectively located at one ends of the multiple second extension portions close to the first extension portion.

[0016] In some embodiments, the semiconductor structure further includes a capacitor, the capacitor includes a first electrode, a capacitive dielectric layer, and a second electrode, wherein, the first electrode is located between adjacent interlayer dielectric layers, the capacitive dielectric layer covers the surface of the first electrode, the second electrode covers the surface of the capacitive dielectric layer, and is in contact with one end of the second extension portion away from the first extension portion.

[0017] In some embodiments, in each conductive layer, the bit line sequentially connects the channel layers outside the multiple word line structures arranged at intervals in the second direction.

[0018] In some of these embodiments, the semiconductor device structure further includes a gate dielectric layer that is at least located between the word line structure and the channel layer.

[0019] In some of these embodiments, each of the interlayer dielectric layers and each of the conductive layers have the branch portions; the thickness of the branch portions in the interlayer dielectric layers is greater than the thickness of the branch portions in the conductive layers; the length of the branch portions in the interlayer dielectric layers is equal to the length of the branch portions in the conductive layers.

[0020] In some of these embodiments, the number of the channel layers is multiple, and each of the channel layers is arranged in one-to-one correspondence with each of the conductive layers, and the multiple channel layers are arranged at intervals along the first direction.

[0021] In a second aspect, the present invention further provides a method for manufacturing a semiconductor device structure, including:

[0022] Providing a substrate;

[0023] Forming an initial stacked structure on the substrate, the initial stacked structure including alternately stacked interlayer dielectric layers and sacrificial layers;

[0024] Forming at least one through hole penetrating the initial stacked structure;

[0025] Forming a word line structure in the through hole; wherein, the word line structure includes a main body portion and a plurality of branch portions, the main body portion is integrally connected to each of the branch portions; wherein, the main body portion extends along a first direction perpendicular to the substrate; each of the branch portions is arranged at intervals along the first direction, and extends along a second direction and a third direction parallel to the substrate, and the second direction intersects the third direction;

[0026] Removing each of the sacrificial layers to form a plurality of first trenches, the plurality of first trenches are respectively located between different adjacent interlayer dielectric layers, and are arranged at intervals along the first direction; each of the first trenches extends along the second direction;

[0027] Forming a channel layer in each of the first trenches; the channel layer surrounds the side walls of the word line structure, and each of the channel layers is arranged at intervals along the first direction.

[0028] The manufacturing method of the above semiconductor device structure includes: providing a substrate; forming an initial stacked structure on the substrate, the initial stacked structure including an interlayer dielectric layer and a sacrificial layer that are alternately stacked; forming at least one through hole penetrating the initial stacked structure; forming a word line structure in the through hole; wherein, the word line structure includes a main body portion and a plurality of branch portions, and the main body portion is integrally connected to each branch portion; wherein, the main body portion extends along a first direction perpendicular to the substrate; each branch portion is arranged at intervals along the first direction, and extends along a second direction and a third direction parallel to the substrate, and the second direction intersects the third direction; removing each layer of the sacrificial layer to form a plurality of first trenches, the plurality of first trenches are respectively located between different adjacent interlayer dielectric layers, and are arranged at intervals along the first direction; each first trench extends along the second direction; a channel layer is formed in each layer of the first trench; the channel layer surrounds the side wall of the word line structure, and each layer of the channel layer is arranged at intervals along the first direction. In the manufacturing method of the above semiconductor device structure, when forming the channel layer, the channel layer can be separated along the first direction, and no additional etching process is required to disconnect the channel layer, which can simplify the manufacturing process and improve production efficiency; at the same time, since the channel layer is disconnected between adjacent interlayer dielectric layers, that is, the channel layer does not cover the side surfaces of each interlayer dielectric layer along the third direction, parasitic transistors can be avoided, thereby improving device performance.

[0029] In some embodiments, forming the word line structure in the through hole includes:

[0030] Performing lateral etching based on the through hole to remove part of the sacrificial layer and form a second trench extending along the second direction and the third direction;

[0031] Depositing the sacrificial layer on the inner wall of the second trench to reduce the size of the second trench;

[0032] Performing lateral etching based on the through hole to remove part of the interlayer dielectric layer and form a third trench extending along the second direction and the third direction;

[0033] Sequentially depositing a gate dielectric layer and a word line material layer in the through hole, the second trench, and the third trench; wherein, the word line material layer located in the first trench serves as the main body portion, and the word line material layer located in the second trench and the third trench serves as the branch portion.

[0034] In some of these embodiments, the sacrificial layer includes a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer stacked in sequence along the first direction. The material of the first sacrificial layer is the same as that of the third sacrificial layer and different from that of the second sacrificial layer; the step of forming the word line structure in the through hole includes:

[0035] Performing lateral etching based on the through hole to respectively remove part of the second sacrificial layer and part of the interlayer dielectric layer, and respectively forming a second trench and a third trench extending along the second direction and the third direction;

[0036] Sequentially depositing a gate dielectric layer and a word line material layer in the through hole, the second trench, and the third trench; wherein, the word line material layer located in the first trench serves as the main body part, and the word line material layers located in the second trench and the third trench serve as the branch parts.

[0037] In some of these embodiments, the step of removing each layer of the sacrificial layer to form a first trench extending along the second direction between adjacent interlayer dielectric layers includes:

[0038] Forming fourth trenches on both sides of the initial stacked structure along the third direction, and the fourth trenches penetrate the initial stacked structure along the first direction;

[0039] Performing lateral etching based on the fourth trench to remove each layer of the sacrificial layer and form the first trench located between adjacent interlayer dielectric layers and extending along the second direction.

[0040] In some of these embodiments, after forming a channel layer in each layer of the first trench, the method further includes:

[0041] Forming a conductive layer in each layer of the first trench, and the multiple conductive layers and the multiple interlayer dielectric layers together constitute the stacked structure; the channel layer covers the surface of the conductive layer and is disconnected between adjacent conductive layers.

[0042] In some of these embodiments, after forming a conductive layer in each layer of the first trench, the method further includes:

[0043] Removing part of the channel layer and the conductive layer;

[0044] Sequentially depositing a second electrode material layer, a capacitor dielectric layer, and a first electrode material layer in the first trench and the fourth trench to form a capacitor; wherein, the second electrode material layer is in contact with the channel layer and the conductive layer, the first electrode material layer serves as the first electrode of the capacitor, and the second electrode material layer serves as the second electrode of the capacitor.

[0045] In some of these embodiments, each of the conductive layers includes: a first extension portion extending along the second direction, and the first extension portion serves as a bit line; a plurality of second extension portions located on opposite sides of the first extension portion along the third direction and on the side of the word line structure away from the first extension portion; each of the second extension portions extends along the third direction, and the plurality of second extension portions on the same side of the first extension portion are arranged at intervals along the second direction; after forming an initial stacked structure on the substrate and before forming at least one through hole penetrating the initial stacked structure, the method further includes:

[0046] Forming a fifth trench penetrating the initial stacked structure, and the fifth trench is located between adjacent second extension portions on the same side of the first extension portion;

[0047] Filling an insulating layer in the fifth trench. Description of the Drawings

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0049] Figure 1 It is a flowchart of a method for preparing a semiconductor device structure provided in an embodiment;

[0050] Figure 2 It is a top view structural schematic diagram of a semiconductor device structure provided in an embodiment;

[0051] Figure 3 It is a cross-sectional structural schematic diagram of a semiconductor device structure provided in an embodiment;

[0052] Figure 4 It is a cross-sectional structural schematic diagram of a semiconductor device structure provided in another embodiment;

[0053] Figure 5 It is a cross-sectional structural schematic diagram of the structure obtained in step S20 provided in an embodiment, where (a) is a schematic diagram along the Figure 3 AA' direction in the figure, (b) is a schematic diagram along the Figure 3 BB' direction in the figure, (c) is a schematic diagram along the Figure 3 CC' direction in the figure, (d) is a schematic diagram along the Figure 3 DD' direction in the figure;

[0054] Figure 6Flow chart of the step of forming an insulating layer in the manufacturing method of a semiconductor device structure provided in an embodiment;

[0055] Figure 7 Schematic cross-sectional structure diagram of the structure obtained in step S21 provided in an embodiment, where (a) is a schematic diagram along Figure 3 the AA' direction in, (b) is a schematic diagram along Figure 3 the BB' direction in, (c) is a schematic diagram along Figure 3 the CC' direction in, (d) is a schematic diagram along Figure 3 the DD' direction in;

[0056] Figure 8 Schematic cross-sectional structure diagram of the structure obtained in step S22 provided in an embodiment, where (a) is a schematic diagram along Figure 3 the AA' direction in, (b) is a schematic diagram along Figure 3 the BB' direction in, (c) is a schematic diagram along Figure 3 the CC' direction in, (d) is a schematic diagram along Figure 3 the DD' direction in;

[0057] Figure 9 Schematic cross-sectional structure diagram of the structure obtained in step S30 provided in an embodiment, where (a) is a schematic diagram along Figure 3 the AA' direction in, (b) is a schematic diagram along Figure 3 the BB' direction in, (c) is a schematic diagram along Figure 3 the CC' direction in, (d) is a schematic diagram along Figure 3 the DD' direction in;

[0058] Figure 10 Flow chart of step S40 in the manufacturing method of a semiconductor device structure provided in an embodiment;

[0059] Figure 11 Schematic cross-sectional structure diagram of the structure obtained in step S401a provided in an embodiment, where (a) is a schematic diagram along Figure 3 the AA' direction in, (b) is a schematic diagram along Figure 3 the BB' direction in, (c) is a schematic diagram along Figure 3 the CC' direction in, (d) is a schematic diagram along Figure 3 the DD' direction in;

[0060] Figure 12 Schematic cross-sectional structure diagram of the structure obtained in step S402a provided in an embodiment, where (a) is a schematic diagram along Figure 3 the AA' direction in, (b) is a schematic diagram along Figure 3 the BB' direction in, (c) is a schematic diagram alongFigure 3 Schematic diagram in the CC' direction. Diagram (d) is along Figure 3 the DD' direction in;

[0061] Figure 13 Schematic cross-sectional structure diagram of the structure obtained in step S403a in an embodiment. Among them, diagram (a) is along Figure 3 the AA' direction in, diagram (b) is along Figure 3 the BB' direction in, diagram (c) is along Figure 3 the CC' direction in, diagram (d) is along Figure 3 the DD' direction in;

[0062] Figure 14 Schematic cross-sectional structure diagram of the structure obtained in step S404a in an embodiment. Among them, diagram (a) is along Figure 3 the AA' direction in, diagram (b) is along Figure 3 the BB' direction in, diagram (c) is along Figure 3 the CC' direction in, diagram (d) is along Figure 3 the DD' direction in;

[0063] Figure 15 Schematic cross-sectional structure diagram of the structure obtained in step S50 in an embodiment. Among them, diagram (a) is along Figure 3 the AA' direction in, diagram (b) is along Figure 3 the BB' direction in, diagram (c) is along Figure 3 the CC' direction in, diagram (d) is along Figure 3 the DD' direction in;

[0064] Figure 16 Schematic cross-sectional structure diagram of the structure obtained in step S70 in an embodiment. Among them, diagram (a) is along Figure 3 the AA' direction in, diagram (b) is along Figure 3 the BB' direction in, diagram (c) is along Figure 3 the CC' direction in, diagram (d) is along Figure 3 the DD' direction in;

[0065] Figure 17 Schematic cross-sectional structure diagram of the structure obtained in step S20 in another embodiment. Among them, diagram (a) is along Figure 3 the AA' direction in, diagram (b) is along Figure 3 the BB' direction in, diagram (c) is along Figure 3 the CC' direction in, diagram (d) is along Figure 3 the DD' direction in;

[0066] Figure 18 Schematic cross-sectional structure diagrams of the structure obtained in step S21 provided in another embodiment, where (a) is a schematic diagram along the Figure 3 AA' direction in, (b) is a schematic diagram along the Figure 3 BB' direction in, (c) is a schematic diagram along the Figure 3 CC' direction in, (d) is a schematic diagram along the Figure 3 DD' direction in;

[0067] Figure 19 Schematic cross-sectional structure diagrams of the structure obtained in step S22 provided in another embodiment, where (a) is a schematic diagram along the Figure 3 AA' direction in, (b) is a schematic diagram along the Figure 3 BB' direction in, (c) is a schematic diagram along the Figure 3 CC' direction in, (d) is a schematic diagram along the Figure 3 DD' direction in;

[0068] Figure 20 Schematic cross-sectional structure diagrams of the structure obtained in step S30 provided in another embodiment, where (a) is a schematic diagram along the Figure 3 AA' direction in, (b) is a schematic diagram along the Figure 3 BB' direction in, (c) is a schematic diagram along the Figure 3 CC' direction in, (d) is a schematic diagram along the Figure 3 DD' direction in;

[0069] Figure 21 Flowchart of step S40 in the method for preparing a semiconductor device structure provided in another embodiment;

[0070] Figure 22 Schematic cross-sectional structure diagrams of the structure obtained in step S401b provided in another embodiment, where (a) is a schematic diagram along the Figure 3 AA' direction in, (b) is a schematic diagram along the Figure 3 BB' direction in, (c) is a schematic diagram along the Figure 3 CC' direction in, (d) is a schematic diagram along the Figure 3 DD' direction in;

[0071] Figure 23 Schematic cross-sectional structure diagrams of the structure obtained in step S402b provided in another embodiment, where (a) is a schematic diagram along the Figure 3 AA' direction in, (b) is a schematic diagram along the Figure 3 BB' direction in, (c) is a schematic diagram along the Figure 3 CC' direction in, (d) is a schematic diagram along theFigure 3 Schematic diagram in the DD' direction in China

[0072] Figure 24 Schematic cross-sectional structure diagram of the structure obtained in step S50 provided in another embodiment, where (a) is a schematic diagram along Figure 3 the AA' direction in China, (b) is a schematic diagram along Figure 3 the BB' direction in China, (c) is a schematic diagram along Figure 3 the CC' direction in China, (d) is a schematic diagram along Figure 3 the DD' direction in China;

[0073] Figure 25 Schematic cross-sectional structure diagram of the structure obtained in step S70 provided in another embodiment, where (a) is a schematic diagram along Figure 3 the AA' direction in China, (b) is a schematic diagram along Figure 3 the BB' direction in China, (c) is a schematic diagram along Figure 3 the CC' direction in China, (d) is a schematic diagram along Figure 3 the DD' direction in China;

[0074] Figure 26 Flowchart of the preparation method of the semiconductor device structure provided in another embodiment;

[0075] Figure 27 Schematic cross-sectional structure diagram of the structure obtained in step S80 provided in an embodiment, where (a) is a schematic diagram along Figure 3 the AA' direction in China, (b) is a schematic diagram along Figure 3 the BB' direction in China, (c) is a schematic diagram along Figure 3 the CC' direction in China, (d) is a schematic diagram along Figure 3 the DD' direction in China;

[0076] Figure 28 Schematic cross-sectional structure diagram of the structure obtained in step S90 provided in an embodiment, where (a) is a schematic diagram along Figure 3 the AA' direction in China, (b) is a schematic diagram along Figure 3 the BB' direction in China, (c) is a schematic diagram along Figure 3 the CC' direction in China, (d) is a schematic diagram along Figure 3 the DD' direction in China.

[0077] Figure 29 Schematic cross-sectional structure diagram of the structure obtained in step S80 provided in another embodiment, where (a) is a schematic diagram along Figure 3 the AA' direction in China, (b) is a schematic diagram along Figure 3 the BB' direction in China, (c) is a schematic diagram along Figure 3Schematic diagram in the CC' direction. Diagram (d) is along Figure 3 the schematic diagram in the DD' direction;

[0078] Figure 30 It is a schematic cross-sectional structure diagram of the structure obtained in step S90 provided in another embodiment. Among them, diagram (a) is along Figure 3 the schematic diagram in the AA' direction, diagram (b) is along Figure 3 the schematic diagram in the BB' direction, diagram (c) is along Figure 3 the schematic diagram in the CC' direction, and diagram (d) is along Figure 3 the schematic diagram in the DD' direction.

[0079] Explanation of reference numerals: 10 - substrate, 11 - via hole, 101 - first groove, 102 - second groove, 103 - third groove, 104 - fourth groove, 105 - fifth groove, 20 - interlayer dielectric layer, 30 - sacrificial layer, 301 - first sacrificial layer, 302 - second sacrificial layer, 303 - third sacrificial layer, 40 - insulating layer, 50 - gate dielectric layer, 60 - word line structure, 601 - main body part, 602 - branch part, 70 - channel layer, 80 - conductive layer, 801 - first extension part, 802 - second extension part, 90 - capacitor, 901 - first electrode material layer, 902 - capacitive dielectric layer, 903 - second electrode material layer. Detailed implementation manners

[0080] For the convenience of understanding the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0081] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0082] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be denoted as the second element, component, region, layer, or portion; for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0083] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0084] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / including" etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0085] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of preferred embodiments (and intermediate structures) of the invention, so that variations in the shapes shown, for example due to manufacturing techniques and / or tolerances, can be expected. Thus, embodiments of the invention should not be limited to the specific shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the invention.

[0086] Please refer to Figure 1 , the present invention provides a method for preparing a semiconductor device structure, comprising the following steps:

[0087] S10: Provide a substrate;

[0088] S20: Form an initial stacked structure on the substrate, the initial stacked structure comprising alternately stacked interlayer dielectric layers and sacrificial layers;

[0089] S30: Form at least one through hole penetrating the initial stacked structure;

[0090] S40: Form a word line structure in the through hole; wherein, the word line structure comprises a main body portion and a plurality of branch portions, the main body portion is integrally connected to each branch portion; wherein, the main body portion extends along a first direction perpendicular to the substrate; each branch portion is arranged at intervals along the first direction, and extends along a second direction and a third direction parallel to the substrate, the second direction intersects with the third direction;

[0091] S50: Remove each sacrificial layer to form a plurality of first trenches, the plurality of first trenches are respectively located between different adjacent interlayer dielectric layers, and are arranged at intervals along the first direction; each first trench extends along the second direction;

[0092] S60: Form a channel layer in each first trench; the channel layer surrounds the sidewalls of the word line structure, and each layer of channel layer is arranged at intervals along the first direction.

[0093] Wherein, the semiconductor structure obtained after steps S10 - S60 can be referred to Figures 2 - 3 . Of course, Figures 2 - 3 What is given is an example of a semiconductor structure prepared by using the method for preparing a semiconductor structure of the present invention. There can be other suitable examples of semiconductor structures prepared by using the method for preparing a semiconductor structure of the present invention, and the present invention does not make any limitations herein.

[0094] In addition, in order to show the specific structures of the conductive layers and the positions of the word line structures corresponding to them in the conductive layers, some structural layers (such as the channel layer, insulating layer, etc.) are omitted in the top view of Figure 2 . It should be noted that the actual structure of the semiconductor device structure shall be based on the cross-sectional view in Figure 3 . In addition, it should be noted that the cross-sectional views involved in the present invention (such as Figure 2 , Figure 5 , Figure 6 , etc.) are all intercepted based on the intercepting lines AA’, BB’, CC’ and DD’ in Figure 3 , but it does not mean that the structure of the top view corresponding to this cross-sectional view must be the structure shown in Figure 3 . Here, it is only for the convenience of illustration.

[0095] In addition, for the convenience of understanding the present solution, the first direction involved in the present invention may be the direction perpendicular to the substrate (such as the vertical direction in Figure 3 ), the second direction may be the extending direction of the intercepting line CC’ or DD’ in Figure 3 , and the third direction may be the extending direction of the intercepting line AA’ or BB’ in the top view. Of course, in other suitable application scenarios, the first direction, the second direction and the third direction may also have other definitions, which are not limited in the present invention.

[0096] The method for manufacturing the above semiconductor device structure includes: providing a substrate; forming an initial stacked structure on the substrate, the initial stacked structure including an interlayer dielectric layer and a sacrificial layer stacked alternately; forming at least one through hole penetrating the initial stacked structure; forming a word line structure in the through hole; wherein, the word line structure includes a main body portion and a plurality of branch portions, and the main body portion is integrally connected to each branch portion; wherein, the main body portion extends along a first direction perpendicular to the substrate; each branch portion is arranged at intervals along the first direction and extends along a second direction and a third direction parallel to the substrate, and the second direction intersects with the third direction; removing each sacrificial layer to form a plurality of first trenches, the plurality of first trenches are respectively located between different adjacent interlayer dielectric layers and are arranged at intervals along the first direction; each first trench extends along the second direction; forming a channel layer in each first trench; the channel layer surrounds the side walls of the word line structure, and the channel layers of each layer are arranged at intervals along the first direction. In the method for manufacturing the above semiconductor device structure, the channel layer can be separated along the first direction when forming the channel layer, and no additional etching process is required to disconnect the channel layer, which can simplify the manufacturing process and improve production efficiency; at the same time, since the channel layer is disconnected between adjacent interlayer dielectric layers, that is, the channel layer does not cover the side surfaces of each interlayer dielectric layer along the third direction, parasitic transistors can be avoided, thereby improving device performance.

[0097] In addition, since the word line structure includes a main body portion and a plurality of branch portions, and the branch portions extend along the second direction and the third direction, and since the channel layer covers the side walls of the word line structure, the contact area between the channel layer and the word line structure can be increased, thereby reducing the contact resistance and improving the gate control ability of the gate at the same time.

[0098] Furthermore, the method for manufacturing a semiconductor device of the present invention can avoid the problem that the inner cleaning method in the related art causes great damage to the channel layer. And this manufacturing method does not introduce the side etching process of the conductive layer in the related art, thereby effectively avoiding the problem of poor morphology of the conductive layer after side etching, and making the morphologies of the channel and the gate more excellent.

[0099] In step S10, as Figure 5 shown, a substrate 10 is provided.

[0100] Among them, the material of the substrate 10 can be any suitable substrate material known in the art, for example, at least one of the materials mentioned below: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, and also includes multi-layer structures composed of these semiconductors, etc., or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or can also be double-sided polished wafers (DSP), and can also be a ceramic substrate such as alumina, a quartz or glass substrate, etc. This embodiment is not limited here.

[0101] Two implementation manners for implementing steps S20 to S40 are provided in the present invention, and the difference lies in the different structures of the sacrificial layer 30. As Figures 5 - 14 shown, in some embodiments, the sacrificial layer 30 is a single-layer structure. As Figures 17 - 23 shown, in other embodiments, the sacrificial layer 30 includes a first sacrificial layer 301, a second sacrificial layer 302, and a third sacrificial layer 303 stacked in sequence along the first direction. Among them, the materials of the first sacrificial layer 301 and the third sacrificial layer 303 are the same and different from the material of the second sacrificial layer 302. The steps S20 to S40 will be described below based on these two types of embodiments.

[0102] In some embodiments, steps S20 to S40 are described based on the sacrificial layer 30 being a single-layer structure:

[0103] In step S20, as Figure 5As shown, an initial stack structure is formed on a substrate 10, and the initial stack structure includes alternately stacked interlayer dielectric layers 20 and sacrificial layers 30.

[0104] Among them, the material of the interlayer dielectric layer 20 may include one or a combination of silicon oxide, silicon oxynitride, silicon carbon oxide, and silicon carbon oxynitride. The material of the sacrificial layer 30 may include one or a combination of Carbon and silicon nitride. The material of the interlayer dielectric layer 20 may be different from the material of the sacrificial layer 30.

[0105] On the basis of the above embodiments, as Figure 6 shown, after step S20 and before step S30, the method for fabricating a semiconductor device structure further includes:

[0106] S21: Form a fifth trench 105 penetrating the initial stack structure, as Figure 7 shown.

[0107] S22: Fill the fifth trench 105 with an insulating layer 40, as Figure 8 shown.

[0108] Among them, the insulating layer 40 is used to play a supporting role. The material of the insulating layer 40 can be selected to have an etching rate different from that of the sacrificial layer 30 and the interlayer dielectric layer 20. For example, the material of the insulating layer 40 may include aluminum oxide.

[0109] Optionally, before depositing the insulating layer 40, a thin layer of silicon nitride may be deposited in the fifth trench 105.

[0110] On the basis of the above embodiments, in step S30, as Figure 9 shown, form at least one via 11 penetrating the initial stack structure.

[0111] On the basis of the above embodiments, in step S40, as Figure 14 shown, form a word line structure 60 in the via 11.

[0112] Among them, the word line structure 60 includes a main body portion 601 and a plurality of branch portions 602, and the main body portion 601 is integrally connected to each branch portion 602; wherein, the main body portion 601 extends along a first direction perpendicular to the substrate 10; each branch portion 602 is arranged at intervals along the first direction and extends along a second direction and a third direction parallel to the substrate 10, and the second direction intersects the third direction.

[0113] On the basis of the above embodiments, in some embodiments, as Figure 10 shown, the above step S40 includes:

[0114] S401a: Perform lateral etching based on the through-hole 11 to remove part of the sacrificial layer 30, and form a second trench 102 extending in the second direction and the third direction.

[0115] As Figure 11 shown, wet etching or vapor etching can be used to perform lateral etching based on the through-hole 11. During the lateral etching process, since the materials of the sacrificial layer 30 and the interlayer dielectric layer 20 are different, part of the sacrificial layer 30 can be selectively removed, thereby forming the second trench 102.

[0116] S402a: Deposit the sacrificial layer 30 on the inner wall of the second trench 102 to reduce the size of the second trench 102.

[0117] As Figure 12 shown, optionally, an atomic layer deposition process can be used to deposit the sacrificial layer 30 on the inner walls of the through-hole 11 and the second trench 102, and then remove the sacrificial layer 30 located on the sidewall of the through-hole 11 and covering the side surface of the interlayer dielectric layer 20, so as to obtain the sacrificial layer 30 remaining on the inner wall of the second trench 102. Among them, the process of removing the sacrificial layer 30 located on the sidewall of the through-hole 11 and covering the side surface of the interlayer dielectric layer 20 may include punch etch.

[0118] S403a: Perform lateral etching based on the through-hole 11 to remove part of the interlayer dielectric layer 20, and form a third trench 103 extending in the second direction and the third direction.

[0119] As Figure 13 shown, wet etching or vapor etching can be used to perform lateral etching based on the through-hole 11. During the lateral etching process, since the materials of the interlayer dielectric layer 20 and the sacrificial layer 30 are different, part of the interlayer dielectric layer 20 can be selectively removed, thereby forming the third trench 103.

[0120] S404a: Deposit a gate dielectric layer 50 and a word line material layer in sequence in the through-hole 11, the second trench 102, and the third trench 103; wherein, the word line material layer located in the first trench 101 serves as the main body portion 601, and the word line material layers located in the second trench 102 and the third trench 103 serve as the branch portions 602.

[0121] As Figure 14 shown, an atomic layer deposition process can be used to deposit the gate dielectric layer 50 and the word line material layer in sequence.

[0122] Among them, the material of the gate dielectric layer 50 may include high-K materials. The material of the word line material layer may include metals such as tungsten, copper, gold, titanium, silver, and aluminum, may also include multi-layer metals composed of the above-mentioned metals, and may also include titanium nitride, etc. This embodiment does not limit this here.

[0123] Optionally, before depositing the gate dielectric layer 50, a thin layer of silicon oxide may be deposited first in the vias 11, the second trench 102, and the third trench 103, so that the surface of the gate dielectric layer 50 is covered with a thin layer of silicon oxide.

[0124] Thus, in the case where the sacrificial layer 30 is a single-layer structure, by adopting the steps as Figures 5 - 14 exemplified, a word line structure 60 including a main body portion 601 and a plurality of branch portions 602 can be formed.

[0125] In step S50, as Figure 15 shown, each layer of the sacrificial layer 30 is removed to form a plurality of first trenches 101. The plurality of first trenches 101 are respectively located between different adjacent interlayer dielectric layers 20 and are arranged at intervals along the first direction; each first trench 101 extends along the second direction.

[0126] Among them, each layer of the sacrificial layer 30 can be removed by a wet etching process. It can be understood that the sacrificial layer 30 will be completely removed in step S50.

[0127] In step S60, as Figure 16 shown, a channel layer 70 is formed in each of the first trenches 101; the channel layer 70 surrounds the side walls of the word line structure 60, and the channel layers 70 of each layer are arranged at intervals along the first direction.

[0128] Among them, the material of the channel layer 70 may include a metal oxide semiconductor material. For example, it may be indium gallium zinc oxide (IGZO). When the metal oxide semiconductor material is IGZO, the leakage current of the transistor is small (the leakage current is not greater than or equal to 10-15 A), thereby ensuring the low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide semiconductor material may also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements, and it can be adjusted according to the actual situation specifically.

[0129] Optionally, an atomic layer deposition process may be employed to form a channel layer 70 on the inner walls of the fourth trench 104 and the first trench 101, and then the channel layer 70 on the inner wall of the fourth trench 104 is removed, such that the channel layer 70 surrounds the sidewalls of the word line structure 60, and the channel layers 70 are arranged at intervals along the first direction.

[0130] As Figure 16 shown, it can be found that the channel layer 70 only covers the inner wall of the first trench 101 and is disconnected between adjacent interlayer dielectric layers 20, that is, the channel layer 70 does not cover the side surfaces of the interlayer dielectric layers 20 along the third direction, thereby being able to avoid forming parasitic transistors and improving device performance.

[0131] In some other embodiments, based on the sacrificial layer 30 including a first sacrificial layer 301, a second sacrificial layer 302, and a third sacrificial layer 303, steps S20 to S40 are described as follows:

[0132] In step S20, as Figure 17 shown, an initial stacked structure is formed on the substrate 10, and the initial stacked structure includes alternately stacked interlayer dielectric layers 20 and sacrificial layers 30.

[0133] Among them, the sacrificial layer 30 includes a first sacrificial layer 301, a second sacrificial layer 302, and a third sacrificial layer 303. The material of the first sacrificial layer 301 may be the same as that of the third sacrificial layer 303 and different from that of the second sacrificial layer 302. For example, the materials of the first sacrificial layer 301 and the third sacrificial layer 303 may include silicon nitride, and the material of the second sacrificial layer 302 may include Carbon.

[0134] After step S20 and before step S30, as Figure 6 shown, the manufacturing method of the semiconductor device may further include:

[0135] S21: Form a fifth trench 105 penetrating the initial stacked structure, as Figure 18 shown.

[0136] S22: Fill the fifth trench 105 with an insulating layer 40, as Figure 19 shown.

[0137] Among them, the insulating layer 40 is used to play a supporting role. The material of the insulating layer 40 may be selected to be different from the etching rates of the sacrificial layer 30 and the interlayer dielectric layer 20. For example, the material of the insulating layer 40 may include alumina.

[0138] Optionally, before depositing the insulating layer 40, a thin layer of silicon nitride may also be deposited in the fifth trench 105.

[0139] In step S30, as Figure 20As shown, at least one via hole 11 penetrating the initial stacked structure is formed.

[0140] In step S40, as Figure 23 shown, a word line structure 60 is formed within the via hole 11.

[0141] Among them, the word line structure 60 includes a main body portion 601 and a plurality of branch portions 602, and the main body portion 601 is integrally connected to each branch portion 602; among them, the main body portion 601 extends along a first direction perpendicular to the substrate 10; each branch portion 602 is arranged at intervals along the first direction, and extends along a second direction and a third direction parallel to the substrate 10, and the second direction intersects the third direction.

[0142] Based on the above embodiments, as Figure 21 shown, the above step S40 includes:

[0143] S401b: Perform lateral etching based on the via hole 11 to respectively remove part of the second sacrificial layer 302 and part of the interlayer dielectric layer 20, and respectively form a second trench 102 and a third trench 103 extending along the second direction and the third direction.

[0144] As Figure 22 shown. Optionally, a wet or vapor etching process can be first used to perform lateral etching to remove part of the interlayer dielectric layer 20, and then a wet or vapor etching process can be used to remove part of the second sacrificial layer 302; or, a wet or vapor etching process can be first used to perform lateral etching to remove part of the second sacrificial layer 302, and then a wet or vapor etching process can be used to remove part of the interlayer dielectric layer 20 to form the second trench 102 and the third trench 103.

[0145] S402b: Sequentially deposit a gate dielectric layer 50 and a word line material layer within the via hole 11, the second trench 102, and the third trench 103; among them, the word line material layer located within the first trench 101 serves as the main body portion 601, and the word line material layer located within the second trench 102 and the third trench 103 serves as the branch portion 602.

[0146] As Figure 23 shown, an atomic layer deposition process can be used to sequentially deposit the gate dielectric layer 50 and the word line material layer.

[0147] Among them, the material of the gate dielectric layer 50 can include a high-K material. The material of the word line material layer can include metals such as tungsten, copper, gold, titanium, silver, aluminum, etc., can also include a multi-layer metal composed of the above-mentioned metals, and can also include titanium nitride, etc., and this embodiment does not make any restrictions here.

[0148] Optionally, before depositing the gate dielectric layer 50 , a thinner layer of silicon oxide may be deposited in the through hole 11 , the second trench 102 , and the third trench 103 , so that the surface of the gate dielectric layer 50 is covered with a thinner layer of silicon oxide.

[0149] Therefore, when the sacrificial layer 30 includes a first sacrificial layer 301, a second sacrificial layer 302, and a third sacrificial layer 303, the sacrificial layer 301 is used as follows: Figures 17 - 23 In the exemplary steps, a word line structure 60 including a main body 601 and a plurality of branch parts 602 may be formed.

[0150] In step S50, if Figure 24 As shown, each sacrificial layer 30 is removed to form a plurality of first trenches 101 , which are respectively located between different adjacent interlayer dielectric layers 20 and arranged at intervals along the first direction; each first trench 101 extends along the second direction.

[0151] The sacrificial layers 30 can be removed by wet etching. It is understood that the sacrificial layers 30 will be completely removed in step S50. Therefore, no matter whether the sacrificial layer 30 is a multi-layer structure or a single-layer structure, the structure obtained after removing the sacrificial layer 30 in step S50 will be the same. Figure 24 Just give an example.

[0152] In some embodiments, the above step S50 includes:

[0153] S501: forming fourth grooves 104 on both sides of the initial stacking structure along the third direction, wherein the fourth grooves 104 penetrate the initial stacking structure along the first direction. Figure 24 shown.

[0154] The position of the fourth groove 104 is as follows: Figure 24 As shown in the dotted box in FIG. 1 , that is, vertical etching can be performed along a first direction perpendicular to the substrate 10 based on the initial stacking structure to form a fourth trench 104. The fourth trench 104 is to expose the sacrificial layer 30 while minimizing the impact on the core device structure.

[0155] S502: performing lateral etching based on the fourth trench 104 to remove each sacrificial layer 30, and forming a first trench 101 located between adjacent interlayer dielectric layers 20 and extending along the second direction, such as Figure 24 shown.

[0156] In step S60, if Figure 25 As shown, a channel layer 70 is formed in each layer of the first trench 101 ; the channel layer 70 surrounds the sidewall of the word line structure 60 , and each layer of the channel layer 70 is arranged at intervals along the first direction.

[0157] Among them, the material of the channel layer 70 may include a metal oxide semiconductor material, for example, it may be indium gallium zinc oxide (IGZO). When the metal oxide semiconductor material is IGZO, the leakage current of the transistor is small (the leakage current is not greater than or equal to 10-15A), thereby ensuring the low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide semiconductor material may also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements, and specific adjustments can be made according to the actual situation.

[0158] Optionally, an atomic layer deposition process may be used to form the channel layer 70 on the inner walls of the fourth trench 104 and the first trench 101, and then the channel layer 70 on the inner wall of the fourth trench 104 is removed, so that the channel layer 70 surrounds the side walls of the word line structure 60, and the channel layers 70 of each layer are arranged at intervals along the first direction.

[0159] As Figure 25 shown, it can be found that the channel layer 70 only covers the inner wall of the first trench 101 and is disconnected between adjacent interlayer dielectric layers 20, that is, the channel layer 70 does not cover the side surfaces of each interlayer dielectric layer 20 along the third direction, thereby avoiding the formation of parasitic transistors and improving the device performance.

[0160] In some embodiments, as Figure 16 、 Figure 25 and Figure 26 shown, after step S60, the method for preparing the semiconductor device structure further includes:

[0161] S70: A conductive layer 80 is formed in each layer of the first trench 101, and the multi-layer conductive layer 80 and the multi-layer interlayer dielectric layer 20 together form a stacked structure; the channel layer 70 covers the surface of the conductive layer 80 and is disconnected between adjacent conductive layers 80.

[0162] Among them, the material of the conductive layer 80 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals, or may also include ITO.

[0163] In addition, as Figure 2 shown, from the top view, each conductive layer 80 may include: a first extension portion 801 extending along the second direction, and the first extension portion 801 serves as a bit line; a plurality of second extension portions 802 located on opposite sides of the first extension portion 801 along the third direction, and on the side of the word line structure 60 away from the first extension portion 801; each second extension portion 802 extends along the third direction, and a plurality of second extension portions 802 on the same side of the first extension portion 801 are arranged at intervals along the second direction. According to Figure 2 , Figure 3 and Figure 7 it can be known that the fifth groove 105 is located between adjacent second extension portions 802 on the same side of the first extension portion 801.

[0164] In one example, as Figure 16 shown, the end face shape of the first extension portion 801 in each conductive layer 80 is rectangular, that is, the end face shapes of the bit lines are all rectangular.

[0165] In another example, as Figure 25 shown, grooves (not labeled) are formed on opposite sides of the first extension portion 801 in each conductive layer 80, that is, grooves are formed on opposite sides of the bit lines; the channel layer 70, the gate dielectric layer 50, and a part of the branch portion 602 are also located in the grooves.

[0166] Among them, the number of the through holes 11 is multiple, and the multiple through holes 11 are respectively located at one end of the plurality of second extension portions 802 close to the first extension portion 801. And, from Figure 25 combination with Figure 2 it can be seen that the other end of the second extension portion 802 away from the first extension portion 801 is the position corresponding to the first groove 101.

[0167] As an example, in each conductive layer 80, the bit lines serially connect the channel layers 70 surrounding the plurality of word line structures 60 arranged at intervals along the second direction in sequence.

[0168] As an example, branch portions 602 are provided in each interlayer dielectric layer 20 and each conductive layer 80; the thickness of the branch portion 602 in the interlayer dielectric layer 20 is greater than the thickness of the branch portion 602 in the conductive layer 80; the length of the branch portion 602 in the interlayer dielectric layer 20 is equal to the length of the branch portion 602 in the conductive layer 80.

[0169] As an example, the number of the channel layers 70 is multiple, each layer of the channel layer 70 is arranged in one-to-one correspondence with each layer of the conductive layer 80, and the multiple channel layers 70 are arranged at intervals in the first direction.

[0170] Based on the above embodiments, in some embodiments, as Figure 26 shown, the method for manufacturing the semiconductor device structure further includes:

[0171] S80: Removing a part of the channel layer 70 and the conductive layer 80, as Figure 27 and Figure 29 shown, Figure 27 and Figure 29 are respectively cross-sectional structure schematic diagrams of the structures obtained in step S80 in two different embodiments.

[0172] S90: Sequentially depositing a second electrode material layer 903, a capacitive dielectric layer 902, and a first electrode material layer 901 in the first trench 101 and the fourth trench 104 to form a capacitor 90, as Figure 28 and Figure 30 shown, Figure 28 and Figure 30 are respectively cross-sectional structure schematic diagrams of the structures obtained in step S90 in two different embodiments.

[0173] Wherein, the second electrode material layer 903 is in contact with the channel layer 70 and the conductive layer 80, the first electrode material layer 901 serves as the first electrode of the capacitor 90, and the second electrode material layer 903 serves as the second electrode of the capacitor 90.

[0174] Wherein, the atomic layer deposition process can be used to sequentially deposit the second electrode material layer 903, the capacitive dielectric layer 902, and the first electrode material layer 901. The materials of the first electrode material layer 901 and the second electrode material layer 903 can include low-temperature metals, and the material of the capacitive dielectric layer 902 can include high-K materials.

[0175] The present invention also provides a semiconductor device structure, as Figures 2 - 4 shown, the semiconductor device structure includes: a substrate 10 and a stacked structure located on the substrate 10, at least one through hole 11 penetrating the stacked structure, and a word line structure 60 and a channel layer 70 are arranged in the through hole 11;

[0176] Among them, the stacked structure includes multiple interlayer dielectric layers 20 arranged at intervals in a first direction perpendicular to the substrate 10. The word line structure 60 includes a main body portion 601 and a plurality of branch portions 602, and the main body portion 601 is integrally connected to each branch portion 602; among them, the main body portion 601 extends in the first direction; each branch portion 602 is arranged at intervals in the first direction and extends in a second direction and a third direction parallel to the substrate 10, and the second direction intersects the third direction. The channel layer 70 is located between adjacent interlayer dielectric layers 20 and surrounds the side walls of the word line structure 60.

[0177] The above semiconductor device structure includes a substrate 10 and a stacked structure located on the substrate 10, at least one via hole 11 penetrating the stacked structure, and a word line structure 60 and a channel layer 70 are arranged in the via hole 11; among them, the stacked structure includes multiple interlayer dielectric layers 20 arranged at intervals in a first direction perpendicular to the substrate 10; the word line structure 60 includes a main body portion 601 and a plurality of branch portions 602, and the main body portion 601 is integrally connected to each branch portion 602; among them, the main body portion 601 extends in the first direction; each branch portion 602 is arranged at intervals in the first direction and extends in a second direction and a third direction parallel to the substrate 10, and the second direction intersects the third direction; the channel layer 70 is located between adjacent interlayer dielectric layers 20 and surrounds the side walls of the word line structure 60. Since the channel layer 70 is disconnected between adjacent interlayer dielectric layers 20, that is, the channel layer 70 does not cover the side surfaces of each interlayer dielectric layer 20 in the third direction, parasitic transistors can be avoided, and thus the device performance can be improved.

[0178] In addition, since the word line structure 60 includes the main body portion 601 and a plurality of branch portions 602, and the branch portions 602 extend in the second direction and the third direction, and since the channel layer 70 covers the side walls of the word line structure 60, the contact area between the channel layer 70 and the word line structure 60 can be increased, thereby reducing the contact resistance and improving the gate control ability of the gate at the same time.

[0179] In some embodiments, as Figure 3 shown, the stacked structure further includes multiple conductive layers 80, the conductive layers 80 are located between adjacent interlayer dielectric layers 20, and the channel layer 70 covers the surfaces of the conductive layers 80 and is disconnected between adjacent conductive layers 80.

[0180] In some embodiments, as Figure 3As shown, each conductive layer 80 includes: a first extension portion 801 extending in the second direction, and the first extension portion 801 serves as a bit line; a plurality of second extension portions 802 located on opposite sides of the first extension portion 801 in the third direction and on the side of the word line structure 60 away from the first extension portion 801; each second extension portion 802 extends in the third direction, and the plurality of second extension portions 802 on the same side of the first extension portion 801 are arranged at intervals in the second direction. The number of the through holes 11 is plural, and the plural through holes 11 are respectively located at one ends of the plurality of second extension portions 802 close to the first extension portion 801.

[0181] As an example, in each conductive layer 80, the bit lines serially connect the channel layers 70 surrounding the plurality of word line structures 60 arranged at intervals in the second direction in sequence.

[0182] As an example, each interlayer dielectric layer 20 and each conductive layer 80 have branch portions 602; the thickness of the branch portions 602 in the interlayer dielectric layer 20 is greater than the thickness of the branch portions 602 in the conductive layer 80; the length of the branch portions 602 in the interlayer dielectric layer 20 is equal to the length of the branch portions 602 in the conductive layer 80.

[0183] As an example, the number of the channel layers 70 is plural, each layer of channel layer 70 is arranged corresponding to each layer of conductive layer 80 one by one, and the plural channel layers 70 are arranged at intervals in the first direction.

[0184] In one example, as Figure 3 shown, the end face shapes of the first extension portions 801 in each conductive layer 80 are all rectangular, that is, the end face shapes of the bit lines are all rectangular.

[0185] In another example, as Figure 4 shown, grooves (not marked) are formed on opposite sides of the first extension portion 801 in each conductive layer 80, that is, grooves are formed on opposite sides of the bit lines; the channel layer 70, the gate dielectric layer 50 and part of the branch portions 602 are also located in the grooves.

[0186] In some embodiments, as Figure 3 and Figure 4 shown, the semiconductor structure further includes a capacitor 90, and the capacitor 90 includes a first electrode, a capacitive dielectric layer 902 and a second electrode. Wherein, the first electrode is located between adjacent interlayer dielectric layers 20, the capacitive dielectric layer 902 covers the surface of the first electrode, the second electrode covers the surface of the capacitive dielectric layer 902, and is in contact with one end of the second extension portion 802 away from the first extension portion 801.

[0187] In some embodiments, as Figure 3 shown, the semiconductor device structure further includes a gate dielectric layer 50, and the gate dielectric layer 50 is at least located between the word line structure 60 and the channel layer 70.

[0188] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0189] The above embodiments only express several implementation manners of the present invention, and the description is relatively specific and detailed. However, it should not be construed as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of this invention patent shall be subject to the appended claims.

Claims

1. A semiconductor device structure, characterized in that, Comprising: A substrate and a stacked structure located on the substrate, at least one through hole penetrating the stacked structure, and a word line structure and a channel layer are disposed in the through hole; wherein, The stacked structure includes multiple interlayer dielectric layers arranged at intervals in a first direction perpendicular to the substrate; The word line structure includes a main body portion and multiple branch portions, and the main body portion is integrally connected to each of the branch portions; wherein, the main body portion extends in the first direction; each of the branch portions is arranged at intervals in the first direction and extends in a second direction and a third direction parallel to the substrate, and the second direction intersects with the third direction; The channel layer is located between adjacent interlayer dielectric layers and surrounds the side walls of the word line structure.

2. The semiconductor device structure according to claim 1, wherein The stacked structure further includes multiple conductive layers, the conductive layers are located between adjacent interlayer dielectric layers, and the channel layer covers the surfaces of the conductive layers and is disconnected between adjacent conductive layers.

3. The semiconductor device structure according to claim 2, characterized in that, Each of the conductive layers includes: A first extension portion extending in the second direction, and the first extension portion serves as a bit line; Multiple second extension portions located on opposite sides of the first extension portion in the third direction and on a side of the word line structure away from the first extension portion; each of the second extension portions extends in the third direction, and multiple second extension portions on the same side of the first extension portion are arranged at intervals in the second direction; The number of the through holes is multiple, and the multiple through holes are respectively located at one ends of the multiple second extension portions close to the first extension portion.

4. The semiconductor device structure according to claim 3, wherein, The semiconductor structure further includes a capacitor, the capacitor includes a first electrode, a capacitive dielectric layer, and a second electrode, wherein, the first electrode is located between adjacent interlayer dielectric layers, the capacitive dielectric layer covers the surface of the first electrode, the second electrode covers the surface of the capacitive dielectric layer, and is in contact with one end of the second extension portion away from the first extension portion.

5. The semiconductor device structure according to claim 2, wherein, In each of the conductive layers, the bit line sequentially connects the channel layers surrounding the multiple word line structures arranged at intervals in the second direction.

6. The semiconductor device structure according to claim 2, characterized in that, The semiconductor device structure further includes a gate dielectric layer, and the gate dielectric layer is at least located between the word line structure and the channel layer.

7. The semiconductor device structure according to claim 2, wherein Each of the interlayer dielectric layers and each of the conductive layers have the branch portions; the thickness of the branch portions in the interlayer dielectric layer is greater than the thickness of the branch portions in the conductive layer; the length of the branch portions in the interlayer dielectric layer is equal to the length of the branch portions in the conductive layer.

8. The semiconductor device structure according to claim 2, wherein The number of the channel layers is multiple, each of the channel layers is arranged corresponding to each of the conductive layers, and the multiple channel layers are arranged at intervals in the first direction.

9. A method for fabricating a semiconductor device structure, characterized in that, Comprising: Providing a substrate; Forming an initial stacked structure on the substrate, the initial stacked structure including alternately stacked interlayer dielectric layers and sacrificial layers; Forming at least one through hole penetrating the initial stacked structure; A word line structure is formed within the through hole; wherein, the word line structure includes a main body portion and a plurality of branch portions, and the main body portion is integrally connected to each of the branch portions; wherein, the main body portion extends in a first direction perpendicular to the substrate; each of the branch portions is arranged at intervals in the first direction and extends in a second direction and a third direction parallel to the substrate, and the second direction intersects with the third direction. Each layer of the sacrificial layer is removed to form a plurality of first trenches, and the plurality of first trenches are respectively located between different adjacent interlayer dielectric layers and are arranged at intervals in the first direction; each of the first trenches extends in the second direction. A channel layer is formed within each layer of the first trenches; the channel layer surrounds the side walls of the word line structure, and each layer of the channel layer is arranged at intervals in the first direction.

10. The manufacturing method of the semiconductor device structure according to claim 9, wherein, The step of forming the word line structure within the through hole includes: Performing a lateral etching based on the through hole to remove a part of the sacrificial layer and form a second trench extending in the second direction and the third direction. Depositing the sacrificial layer on the inner wall of the second trench to reduce the size of the second trench. Performing a lateral etching based on the through hole to remove a part of the interlayer dielectric layer and form a third trench extending in the second direction and the third direction. A gate dielectric layer and a word line material layer are sequentially deposited within the through hole, the second trench, and the third trench; wherein, the word line material layer located within the first trench serves as the main body portion, and the word line material layer located within the second trench and the third trench serves as the branch portions.

11. The method for preparing the semiconductor device structure according to claim 9, wherein, The sacrificial layer includes a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer stacked in sequence along the first direction, and the material of the first sacrificial layer is the same as that of the third sacrificial layer and different from that of the second sacrificial layer. The step of forming the word line structure within the through hole includes: Performing a lateral etching based on the through hole to respectively remove a part of the second sacrificial layer and a part of the interlayer dielectric layer, and respectively form a second trench and a third trench extending in the second direction and the third direction. A gate dielectric layer and a word line material layer are sequentially deposited within the through hole, the second trench, and the third trench; wherein, the word line material layer located within the first trench serves as the main body portion, and the word line material layer located within the second trench and the third trench serves as the branch portions.

12. The method for preparing a semiconductor device structure according to claim 10 or 11, characterized in that, The step of removing each layer of the sacrificial layer to form a first trench extending in the second direction between adjacent interlayer dielectric layers includes: Fourth trenches are formed on both sides of the initial stacked structure along the third direction, and the fourth trenches penetrate through the initial stacked structure along the first direction. Performing a lateral etching based on the fourth trench to remove each layer of the sacrificial layer and form the first trench located between adjacent interlayer dielectric layers and extending in the second direction.

13. The method for preparing the semiconductor device structure according to claim 12, wherein After a channel layer is formed within each layer of the first trenches, the method further includes: A conductive layer is formed in each of the first trenches of the layers, and the multiple conductive layers and the multiple interlayer dielectric layers together form the stacked structure; the channel layer covers the surface of the conductive layer and is disconnected between adjacent conductive layers.

14. The manufacturing method of the semiconductor device structure according to claim 13, characterized in that, After a conductive layer is formed in each of the first trenches of the layers, the method further includes: Removing a part of the channel layer and the conductive layer; Sequentially depositing a second electrode material layer, a capacitive dielectric layer, and a first electrode material layer in the first trench and the fourth trench to form a capacitor; wherein, the second electrode material layer is in contact with the channel layer and the conductive layer, the first electrode material layer serves as the first electrode of the capacitor, and the second electrode material layer serves as the second electrode of the capacitor.

15. The method for preparing the semiconductor device structure according to claim 13, wherein, Each of the conductive layers includes: a first extension portion extending along the second direction, and the first extension portion serves as a bit line; a plurality of second extension portions located on opposite sides of the first extension portion along the third direction and on the side of the word line structure away from the first extension portion; each of the second extension portions extends along the third direction, and a plurality of the second extension portions on the same side of the first extension portion are arranged at intervals along the second direction; after forming an initial stacked structure on the substrate and before forming at least one through hole penetrating the initial stacked structure, the method further includes: Forming a fifth trench penetrating the initial stacked structure, and the fifth trench is located between adjacent second extension portions on the same side of the first extension portion; Filling an insulating layer in the fifth trench.

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