Formation method of NORD flash memory

Abstract

The invention provides a forming method of a NORD flash memory. The forming method comprises the following steps: forming a shallow trench isolation structure in a substrate in a peripheral region; forming an ONO layer, a control gate layer and a first hard mask layer on the surface of the floating gate material layer and the surface of the shallow trench isolation structure in the peripheral region; word lines are formed, the word lines are separated from the side walls of the first gate oxide material layer, the floating gate material layer, the ONO layer and the control gate layer and the substrate through isolation structures, and the word lines are separated from the first hard mask layer through first side walls; removing the first hard mask layer; removing the first gate oxide material layer, the control gate layer, the ONO layer and the floating gate material layer which are not covered by the first side wall; sequentially forming a second gate oxide layer, a gate polycrystalline silicon layer and a second hard mask layer on the surfaces of the word line and the substrate and the surface of the shallow trench isolation structure; removing a part of the second hard mask layer and the gate polysilicon layer on the substrate in the peripheral region, and forming a logic gate on the surface of the second gate oxide layer in the peripheral region; and removing the gate polycrystalline silicon layer and the second hard mask layer in the device region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a method for forming a NORD flash memory. Background Art

[0002] NORD flash memories are widely used in various electronic products.

[0003] The formation method of the NORD flash memory in the prior art is as follows. Refer to Figure 1 , first, a substrate 101 is provided. The substrate 101 is divided into a device region and a peripheral region. A shallow trench isolation structure 102 is formed in a part of the substrate 101 in the peripheral region. A first gate oxide material layer 103, a floating gate material layer 104, an ONO material layer 105, and a control gate material layer 106 are sequentially formed on the surface of the substrate 101 in the device region. At the same time, the first gate oxide material layer 103, the floating gate material layer 104, the ONO material layer 105, and the control gate material layer 106 are sequentially formed on the surface of the substrate 101 in the peripheral region. The ONO material layer 105 and the control gate material layer 106 also sequentially cover the surface of the shallow trench isolation structure 102. A first hard mask layer 107 having a first opening is formed on the surface of the control gate material layer 106. The first opening is located in the device region. A first sidewall 108 covering a part of the surface of the control gate material layer 106 is formed in the first opening. A word line opening is formed in the first sidewall 108. The word line opening penetrates through the control gate material layer 106, the ONO material layer 105, the floating gate material layer 104, and the first gate oxide material layer 103, exposing the surface of the substrate 101. A word line 109, a second sidewall 110 separating the word line 109 from the first sidewall 108, and a tunneling oxide layer 111 are formed in the word line opening. The first sidewall 108 covers the sidewalls of the control gate material layer 106 and the ONO material layer 105. The tunneling oxide layer 111 covers the surface of the first sidewall 108, the sidewalls of the floating gate material layer 104 and the first gate oxide material layer 103, and the surface of the substrate 101.

[0004] Next, refer to Figure 2 , remove the first hard mask layer 107 in the peripheral region, the control gate material layer 106 and the ONO material layer 105 on the surface of the shallow trench isolation structure 102, and the control gate material layer 106, the ONO material layer 105, the floating gate material layer 104, and the first gate oxide material layer 103 on the surface of the substrate 101 in the peripheral region.

[0005] Next, refer to Figure 3, a second gate oxide layer 112, a gate polysilicon layer 113, and a second hard mask layer 114 are sequentially formed. The second gate oxide layer 112, the gate polysilicon layer 113, and the second hard mask layer 114 cover the surfaces of the word line 109 in the device region, the first sidewall 108, and the first hard mask layer 107. The second gate oxide layer 112 covers the surface of the substrate 101 in the peripheral region. The gate polysilicon layer 113 and the second hard mask layer 114 cover the surfaces of the second gate oxide layer 112 and the shallow trench isolation structure 102 in the peripheral region.

[0006] Next, please refer to Figure 4 , use the first patterned photoresist layer to cover the surface of the second hard mask layer 114 in the peripheral region, and etch the second gate oxide layer 112, the gate polysilicon layer 113, and the second hard mask layer 114 in the device region. Then, continue to etch and remove the first hard mask layer 107 in the device region.

[0007] Next, please refer to Figure 5 , a TEOS layer 115 is formed in both the device region and the peripheral region. The TEOS layer 115 covers the surfaces of the word line 109, the first sidewall 108, and the control gate material layer 106 in the device region. The TEOS layer 115 covers the surface of the gate polysilicon layer 113 in the peripheral region.

[0008] Next, please refer to Figure 6 , a second patterned photoresist layer is formed on the surface of a part of the TEOS layer 115 in the peripheral region. Use the second patterned photoresist layer to sequentially etch the TEOS layer 115 in the device region, and the control gate material layer 106, the ONO material layer 105, the floating gate material layer 104, and the first gate oxide material layer 103 that are not covered by the first sidewall 108 in the device region. At the same time, etch the TEOS layer 115, the gate polysilicon layer 113, and the second gate oxide layer 112 that are not covered by the second patterned photoresist layer in the peripheral region. The remaining gate polysilicon layer 113 located on both sides of the shallow trench isolation structure 102 and spaced from the shallow trench isolation structure 102 serves as the logic gate 116.

[0009] However, the formation method of the existing NORD flash memory has many steps, especially many photolithography steps, and the cost is relatively high. Summary of the Invention

[0010] The purpose of the present invention is to provide a formation method of a NORD flash memory, which can reduce the formation steps of the NORD flash memory, thereby reducing the cost.

[0011] To achieve the above purpose, the present invention provides a formation method of a NORD flash memory, including:

[0012] Providing a substrate, which is divided into a device region and a peripheral region;

[0013] A first gate oxide material layer and a floating gate material layer are sequentially formed on the surfaces of the substrates in the device region and the peripheral region;

[0014] A shallow trench is formed in the floating gate material layer, the first gate oxide material layer, and a part of the substrate in the peripheral region, the first gate oxide material layer and the floating gate material layer in the peripheral region are removed, and a shallow trench isolation structure is formed in the substrate in the peripheral region, and the surface of the shallow trench isolation structure is higher than the surface of the floating gate material layer;

[0015] An ONO layer, a control gate layer, and a first hard mask layer are sequentially formed on the surface of the floating gate material layer and the surface of the shallow trench isolation structure;

[0016] A word line is formed in the first gate oxide material layer, the floating gate material layer, the ONO layer, and the control gate layer in the device region by using the first hard mask layer, and the word line is separated from the side walls of the first gate oxide material layer, the floating gate material layer, the ONO layer, and the control gate layer and the surface of the substrate by an isolation structure, and the word line is separated from the first hard mask layer by a first spacer;

[0017] The first hard mask layer is removed;

[0018] The first gate oxide material layer, the control gate layer, the ONO layer, and the floating gate material layer not covered by the first spacer are removed to expose the surface of the substrate;

[0019] A second gate oxide layer, a gate polysilicon layer, and a second hard mask layer are sequentially formed on the surface of the word line, the surface of the substrate, and the surface of the shallow trench isolation structure;

[0020] Part of the second hard mask layer and the gate polysilicon layer above the substrate in the peripheral region and the second hard mask layer and the gate polysilicon layer above the shallow trench isolation structure are removed to expose part of the surface of the second gate oxide layer, so as to form a logic gate on the surface of the second gate oxide layer on the surface of the substrate in the peripheral region;

[0021] The gate polysilicon layer and the second hard mask layer in the device region are removed.

[0022] Optionally, in the method for forming the NORD flash memory, the method for removing part of the second hard mask layer and the gate polysilicon layer above the substrate in the peripheral region and the second hard mask layer and the gate polysilicon layer above the shallow trench isolation structure to expose part of the surface of the second gate oxide layer to form a logic gate on the surface of the second gate oxide layer on the surface of the substrate in the peripheral region includes:

[0023] A first patterned photoresist layer is formed on the surface of the second hard mask layer;

[0024] Etch the part of the second hard mask layer and the gate polysilicon layer above the substrate in the peripheral region not covered by the first patterned photoresist layer, and the second hard mask layer and the gate polysilicon layer above the shallow trench isolation structure, to expose the surface of part of the second gate oxide layer, and the remaining gate polysilicon layer forms a logic gate.

[0025] Optionally, in the method for forming the NORD flash memory, the method for removing the gate polysilicon layer and the second hard mask layer in the device region includes:

[0026] Form a second patterned photoresist layer on the surface of the second gate oxide layer in the peripheral region and the surface of the logic gate;

[0027] Etch the gate polysilicon layer and the second hard mask layer in the device region.

[0028] Optionally, in the method for forming the NORD flash memory, the method for forming a shallow trench isolation structure in the substrate in the peripheral region, where the surface of the shallow trench isolation structure is higher than the surface of the floating gate material layer, includes:

[0029] Form a silicon nitride mask layer on the surface of the floating gate material layer, and etch the silicon nitride mask layer and part of the substrate to form shallow trenches in the silicon nitride mask layer and the substrate;

[0030] Fill the shallow trenches with silicon oxide to form a shallow trench isolation structure;

[0031] Remove the silicon nitride mask layer..

[0032] Optionally, in the method for forming the NORD flash memory, the substrate includes a wafer.

[0033] Optionally, in the method for forming the NORD flash memory, the isolation structure includes a second sidewall and a tunneling oxide layer, the second sidewall covers the sidewalls of the control gate layer, and the tunneling oxide layer covers the surface of the second sidewall, the sidewalls of the ONO material layer, the sidewalls of the floating gate material layer, and the surface of the substrate.

[0034] Optionally, in the method for forming the NORD flash memory, the materials of the first gate oxide layer, the first sidewall, and the tunneling oxide layer all include silicon oxide.

[0035] Optionally, in the method for forming the NORD flash memory, the materials of the first hard mask layer and the second sidewall both include silicon nitride.

[0036] Optionally, in the method for forming the NORD flash memory, the materials of the floating gate material layer, the control gate material layer, and the gate polysilicon layer all include polysilicon.

[0037] In the method for forming a NORD flash memory provided by the present invention, it includes: providing a substrate, which is divided into a device region and a peripheral region; sequentially forming a first gate oxide material layer and a floating gate material layer on the surfaces of the substrates in the device region and the peripheral region; forming a shallow trench in the floating gate material layer, the first gate oxide material layer and a part of the substrate in the peripheral region, removing the first gate oxide material layer and the floating gate material layer in the peripheral region, and forming a shallow trench isolation structure in the substrate in the peripheral region, the surface of the shallow trench isolation structure being higher than the surface of the floating gate material layer; sequentially forming an ONO layer, a control gate layer and a first hard mask layer on the surface of the floating gate material layer and the surface of the shallow trench isolation structure; using the first hard mask layer to form a word line in the first gate oxide material layer, the floating gate material layer, the ONO layer and the control gate layer in the device region, the word line being separated from the side walls of the first gate oxide material layer, the floating gate material layer, the ONO layer and the control gate layer and the surface of the substrate by an isolation structure, and the word line being separated from the first hard mask layer by a first spacer; removing the first hard mask layer; removing the first gate oxide material layer, the control gate layer, the ONO layer and the floating gate material layer not covered by the first spacer to expose the surface of the substrate; sequentially forming a second gate oxide layer, a gate polysilicon layer and a second hard mask layer on the surface of the word line, the surface of the substrate and the surface of the shallow trench isolation structure; removing a part of the second hard mask layer and the gate polysilicon layer above the substrate in the peripheral region and the second hard mask layer and the gate polysilicon layer above the shallow trench isolation structure to expose the surface of a part of the second gate oxide layer, so as to form a logic gate on the surface of the second gate oxide layer on the surface of the substrate in the peripheral region; removing the gate polysilicon layer and the second hard mask layer in the device region. The present invention reduces the formation steps of the NORD flash memory, thereby reducing the cost. Description of the Drawings

[0038] Figures 1 to 6 is a schematic diagram of the result in the process of forming a NORD flash memory in the prior art;

[0039] Figure 7 is a flowchart of the method for forming a NORD flash memory according to an embodiment of the present invention;

[0040] Figures 8 to 15 is a schematic diagram of the result in the process of forming a NORD flash memory according to an embodiment of the present invention;

[0041] In the figure: 101 - substrate, 102 - shallow trench isolation structure, 103 - first gate oxide material layer, 104 - floating gate material layer, 105 - ONO material layer, 106 - control gate material layer, 107 - first hard mask layer, 108 - first sidewall, 109 - word line, 110 - second sidewall, 111 - tunneling oxide layer, 112 - second gate oxide layer, 113 - gate polysilicon layer, 114 - second hard mask layer, 115 - TEOS layer, 116 - logic gate, 201 - substrate, 202 - shallow trench isolation structure, 203 - first gate oxide material layer, 204 - floating gate material layer, 205 - ONO material layer, 206 - control gate material layer, 207 - first hard mask layer, 208 - first sidewall, 209 - word line, 210 - second sidewall, 211 - tunneling oxide layer, 212 - second gate oxide layer, 213 - gate polysilicon layer, 214 - second hard mask layer, 215 - first patterned photoresist layer, 216 - logic gate, 217 - second patterned photoresist layer. Detailed implementation manners

[0042] The following will describe in more detail the specific implementation manners of the present invention with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0043] In the following text, terms such as "first" and "second" are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It should be understood that, under appropriate circumstances, these terms used in this way can be replaced. Similarly, if the methods described herein include a series of steps, and the order of these steps presented herein is not necessarily the only order in which these steps can be executed, and some of the described steps can be omitted and / or some other steps not described herein can be added to the method.

[0044] Moreover, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or there can also be an intervening layer. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or there can also be one or more intervening layers. Additionally, the references to "on" and "under" each layer can be based on the drawings.

[0045] Please refer to Figure 7 , the present invention provides a method for forming a NORD flash memory, including:

[0046] S1: Provide a substrate, which is divided into a device area and a peripheral area;

[0047] S2: Form a first gate oxide material layer and a floating gate material layer in sequence on the surfaces of the substrates in the device region and the peripheral region;

[0048] S3: Remove the first gate oxide material layer and the floating gate material layer in the peripheral region, and form a shallow trench isolation structure in the substrate in the peripheral region, where the surface of the shallow trench isolation structure is higher than the surface of the floating gate material layer;

[0049] S4: Form an ONO layer, a control gate layer, and a first hard mask layer in sequence on the surface of the floating gate material layer and the surface of the shallow trench isolation structure;

[0050] S5: Use the first hard mask layer to form word lines in the first gate oxide material layer, the floating gate material layer, the ONO layer, and the control gate layer in the device region. The word lines are separated from the sidewalls of the first gate oxide material layer, the floating gate material layer, the ONO layer, and the control gate layer and the surface of the substrate through an isolation structure, and the word lines are separated from the first hard mask layer through a first spacer;

[0051] S6: Remove the first hard mask layer;

[0052] S7: Remove the first gate oxide material layer, the control gate layer, the ONO layer, and the floating gate material layer not covered by the first spacer in the device region to expose the surface of the substrate;

[0053] S8: Form a second gate oxide layer, a gate polysilicon layer, and a second hard mask layer in sequence on the surfaces of the word lines, the substrate, and the shallow trench isolation structure;

[0054] S9: Remove a part of the second hard mask layer and the gate polysilicon layer above the substrate in the peripheral region and the second hard mask layer and the gate polysilicon layer above the shallow trench isolation structure to expose a part of the surface of the second gate oxide layer, so as to form a logic gate on the surface of the second gate oxide layer on the surface of the substrate in the peripheral region;

[0055] S10: Remove the gate polysilicon layer and the second hard mask layer in the device region.

[0056] First, please refer to Figure 8, a substrate 201 is provided. The substrate 201 is divided into a device region and a peripheral region. On the surfaces of the substrate 201 in both the device region and the peripheral region, a first gate oxide material layer 203 and a floating gate material layer 204 are sequentially formed; the first gate oxide material layer and the floating gate material layer in the peripheral region are removed. A silicon nitride mask layer is formed on the surface of the substrate in the peripheral region, the silicon nitride mask layer and a part of the substrate 201 are etched to form a shallow trench in the substrate 201; silicon oxide is filled into the shallow trench to form a shallow trench isolation structure 202 in the substrate 201 in the peripheral region. The surface of the shallow trench isolation structure 202 is higher than the surface of the floating gate material layer 204. Then, the silicon nitride mask layer is removed. Then, an ONO material layer 205, a control gate material layer 206, and a first hard mask layer 207 are sequentially formed on the surface of the floating gate material layer 204 in the device region and the surface of the shallow trench isolation structure 202 in the peripheral region. The ONO material layer 205, the control gate material layer 206, and the first hard mask layer 207 cover the surface of the shallow trench isolation structure 202 at the same time. A first opening is formed in a part of the first hard mask layer 207 in the device region, and the surface of the control gate material layer 206 is exposed in the first opening. A first sidewall 208 is formed on the surface of a part of the control gate material layer 206 in the first opening. The control gate material layer 206 is etched using the first sidewall 208 as a mask, and a second sidewall 210 is formed on the sidewall of the control gate material layer 206 and the surface of the first sidewall 208. The ONO material layer 205, the floating gate material layer 204, and the first gate oxide material layer 203 are etched using the second sidewall 210 as a mask to expose the surface of the substrate 201. A tunneling oxide layer 211 is formed to cover the surface of the second sidewall 210, the sidewalls of the ONO material layer 205, the sidewalls of the floating gate material layer 204, the sidewalls of the first gate oxide material layer 203, and the surface of the substrate 201. A word line 209 is formed in the word line opening formed in the tunneling oxide layer 211.

[0057] Next, please refer to Figure 9 , the first hard mask layer 207 is removed to expose the surface of the control gate material layer 206.

[0058] Next, please refer to Figure 10 , the control gate material layer 206, the ONO material layer 205, the floating gate material layer 204, and the first gate oxide material layer 203 that are not covered by the first sidewall 208 are removed.

[0059] Next, please refer to Figures 11 to 13, a second gate oxide layer 212, a gate polysilicon layer 213, and a second hard mask layer 214 are formed on the surfaces of the word line 209 and the substrate 201. A first patterned photoresist layer 215 is formed on the surface of a part of the second hard mask layer 214 in the peripheral region. The second hard mask layer 214 and the gate polysilicon layer 213 in the peripheral region are etched using the first patterned photoresist layer 215 to form logic gates 216 on both sides of the shallow trench isolation structure 202 respectively. Preferably, when forming the structure of the device region, some of the same film layers are also formed in the end region, such as Figure 13 , which is a schematic diagram of the end region and the peripheral region. The ONO material layer 205, the control gate material layer 206, the first sidewall 208, the word line 209, the second sidewall 210, and the tunneling oxide layer 211 are formed on the surface of the shallow trench isolation structure 202. Compared with the structure of the device region, the first gate oxide material layer 203 and the floating gate material layer 204 are missing. The relative positions and formation methods of the remaining film layers are the same, and the same film layers of the structure of the device region and the structure of the end region are formed together.

[0060] Next, please refer to Figure 14 , a second patterned photoresist layer 217 is formed on the surface of the logic gate 216 in the peripheral region and on the surface of the second gate oxide layer 212. The peripheral region is covered using the second patterned photoresist layer 217, and the second hard mask layer 214 and the gate polysilicon layer 213 in the device region and the second gate oxide layer 212 and the word line 209 in the end region are etched away, such as Figure 15 , Figure 15 , which is a schematic diagram of the structure of the end region and the peripheral region. Finally, the second patterned photoresist layer 217 is removed.

[0061] In summary, in the method for forming a NORD flash memory provided by the embodiments of the present invention, it includes: providing a substrate, which is divided into a device region and a peripheral region; sequentially forming a first gate oxide material layer and a floating gate material layer on the surfaces of the substrates in the device region and the peripheral region; forming a shallow trench in the floating gate material layer, the first gate oxide material layer, and a part of the substrate in the peripheral region, removing the first gate oxide material layer and the floating gate material layer in the peripheral region, and forming a shallow trench isolation structure in the substrate in the peripheral region, the surface of the shallow trench isolation structure being higher than the surface of the floating gate material layer; sequentially forming an ONO layer, a control gate layer, and a first hard mask layer on the surface of the floating gate material layer and the surface of the shallow trench isolation structure; using the first hard mask layer to form a word line in the first gate oxide material layer, the floating gate material layer, the ONO layer, and the control gate layer in the device region, the word line being separated from the sidewalls of the first gate oxide material layer, the floating gate material layer, the ONO layer, and the control gate layer and the surface of the substrate by an isolation structure, and the word line being separated from the first hard mask layer by a first spacer; removing the first hard mask layer; removing the first gate oxide material layer, the control gate layer, the ONO layer, and the floating gate material layer not covered by the first spacer to expose the surface of the substrate; sequentially forming a second gate oxide layer, a gate polysilicon layer, and a second hard mask layer on the surfaces of the word line, the substrate, and the shallow trench isolation structure; removing a part of the second hard mask layer and the gate polysilicon layer above the substrate in the peripheral region and the second hard mask layer and the gate polysilicon layer above the shallow trench isolation structure to expose the surface of a part of the second gate oxide layer, so as to form a logic gate on the surface of the second gate oxide layer on the surface of the substrate in the peripheral region; removing the gate polysilicon layer and the second hard mask layer in the device region. The present invention reduces the formation steps of the NORD flash memory, thereby reducing the cost.

[0062] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art within the technical field, without departing from the technical solution of the present invention, making any form of equivalent substitution or modification and other changes to the technical solution and technical content disclosed by the present invention, all fall within the content of the technical solution of the present invention and still belong to the protection scope of the present invention.

Claims

1. A method for forming a NORD flash memory, characterized in that, Comprising: Providing a substrate, which is divided into a device region and a peripheral region; Successively forming a first gate oxide material layer and a floating gate material layer on the surfaces of the substrates in the device region and the peripheral region; Removing the first gate oxide material layer and the floating gate material layer in the peripheral region, and forming a shallow trench isolation structure in the substrate of the peripheral region, the surface of the shallow trench isolation structure being higher than the surface of the floating gate material layer; Successively forming an ONO layer, a control gate layer and a first hard mask layer on the surface of the floating gate material layer and the surface of the shallow trench isolation structure; Using the first hard mask layer to form word lines in the first gate oxide material layer, the floating gate material layer, the ONO layer and the control gate layer in the device region, the word lines being separated from the side walls of the first gate oxide material layer, the floating gate material layer, the ONO layer and the control gate layer and the surface of the substrate by an isolation structure, and the word lines being separated from the first hard mask layer by a first sidewall; Removing the first hard mask layer; Removing the first gate oxide material layer, the control gate layer, the ONO layer and the floating gate material layer not covered by the first sidewall to expose the surface of the substrate; Successively forming a second gate oxide layer, a gate polysilicon layer and a second hard mask layer on the surfaces of the word lines, the substrate and the shallow trench isolation structure; Removing a part of the second hard mask layer and the gate polysilicon layer above the substrate in the peripheral region and the second hard mask layer and the gate polysilicon layer above the shallow trench isolation structure to expose a part of the surface of the second gate oxide layer, so as to form a logic gate on the surface of the second gate oxide layer on the surface of the substrate in the peripheral region; Removing the gate polysilicon layer and the second hard mask layer in the device region.

2. The method for forming the NORD flash memory according to claim 1, wherein, The method for removing a part of the second hard mask layer and the gate polysilicon layer above the substrate in the peripheral region and the second hard mask layer and the gate polysilicon layer above the shallow trench isolation structure to expose a part of the surface of the second gate oxide layer, so as to form a logic gate on the surface of the second gate oxide layer on the surface of the substrate in the peripheral region includes: Forming a first patterned photoresist layer on the surface of the second hard mask layer; Etching a part of the second hard mask layer and the gate polysilicon layer above the substrate in the peripheral region and the second hard mask layer and the gate polysilicon layer above the shallow trench isolation structure not covered by the first patterned photoresist layer to expose a part of the surface of the second gate oxide layer, and the remaining gate polysilicon layer forms a logic gate.

3. The method for forming the NORD flash memory according to claim 1, wherein The method for removing the gate polysilicon layer and the second hard mask layer in the device region includes: Forming a second patterned photoresist layer on the surface of the second gate oxide layer in the peripheral region and the surface of the logic gate; Etching the gate polysilicon layer and the second hard mask layer in the device region.

4. The method for forming the NORD flash memory according to claim 1, wherein, The method for forming a shallow trench isolation structure in the substrate of the peripheral region, the surface of the shallow trench isolation structure being higher than the surface of the floating gate material layer includes: Forming a silicon nitride mask layer on the surface of the floating gate material layer, etching the silicon nitride mask layer and a part of the substrate to form a shallow trench in the silicon nitride mask layer and the substrate; Filling the shallow trench with silicon oxide to form a shallow trench isolation structure; Removing the silicon nitride mask layer.

5. The method for forming the NORD flash memory according to claim 1, wherein The substrate includes a wafer.

6. The method for forming a NORD flash memory according to claim 1, wherein The isolation structure includes a second sidewall and a tunneling oxide layer. The second sidewall covers the sidewalls of the control gate layer, and the tunneling oxide layer covers the surface of the second sidewall, the sidewalls of the ONO material layer, the sidewalls of the floating gate material layer, and the surface of the substrate.

7. The method for forming the NORD flash memory according to claim 6, wherein The materials of the first gate oxide layer, the first sidewall, and the tunneling oxide layer all include silicon oxide.

8. The method for forming the NORD flash memory according to claim 1, characterized in that, The materials of the first hard mask layer and the second sidewall both include silicon nitride.

9. The method for forming the NORD flash memory according to claim 1, wherein, The materials of the floating gate material layer, the control gate material layer, and the gate polysilicon layer all include polysilicon.

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