Gallium nitride device based on suspended gate process and manufacturing method thereof

Abstract

The invention relates to a gallium nitride device based on a suspended gate process and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The device sequentially comprises a substrate, a GaN buffer layer, a GaN channel layer, an AlN insertion layer and an AlGaN barrier layer from bottom to top, source electrode metal and drain electrode metal are arranged on the two sides of the AlGaN barrier layer respectively, the bottom of the source electrode metal and the bottom of the drain electrode metal extend to the GaN buffer layer, a p-GaN cap layer is arranged on the upper side of the AlGaN barrier layer, and grid electrode metal is arranged on the upper side of the p-GaN cap layer and the side close to the drain electrode metal. According to the invention, the grid regulation and control capability can be effectively improved, the electric leakage can be reduced, the breakdown voltage can be improved, the current collapse and the hot carrier effect can be inhibited, and a new solution is provided for the preparation of high-performance GaN power and radio frequency devices.

Description

Technical Field

[0001] The present invention relates to a gallium nitride device based on a suspended gate process and a manufacturing method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] As the performance of Si-based materials gradually approaches the theoretical limit, products represented by GaN in the third-generation semiconductor materials are gradually becoming the mainstream of semiconductor device development. GaN materials have excellent electrical properties such as high bandgap width, high electron mobility, high saturation velocity and high breakdown electric field, which makes them show great application potential in harsh working environments such as high frequency, high power and high temperature. This has made GaN devices gain widespread attention and application in power electronics, microwave radio frequency and 5G communications.

[0003] However, traditional enhanced GaN HEMT devices still face a number of technical bottlenecks in practical applications, including unstable threshold voltage, limited breakdown voltage, insufficient gate withstand voltage, and large leakage current. First, the low threshold voltage with large drift is prone to false triggering, making the drive circuit design more complicated and may aggravate the reliability degradation of the device. Secondly, due to the limitations of material and process conditions, the breakdown voltage of the device is low, which affects its application in high-power and high-voltage applications. In addition, insufficient gate withstand voltage will increase the risk of device failure, while large leakage current will cause additional power consumption and thermal management problems.

[0004] In response to these challenges, researchers have proposed a variety of improvement plans, such as increasing the threshold voltage by thickening the p-GaN layer, optimizing the interface quality by nitridation, extending the drift region length and introducing field plates to enhance the breakdown voltage, or optimizing the electron transport characteristics by adjusting the AlGaN composition. However, while these methods improve a certain performance, they often bring new technical difficulties, such as increased process complexity, increased on-resistance, decreased electron mobility, and reliability issues such as gate leakage, parasitic effects, and current collapse. Therefore, how to strike a balance between increasing the threshold voltage, optimizing the breakdown characteristics, and reducing parasitic effects is still an important research direction in the current design and manufacturing of GaN HEMT devices. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention provides a gallium nitride device based on a suspended gate process, creates a process method for a suspended gate, and adopts isotropic dry etching and wet etching as independent implementation schemes to achieve effective removal of the dielectric layer under the gate, thereby improving the electrical performance of the device. Moreover, it can effectively improve the gate regulation capability, reduce leakage, increase the breakdown voltage, and inhibit current collapse and hot carrier effects, providing a new solution for the preparation of high-performance GaN power and radio frequency devices.

[0006] The present invention also provides a method for manufacturing the gallium nitride device based on the suspended gate process.

[0007] The technical solution of the present invention is as follows: A gallium nitride device based on the suspended gate process, which sequentially includes a substrate, a GaN buffer layer, a GaN channel layer, an AlN interlayer, and an AlGaN barrier layer from bottom to top. Source metal and drain metal are respectively disposed on both sides of the AlGaN barrier layer. The bottom of the source metal and the drain metal extends to the GaN buffer layer. A p-GaN cap layer is disposed on the upper side of the AlGaN barrier layer. Gate metal is disposed on the upper side of the p-GaN cap layer and on one side close to the drain metal.

[0008] Preferably according to the present invention, the gate-source spacing of the device is 5 μm, and the gate-source spacing is the distance from the p-GaN cap layer to the source metal. The gate length is 2 μm, and the gate length is the distance between both ends (left end to right end) of the p-GaN cap layer. The gate-drain spacing is 13 μm, and the gate-drain spacing is the distance from the p-GaN cap layer to the drain metal. The gate width is 100 μm, and the gate width is the extension width of the gate into the paper plane.

[0009] Preferably according to the present invention, the length of the gate metal on the upper side of the p-GaN cap layer is the same as the distance between both ends of the p-GaN cap layer. The gate metal on one side of the p-GaN cap layer is vertically disposed at one end of the gate metal on the upper side of the p-GaN cap layer. The gate metal on one side of the p-GaN cap layer is called a suspended gate.

[0010] Preferably according to the present invention, the width of the suspended gate is 5 - 200 nm, and the height of the suspended gate is 50% - 90% of the height of the p-GaN cap layer, so that a certain suspended distance is maintained between the bottom of the suspended gate and the AlGaN barrier layer.

[0011] Preferably according to the present invention, the material of the substrate is silicon carbide, silicon or sapphire; The thickness of the GaN buffer layer is 0.1 - 50 μm; The thickness of the GaN channel layer is 1 - 1000 nm; The thickness of the AlN interlayer is 0.2 - 2 nm; The thickness of the AlGaN barrier layer is 5 - 50 nm, and the molar ratio of Al is 5% - 35%; The thickness of the p-GaN cap layer is 1 - 1000 nm, and the doping concentration is 1×10 17 -1×10 20 cm -3 , and the doping source is magnesium or boron; The source metal and the drain metal are made of the same material, which is a Ti / Al / Ni / Au metal stack, a Ti / Al / Ti / Au metal stack, or a Ti / Al / Mo / Au metal stack; The material of the gate metal is a Ni / Au metal stack.

[0012] According to a further preference of the present invention, the material of the substrate is silicon carbide; The thickness of the GaN buffer layer is 5.2 μm; The thickness of the GaN channel layer is 200 nm; The thickness of the AlN interlayer is 0.5 nm; The thickness of the AlGaN barrier layer is 12.5 nm, and the molar ratio of Al is 18%; The thickness of the p-GaN cap layer is 100 nm, and the doping concentration is 3×10 19 cm -3 ; The materials of the source metal and the drain metal are Ti / Al / Ni / Au metal stacks.

[0013] The manufacturing method of the gallium nitride device based on the suspended gate process is as follows: S1. Grow a GaN buffer layer, a GaN channel layer, an AlN interlayer, an AlGaN barrier layer, and a p-GaN cap layer on the substrate; S2. Dry-etch the excess p-GaN cap layer; S3. Remove the GaN channel layer, the AlN interlayer, and the AlGaN barrier layer outside the device by dry-etching to form a mesa; S4. Evaporate the source metal and the drain metal on the mesa; S5. Anneal in the drain metal and source metal regions to form ohmic contacts; S6. Deposit a dielectric layer above the AlGaN barrier layer and the p-GaN cap layer; S7. Open holes in the dielectric layer above the p-GaN cap layer by dry-etching; S8. Evaporate the gate metal on the side of the p-GaN cap layer close to the drain metal and above the p-GaN cap layer; S9. Remove the dielectric layer on the AlGaN barrier layer by dry-etching or wet-etching to realize the suspension of the suspended gate.

[0014] According to a preference of the present invention, in step S1, the growth methods of the GaN buffer layer, the GaN channel layer, the AlN interlayer, the AlGaN barrier layer, and the p-GaN cap layer are high-quality film-forming methods such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE); The etching methods in steps S2, S3, and S7 are inductively coupled plasma etching (ICP) or reactive ion etching (RIE).

[0015] According to a further preference of the present invention, in step S1, the growth method is metal-organic chemical vapor deposition; In steps S2, S3, and S7, the etching method is inductively coupled plasma etching.

[0016] Preferably according to the present invention, in step S9, the etching method is isotropic inductively coupled plasma etching. During the inductively coupled plasma etching process, the RF power is reduced, and at the same time, SF6 and O2 gases are introduced to achieve etching control. Specifically, O2 reacts with the GaN surface to form a protective film, effectively protecting the p-GaN cap layer region; while the lower RF power suppresses the downward anisotropic diffusion during the etching process, promoting uniform etching in the horizontal direction, that is, isotropic etching, thereby removing the dielectric layer under the gate metal and achieving a suspended effect; the ICP power is set to 1000W, the RF power is set to 100W, SF6 is set to 60 sccm, O2 is set to 20 sccm, and the pressure is set to 1.5 Pa.

[0017] For wet etching, a buffered oxide etchant (BOE) solution plus isopropyl alcohol (IPA) is used. The ratio of the oxide etchant solution to isopropyl alcohol is 95% : 5% to 60% : 40%, and ultrasonic vibration immersion is supplemented to ensure sufficient removal of the dielectric layer under the gate, thereby achieving gate suspension.

[0018] Preferably according to the present invention, in step S5, the annealing treatment method for the source metal and the drain metal is selective laser annealing; The thickness of the dielectric layer is 0 - 100 nm, and the material of the dielectric layer is Si3N4 or SiO2.

[0019] The beneficial effects of the present invention are as follows: 1. Threshold voltage improvement: By adopting a suspended gate design, the present invention forms a wider longitudinal depletion region within the p-GaN cap layer region, achieving a significant increase in the threshold voltage, thereby greatly enhancing the device's turn-on control ability and anti-mis-triggering performance.

[0020] 2. Suppression of parasitic effects and current collapse: By designing a suspended gate structure, the present invention significantly reduces the RC delay problem caused by parasitic capacitance and effectively alleviates the current collapse phenomenon, thereby improving the device's dynamic response and energy efficiency under high-frequency and high-power operating conditions.

[0021] 3. Breakdown voltage improvement: Compared with conventional p-GaN HEMT devices, the present invention shows a higher breakdown voltage under high-voltage operating conditions by adopting a suspended gate structure, thereby greatly enhancing the stability and reliability of the device in high-voltage applications.

[0022] 4. Increase in gate breakdown voltage tolerance: The presence of the suspended gate in the present invention makes the electric field distribution in the gate region more uniform, effectively improving the gate breakdown voltage level, thereby ensuring more stable and reliable operation of the device in a high-voltage environment.

[0023] 5. Greatly reduce leakage current: By setting a gap between the left side of the gate metal and the left side of the p-GaN cap layer, the present invention avoids the sidewall leakage path of channel electrons upward, effectively improves the gate breakdown voltage level, and significantly reduces the gate leakage current, enabling the device to remain in a low-leakage state even at high temperatures or large bias voltages, thereby enhancing the overall energy efficiency and stability.

[0024] 6. Improve current regulation and conduction performance: The optimized floating gate structure of the present invention not only improves the electric field distribution but also solves the problems of decreased electron mobility and increased on-resistance that may be caused by the presence of the dielectric layer, further enhancing the conduction ability of the device and making it suitable for high-efficiency power switch applications.

[0025] 7. Enhanced surge resistance: The balanced electric field distribution and all-round depletion region control of the present invention reduce the risk of damage to the material caused by local high fields, thereby significantly enhancing the surge resistance of the device and ensuring the reliability during long-term operation.

[0026] 8. Prolong the service life of the device: The introduction of the floating gate structure of the present invention reduces the degradation and damage problems of the device during long-term operation, prolonging the service life of the device.

[0027] 9. Expand the application scope: The GaN HEMT device of the present invention, which has increased threshold voltage, breakdown voltage, and gate breakdown voltage while reducing the gate leakage current, can be widely applied to high-power fields such as radio frequency communication, radar systems, satellite communication, and power electronics. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic structural diagram of the present invention; Figure 2 is a schematic structural diagram of a conventional device; Figure 3 is a comparison diagram of the transfer curves of the present invention and a conventional device; Figure 4 is a comparison diagram of the breakdown curves of the present invention and a conventional device; Figure 5 is a comparison diagram of the gate breakdown voltages of the present invention and a conventional device; Wherein: 1. Substrate; 2. GaN buffer layer; 3. GaN channel layer; 4. AlN interlayer; 5. AlGaN barrier layer; 6. p-GaN cap layer; 7. Source metal; 8. Drain metal; 9. Gate metal. DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention will be further described below through examples in conjunction with the drawings, but is not limited thereto.

[0030] Example 1: As Figure 1As shown, a gallium nitride device based on a suspended gate process comprises, from bottom to top, a substrate 1, a GaN buffer layer 2, a GaN channel layer 3, an AlN intercalation layer 4 and an AlGaN barrier layer 5, source metal 7 and drain metal 8 are respectively arranged on both sides of the AlGaN barrier layer 5, the bottoms of the source metal 7 and the drain metal 8 extend to the GaN buffer layer 2, a p-GaN cap layer 6 is arranged on the upper side of the AlGaN barrier layer 5, and a gate metal 9 is arranged on the upper side of the p-GaN cap layer 6 and on the side close to the drain metal 8.

[0031] The gate-source spacing of the device is 5μm, which is the distance from the p-GaN cap layer 6 to the source metal 7. The gate length is 2μm, which is the distance between the two ends of the p-GaN cap layer 6 (from the left end to the right end). The gate-drain spacing is 13μm, which is the distance from the p-GaN cap layer 6 to the drain metal 8. The gate width is 100μm, which is the extension width of the gate into the paper.

[0032] The length of the gate metal 9 on the upper side of the p-GaN cap layer 6 is the same as the distance between the two ends of the p-GaN cap layer 6. The gate metal 9 on one side of the p-GaN cap layer 6 is vertically arranged at one end of the gate metal on the upper side of the p-GaN cap layer. The gate metal 9 on one side of the p-GaN cap layer 6 is called a suspended gate. For gate leakage, the leakage path is that electrons leak upward from the left side wall of the p-GaN cap layer to the gate metal. The two gate metals designed in the present invention will not completely cover the top of the p-GaN cap layer, that is, there is a gap between the left side of the gate metal and the left side of the p-GaN cap layer. For the top of the p-GaN cap layer near the source metal, the vacancy of the gate metal can stagger the sidewall leakage path, effectively improving the gate withstand voltage level and greatly reducing leakage.

[0033] The suspension below the right side of the p-GaN cap layer 6 can effectively reduce the gate capacitance and improve the gate control capability; at the same time, the gate sidewall metal does not contact the barrier layer, which can effectively avoid the electric field concentration phenomenon near the drain below the gate, thereby increasing the breakdown voltage and suppressing the current collapse; in addition, the side gate provides a longitudinal depletion region, and the suspended gate can provide a gradient longitudinal depletion region, which can suppress the hot carrier effect while increasing the threshold voltage.

[0034] The width of the suspended gate is 200 nm, the height of the suspended gate is 70 nm, and the suspended distance between the bottom of the suspended gate and the AlGaN barrier layer is 30 nm, so that a certain suspended distance is maintained between the bottom of the suspended gate and the AlGaN barrier layer.

[0035] The material of the gate metal 9 is a Ni / Au metal stack.

[0036] The material of substrate 1 is silicon carbide; The thickness of the GaN buffer layer 2 is 5.2 μm; The thickness of the GaN channel layer 3 is 200 nm; The thickness of the AlN interlayer 4 is 0.5 nm; The thickness of the AlGaN barrier layer 5 is 12.5 nm, and the molar ratio of Al is 18%; The thickness of the p-GaN cap layer 6 is 100 nm, and the doping concentration is 3×10 19 cm -3 , and the doping source is magnesium or boron; The materials of the source metal 7 and the drain metal 8 are Ti / Al / Ni / Au metal stacks.

[0037] The manufacturing method of the above-mentioned gallium nitride device based on the suspended gate process is as follows: S1. Grow the GaN buffer layer 2, the GaN channel layer 3, the AlN interlayer 4, the AlGaN barrier layer 5, and the p-GaN cap layer 6 on the substrate 1; S2. Dry-etch the excess p-GaN cap layer 6; S3. Remove the GaN channel layer 3, the AlN interlayer 4, and the AlGaN barrier layer outside the device by dry-etching to form a mesa; S4. Evaporate the source metal 7 and the drain metal 8 on the mesa; S5. Anneal in the regions of the drain metal 8 and the source metal 7 to form ohmic contacts; S6. Deposit a dielectric layer above the AlGaN barrier layer 5 and the p-GaN cap layer 6; S7. Open holes in the dielectric layer above the p-GaN cap layer 6 by dry-etching; S8. Evaporate the gate metal 9 on one side of the p-GaN cap layer 6 close to the drain metal 8 and above the p-GaN cap layer 6; S9. Remove the dielectric layer on the AlGaN barrier layer by dry-etching to realize the suspension of the suspended gate.

[0038] In step S1, the growth methods of the GaN buffer layer 2, the GaN channel layer 3, the AlN interlayer 4, the AlGaN barrier layer 5, and the p-GaN cap layer 6 are metal organic chemical vapor deposition; The etching methods in steps S2, S3, and S7 are inductively coupled plasma etching.

[0039] In step S9, the etching method is isotropic inductively coupled plasma etching. During the inductively coupled plasma etching process, the RF power is reduced, and SF6 and O2 gases are introduced simultaneously to achieve etching control. Specifically, O2 reacts with the GaN surface to form a protective film, effectively protecting the p-GaN cap layer 6 region; while the lower RF power suppresses the downward anisotropic diffusion during the etching process, promoting uniform etching in the horizontal direction, that is, isotropic etching, so as to remove the dielectric layer under the gate metal and achieve the suspended effect. The ICP power is set to 1000W, the RF power is set to 100W, SF6 is set to 60 sccm, O2 is set to 20 sccm, and the pressure is set to 1.5 Pa.

[0040] In step S5, the annealing treatment method for the source metal 7 and the drain metal 8 is laser selective annealing; The thickness of the dielectric layer is 30 nm, and the material of the dielectric layer is SiO2.

[0041] Conventional devices such as Figure 2 As shown, the gate metal 9 is disposed above the p-GaN cap layer 6.

[0042] In Sentaurus TCAD simulation, the performance of this embodiment and conventional devices is verified; (1) Simulation model construction: In the Sentaurus TCAD software, a two-dimensional structure model of this embodiment and conventional devices is constructed.

[0043] (2) Simulation parameter setting: Set boundary conditions and initial conditions, including voltage and current, etc. For the transfer curve, first apply a drain voltage of 10V, and then apply a varying gate voltage. For breakdown, first apply a gate voltage of -6V to ensure depletion, and then apply a drain voltage until breakdown. For gate withstand voltage, first make the drain suspended, and then apply a gate voltage until breakdown.

[0044] (3) Simulation process: Conduct the simulation and observe the changes in electrical properties of this embodiment compared with conventional devices.

[0045] (4) Result analysis: According to the constant current method with 10-4 mA / mm as the judgment standard, as Figure 3 can be seen, the threshold voltage of the suspended gate device in this embodiment is increased from 1.7V of the conventional device to 2.07V. In Figure 4 the breakdown curve, taking the critical breakdown field strength of 3.3 MV / cm of the GaN material as the discrimination standard, the breakdown voltage of the suspended gate device reaches 2228V, which is better than 957V of the conventional device. In Figure 5In the gate breakdown voltage curve, with the gate current reaching 1 mA / mm as the standard, the gate breakdown voltage of the floating gate device reached 45.28 V, which is better than 11.25 V of the conventional device. This indicates that the enhanced gallium nitride device architecture based on floating gate modulation can significantly improve the overall performance and reliability of the device.

[0046] Example 2: A manufacturing method of a gallium nitride device based on a floating gate process, the steps are as described in Example 1, the difference is: In step S9, wet etching is used, and buffered oxide etchant (BOE) solution plus isopropyl alcohol (IPA) is used. The ratio of BOE to IPA is 80%:20%, that is, about 20% volume fraction of IPA is added to the BOE etching solution, and ultrasonic vibration immersion is supplemented to ensure that the dielectric layer under the gate is fully removed, so as to realize the floating gate.

Claims

1. A gallium nitride device based on a suspended gate process, characterized in that, From bottom to top, there are a substrate, a GaN buffer layer, a GaN channel layer, an AlN interlayer, and an AlGaN barrier layer. Source metal and drain metal are respectively disposed on both sides of the AlGaN barrier layer. The bottoms of the source metal and the drain metal extend to the GaN buffer layer. A p-GaN cap layer is disposed on the upper side of the AlGaN barrier layer. Gate metal is disposed on the upper side of the p-GaN cap layer and on the side close to the drain metal.

2. The gallium nitride device based on the floating gate process according to claim 1, characterized in that The length of the gate metal on the upper side of the p-GaN cap layer is the same as the distance between both ends of the p-GaN cap layer. The gate metal on one side of the p-GaN cap layer is vertically disposed at one end of the gate metal on the upper side of the p-GaN cap layer. The gate metal on one side of the p-GaN cap layer is called a floating gate.

3. The gallium nitride device based on a floating gate process according to claim 2, wherein The width of the floating gate is 5 - 200 nm, and the height of the floating gate is 50% - 90% of the height of the p-GaN cap layer. The gate-source spacing of the device is 5 μm. The gate-source spacing is the distance from the p-GaN cap layer to the source metal. The gate length is 2 μm. The gate length is the distance between both ends of the p-GaN cap layer. The gate-drain spacing is 13 μm. The gate-drain spacing is the distance from the p-GaN cap layer to the drain metal. The gate width is 100 μm. The gate width is the extension width of the gate into the paper plane.

4. The gallium nitride device based on the floating gate process according to claim 3, wherein The material of the substrate is silicon carbide, silicon, or sapphire. The thickness of the GaN buffer layer is 0.1 - 50 μm. The thickness of the GaN channel layer is 1 - 1000 nm. The thickness of the AlN interlayer is 0.2 - 2 nm. The thickness of the AlGaN barrier layer is 5 - 50 nm, and the molar ratio of Al is 5% - 35%. The thickness of the p-GaN cap layer is 1 - 1000 nm, and the doping concentration is 1×10 17 - 1×10 20 cm -3 , and the doping source is magnesium or boron; The source metal and the drain metal are made of the same material, which is a Ti / Al / Ni / Au metal stack, a Ti / Al / Ti / Au metal stack, or a Ti / Al / Mo / Au metal stack. The material of the gate metal is a Ni / Au metal stack.

5. The gallium nitride device based on the floating gate process according to claim 4, wherein The material of the substrate is silicon carbide. The thickness of the GaN buffer layer is 5.2 μm. The thickness of the GaN channel layer is 200 nm. The thickness of the AlN interlayer is 0.5 nm. The thickness of the AlGaN barrier layer is 12.5 nm, and the molar ratio of Al is 18%. The thickness of the p-GaN cap layer is 100 nm, and the doping concentration is 3×10 19 cm -3 ; The source metal and the drain metal are made of a Ti / Al / Ni / Au metal stack.

6. The manufacturing method of the gallium nitride device based on the suspended gate process according to claim 5, characterized in that, The steps are as follows: S1. Grow a GaN buffer layer, a GaN channel layer, an AlN interlayer, an AlGaN barrier layer, and a p-GaN cap layer on the substrate. S2. Dry-etch the excess p-GaN cap layer. S3. Remove the GaN channel layer, the AlN interlayer, and the AlGaN barrier layer outside the device by dry etching to form a mesa. S4. Evaporate the source metal and the drain metal on the mesa. S5. Anneal in the regions of the drain metal and the source metal to form an ohmic contact. S6. Deposit a dielectric layer above the AlGaN barrier layer and the p-GaN cap layer. S7. Open holes in the dielectric layer above the p-GaN cap layer by dry etching. S8. Evaporate the gate metal on the side of the p-GaN cap layer close to the drain metal and above the p-GaN cap layer. S9. Remove the dielectric layer on the AlGaN barrier layer by dry etching or wet etching to realize the floating of the floating gate.

7. The manufacturing method of the gallium nitride device based on the suspended gate process according to claim 6, wherein In step S1, the growth methods of the GaN buffer layer, the GaN channel layer, the AlN interlayer, the AlGaN barrier layer, and the p-GaN cap layer are metal-organic chemical vapor deposition or molecular beam epitaxy; In steps S2, S3, and S7, the etching method is inductively coupled plasma etching or reactive ion etching.

8. The manufacturing method of the gallium nitride device based on the floating gate process according to claim 7, wherein, In step S1, the growth method is metal-organic chemical vapor deposition; In steps S2, S3, and S7, the etching method is inductively coupled plasma etching.

9. The manufacturing method of the gallium nitride device based on the suspended gate process according to claim 8, characterized in that, In step S9, the etching method is isotropic inductively coupled plasma etching. During the inductively coupled plasma etching process, the RF power is reduced, and SF6 and O2 gases are introduced simultaneously to achieve etching control. The ICP power is set to 1000W, the RF power is set to 100W, SF6 is set to 60 sccm, O2 is set to 20 sccm, and the pressure is set to 1.5 Pa; Wet etching is performed using a buffered oxide etchant solution plus isopropyl alcohol. The ratio of the oxide etchant solution to isopropyl alcohol is 95%:5% to 60%:40%, and ultrasonic vibration soaking is used as an auxiliary.

10. The manufacturing method of the gallium nitride device based on the suspended gate process according to claim 9, wherein, In step S5, the annealing treatment method for the source metal and the drain metal is laser selective annealing; The thickness of the dielectric layer is 0 - 100 nm, and the material of the dielectric layer is Si3N4 or SiO2.

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