Semiconductor device and manufacturing method thereof, power module, power conversion circuit and vehicle
By thickening the trench bottom gate dielectric layer and setting a separation gate, isolation layer and gate structure in a trench type semiconductor device, the problem of electric field concentration is solved, the reliability of the device is improved and the conduction loss is reduced.
Patent Information
- Application Number
- CN202510501781.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-21
- Publication Date
- 2025-07-22
AI Technical Summary
The gate dielectric layer of the trench type semiconductor device is easily broken down due to the concentration of electric field at the bottom of the trench, which affects reliability and increases conduction loss.
A gate dielectric layer with a thickness greater than the side wall is provided at the bottom of the trench, and a separation gate, an isolation layer and a gate are stacked in sequence in the trench. The thickness of the separation gate is smaller than the thickness of the gate, and the gate and drain are separated to reduce Cgd.
The pressure bearing capacity of the dielectric layer at the bottom of the trench is improved, the conduction loss is reduced, and the reliability of the device is enhanced.
Smart Images
Figure CN120358775A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. Background Art
[0002] Semiconductor devices can be divided into trench-type semiconductor devices and planar semiconductor devices. Among them, trench-type semiconductor devices have smaller on-resistance and higher integration compared to planar semiconductor devices.
[0003] However, due to the unique "U" - shaped structure of trench-type semiconductor devices, there is a problem of electric field concentration at the bottom of the trench, which leads to premature breakdown of the gate dielectric layer at the bottom of the trench and affects the reliability of trench-type semiconductor devices. Summary of the Invention
[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle, which can increase the pressure-bearing capacity of the gate dielectric layer at the bottom of the trench, and do not affect the on - characteristics of the semiconductor device. It can also reduce the Cgd of the semiconductor device, reduce the on - loss of the semiconductor device, and improve the reliability of the semiconductor device.
[0005] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes:
[0006] A semiconductor body having opposite first and second surfaces; the semiconductor body further includes a well region and a first region; the semiconductor body is of a first conductivity type, the first region is of the first conductivity type and is disposed on the first surface, the well region is of a second conductivity type and is located on the side of the first region away from the first surface; a trench is further provided on the first surface, and the trench extends from the first surface into the semiconductor body;
[0007] A source electrode located on one side of the first surface of the semiconductor body;
[0008] A drain electrode located on one side of the second surface of the semiconductor body;
[0009] The trench gate structure includes:
[0010] A gate dielectric layer covering the bottom and side walls of the trench, wherein the thickness of the gate dielectric layer located at the bottom of the trench is greater than the thickness of the gate dielectric layer located at the side walls of the trench;
[0011] A split gate, an isolation layer, and a gate electrode stacked in sequence along the direction from the bottom to the top of the trench, wherein the split gate is electrically connected to the source electrode, and the ratio of the thickness of the gate electrode to the thickness of the split gate is greater than 5.
[0012] Optionally, the semiconductor body further includes a second region doped with the second conductivity type;
[0013] The second region is disposed on the first surface and on a side of the first region away from the trench; the depth of the second region is greater than or equal to the depth of the trench.
[0014] Optionally, a surface of the gate away from the isolation layer is lower than the first surface.
[0015] Optionally, the thickness of the split gate is 500 Å to 1000 Å;
[0016] The thickness of the isolation layer is 500 Å to 1000 Å;
[0017] The thickness of the gate is 0.8 μm to 1.2 μm;
[0018] The thickness of the gate dielectric layer at the bottom of the trench is 3000 Å to 5000 Å;
[0019] The thickness of the gate dielectric layer on the sidewall of the trench is 300 Å to 800 Å.
[0020] Optionally, the semiconductor device further includes a gate conductive layer and an interlayer insulating layer;
[0021] The interlayer insulating layer covers the gate and is provided with a conductive via;
[0022] The gate conductive layer fills the conductive via and is electrically connected to the gate.
[0023] Optionally, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body;
[0024] The material of the gate dielectric layer is the same as the material of the isolation layer;
[0025] The material of the gate is the same as the material of the split gate.
[0026] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the manufacturing method including:
[0027] Forming a semiconductor body, wherein the semiconductor body has opposite first and second surfaces; the semiconductor body further includes a well region and a first region; the semiconductor body is doped with a first conductivity type, the first region is doped with the first conductivity type and is disposed on the first surface, the well region is doped with a second conductivity type and is located on a side of the first region away from the first surface; a trench is further disposed on the first surface, and the trench extends from the first surface into the semiconductor body;
[0028] Form a gate dielectric layer, and a split gate, an isolation layer, and a gate electrode that are sequentially stacked in the direction from the bottom to the top of the trench. Among them, the gate dielectric layer covers the bottom and sidewalls of the trench, and the thickness of the gate dielectric layer located at the bottom of the trench is greater than the thickness of the gate dielectric layer located at the sidewalls of the trench;
[0029] Form a source electrode on one side of the first surface of the semiconductor body; among them, the split gate is electrically connected to the source electrode, and the ratio of the thickness of the gate electrode to the thickness of the split gate is greater than 5;
[0030] Form a drain electrode on one side of the second surface of the semiconductor body.
[0031] Optionally, forming a gate dielectric layer, and a split gate, an isolation layer, and a gate electrode that are sequentially stacked in the direction from the bottom to the top of the trench includes:
[0032] Form a first dielectric layer on the sidewalls and bottom of the trench;
[0033] Form a first gate transition layer that fills the trench on the first dielectric layer;
[0034] Remove a part of the first dielectric layer and a part of the first gate transition layer in the trench. The remaining first gate transition layer serves as the split gate; the remaining first dielectric layer serves as the gate dielectric layer at the bottom of the trench;
[0035] Form a second dielectric layer on the side of the split gate and the gate dielectric layer at the bottom of the trench away from the second surface;
[0036] Remove a part of the second dielectric layer and expose the sidewalls of the trench. The second dielectric layer that covers the split gate and does not contact the sidewalls of the trench serves as the isolation layer;
[0037] Form a third dielectric layer on the exposed sidewalls of the trench. The third dielectric layer serves as the gate dielectric layer of the sidewalls of the trench;
[0038] Form the gate electrode on the side of the isolation layer away from the split gate.
[0039] Optionally, the forming of the semiconductor body includes:
[0040] Provide a semiconductor transition body; among them, the semiconductor transition body includes a first surface and a second surface that are oppositely arranged;
[0041] Sequentially form the well region, the first region, and the second region in the semiconductor transition body;
[0042] Form the trench, which extends from the first surface into the semiconductor transition body and penetrates through the first region and the well region, and the remaining semiconductor transition body serves as the semiconductor body.
[0043] Optionally, forming the semiconductor body includes:
[0044] Forming a silicon carbide semiconductor body or a gallium nitride semiconductor body.
[0045] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device provided in any embodiment of the present invention, and the substrate is used to carry the semiconductor device.
[0046] According to another aspect of the present invention, a power conversion circuit is provided. The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;
[0047] The power conversion circuit includes a circuit board and at least one semiconductor device provided in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.
[0048] According to another aspect of the present invention, a vehicle is provided. The vehicle includes a load and a power conversion circuit provided in any embodiment of the present invention. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.
[0049] An embodiment of the present invention provides a semiconductor device. The gate dielectric layer in the semiconductor device is formed on the bottom and sidewalls of the trench, and the thickness of the gate dielectric layer located at the bottom of the trench is greater than the thickness of the gate dielectric layer located on the sidewalls of the trench. Such a setting can increase the pressure-bearing capacity of the gate dielectric layer at the bottom of the trench, solve the problem that the gate dielectric layer is easily broken down due to the electric field concentration at the bottom of the semiconductor device, and at the same time, the gate dielectric layer on the sidewalls of the trench is relatively thin and does not affect the conduction characteristics of the semiconductor device. In addition, the embodiment of the present invention also provides a separation gate, an isolation layer, and a gate that are located in the trench and surrounded by the gate dielectric layer and are stacked in sequence from the bottom to the top of the trench. Among them, the thickness of the separation gate is less than the thickness of the gate, and the ratio of the thickness of the gate to the thickness of the separation gate is greater than 5. Such a setting can enable the separation gate and the isolation layer to be used to separate the gate and the drain of the semiconductor device to reduce Cgd of the semiconductor device and reduce the conduction loss of the semiconductor device. In summary, the semiconductor device provided by the embodiment of the present invention can increase the pressure-bearing capacity of the gate dielectric layer at the bottom of the trench, does not affect the conduction characteristics of the semiconductor device, can also reduce Cgd of the semiconductor device, reduce the conduction loss of the semiconductor device, and improve the reliability of the semiconductor device.
[0050] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become readily apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.
[0052] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;
[0053] Figure 2 is a schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention;
[0054] Figure 3 is a schematic flowchart of a manufacturing method of a semiconductor device provided according to an embodiment of the present invention;
[0055] Figure 4 is a schematic flowchart of another manufacturing method of a semiconductor device provided according to an embodiment of the present invention;
[0056] Figure 5 is a schematic structural diagram of a semiconductor body provided according to an embodiment of the present invention;
[0057] Figure 6 is a schematic structural diagram after forming a first dielectric layer;
[0058] Figure 7 is a schematic structural diagram after forming a first gate transition layer;
[0059] Figure 8 is a schematic structural diagram after forming a split gate;
[0060] Figure 9 and Figure 10 is a schematic process structural diagram of forming a second dielectric layer;
[0061] Figure 11 is a schematic structural diagram after forming an isolation layer;
[0062] Figure 12 is a schematic structural diagram after forming a third dielectric layer on the exposed sidewalls of the trenches;
[0063] Figure 13 and Figure 14 is a schematic process structural diagram of forming a gate;
[0064] Figure 15 It is a schematic structural diagram of a semiconductor device fabricated by using the manufacturing method of the semiconductor device provided in the embodiment of the present invention;
[0065] Figure 16 It is a schematic structural diagram of a semiconductor transition body according to the embodiment of the present invention;
[0066] Figures 17 to 19 It is a schematic process diagram of successively forming a well region, a first region, and a second region;
[0067] Figure 20 It is a schematic structural diagram after forming a trench. Detailed implementation manners
[0068] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.
[0069] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.
[0070] After research and analysis by the inventor, it is found that the reason why the gate dielectric layer at the bottom of the trench of a trench-type semiconductor device is easily broken down in advance is that in the existing manufacturing method of a trench-type semiconductor device, a gate dielectric layer is usually formed by high-temperature oxidation. However, due to the different crystal phases of the bottom and the sidewalls of the trench, the growth rate of the gate dielectric layer on the sidewalls of the trench is faster, and finally a gate dielectric layer with a thick sidewall and a thin bottom is formed, resulting in the problem that the electric field at the bottom of the trench is concentrated and the gate dielectric layer at the bottom of the trench is easily broken down in advance.
[0071] Embodiments of the present invention provide a semiconductor device, which can increase the pressure-bearing capacity of the gate dielectric layer at the bottom of the trench, without affecting the conduction characteristics of the semiconductor device, can also reduce the Cgd (Cgd refers to the capacitance between the gate and the drain) of the semiconductor device, reduce the conduction loss of the semiconductor device, and improve the reliability of the semiconductor device.
[0072] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention. Refer to Figure 1 , the semiconductor device provided in this embodiment includes: a semiconductor body 110, a source electrode 120, a drain electrode 130, a gate dielectric layer 113, and a split gate 114, an isolation layer 115, and a gate electrode 116 stacked in sequence along the direction from the bottom to the top of the trench; the semiconductor body 110 includes a first surface S1 and a second surface S2 arranged opposite to each other; the source electrode 120 is located on one side of the first surface S1 of the semiconductor body 110; the drain electrode 130 is located on one side of the second surface S2 of the semiconductor body 110.
[0073] The semiconductor body 110 further includes a well region 111 and a first region 112. The semiconductor body 110 is of a first conductivity type. The first region 112 is of the first conductivity type and is disposed on the first surface S1. The well region 111 is of a second conductivity type and is located on the side of the first region 112 away from the first surface S1; a trench is further provided on the first surface S1, and the trench extends from the first surface S1 into the semiconductor body 110; the gate dielectric layer 113 covers the bottom and side walls of the trench, and the thickness d1 of the gate dielectric layer 113 at the bottom of the trench is greater than the thickness d2 of the gate dielectric layer 113 at the side wall of the trench; the split gate 114 is electrically connected to the source electrode 120, and the ratio of the thickness d4 of the gate electrode 116 to the thickness d3 of the split gate 114 is greater than 5.
[0074] Specifically, the semiconductor device provided in this embodiment may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
[0075] The semiconductor body 110 may include a substrate 101 and an epitaxial layer 102. In some embodiments of the present invention, the semiconductor body 110 may also only include the epitaxial layer 102. The epitaxial layer 102 is a semiconductor layer formed on the basis of the substrate 101 through a single epitaxial process. The epitaxial process includes processes such as Chemical Vapor Epitaxial Growth (CVE), Molecular Beam Epitaxy (MBD), and Atomic Layer Epitaxy (ALE). The conductivity characteristics of the first conductivity type are opposite to those of the second conductivity type.
[0076] The source electrode 120 is also electrically connected to the first region 112, and the first region 112 may be an active region of the semiconductor device.
[0077] The material of the gate dielectric layer 113 located at the bottom of the trench may be the same as that of the gate dielectric layer 113 located on the sidewalls of the trench. The gate dielectric layer 113 has an insulating function. The gate dielectric layer 113 is used to insulate the spacer gate 116 from the semiconductor body 110, and is also used to insulate the spacer split gate 114 from the semiconductor body 110. The thickness d2 of the gate dielectric layer 113 on the sidewalls of the trench refers to the thickness of the gate dielectric layer 113 on the sidewalls of the trench in the direction perpendicular to the depth of the trench. The thickness d1 of the gate dielectric layer 113 at the bottom of the trench refers to the thickness of the gate dielectric layer 113 at the bottom of the trench in the direction parallel to the depth of the trench. In this embodiment, it is set that the thickness d1 of the gate dielectric layer 113 at the bottom of the trench is greater than the thickness d2 of the gate dielectric layer 113 on the sidewalls of the trench, which can increase the pressure-bearing capacity of the gate dielectric layer 113 at the bottom of the trench, solve the problem that the gate dielectric layer 113 is easily broken down due to the electric field concentration at the bottom of the trench-type semiconductor device, and at the same time, the gate dielectric layer 113 on the sidewalls of the trench is relatively thin and will not affect the conduction characteristics of the semiconductor device.
[0078] In this embodiment, the split gate 114, the isolation layer 115, and the gate 116 are all located in the trench. The vertical projection of the isolation layer 115 on the second surface S2 can cover the vertical projection of the split gate 114 on the second surface S2, and can also cover the vertical projection of the gate 116 on the second surface S2. The isolation layer 115 is used to insulate and separate the split gate 114 from the gate 116. The material of the isolation layer 115 may be the same as that of the gate dielectric layer 113. The material of the split gate 114 may be the same as that of the gate 116.
[0079] In this embodiment, it is set that the thickness d4 of the gate 116 is greater than the thickness d3 of the split gate 114, and the ratio of the thickness d4 of the gate 116 to the thickness d3 of the split gate 114 is greater than 5, which indicates that the split gate 114 located in the trench is shorter. With this setting, the trench can be a non-deep trench structure, which is convenient for the fabrication of the trench. In this embodiment, it is set that the split gate 114 is shorter. The split gate 114 does not have a voltage-dividing function. The split gate 114 and the isolation layer 115 can be used to space the gate 116 from the drain 130 of the semiconductor device, thereby shielding the gate 116 and the drain 130 of the semiconductor device, reducing the overlapping area between the gate 116 and the drain 130, reducing Cgd of the semiconductor device, and thus reducing the conduction loss of the semiconductor device.
[0080] This embodiment provides a semiconductor device. In this semiconductor device, the gate dielectric layer is formed at the bottom and sidewalls of the trench, and the thickness of the gate dielectric layer at the bottom of the trench is greater than that at the sidewalls of the trench. Such a setting can increase the pressure-bearing capacity of the gate dielectric layer at the bottom of the trench, solve the problem that the gate dielectric layer is easily broken down due to the electric field concentration at the bottom of the semiconductor device, and at the same time, the gate dielectric layer at the sidewalls of the trench is relatively thin and does not affect the conduction characteristics of the semiconductor device. In addition, this embodiment also provides a split gate, an isolation layer, and a gate that are located in the trench and surrounded by the gate dielectric layer, and are stacked in sequence in the direction from the bottom to the top of the trench. Among them, the thickness of the split gate is less than that of the gate, and the ratio of the thickness of the gate to the thickness of the split gate is greater than 5. Such a setting enables the split gate and the isolation layer to be used to separate the gate and the drain of the semiconductor device, so as to reduce Cgd of the semiconductor device and lower the conduction loss of the semiconductor device. In summary, the semiconductor device provided by this embodiment can increase the pressure-bearing capacity of the gate dielectric layer at the bottom of the trench, does not affect the conduction characteristics of the semiconductor device, can also reduce Cgd of the semiconductor device, lower the conduction loss of the semiconductor device, and improve the reliability of the semiconductor device.
[0081] Optionally, continue to refer to Figure 1 , the semiconductor body 110 further includes a second region 117 of a second conduction type; the second region 117 is disposed on the first surface S1 and on the side of the first region 112 away from the trench; the depth of the second region 117 is greater than or equal to the depth of the trench.
[0082] Specifically, the active region of the semiconductor device may only include the first region 112, or may also include the first region 112 and the second region 117. The second region 117 may form a good ohmic contact with the source electrode 120. The second region 117 may be adjacent to the first region 112.
[0083] In this embodiment, the depth of the second region 117 is set to be greater than or equal to the depth of the trench, which can protect the bottom and the surrounding of the trench from being directly broken down by high voltage, reduce the electric field, and ensure the normal operation of the semiconductor device. In addition, since the thickness of the split gate 114 in this embodiment is relatively thin, this embodiment does not need to fabricate a particularly deep trench, and the trench is a non-deep trench structure. Therefore, the depth of the second region 117 does not need to be particularly deep, which facilitates the fabrication of the second region 117.
[0084] Optionally, Figure 2 is a schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention. Refer to Figure 2 , the surface of the gate 116 away from the isolation layer 115 is lower than the first surface S1.
[0085] Specifically, the distance between the surface of the gate 116 away from the isolation layer 115 and the first surface S1 can be 500 Å to 10,000 Å. In this embodiment, setting the surface of the gate 116 away from the isolation layer 115 lower than the first surface S1 can reduce the current between the gate 116 and the drain 150 and reduce Cgd.
[0086] Optionally, continue to refer to Figure 2 , the thickness d3 of the split gate 114 is 500 Å to 1000 Å; the thickness of the isolation layer 115 is 500 Å to 1000 Å; the thickness d4 of the gate 116 is 0.8 μm to 1.2 μm; the thickness d1 of the gate dielectric layer 113 at the bottom of the trench is 3000 Å to 5000 Å; the thickness d2 of the gate dielectric layer 113 on the sidewall of the trench is 300 Å to 800 Å.
[0087] Specifically, setting the thickness d3 of the split gate 114 to be 500 Å to 1000 Å, the thickness of the isolation layer 115 to be 500 Å to 1000 Å, and the thickness d4 of the gate 116 to be 0.8 μm to 1.2 μm can not only make the split gate 114 and the isolation layer 115 play an isolation role, but also make the total thickness of the split gate 114 and the isolation layer 115 not too thick, so that it is not necessary to fabricate a deeper trench, which is convenient for trench fabrication.
[0088] Setting the thickness d1 of the gate dielectric layer 113 at the bottom of the trench to be 3000 Å to 5000 Å can further improve the pressure-bearing capacity of the gate dielectric layer at the bottom of the trench. Setting the thickness d2 of the gate dielectric layer 113 on the sidewall of the trench to be 300 Å to 800 Å makes the gate dielectric layer on the sidewall of the trench not affect the conduction characteristics of the semiconductor device.
[0089] Optionally, continue to refer to Figure 2 , the semiconductor structure provided in this embodiment further includes an interlayer insulating layer 140 and a gate conductive layer 150; the interlayer insulating layer 140 covers the gate 116 and is provided with a conductive via 141; the gate conductive layer 150 fills the conductive via 141 and is electrically connected to the gate 116.
[0090] Specifically, the materials of the gate conductive layer 150, the source 120, and the drain 130 can all be metal materials. The material of the interlayer insulating layer 140 can be silicon oxide. The source 120 can cover a part of the interlayer insulating layer 140 and the first region 112 and the second region 117 not covered by the interlayer insulating layer 140. The source 120 and the gate conductive layer 150 are arranged at intervals.
[0091] Optionally, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body; the material of the gate dielectric layer is the same as that of the isolation layer; the material of the gate is the same as that of the split gate.
[0092] Specifically, the MOSFET power device corresponding to the silicon carbide semiconductor body is a silicon carbide MOSFET power device. The MOSFET power device corresponding to the gallium nitride semiconductor body is a gallium nitride MOSFET power device. The silicon carbide MOSFET power device or the gallium nitride MOSFET power device has the advantages of high breakdown voltage, low on-resistance, and high frequency, and can further improve the performance of semiconductor devices. Among them, when silicon carbide or gallium nitride is used as the semiconductor body, due to the high temperature resistance of silicon carbide or gallium nitride materials.
[0093] Setting the material of the gate dielectric layer to be the same as that of the isolation layer can reduce the manufacturing cost of semiconductor devices. The materials of both the gate dielectric layer and the isolation layer can be silicon dioxide. Setting the material of the gate to be the same as that of the split gate can also reduce the manufacturing cost of semiconductor devices. The materials of both the gate and the split gate can be polysilicon or metal materials.
[0094] Next, the manufacturing method of the semiconductor device provided by the embodiment of the present invention will be introduced:
[0095] Figure 3 is a schematic flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present invention. Refer to Figure 3 The manufacturing method of the semiconductor device provided in this embodiment includes the following steps:
[0096] S110. Form a semiconductor body.
[0097] Among them, the semiconductor body has opposite first and second surfaces. The semiconductor body further includes a well region and a first region; the semiconductor body is of a first conductivity type, the first region is of the first conductivity type and is disposed on the first surface, the well region is of a second conductivity type and is located on the side of the first region away from the first surface; a trench is further provided on the first surface, and the trench extends from the first surface into the semiconductor body.
[0098] S120. Form a gate dielectric layer and a split gate, an isolation layer, and a gate stacked in sequence from the bottom to the top of the trench.
[0099] Among them, the gate dielectric layer covers the bottom and side walls of the trench, and the thickness of the gate dielectric layer at the bottom of the trench is greater than the thickness of the gate dielectric layer at the side walls of the trench;
[0100] Among them, the split gate is electrically connected to the source electrode, and the ratio of the thickness of the gate to the thickness of the split gate is greater than 5.
[0101] S130. Form a source electrode on one side of the first surface of the semiconductor body.
[0102] S140. Form a drain electrode on one side of the second surface of the semiconductor body.
[0103] The manufacturing method of the semiconductor device provided in this embodiment can increase the pressure-bearing capacity of the gate dielectric layer at the bottom of the trench in the manufactured semiconductor device, without affecting the conduction characteristics of the semiconductor device, can also reduce Cgd of the semiconductor device, reduce the conduction loss of the semiconductor device, and improve the reliability of the semiconductor device.
[0104] Figure 4 It is a schematic flow chart of another manufacturing method of a semiconductor device provided according to an embodiment of the present invention. Refer to Figure 4 , the manufacturing method of the semiconductor device provided in this embodiment includes the following steps:
[0105] S210. Form a semiconductor body.
[0106] Among them, Figure 5 It is a schematic structural diagram of a semiconductor body provided according to an embodiment of the present invention. Refer to Figure 5 , the semiconductor body includes a first surface S1 and a second surface S2 arranged oppositely. The semiconductor transition body further includes a well region 111 and a first region 112. The first surface S1 is further provided with a trench 210, and the trench 210 extends from the first surface S1 into the semiconductor body.
[0107] Specifically, the semiconductor body may include a substrate 101 and an epitaxial layer 102. In some embodiments of the present invention, the semiconductor body may also only include the epitaxial layer 102. The bottom of the trench 210 is located in the epitaxial layer 102.
[0108] S220. Form a first dielectric layer on the sidewalls and bottom of the trench.
[0109] Specifically, Figure 6 It is a schematic structural diagram after forming the first dielectric layer. Refer to Figure 6 , the first dielectric layer 220 covers the bottom and sidewalls of the trench 210, and the first dielectric layer 220 does not fill the trench 210. The first dielectric layer 220 can be formed by carbon film deposition, high-temperature annealing, and sacrificial oxidation.
[0110] S230. Form a first gate transition layer filling the trench on the first dielectric layer.
[0111] Specifically, Figure 7 It is a schematic structural diagram after forming the first gate transition layer. Refer to Figure 7 , the surface of the first gate transition layer 230 away from the bottom of the trench 210 can be flush with the first surface S1. The first gate transition layer 230 can be formed by a deposition process, and the material of the first gate transition layer 230 can be polysilicon.
[0112] S240. Remove part of the first dielectric layer and part of the first gate transition layer in the trench. The remaining first gate transition layer serves as the isolation gate, and the remaining first dielectric layer serves as the gate dielectric layer at the bottom of the trench.
[0113] Specifically, Figure 8 is a schematic structural diagram after forming the isolation gate. When removing the first gate transition layer 230, the first dielectric layer 220 will also be removed. Therefore, referring to Figure 8 , after forming the isolation gate 114, the sidewall of the trench 210 can be without the first dielectric layer 220.
[0114] The first dielectric layer 220 and the first gate transition layer 230 are removed simultaneously. A wet etching method can be used to remove part of the first dielectric layer 220 and part of the first gate transition layer 230, with the remaining first gate transition layer in the trench 210 serving as the isolation gate 114, and the remaining first dielectric layer in the trench 210 serving as the gate dielectric layer 113 at the bottom of the trench.
[0115] S250. Form a second dielectric layer on the side of the isolation gate and the gate dielectric layer at the bottom of the trench away from the second surface.
[0116] Among them, the surface of the second dielectric layer away from the bottom of the trench can be flush with the first surface.
[0117] Specifically, Figure 9 and Figure 10 are schematic structural diagrams of the process of forming the second dielectric layer. Referring to Figure 9 , first form a second dielectric layer 240 that fills the trench and covers the first surface S1. The second dielectric layer 240 can be formed by a deposition process, and then a chemical mechanical polishing process can be used to process the second dielectric layer 240 to remove the second dielectric layer 240 covering the first surface S1, so that the surface of the processed second dielectric layer 240 away from the bottom of the trench is flush with the first surface S1 (refer to Figure 10 ). Setting the surface of the second dielectric layer 240 away from the bottom of the trench to be flush with the first surface S1 can facilitate the formation of a flat isolation layer in step S260.
[0118] S260. Remove part of the second dielectric layer and expose the sidewall of the trench. The second dielectric layer that covers the isolation gate and does not contact the sidewall of the trench serves as the isolation layer.
[0119] Specifically, Figure 11 is a schematic structural diagram after forming the isolation layer. Referring to Figure 11, a wet etching method can be used to remove part of the second dielectric layer. After removing part of the second dielectric layer, the sidewalls of the trench will be exposed. After performing step S260, if the remaining second dielectric layer in trench 210 covers the isolation gate and does not contact the trench sidewalls, the remaining second dielectric layer in the trench can be used as the isolation layer 115. If the remaining second dielectric layer in trench 210 covers the isolation gate and also contacts the sidewalls of trench 210, the second dielectric layer contacting the sidewalls of trench 210 is used as part of the gate dielectric layer 113 of the sidewalls of trench 210, and the second dielectric layer covering the isolation gate 114 and not contacting the sidewalls of trench 210 is used as the isolation layer 115.
[0120] S270. Form a third dielectric layer on the exposed trench sidewalls, and the third dielectric layer serves as the gate dielectric layer of the trench sidewalls.
[0121] Specifically, Figure 12 is a schematic structural diagram after forming the third dielectric layer on the exposed trench sidewalls. Refer to Figure 12 , the sidewalls of trench 210 can be oxidized to form the third dielectric layer. If the remaining second dielectric layer in trench 210 covers the isolation gate and also contacts the sidewalls of trench 210, the third dielectric layer formed in step S270, the second dielectric layer located on the trench sidewalls after step S260, and the first dielectric layer located at the bottom of the trench after step S240 together constitute the gate dielectric layer 113 of the semiconductor device. Among them, the third dielectric layer formed in step S270 and the second dielectric layer located on the trench sidewalls after step S260 together serve as the gate dielectric layer 113 located on the trench sidewalls. If the remaining second dielectric layer in trench 210 covers the isolation gate and does not contact the trench sidewalls, all the third dielectric layer formed in S270 is used as the gate dielectric layer 113 of the trench sidewalls.
[0122] S280. Form a gate on the side of the isolation layer away from the isolation gate.
[0123] Among them, the surface of the gate away from the isolation layer is lower than the first surface or flush with the first surface.
[0124] Specifically, Figure 13 and Figure 14 are schematic structural diagrams of the process of forming the gate. Refer to Figure 13 , a gate 116 that fills the trench and covers the first surface S1 can be formed by a deposition process, and then the gate 116 covering the first surface S1 is removed to form a gate 116 flush with the first surface S1. Then, the gate 116 can be further etched back to form a gate 116 lower than the first surface S1.
[0125] S290. Form an interlayer insulating layer, a source electrode, a gate conductive layer, and a drain electrode.
[0126] Specifically, Figure 15It is a schematic structural diagram of a semiconductor device fabricated by using the manufacturing method of the semiconductor device provided by the embodiment of the present invention. Refer to Figure 15 , the source electrode 120 is located on one side of the semiconductor body 110, the interlayer insulating layer 140 is located on the side of the gate electrode 116 away from the well region 111, and the interlayer insulating layer 140 includes a conductive via 141. The gate conductive layer 150 fills the conductive via 141 and is electrically connected to the gate electrode 116; the drain electrode 130 is located on the second surface S2.
[0127] Optionally, forming the semiconductor body includes the following steps:
[0128] S211. Provide a semiconductor transition body.
[0129] Among them, Figure 16 It is a schematic structural diagram of a semiconductor transition body according to an embodiment of the present invention. Refer to Figure 16 , the semiconductor transition body includes a first surface S1 and a second surface S2 arranged opposite to each other.
[0130] Specifically, the semiconductor transition body may further include a substrate 101 and an epitaxial layer 102 located on one side of the substrate 101.
[0131] S212. Sequentially form a well region, a first region, and a second region in the semiconductor transition body;
[0132] Specifically, Figures 17 to 19 It is a schematic structural process diagram for sequentially forming a well region, a first region, and a second region. Refer to Figure 17 , first-type doping ions can be implanted into the epitaxial layer 102 to form the well region 111. Refer to Figure 18 , a first photoresist layer 310 can be first formed on the side of the well region 111 away from the epitaxial layer 102. The first photoresist layer 310 exposes the well region 111 of the first region, and then second-type doping ions are implanted into the well region 111 to form the first region 112, and then the first photoresist layer 310 is removed. Refer to Figure 19 , the second region 117 can be formed by using the method of forming the first region 112.
[0133] S213. Form a trench.
[0134] Among them, Figure 20 It is a schematic structural diagram after forming the trench. Refer to Figure 20 , the trench 210 extends from the first surface S1 into the semiconductor transition body and penetrates through the first region 112 and the well region 111. The remaining semiconductor transition body serves as the semiconductor body.
[0135] Specifically, before forming the trench 210, a second photoresist layer 320 may be formed on the first surface S1 first, where the area for fabricating the trench 210 is exposed in the second photoresist layer, and then etching is performed to form the trench 210.
[0136] Optionally, forming a semiconductor body includes: forming a silicon carbide semiconductor body or a gallium nitride semiconductor body.
[0137] Specifically, the MOSFET power device corresponding to the silicon carbide semiconductor body is a silicon carbide MOSFET power device. The MOSFET power device corresponding to the gallium nitride semiconductor body is a gallium nitride MOSFET power device. The silicon carbide MOSFET power device or the gallium nitride MOSFET power device has the advantages of high breakdown voltage, low on-resistance, and high frequency, and can further improve the performance of the semiconductor device.
[0138] An embodiment of the present invention provides a power module, including a substrate and at least one semiconductor device according to any embodiment of the present invention. The substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the semiconductor device according to any embodiment of the present invention are included in this power module, which will not be elaborated here.
[0139] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device according to any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board. Therefore, the beneficial effects of the semiconductor device according to any embodiment of the present invention are included in this power conversion circuit, which will not be elaborated here.
[0140] An embodiment of the present invention further provides a vehicle, including a load and a power conversion circuit according to any embodiment of the present invention. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load. Therefore, the beneficial effects of the power conversion circuit according to any embodiment of the present invention are included in this vehicle, which will not be elaborated here.
[0141] It should be understood that various forms of the processes shown above can be used, reordering, adding, or deleting steps. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. There is no limitation here.
[0142] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
Claims
1. A semiconductor device, characterized in that, Comprising: A semiconductor body having opposite first and second surfaces; the semiconductor body further includes a well region and a first region; the semiconductor body is of a first conductivity type, the first region is of the first conductivity type and is disposed on the first surface, the well region is of a second conductivity type and is located on a side of the first region away from the first surface; the first surface is further provided with a trench that extends from the first surface into the semiconductor body; A source electrode located on one side of the first surface of the semiconductor body; A drain electrode located on one side of the second surface of the semiconductor body; A gate dielectric layer covering the bottom and sidewalls of the trench, wherein the thickness of the gate dielectric layer located at the bottom of the trench is greater than the thickness of the gate dielectric layer located at the sidewalls of the trench; A split gate, an isolation layer, and a gate electrode stacked in sequence along the bottom to top direction of the trench, wherein the split gate is electrically connected to the source electrode, and the ratio of the thickness of the gate electrode to the thickness of the split gate is greater than 5.
2. The semiconductor device according to claim 1, wherein The semiconductor body further includes a second region of the second conductivity type; The second region is disposed on the first surface and is located on a side of the first region away from the trench; the depth of the second region is greater than or equal to the depth of the trench.
3. The semiconductor device according to claim 1, wherein The surface of the gate electrode away from the isolation layer is lower than the first surface.
4. The semiconductor device according to claim 1, wherein The thickness of the split gate is 500 Å to 1000 Å; The thickness of the isolation layer is 500 Å to 1000 Å; The thickness of the gate electrode is 0.8 μm to 1.2 μm; The thickness of the gate dielectric layer at the bottom of the trench is 3000 Å to 5000 Å; The thickness of the gate dielectric layer at the sidewalls of the trench is 300 Å to 800 Å.
5. The semiconductor device according to claim 1, wherein It further includes a gate conductive layer and an interlayer insulating layer; The interlayer insulating layer covers the gate electrode and is provided with a conductive via; The gate conductive layer fills the conductive via and is electrically connected to the gate electrode.
6. The semiconductor device according to claim 1, characterized in that, The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body; The material of the gate dielectric layer is the same as the material of the isolation layer; The material of the gate electrode is the same as the material of the split gate.
7. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a semiconductor body, wherein the semiconductor body has opposite first and second surfaces; the semiconductor body further includes a well region and a first region; the semiconductor body is of a first conductivity type, the first region is of the first conductivity type and is disposed on the first surface, the well region is of a second conductivity type and is located on a side of the first region away from the first surface; the first surface is further provided with a trench that extends from the first surface into the semiconductor body; Forming a gate dielectric layer and a split gate, an isolation layer, and a gate electrode stacked in sequence along the bottom to top direction of the trench, wherein the gate dielectric layer covers the bottom and sidewalls of the trench, and the thickness of the gate dielectric layer located at the bottom of the trench is greater than the thickness of the gate dielectric layer located at the sidewalls of the trench; Forming a source electrode on one side of the first surface of the semiconductor body; wherein the split gate is electrically connected to the source electrode, and the ratio of the thickness of the gate electrode to the thickness of the split gate is greater than 5; Forming a drain electrode on one side of the second surface of the semiconductor body.
8. The manufacturing method of the semiconductor device according to claim 7, wherein Form a gate dielectric layer, a split gate, an isolation layer, and a gate electrode that are sequentially stacked in the direction from the bottom to the top of the trench, including: Form a first dielectric layer on the sidewalls and the bottom of the trench; Form a first gate transition layer that fills the trench on the first dielectric layer; Remove a part of the first dielectric layer and a part of the first gate transition layer in the trench. The remaining first gate transition layer serves as the split gate; the remaining first dielectric layer serves as the gate dielectric layer at the bottom of the trench; Form a second dielectric layer on the side of the split gate and the gate dielectric layer at the bottom of the trench that is away from the second surface; Remove a part of the second dielectric layer and expose the sidewalls of the trench. The second dielectric layer that covers the split gate and does not contact the sidewalls of the trench serves as the isolation layer; Form a third dielectric layer on the exposed sidewalls of the trench. The third dielectric layer serves as the gate dielectric layer on the sidewalls of the trench; Form the gate electrode on the side of the isolation layer that is away from the split gate.
9. The manufacturing method of the semiconductor device according to claim 7, wherein, The forming of the semiconductor body includes: Provide a semiconductor transition body; wherein, the semiconductor transition body includes a first surface and a second surface that are oppositely arranged; Form the well region, the first region, and the second region in the semiconductor transition body in sequence; Form the trench. The trench extends from the first surface of the semiconductor transition body into the semiconductor transition body and penetrates the first region and the well region. The remaining semiconductor transition body serves as the semiconductor body.
10. The manufacturing method of the semiconductor device according to claim 7, wherein The forming of the semiconductor body includes: Form a silicon carbide semiconductor body or a gallium nitride semiconductor body.
11. A power module, characterized in that, Include a substrate and at least one semiconductor device as described in any one of claims 1-6. The substrate is used to carry the semiconductor device.
12. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-6. The semiconductor device is electrically connected to the circuit board.
13. A vehicle, characterized in that, Include a load and the power conversion circuit as described in claim 12. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.