Vertical power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with double current apertures and preparation method thereof
By forming a dual current aperture in GaN vertical trench power MOSFET device and using p+-GaN and p-island to shield the electric field, the electric field aggregation problem at the corner of the gate trench is solved, the breakdown voltage and switching speed of the device are improved, and it is suitable for high-frequency circuits.
Patent Information
- Application Number
- CN202510305791.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-14
- Publication Date
- 2025-07-22
AI Technical Summary
The existing GaN vertical trench power MOSFET devices are prone to premature breakdown due to electric field aggregation at the corners of the gate trench at high voltages, and the large gate leakage capacitance leads to high switching losses, limiting their application in high frequency conditions.
On the basis that the gate trench does not pass through the p+-GaN layer, a dual current aperture is formed through ion implantation or regeneration, and the electric field is shielded using p+-GaN and p-island to reduce the electric field congestion at the corners of the gate trench, and reduce the gate leakage capacitance through secondary epitaxial.
It increases the breakdown voltage of the device, reduces the gate leakage capacitance, increases the switching speed and reduces the switching energy loss, making the device suitable for high-frequency circuits.
Smart Images
Figure CN120358778A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a vertical power MOSFET device with a dual-current aperture and a preparation method thereof, belonging to the technical field of semiconductor transistors. Background Art
[0002] Power semiconductor transistors are considered the core of power electronic systems and are widely used in many fields such as consumer electronics, rail transit, photovoltaic power generation, and industrial control, undertaking functions such as frequency conversion, rectification, voltage transformation, power amplification, and power management. Compared with traditional silicon (Si)-based semiconductors, gallium nitride (GaN), as a wide-bandgap semiconductor, has attracted much attention due to its advantages such as a larger bandgap width, a larger critical breakdown field strength, and a high electron saturation drift velocity. Therefore, GaN-based power transistors can meet the needs of the next-generation power electronic systems.
[0003] Thanks to the two-dimensional electron gas (2DEG) with high mobility located at the AlGaN / GaN interface, GaN-based lateral high electron mobility transistors (HEMTs) have been commercialized at the medium-power (650V) level. However, for applications at high voltage levels (>1200V), a larger source-drain spacing is required, which will increase the chip size and the cost of the required rated current. At the same time, the parasitic elements of HEMTs are proportional to the spacing between the pin and the gate to the drain. Devices that achieve high breakdown voltage by increasing the source-drain spacing will increase the parasitic effect and limit the switching speed of the device. In addition, the 2DEG channel of HEMTs is located at the place where the device surface is contacted, making it particularly vulnerable to surface states and causing current collapse.
[0004] Compared with GaN-based HEMTs, GaN vertical power transistors can provide a higher breakdown voltage by increasing the thickness of the epitaxial region without increasing the chip package size. In addition, vertical GaN power transistors also exhibit avalanche capabilities. When the bias voltage is too high in the short term and exceeds the breakdown voltage, the device can be protected to avoid breakdown affecting the stability of the system.
[0005] Currently, there are many GaN vertical structures, such as fin-type power field-effect transistors (FinFETs), current aperture vertical electron transistors (CAVETs), junction FETs (JFETs), and trench MOSFETs (T-MOSFETs). Among these vertical GaN power transistors, T-MOSFET has been widely studied because its threshold voltage is 3 - 5V, which can avoid the mis-turn-on of the device caused by the noise of the input signal, and it has a relatively simple manufacturing process. However, for the GaN vertical trench power MOSFET, the electric field concentration problem at the gate trench corner may lead to the premature breakdown of the device, resulting in device instability. In addition, the large gate-drain capacitance in the vertical trench power MOSFET will cause large switching losses, which is not conducive to the device operating at high frequencies. Therefore, the present invention is proposed. Summary of the Invention
[0006] Aiming at the deficiencies of the prior art, the present invention provides a vertical power MOSFET device with double current apertures and its manufacturing method, that is, the gate trench is not etched through the p-body (p + -GaN) layer. At the same time, two forward-conducting current apertures are formed by ion implantation or regrowth (regrowth), and a part of p + -GaN is reserved between the two current apertures as the p-island. Due to the electric field shielding of p + -GaN and the p-island, the electric field crowding effect at the gate trench corner under high voltage is significantly reduced, the breakdown voltage of the device is improved, and at the same time, the gate-drain capacitance is reduced, and the dynamic performance of the device is significantly improved.
[0007] The technical solution of the present invention is as follows:
[0008] A vertical power MOSFET device with double current apertures is provided with a drain electrode, an n + -GaN substrate, an n - -GaN drift layer, a p + -GaN layer, and an n + -GaN layer from bottom to top. The trench is etched through the n + -GaN layer but not through the p + -GaN layer, and the bottom of the trench is higher than the bottom of the p + -GaN layer. To form an electron conduction channel, 2 n-GaN conductive current apertures are formed by ion implantation or regrowth under the left and right corners at the bottom of the trench. An SiO2 film is covered above the trench to form a gate dielectric, a gate metal is arranged in the trench, and a source electrode is arranged on the side of the SiO2 film.
[0009] Preferably according to the present invention, the trench depth is 0.9μm and the width is 2μm.
[0010] Preferably according to the present invention, the thickness of the SiO2 thin film is 80 nm.
[0011] Preferably according to the present invention, the width of the p-island between two current apertures is 1.2 μm.
[0012] The preparation method of the above-mentioned vertical power MOSFET device with double current apertures is formed by ion implantation, and the steps are as follows:
[0013] (1) n + - An epitaxial structure is grown on the GaN substrate, including n - - GaN drift layer, p + - GaN layer and n + - GaN layer;
[0014] (2) Using SiO2 as a hard mask on the epitaxial structure, ICP (Cl2 / BCl3 / Ar) etching is carried out to form trenches;
[0015] (3) Using ion implantation to form an n-GaN current aperture at the bottom of the trench;
[0016] (4) Using PECVD to deposit a layer of SiO2 thin film on the bottom and side walls of the trench as the gate dielectric;
[0017] (5) Using electron beam evaporation to form the gate metal;
[0018] (6) Using electron beam evaporation to form the source and drain of ohmic contact.
[0019] The preparation method of the above-mentioned vertical power MOSFET device with double current apertures is formed by secondary epitaxy, and the steps are as follows:
[0020] (a) n + - An n-GaN drift layer and a p - - GaN layer are grown on the GaN substrate. At this time, the thickness of the p + - GaN layer is at least one-third of the designed thickness; + - GaN layer thickness is at least one-third of the designed thickness;
[0021] (b) Using SiO2 as a hard mask on the p + - GaN layer, ICP (Cl2 / BCl3 / Ar) etching is carried out to form 2 grooves;
[0022] (c) Cover the mask outside the groove, and use the secondary epitaxy process (regrowth) to grow the n-GaN current aperture at the groove;
[0023] (d) Remove the SiO2 mask, and epitaxially grow a complete p + - GaN layer, p+ - Growing n on the GaN layer + - GaN layer;
[0024] (e) Using SiO2 as a hard mask to perform ICP (Cl2 / BCl3 / Ar) trench etching to form trenches;
[0025] (f) Removing the surface SiO2 hard mask and performing post-annealing treatment (PIA) to improve the hole activation rate inside the p-GaN layer, and depositing a SiO2 thin film on the bottom and sidewalls of the trenches as the gate dielectric using PECVD; + - GaN layer, and depositing a SiO2 thin film on the bottom and sidewalls of the trenches as the gate dielectric using PECVD;
[0026] (g) Forming the gate metal by electron beam evaporation of metal Ni;
[0027] (h) Forming the source and drain of the ohmic contact by electron beam evaporation.
[0028] Since ion implantation requires a large amount of energy to implant doping particles into the crystal interior, it may cause significant lattice damage, which in turn leads to a decline in device performance. However, the method is simple and requires fewer process steps. Therefore, the present invention also proposes a regrowth preparation method to reduce lattice damage.
[0029] The beneficial effects of the present invention are as follows:
[0030] During the trench etching process of the present invention, the p-GaN layer is not etched through, and conduction is carried out through the current aperture. This design enables the trench gate to be almost wrapped by the p-GaN layer and p-island, effectively improving the electric field crowding effect at the trench corners and enhancing the breakdown level of the device. In addition, the capacitance corresponding area of the gate and drain is reduced, and most of the electric field lines are shielded by the grounded p-GaN layer and p-island, which can significantly reduce the gate-drain capacitance Cgd, improve the switching speed, and reduce the switching energy loss. + - GaN layer and p-island, effectively improving the electric field crowding effect at the trench corners and enhancing the breakdown level of the device. In addition, the capacitance corresponding area of the gate and drain is reduced, and most of the electric field lines are shielded by the grounded p-GaN layer and p-island, which can significantly reduce the gate-drain capacitance Cgd + - GaN layer and p-island shielding, which can significantly reduce the gate-drain capacitance Cgd GD , improve the switching speed, and reduce the switching energy loss. Description of the Drawings
[0031] Figure 1 It is the process flow chart of forming a current aperture by ion implantation in Embodiment 2 of the present invention;
[0032] Figure 2 It is the process flow chart of forming a current aperture by secondary epitaxy in Embodiment 3 of the present invention;
[0033] Figure 3 It is the MOSFET device prepared in Embodiment 3 of the present invention at V DSWhen V = 1200V, schematic diagram of the maximum electric field at the corner of the gate trench varying with the doping concentration of the conductive channel n-GaN and the width of the p-island. The abscissa is the doping concentration of the current aperture, and the ordinate is the electric field strength;
[0034] Figure 4 Threshold voltage (V TH ) of the MOSFET device prepared in Example 3 of the present invention varying with the conductive channel length. Among them, the abscissa is the conductive channel length, and the ordinate is the threshold voltage;
[0035] Figure 5 Schematic diagram of the influence of the conductive channel length of the MOSFET device prepared in Example 3 of the present invention on the forward performance of the device. Among them, the abscissa is the drain voltage, and the ordinate is the source-drain current;
[0036] Figure 6 Reverse transfer capacitance (C RSS ) comparison diagram of the MOSFET device (DCA-MOS) prepared in Example 3 of the present invention, the traditional trench-gate MOS (T-MOS), and the single-current-aperture MOSFET (SCA-MOS). Among them, the abscissa is the drain voltage (V DS ), and the ordinate is the reverse transfer capacitance;
[0037] Where: 1. Drain; 2. n + -GaN substrate; 3. n - -GaN drift layer; 4. p + -GaN layer; 5. n + -GaN layer; 6. Current aperture; 7. SiO2 film; 8. Gate metal; 9. Source. Detailed implementation manners
[0038] The present invention will be further described below by way of examples in conjunction with the drawings, but not limited thereto.
[0039] Example 1:
[0040] This example provides a vertical power MOSFET device with a double current aperture, which is sequentially provided with a drain 1, an n + -GaN substrate 2, an n - -GaN drift layer 3, a p + -GaN layer 4, an n + -GaN layer 5 from bottom to top. The gate trench passes through the n + -GaN layer, and the bottom of the trench is higher than the bottom of the p + -GaN layer, that is, the trench etching does not penetrate through the p +-GaN layer, two conductive current apertures 6 are arranged side by side at the bottom of the trench, a SiO2 thin film 7 is provided on the side wall of the trench and the conductive channel, a gate metal 8 is provided in the SiO2 thin film, and a source electrode 9 is provided on the side of the SiO2 thin film.
[0041] The current aperture is n-GaN, and the width of the p-island between the two current apertures is 1.2 μm.
[0042] Example 2:
[0043] A preparation method of a vertical power MOSFET device with double current apertures as described in Example 1, formed by ion implantation, as Figure 1 shown, the steps are as follows:
[0044] (1) Grow an epitaxial structure on the n + -GaN substrate 2, including n - -GaN drift layer 3, p + -GaN layer 4 and n + -GaN layer 5, the thickness of the n - -GaN drift layer 3 is 12.5 μm, the thickness of the p + -GaN layer 4 is 1 μm, and the thickness of the n + -GaN layer 5 is 0.2 μm;
[0045] (2) Use SiO2 as a hard mask on the epitaxial structure for ICP (Cl2 / BCl3 / Ar) etching to form a trench, the depth of the trench is 0.9 μm, and the width is 2 μm;
[0046] (3) Use ion implantation to form current apertures 6 at the bottom of the trench;
[0047] (4) Use PECVD to deposit a layer of SiO2 thin film 7 on the bottom and side walls of the trench as the gate dielectric, and the thickness of the SiO2 thin film 7 is 80 nm;
[0048] (5) Use electron beam evaporation to form the gate metal 8;
[0049] (6) Use electron beam evaporation to form the source electrode 9 and the drain electrode 1 for ohmic contact.
[0050] Example 3:
[0051] A preparation method of a vertical power MOSFET device with double current apertures as described in Example 1, formed by secondary epitaxy, as Figure 2 shown, the steps are as follows:
[0052] (a) Grow n + -GaN drift layer 3 and p - -GaN on the n +- GaN layer 4, n - - The thickness of the GaN drift layer 3 is 12.5 μm, p + - The thickness of the GaN layer 4 is 0.5 μm;
[0053] (b) On the p + - Using SiO2 as a hard mask for ICP (Cl2 / BCl3 / Ar) etching on the GaN layer 4 to form 2 grooves, the groove depth is 0.5 μm, and the width is 0.7 μm;
[0054] (c) Cover the mask outside the grooves, and use the regrowth process to grow an n-GaN current aperture at the grooves;
[0055] (d) Remove the SiO2 mask, and epitaxially grow 0.5 μm thick p + - GaN to form a complete p + - The thickness of the GaN layer, p + - Grow 0.2 μm thick n + - GaN layer on the GaN layer;
[0056] (e) Using SiO2 as a hard mask for ICP (Cl2 / BCl3 / Ar) trench etching to form trenches, the trench width is 2 μm, and the etching depth is 0.9 μm;
[0057] (f) Remove the surface SiO2 hard mask, perform post-implantation annealing (PIA) to improve the hole activation rate inside the p + - GaN layer, and deposit a 80 nm thick SiO2 thin film on the bottom and sidewalls of the trenches by PECVD;
[0058] (g) Use electron beam evaporation to deposit metal Ni to form the gate metal;
[0059] (h) Use electron beam evaporation to form the source and drain of ohmic contacts.
[0060] By studying the effects of the width of the p-island and the doping concentration of the current aperture on the breakdown and forward performance of the device, to determine the optimal parameters of the device, and simulate the MOSFET device prepared in this embodiment;
[0061] As Figure 3 shown, reducing the n-type doping concentration of the current aperture and increasing the width of the p-island can better protect the gate from high electric field invasion. Compared with the traditional trench MOSFET, the device proposed in this embodiment significantly increases the breakdown voltage of the device while ensuring that the electric field strength at the gate trench is below 3 MV / cm without sacrificing the forward conduction characteristics too much.
[0062] AsFigure 4 As shown, when the channel length is below the critical value, due to the short-channel effect, the threshold voltage will rapidly decrease; as Figure 5 shown, the shorter the channel length, the smaller the forward conduction resistance;
[0063] As Figure 6 shown, the reverse transfer capacitance of the device proposed in this patent is significantly reduced compared with the reference device, and the switching speed of the device is faster, which can be applied in higher-frequency circuits.
[0064] At the same time, the channel resistance of the traditional GaN trench MOSFET is affected by surface charges and accounts for a large part of the total resistance. Reducing the channel length also leads to a reduction in the thickness of the trench sidewall, which may cause the complete depletion of holes in the trench sidewall and lead to the premature reach-through of the device. In the newly proposed structure, due to the p + -GaN electric field modulation effect, the reach-through phenomenon is effectively suppressed. Therefore, the device can reduce the channel resistance by reducing the channel length to further improve the device performance without considering the problem of premature reach-through of the trench sidewall. In addition, the gate-drain capacitance in the traditional trench MOSFET is large, which requires charging and discharging of the gate-drain capacitance during the switching process of the device, which may lead to large switching losses. In the proposed new structure, the gate is coated with a p + -GaN layer and p-island, shielding the electric field lines between the gate and the drain, which will significantly reduce the gate-drain capacitance, make the switching speed of the device faster, and the switching loss smaller, and can be used in high-frequency circuits.
Claims
1. A vertical power MOSFET device with a dual-current aperture, which is sequentially provided with a drain, an n + -GaN substrate, an n - -GaN drift layer, a p + -GaN layer and an n + -GaN layer from bottom to top. The trench etching process passes through the n + -GaN layer but does not pass through the p + -GaN layer. The bottom of the trench is higher than the bottom of the p + -GaN layer, that is, the trench etching does not pass through the p + -GaN layer. To form an electron conduction channel, two n-GaN current apertures are formed by ion implantation or regrowth under the left and right corners of the trench. The trench and the n + -GaN layer are covered with an SiO2 thin film. A gate metal is arranged in the trench, and a source metal is arranged on the side of the SiO2 thin film.
2. The vertical power MOSFET device with a dual-current aperture as described in claim 1, characterized in that, The groove depth is 0.9 μm and the width is 2 μm.
3. The vertical power MOSFET device with a dual-current aperture according to claim 2, characterized in that, The conductive channel is n-type GaN.
4. The vertical power MOSFET device with a dual-current aperture as described in claim 3, characterized in that, The thickness of the SiO2 thin film is 80 nm.
5. The vertical power MOSFET device with a dual-current aperture as described in claim 4, wherein, p between the two current apertures + - The width of the GaN layer is 1.2 μm.
6. The manufacturing method of the vertical power MOSFET device with a dual-current aperture as described in claim 5, characterized in that, It is formed by ion implantation, and the steps are as follows: (1) An epitaxial structure is grown on a substrate, including an n - -GaN drift layer, a p + -GaN layer, and an n + -GaN layer; (2) Use SiO2 as a hard mask on the epitaxial structure for ICP etching to form a groove; (3) Use ion implantation to form a current aperture at the bottom of the groove; (4) Use PECVD to deposit a layer of SiO2 thin film on the bottom and side walls of the groove; (5) Use electron beam evaporation to form the gate metal; (6) Use electron beam evaporation to form the source and drain of the ohmic contact.
7. The manufacturing method of a vertical power MOSFET device with a dual-current aperture as claimed in claim 5, wherein, It is formed by secondary epitaxy, and the steps are as follows: (a) Growth of an n - -GaN drift layer and a p + -GaN layer, where the thickness of the p + -GaN layer is at least one-third of the designed thickness; (b) On p + -ICP etching is carried out using SiO2 as a hard mask on the GaN layer to form two grooves; (c) Cover the mask outside the groove, and use the secondary epitaxy process to grow the n-GaN current aperture at the groove; (d) Remove the SiO2 mask and epitaxially grow a complete p + - GaN layer thickness, p + - n is grown on the p-GaN layer + - GaN layer; (e) Use SiO2 as a hard mask for ICP trench etching to form a trench; (f) Remove the surface SiO2 hard mask, perform post-annealing treatment, and use PECVD to partially deposit a layer of SiO2 thin film on the bottom and side walls of the trench; (g) Use electron beam evaporation to form the gate metal; (h) Use electron beam evaporation to form the source and drain of the ohmic contact.