Manufacturing method and device of ER193 type double-differential comparator circuit

Abstract

The invention provides a manufacturing method and device of an ER193 type double-differential comparator circuit, and belongs to the technical field of semiconductor manufacturing. According to the manufacturing method of the ER193 type double-differential comparator circuit, it is ensured that drift of an epitaxial layer is corrected in the upper isolation photoetching process by adjusting the isolation photoetching position of a wafer, and even if the epitaxial layer drifts, the epitaxial layer does not drift, so that the reliability of the ER193 type double-differential comparator circuit is improved. The photoetching pattern can still be accurately formed on the wafer, and poor circuit function or inconsistent electrical performance caused by alignment errors is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a manufacturing method and device for an ER193 type dual differential comparator circuit. Background Art

[0002] The ER193 type dual differential comparator circuit adopts a bipolar process, mainly referring to using bipolar transistors as basic elements. This process has a relatively high switching speed and gain, and is suitable for high-frequency and high-precision applications. The dual differential comparator can compare two input signals and output a signal representing the relationship between the two, and is usually used for signal processing and conversion. Compared with other processes, the bipolar process performs better in signal amplification and response speed, and is suitable for high-speed signal processing. Due to its characteristics, the ER193 circuit is widely used in fields such as analog-to-digital conversion, data acquisition, and high-frequency communication.

[0003] The ER193 type dual differential comparator circuit generally adopts a bipolar process. Unidirectional isolation requires a relatively long high-temperature process, which affects the service life of the furnace tube. Moreover, the growth characteristics of the epitaxial structure determine the phenomenon of the buried layer pattern drifting on the epitaxial layer. This phenomenon will cause harm to the process, resulting in a zero breakdown voltage between islands and unsuccessful isolation. Summary of the Invention

[0004] The present invention provides a manufacturing method and device for an ER193 type dual differential comparator circuit, aiming to solve the defect that the electrical isolation of the ER193 type dual differential comparator circuit in the prior art is prone to failure, and achieve the effect of normal circuit function.

[0005] The present invention provides a manufacturing method for an ER193 type dual differential comparator circuit, including: After performing lower isolation processing on the wafer, it is determined to remove the surface oxide layer of the wafer; It is determined that the wafer forms an epitaxial layer and upper isolation oxidation is performed on the wafer; When performing upper isolation lithography, it is determined to adjust the isolation lithography position of the wafer to correct the drift of the epitaxial layer; It is determined to perform pre-diffusion and re-diffusion on the wafer after correcting the drift of the epitaxial layer to obtain a target circuit on the wafer.

[0006] According to the manufacturing method for an ER193 type dual differential comparator circuit provided by the present invention, the adjustment of the isolation lithography position of the wafer to correct the drift of the epitaxial layer includes: When the alignment parameters of the lithography machine for performing upper isolation lithography are in an adjustable state, based on the drift direction and magnitude of the epitaxial layer on the wafer, the alignment parameters of the lithography machine are adjusted.

[0007] A manufacturing method of an ER193 type double differential comparator circuit provided by the present invention, adjusting the alignment parameters of a lithography machine based on the drift direction and magnitude of an epitaxial layer on a wafer, includes: Adjusting the alignment parameters of the lithography machine to drift the alignment position of the lithography machine in the opposite direction of the drift direction of the epitaxial layer by a length equal to the thickness of the epitaxial layer.

[0008] A manufacturing method of an ER193 type double differential comparator circuit provided by the present invention, adjusting the isolation lithography position of the wafer to correct the drift of the epitaxial layer, includes: In the case where the alignment parameters of the lithography machine for upper isolation lithography are in an unadjustable state, determining that an etching mark for etching an isolation region in a layout for upper isolation lithography deviates from a target offset amount in a target offset direction based on the drift direction and magnitude of the epitaxial layer on the wafer.

[0009] A manufacturing method of an ER193 type double differential comparator circuit provided by the present invention, the target offset direction is the opposite direction of the drift direction of the epitaxial layer, and the target offset amount is the thickness magnitude of the epitaxial layer.

[0010] A manufacturing method of an ER193 type double differential comparator circuit provided by the present invention, after performing lower isolation processing on the wafer and before determining to remove the surface oxide layer of the wafer, the method further includes: Determining to perform buried layer oxidation on the wafer; After buried layer oxidation, determining to perform arsenic implantation and arsenic annealing on the wafer respectively; Determining to perform lower isolation oxidation, lower isolation lithography, lower isolation implantation, and lower isolation annealing on the wafer respectively.

[0011] A manufacturing method of an ER193 type double differential comparator circuit provided by the present invention, after determining to perform pre-diffusion and re-diffusion on the wafer after correcting the drift of the epitaxial layer, the method includes: Determining to perform base region oxidation, base region pre-diffusion, boron silicate glass removal, and base region re-diffusion on the wafer respectively; Determining to perform emitter region lithography, emitter region pre-diffusion, phosphorus silicate glass removal, and emitter region re-diffusion on the wafer; Determining to perform via hole lithography and metal sputtering on the wafer.

[0012] The present invention also provides a manufacturing apparatus for an ER193 type double differential comparator circuit, including: A first processing module, configured to determine to remove the surface oxide layer of the wafer after performing lower isolation processing on the wafer; A second processing module, configured to determine that the wafer forms an epitaxial layer and perform upper isolation oxidation on the wafer; A third processing module, configured to determine an isolation lithography position for adjusting a wafer to correct epitaxial layer drift during upper isolation lithography; A fourth processing module, configured to determine pre-diffusion and re-diffusion for the wafer after correcting the epitaxial layer drift, so as to obtain a target circuit on the wafer.

[0013] The present invention further provides an ER193 type dual differential comparator circuit, which is manufactured by using the manufacturing method of any of the ER193 type dual differential comparator circuits.

[0014] The present invention further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the program, the manufacturing method of any of the ER193 type dual differential comparator circuits as described above is implemented.

[0015] The present invention further provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the manufacturing method of any of the ER193 type dual differential comparator circuits as described above is implemented.

[0016] The present invention further provides a computer program product, including a computer program, and when the computer program is executed by a processor, the manufacturing method of any of the ER193 type dual differential comparator circuits as described above is implemented.

[0017] The manufacturing method and device of the ER193 type dual differential comparator circuit provided by the present invention ensure the correction of epitaxial layer drift during upper isolation lithography by adjusting the isolation lithography position of the wafer. Even if the epitaxial layer drifts, the lithography pattern can still be accurately formed on the wafer, avoiding circuit malfunction or inconsistent electrical performance caused by alignment errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 is one of the flow schematic diagrams of the manufacturing method of the ER193 type dual differential comparator circuit provided by the present invention; Figure 2 is the second of the flow schematic diagrams of the manufacturing method of the ER193 type dual differential comparator circuit provided by the present invention; Figure 3It is a schematic structural diagram of a manufacturing apparatus for an ER193 type dual differential comparator circuit provided by the present invention; Figure 4 It is a schematic structural diagram of an electronic device provided by the present invention. Detailed implementation manners

[0020] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without making creative efforts based on the embodiments in the present invention belong to the scope of protection of the present invention.

[0021] The following combines Figures 1 - 4 to describe the manufacturing method and apparatus for an ER193 type dual differential comparator circuit of the present invention.

[0022] The manufacturing method for an ER193 type dual differential comparator circuit according to an embodiment of the present invention mainly includes step 110, step 120, step 130 and step 140.

[0023] Step 110, after performing lower isolation processing on the wafer, determine to remove the surface oxide layer of the wafer; Step 120, determine that the wafer forms an epitaxial layer and perform upper isolation oxidation on the wafer; Step 130, when performing upper isolation lithography, determine to adjust the isolation lithography position of the wafer to correct the epitaxial layer drift; Step 140, determine to perform pre-diffusion and re-diffusion on the wafer after correcting the epitaxial layer drift to obtain a target circuit on the wafer.

[0024] In this embodiment, the above steps are a series of process steps related to wafer processing in the semiconductor manufacturing process.

[0025] The process of removing the surface oxide layer of the wafer is to process the surface of the wafer. Usually, it is to remove the oxide layer (the oxide layer formed in the previous process steps) to facilitate the smooth progress of subsequent processes. The removal of the oxide layer is usually to ensure that subsequent processes (such as epitaxial growth, circuit design, etc.) can be more accurate and efficient.

[0026] In the semiconductor manufacturing process, the oxide layer is usually used for protection or electrical isolation, but it needs to be removed in some steps to perform more refined processing. For example, after removing the oxide layer, other types of surface treatment or epitaxial growth can be performed.

[0027] The step of forming an epitaxial layer on the wafer and performing upper isolation oxidation is to grow an epitaxial layer on the wafer surface. The epitaxial layer is usually formed through an epitaxial growth process and can be made of materials such as single-crystalline silicon. The formation of the epitaxial layer is to enhance the characteristics of the wafer, such as improving electrical performance.

[0028] Epitaxial growth is a process in which atoms (or molecules) of a certain substance are regularly arranged and grow directionally on the surface of a crystal (generally called a substrate) that has been microfabricated. The grown epitaxial layer is a continuous, smooth, and single-crystalline layer that has a corresponding relationship with the lattice structure of the substrate. In the bipolar process of integrated circuit manufacturing, when growing an epitaxial layer on a single crystal wafer, the problem of introducing buried layer drift will occur.

[0029] After epitaxial growth, an oxidation treatment (upper isolation oxidation) is performed on the surface. This oxide layer can act as an isolation layer to prevent electrical interference between different regions or be used in subsequent lithography processes.

[0030] During the growth process of the epitaxial layer, "drift" or non-uniform distribution of the epitaxial layer may occur due to factors such as temperature, material differences, and equipment deviations. At this time, it is necessary to adjust the lithography position to ensure that the position of the pattern during the lithography process matches the actual distribution of the epitaxial layer and avoid errors.

[0031] For example, in the LM193 standard process, it is necessary to grow N-epitaxy on a P single-crystal substrate, and the pattern will drift during the N-epitaxy growth. This phenomenon is caused by the growth characteristics of the epitaxial layer.

[0032] The diffusion process is a process of introducing dopants (such as boron, phosphorus, etc.) into the wafer interior. Prediffusion and re-diffusion are usually processes of controlling the doping depth and concentration to ensure that the characteristics of the circuit meet the design requirements.

[0033] Usually, after the epitaxial layer treatment, a certain diffusion is first carried out, possibly to form certain electrical characteristics on the wafer surface. In subsequent steps, further diffusion or adjustment of the dopant concentration is performed to ensure that the performance of the final circuit meets the design requirements. Finally, through these diffusion steps, a target circuit with precise electrical characteristics is obtained.

[0034] The above steps refer to a series of process steps in semiconductor manufacturing, such as removing the oxide layer, epitaxial growth, lithography correction, and diffusion, to precisely control the characteristics of the wafer surface and finally obtain a target circuit that meets the design requirements.

[0035] In some embodiments, after the wafer undergoes lower isolation treatment and before determining to remove the surface oxide layer of the wafer, the manufacturing method of the ER193 type dual differential comparator circuit further includes the following process.

[0036] It is possible to first determine the buried oxide of the wafer; after the buried oxide, determine the arsenic implantation and arsenic annealing of the wafer respectively; determine the lower isolation oxidation, lower isolation lithography, lower isolation implantation and lower isolation annealing of the wafer respectively.

[0037] The entire process of the buried oxide process flow consists of 16 steps in total, and the process is as follows.

[0038] The first step: Take out the boat for 15 minutes. In the standby state of the equipment, in order to maintain cleanliness, place the quartz boat in the furnace tube and take out the boat when making wafers.

[0039] The second step: Cool down for 10 minutes. Since the temperature of the furnace tube is 800 °C, it is still in a high-temperature state after taking out the boat, so it needs to be cooled to a certain temperature before loading the wafers.

[0040] The third step: Load the wafers for 10 minutes. Load the wafers that need to form the oxide layer onto the quartz boat.

[0041] The fourth step: Insert the boat for 17 minutes. After loading the wafers, send the quartz boat into the furnace tube for processing.

[0042] The fifth step: Hold for 15 minutes to ensure that the temperature and gas atmosphere inside the furnace tube are stable after inserting the boat.

[0043] The sixth step: Heat up for 64 minutes. The diffusion furnace heats up 5 °C per minute, and after 64 minutes, it reaches the process temperature of 1120 °C.

[0044] The seventh step: Dry oxygen for 5 minutes, temperature: 1120 °C, oxygen flow rate 8 L / min, in order to obtain a dense silicon dioxide surface, thereby improving the ability to block impurities.

[0045] The eighth step: DCE for 5 minutes, temperature 1120 °C, oxygen flow rate 8 L / min, and at the same time use small nitrogen to carry trichloroethylene (DCE) with a flow rate of 0.05 L / min. Chlorine-doped oxidation is to add a certain amount of chlorine-containing gas in the oxidation atmosphere, such as HCl, C2HCl3, etc. Chlorine-doped oxidation can reduce the contamination of sodium ions in silicon dioxide, inhibit oxidation stacking faults, and improve the quality of the oxide film. It is a commonly used oxidation method.

[0046] The ninth step: Dry oxygen for 5 minutes, temperature: 1120 °C, oxygen flow rate 8 L / min, react most heavy metal atoms with chlorine to form volatile gaseous chlorides and discharge them outside the furnace tube to ensure the purity of the oxide layer.

[0047] Step 10: Wet oxidation for 85 min, temperature 1120°C, oxygen flow rate 7 L / min, hydrogen flow rate 10 L / min. Wet oxidation is mainly used to form the required thickness of the silicon dioxide film and improve production efficiency. If it is used as a masking film for impurity diffusion, its thickness is mainly determined by the junction depth formed by diffusion and the diffusion temperature. That is, first, the diffusion time required needs to be determined, and then the thickness of the oxide film required to block the diffusion of impurities in silicon dioxide under this diffusion time needs to be determined.

[0048] Step 11: Dry oxidation for 5 min, temperature: 1120°C, oxygen flow rate 8 L / min. React most heavy metal atoms with chlorine to form volatile gaseous chlorides and discharge them outside the furnace tube to ensure the purity of the oxide layer.

[0049] Step 12: Cooling for 104 min. The oxidation process is completed, and the temperature needs to be reduced to the standby temperature of the equipment. Generally, the cooling rate is 3°C / min.

[0050] Step 13: Boat unloading for 15 min. After the temperature drops to the standby temperature, the equipment starts to unload the boat.

[0051] Step 14: Cooling for 10 min. Since the furnace tube temperature is 800°C, it is still in a high-temperature state after boat unloading, so it needs to be cooled to a certain temperature before the wafer can be removed.

[0052] Step 15: Boat loading for 17 min. In the standby state of the equipment, to maintain cleanliness, the quartz boat is placed in the furnace tube.

[0053] Step 16: The entire process flow is completed, and the equipment is in standby.

[0054] During the buried layer lithography process, it mainly goes through processes such as HMDS, coating (using negative photoresist with a thickness of 19000 ± 2000 Å), pre-baking (30 min), alignment, development, hardening (30 min), wet etching (oxide layer etching: using BOE solution for 10 min), and resist stripping (removing solution for 10 min).

[0055] The implantation dose of arsenic As is 5E+15, and the measured value of the sheet resistance is 15 ± 3 Ω / sq.

[0056] The process flow of arsenic annealing is as follows in 13 steps.

[0057] Step 1: Boat unloading for 15 min. In the standby state of the equipment, to maintain cleanliness, the quartz boat is placed in the furnace tube, and the boat is unloaded when wafers need to be processed.

[0058] Step 2: Cooling for 10 min. Since the furnace tube temperature is 800°C, it is still in a high-temperature state after boat unloading, so it needs to be cooled to a certain temperature before the wafer can be loaded.

[0059] Step 3: Load the wafers for 10 min. Load the wafers that need to have an oxide layer onto the quartz boat.

[0060] Step 4: Insert the boat for 17 min. After loading the wafers, send the quartz boat into the furnace tube to carry out the process.

[0061] Step 5: Hold for 15 min. Ensure that the temperature and gas atmosphere inside the furnace tube are stable after inserting the boat.

[0062] Step 6: Heat up for 80 min. The diffusion furnace heats up at a rate of 5 °C per minute for 1 minute, and reaches the process required temperature of 1200 °C after 80 min.

[0063] Step 7: Dry oxidation for 60 min. Temperature: 1200 °C, oxygen flow rate 8 L / min, in order to obtain a dense silicon dioxide surface, thereby improving the ability to block impurities.

[0064] Step 8: Nitrogen push and diffusion for 300 min. Temperature 1200 °C, nitrogen flow rate 8 L / min, carry out impurity diffusion, and this time can reach the required junction depth.

[0065] Step 9: Cool down for 114 min. After the oxidation process is completed, the temperature needs to be lowered to the standby temperature of the equipment. Generally, the cooling rate is 3 °C / min.

[0066] Step 10: Remove the boat for 15 min. After the temperature drops to the standby temperature, the equipment starts to remove the boat. Step 11: Cool down for 10 min. Since the furnace tube temperature is 800 °C, it is still in a high temperature state after removing the boat, so it needs to be cooled down to a certain temperature before the wafers can be removed.

[0067] Step 12: Insert the boat for 17 min. In the standby state of the equipment, place the quartz boat in the furnace tube to keep it clean.

[0068] Step 13: The entire process flow is completed, and the equipment is in standby.

[0069] After that, carry out the next isolation oxidation process, and the entire process has a total of 16 steps.

[0070] Step 1: Remove the boat for 15 min. In the standby state of the equipment, place the quartz boat in the furnace tube to keep it clean, and remove the boat when making wafers is needed.

[0071] Step 2: Cool down for 10 min. Since the furnace tube temperature is 800 °C, it is still in a high temperature state after removing the boat, so it needs to be cooled down to a certain temperature before the wafers can be loaded.

[0072] Step 3: Load the wafers for 10 min. Load the wafers that need to have an oxide layer onto the quartz boat.

[0073] Step 4: After 17 minutes of boat entry, after the wafers are loaded, the quartz boat is sent into the furnace tube for the process.

[0074] Step 5: Hold for 15 minutes to ensure that the temperature and gas atmosphere inside the furnace tube are stable after boat entry.

[0075] Step 6: Heat up for 58 minutes. The diffusion furnace heats up by 5 °C per minute for 1 minute, and reaches the process temperature of 1090 °C after 58 minutes.

[0076] Step 7: Dry oxygen for 5 minutes, temperature: 1090 °C, oxygen flow rate 8 L / min, to obtain a dense silicon dioxide surface, thereby improving the ability to block impurities.

[0077] Step 8: DCE for 5 minutes, temperature 1090 °C, oxygen flow rate 8 L / min, and at the same time use small nitrogen to carry trichloroethylene (DCE) with a flow rate of 0.05 L / min. Chlorine-doped oxidation is to add a certain amount of chlorine-containing gas in the oxidation atmosphere, such as HCl, C2HCl3, etc. Chlorine-doped oxidation can reduce the contamination of sodium ions in silicon dioxide, inhibit oxidation stacking faults, and improve the quality of the oxide film. It is a commonly used oxidation method.

[0078] Step 9: Dry oxygen for 5 minutes, temperature: 1090 °C, oxygen flow rate 8 L / min, to react most heavy metal atoms with chlorine to form volatile gaseous chlorides and discharge them outside the furnace tube to ensure the purity of the oxide layer.

[0079] Step 10: Wet oxygen for 88 minutes, temperature 1090 °C, oxygen flow rate 7 L / min, hydrogen flow rate 10 L / min. Wet oxygen is mainly used to form the required thickness of the silicon dioxide film and improve production efficiency. If it is used as a masking film for impurity diffusion, its thickness is mainly determined by the junction depth formed by diffusion and the diffusion temperature, that is, first determine the diffusion time required, and then determine how thick an oxide film is needed to block the diffusion of impurities in silicon dioxide under this diffusion time.

[0080] Step 11: Dry oxygen for 5 minutes, temperature: 1090 °C, oxygen flow rate 8 L / min. After wet oxygen oxidation, the presence of surface silanol reduces the adhesion between silicon dioxide and photoresist. Therefore, a second dry oxygen is required to improve the performance of the silicon dioxide and silicon interface, and at the same time dry the silicon dioxide surface to improve the adhesion between silicon dioxide and photoresist.

[0081] Step 12: Cool down for 94 minutes. After the oxidation process is completed, the temperature needs to be lowered to the standby temperature of the equipment. Generally, the cooling rate is 3 °C / min.

[0082] Step 13: Unload the boat for 15 minutes. After the temperature drops to the standby temperature, the equipment starts to unload the boat. The fourteenth step: Cool down for 10 min. Since the temperature of the furnace tube is 800 °C, it is still in a high-temperature state after taking out the boat. Therefore, it needs to be cooled to a certain temperature before the wafer can be removed.

[0083] The fifteenth step: Insert the boat for 17 min. In the standby state of the equipment, to maintain cleanliness, place the quartz boat in the furnace tube.

[0084] The sixteenth step: The entire process flow is completed, and the equipment is in standby.

[0085] The process of lower isolation lithography includes HMDS, coating (using negative photoresist with a thickness of 19000 ± 2000 Å), pre-baking (30 min), alignment, development, hard baking (30 min), wet etching (oxide layer etching: use solution BOE to etch for 10 min), and resist stripping (using stripping solution for 10 min).

[0086] The implantation dose of lower isolation implantation is 8E+14, and the measured sheet resistance is 140 ± 20 Ω / sq.

[0087] The lower isolation annealing mainly includes the following steps.

[0088] The first step: Take out the boat for 15 min. In the standby state of the equipment, to maintain cleanliness, place the quartz boat in the furnace tube and take out the boat when making wafers.

[0089] The second step: Cool down for 10 min. Since the temperature of the furnace tube is 800 °C, it is still in a high-temperature state after taking out the boat. Therefore, it needs to be cooled to a certain temperature before loading the wafer.

[0090] The third step: Load the wafer for 10 min. Load the wafers that need to form the oxide layer onto the quartz boat.

[0091] The fourth step: Insert the boat for 17 min. After loading the wafer, send the quartz boat into the furnace tube for the process.

[0092] The fifth step: Hold for 15 min to ensure that the temperature and gas atmosphere inside the furnace tube are stable after inserting the boat.

[0093] The sixth step: Heat up for 56 min. The temperature of the diffusion furnace rises by 5 °C per minute, and reaches the process required temperature of 1080 °C after 56 min.

[0094] The seventh step: Drive the junction for 60 min. The junction depth formed by diffusion is determined by the diffusion temperature and time.

[0095] The eighth step: Cool down for 94 min. After the oxidation process is completed, the temperature needs to be cooled to the standby state temperature of the equipment. Generally, the cooling rate is 3 °C / min.

[0096] Step 9: Boat out for 15 minutes. After the temperature drops to the standby temperature, the equipment starts to boat out. Step 10: Cool down for 10 minutes. Since the temperature of the furnace tube is 800 °C, it is still in a high-temperature state after the boat out, so it needs to be cooled down to a certain temperature before the wafer can be removed.

[0097] Step 11: Boat in for 17 minutes. In the standby state of the equipment, to maintain cleanliness, the quartz boat is placed in the furnace tube.

[0098] Step 16: The entire process flow is completed and the equipment is on standby.

[0099] After this step, the removal of the surface oxide layer starts, and then epitaxial growth is carried out. The requirements for epitaxial growth are determined according to specific product characteristics, such as a width of 12 ± 0.2 μm.

[0100] The process of upper isolation oxidation can refer to the process of lower isolation oxidation. The process of upper isolation lithography is as follows: HMDS, spin coating (using negative photoresist with a thickness of 19000 ± 2000 Å), pre-baking (30 minutes), alignment, development, hard baking (30 minutes), wet etching (oxide layer etching: using solution BOE to etch for 10 minutes), and resist stripping (using stripping solution for 10 minutes).

[0101] During the lithography process, ultraviolet light is used to irradiate the photoresist on the wafer through a mask. Through steps such as exposure and development, the pattern is transferred to the wafer surface. This pattern creates the structure of the circuit on the wafer.

[0102] When the epitaxial layer drifts, it may cause the misalignment of the position on the wafer surface with the designed pattern. To correct this, it is crucial to adjust the lithography position.

[0103] In some embodiments, to correct the offset caused by the drift of the epitaxial layer, it is necessary to align the positioning of the lithography pattern with the actual position of the epitaxial layer by finely adjusting the position of the mask.

[0104] In some embodiments, during the lithography process, alignment marks are usually used to ensure the correct alignment of the lithography pattern. If the epitaxial layer drifts, it is necessary to recalibrate the positions of these alignment marks.

[0105] In some embodiments, the exposure time, exposure intensity, or other process parameters can also be adjusted to compensate for the impact of epitaxial layer drift on pattern positioning.

[0106] By adjusting the lithography position to correct the epitaxial layer drift, it is ensured that the lithography pattern can be accurately transferred to the wafer surface, avoiding pattern offset caused by the drift of the epitaxial layer, which ultimately affects the function and performance of the circuit. The upper isolation lithography is not only for defining the circuit structure, but may also involve the precise positioning of the electrical isolation area. Uncorrected drift will affect the integrity of these isolation areas, thus affecting the normal operation of the circuit. The semiconductor manufacturing process requires extremely high precision and consistency. Through this position correction, the high precision and stability of the entire manufacturing process are ensured, and the final product is guaranteed to meet the design specifications.

[0107] According to the manufacturing method of the ER193 type dual differential comparator circuit provided by the embodiment of the present invention, by adjusting the isolation lithography position of the wafer, it is ensured that the epitaxial layer drift is corrected during the upper isolation lithography process. Even if the epitaxial layer drifts, the lithography pattern can still be accurately formed on the wafer, avoiding poor circuit function or inconsistent electrical performance caused by alignment errors.

[0108] After lithography, upper isolation pre-diffusion can be carried out, which mainly includes the following steps.

[0109] The first step: Take out the boat for 15 minutes. In the standby state of the equipment, in order to maintain cleanliness, place the quartz boat in the furnace tube and take out the boat when wafers need to be processed.

[0110] The second step: Cool down for 10 minutes. Since the furnace tube temperature is 800 °C, it is still in a high-temperature state after taking out the boat, so it needs to be cooled to a certain temperature before loading the wafers.

[0111] The third step: Load the wafers for 10 minutes. Load the wafers that need to form the oxide layer onto the quartz boat.

[0112] The fourth step: Insert the boat for 17 minutes. After loading the wafers, send the quartz boat into the furnace tube for processing.

[0113] The fifth step: Hold for 15 minutes to ensure that the temperature and gas atmosphere inside the furnace tube are stable after inserting the boat.

[0114] The sixth step: Heat up for 44 minutes. The diffusion furnace heats up 5 °C per minute, and reaches the process required temperature of 1020 °C after 56 minutes.

[0115] The seventh step: Diffuse for 14 minutes to diffuse the impurity source on the boron source wafer to form a shallow junction on the wafer surface.

[0116] The eighth step: Cool down for 74 minutes. After the process flow is completed, the temperature needs to be reduced to the standby state temperature of the equipment. Generally, the cooling rate is 3 °C / min.

[0117] The ninth step: Take out the boat for 15 minutes. After the temperature drops to the standby temperature, the equipment starts to take out the boat. Step 10: Cool down for 10 min. Since the temperature of the furnace tube is 800 °C, it is still in a high-temperature state after taking out the boat. Therefore, it needs to be cooled to a certain temperature before the wafer can be removed.

[0118] Step 11: Insert the boat for 17 min. In the standby state of the equipment, to maintain cleanliness, place the quartz boat in the furnace tube.

[0119] Step 12: The entire process flow is completed, and the equipment is in standby.

[0120] On this basis, upper isolation and re-diffusion can be carried out, mainly including the following processes.

[0121] Step 1: Take out the boat for 15 min. In the standby state of the equipment, to maintain cleanliness, place the quartz boat in the furnace tube and take out the boat when making wafers.

[0122] Step 2: Cool down for 10 min. Since the temperature of the furnace tube is 800 °C, it is still in a high-temperature state after taking out the boat. Therefore, it needs to be cooled to a certain temperature before loading the wafer.

[0123] Step 3: Load the wafer for 10 min. Load the wafers that need to form the oxide layer onto the quartz boat.

[0124] Step 4: Insert the boat for 17 min. After loading the wafer, send the quartz boat into the furnace tube for processing.

[0125] Step 5: Hold for 15 min. Ensure that the temperature and gas atmosphere inside the furnace tube are stable after inserting the boat.

[0126] Step 6: Heat up for 76 min. The temperature of the diffusion furnace increases by 5 °C per minute during heating. After 76 min, it reaches the process temperature of 1180 °C.

[0127] Step 7: Dry nitrogen for 200 min, temperature: 1180 °C, nitrogen flow rate: 8 L / min. After a large number of experiments, a complete isolation state can be achieved in 200 min.

[0128] Step 8: Cool down for 34 min. After isolation is completed, low-temperature silicon dioxide is fabricated after high-temperature drive-in. Generally, the cooling rate is 3 °C / min.

[0129] Step 9: Dry oxygen for 5 min, temperature: 1050 °C, oxygen flow rate: 8 L / min. Oxygen is introduced into the furnace tube for 5 min before hydrogen-oxygen synthesis to ensure the gas atmosphere in the furnace tube and the safety of hydrogen-oxygen synthesis.

[0130] Step 10: Wet oxygen for 45 min, temperature: 1050 °C, oxygen flow rate: 7 L / min, hydrogen flow rate: 10 L / min. Wet oxygen is mainly used to form the required thickness of the silicon dioxide film and improve production efficiency.

[0131] The eleventh step: Dry oxidation for 5 minutes, temperature: 1050 °C, oxygen flow rate 8 L / min. After wet oxidation, the presence of surface silanol reduces the adhesion between silica and photoresist. Therefore, a second dry oxidation is required to improve the performance of the silica and silicon interface and also dry the silica surface to enhance the adhesion between silica and photoresist.

[0132] The twelfth step: Cool down for 84 minutes. The oxidation process is completed, and the temperature needs to be reduced to the standby temperature of the equipment. Generally, the cooling rate is 3 °C / min.

[0133] The thirteenth step: Unload the boat for 15 minutes. After the temperature drops to the standby temperature, the equipment starts to unload the boat. The fourteenth step: Cool down for 10 minutes. Since the furnace tube temperature is 800 °C, the wafer is still in a high-temperature state after unloading the boat. Therefore, it needs to be cooled to a certain temperature before the wafer can be removed.

[0134] The fifteenth step: Load the boat for 17 minutes. In the standby state of the equipment, to maintain cleanliness, the quartz boat is placed in the furnace tube.

[0135] The sixteenth step: The entire process flow is completed, and the equipment is in standby.

[0136] In some embodiments, adjusting the isolation lithography position of the wafer to correct epitaxial layer drift includes: when the alignment parameters of the lithography machine for upper isolation lithography are in an adjustable state, adjusting the alignment parameters of the lithography machine based on the drift direction and magnitude of the epitaxial layer on the wafer.

[0137] During the exposure process of the lithography machine, it is necessary to accurately align the designed pattern with the existing structures (such as epitaxial layer, oxide layer, metal layer, etc.) on the wafer surface. Alignment is achieved through the alignment system in the lithography machine. Usually, the lithography machine uses a set of alignment marks to ensure the accurate position of the pattern on the wafer.

[0138] Alignment parameters refer to the settings and parameters in the lithography machine used to control and adjust the alignment process, mainly including position offset, rotation angle, and scaling factor.

[0139] The position offset is the relative position between the alignment marks on the wafer and the photomask pattern. The rotation angle is the relative rotation between the photomask and the wafer. The scaling factor is the scaling degree of the lithography pattern on the wafer. These parameters determine whether the lithography pattern can be accurately aligned with the existing structures on the wafer.

[0140] In some cases, the epitaxial layer may have drifted (e.g., shifted in a certain direction or having non-uniform thickness). This will cause an alignment error between the lithography pattern and the epitaxial layer. To correct this error, it is necessary to adjust the alignment parameters of the lithography machine according to the drift direction and magnitude of the epitaxial layer.

[0141] In this embodiment, by measuring or estimating the drift direction and degree of the epitaxial layer, it is possible to determine how to adjust the alignment during the lithography process. For example, if the epitaxial layer is offset in a specific direction, the alignment system of the lithography machine can correspondingly adjust the position of the alignment mark, so that the lithography pattern is realigned with the existing structure on the wafer.

[0142] The alignment system of the lithography machine is usually adjustable, which means that the alignment parameters of the lithography machine can be adjusted manually or automatically to compensate for this deviation. For example, adjusting the offset in the X and Y directions, or adjusting the rotation angle to correct the drift of the epitaxial layer.

[0143] On a lithography machine with adjustable alignment parameters, the correction scheme is to compensate for the drift effect by adjusting the alignment parameters of the lithography machine. Specifically, since the drift direction and magnitude of the epitaxial layer are known, the drift of the epitaxial pattern can be corrected by adjusting the alignment of the lithography machine (usually the offset in the left-right direction). This adjustment directly acts on the alignment system of the lithography machine, and by compensating for the drift, ensures that the pattern in the lithography process is aligned with the actual required position. Since the amount of drift is usually the same as the thickness of the epitaxial layer, this can eliminate the influence of drift by offsetting a certain amount to the left during alignment.

[0144] For example, for the i9C lithography machine, when adjusting the alignment parameters during the isolation lithography alignment, offsetting the data equivalent to the thickness of the epitaxial layer to the left can correct the buried layer drift effect.

[0145] When the epitaxial layer drifts, in order to ensure that the pattern of the upper isolation lithography can be accurately transferred to the wafer surface, it is necessary to adjust the alignment parameters of the lithography machine (such as position offset, rotation angle, etc.) to compensate for the drift of the epitaxial layer. This adjustment is based on the drift direction and magnitude of the epitaxial layer, with the aim of ensuring the pattern alignment accuracy during the lithography process to guarantee the performance and quality of the final semiconductor device.

[0146] In some embodiments, based on the drift direction and magnitude of the epitaxial layer on the wafer, the alignment parameters of the lithography machine are adjusted, including: adjusting the alignment parameters of the lithography machine to drift the alignment position of the lithography machine in the opposite direction of the drift direction of the epitaxial layer by a length equal to the thickness of the epitaxial layer.

[0147] In other words, according to the drift direction and magnitude of the epitaxial layer, the alignment parameters of the lithography machine are adjusted so that the alignment position of the lithography machine is offset in the opposite direction of the drift of the epitaxial layer, corresponding to the drift amount of the epitaxial layer, thereby compensating for the drift of the epitaxial layer.

[0148] In some embodiments, adjusting the isolation lithography position of the wafer to correct the epitaxial layer drift includes, when the alignment parameters of the lithography machine for upper isolation lithography are in an unadjustable state, determining that the etching mark for the etched isolation region in the layout for upper isolation lithography deviates from the target offset amount in the target offset direction based on the drift direction and magnitude of the epitaxial layer on the wafer.

[0149] When performing upper isolation lithography, if the alignment parameters of the lithography machine are unadjustable (i.e., it is impossible to directly compensate for the epitaxial layer drift by adjusting the alignment of the lithography machine), it is necessary to indirectly compensate for the epitaxial layer drift by adjusting the etching mark in the layout design.

[0150] The unadjustability of the lithography machine alignment parameters means that the alignment system of the lithography machine cannot be manually adjusted or the alignment parameters cannot be dynamically adjusted during the lithography process. Therefore, it is impossible to correct the epitaxial layer drift by directly adjusting the alignment position of the lithography machine.

[0151] Since the alignment of the lithography machine cannot be adjusted, the drift can be indirectly compensated by adjusting the layout design. Specifically, when designing the layout for upper isolation lithography, the etching mark (the graphical feature used to identify the isolation region) will be adjusted according to the drift of the epitaxial layer.

[0152] According to the drift direction and magnitude of the epitaxial layer, the etching mark in the layout is offset in the target offset direction. The purpose of this is that during the etching process, the etching mark can be aligned with the actual position of the epitaxial layer, thereby ensuring that the position of the finally etched isolation region is correct.

[0153] This offset amount is determined according to the magnitude of the epitaxial layer drift. For example, if the epitaxial layer is offset by 0.5 microns, then the etching mark in the layout also needs to be offset by 0.5 microns in the drift direction to compensate for the influence brought by the drift.

[0154] For some lithography machines that cannot adjust the alignment parameters, drift compensation cannot be performed on the lithography machine itself. Therefore, in this case, the solution is to correct the drift by modifying the layout design itself. Specifically, when designing the layout, the etching mark for the etched isolation region is offset to the left, and this offset amount is the same as the thickness of the epitaxial layer.

[0155] In this way, although the lithography machine cannot dynamically adjust the alignment, the drift effect can be compensated through design-level compensation. In this case, the offset of the etching region during design is equivalent to reserving space for drift in the design, thereby ensuring that the drift will not have an adverse impact on the final pattern position during the actual manufacturing process.

[0156] In some embodiments, according to the actual offset situation, the target offset direction is the opposite direction of the drift direction of the epitaxial layer, and the target offset amount is the magnitude of the thickness of the epitaxial layer.

[0157] As Figure 2 shown, after determining pre-diffusion and re-diffusion for the wafer after correcting the drift of the epitaxial layer, the manufacturing method of the ER193 type dual differential comparator circuit further includes step 210, step 220, and step 230.

[0158] Step 210, determine to perform base region oxidation, base region pre-diffusion, boron silicate glass removal, and base region re-diffusion on the wafer respectively.

[0159] Step 220, determine to perform emitter region lithography, emitter region pre-diffusion, phosphosilicate glass removal, and emitter region re-diffusion on the wafer; Step 230, determine to perform via hole lithography and metal sputtering on the wafer.

[0160] In the step of base region oxidation, a thin layer of silicon dioxide (SiO2) is formed on the base region of the wafer (usually a silicon substrate). The function of the oxide layer is to isolate different semiconductor regions, prevent impurity diffusion, and provide a protective layer for subsequent processes.

[0161] Base region pre-diffusion is to perform a pre-diffusion process under the oxide layer of the base region. This process usually diffuses a dopant (such as boron) into the base region to form a P-type or N-type semiconductor region. This step is to prepare for the subsequent formation of a PN junction (such as the junction between the base region and the emitter region).

[0162] Boron silicate glass removal may use boron silicate glass (BSG) as a diffusion source or isolation material during the diffusion process. Removing the boron silicate glass is to remove the unnecessary materials to ensure that the crystal structure or circuit function will not be disturbed in subsequent processes.

[0163] The base region re-diffusion step refers to re-diffusing dopants (for example, boron) after the initial diffusion to further adjust the conductivity characteristics of the semiconductor region and ensure the formation of correct electrical regions in the wafer.

[0164] In the stage of emitter region lithography, the position of the emitter region is defined on the surface of the wafer through the lithography process. The lithography process uses a mask and ultraviolet light to transfer the required pattern to the photoresist on the wafer. This step is to accurately define the position of the emitter region on the wafer for subsequent doping and diffusion.

[0165] The step of emitter region pre-diffusion involves diffusing a dopant (such as phosphorus) into the emitter region to form an N-type semiconductor region (if it is an NPN transistor). Pre-diffusion is to ensure that the doping concentration and electrical properties of the emitter region meet the design requirements.

[0166] Phosphosilicate glass is usually used as a diffusion source or a protective layer. After the diffusion is completed, the phosphosilicate glass needs to be removed to avoid affecting subsequent processes or causing non-uniformity on the wafer surface.

[0167] Similar to base re-diffusion, emitter re-diffusion is to re-diffuse dopants into the emitter to ensure that the dopant concentration in the emitter reaches the required level and form an efficient PN junction.

[0168] Via hole lithography is to define the positions of via holes on the wafer through the lithography process. Via holes are used to connect the metal layer on the wafer to the external circuit or the leads in the package. This step prepares for subsequent electrical connections.

[0169] Metal sputtering is a physical vapor deposition technique used to deposit metal thin films (such as aluminum or copper) onto the wafer surface. These metal layers are usually used for the interconnection parts of the circuit. After metal sputtering, subsequent processing such as etching is required to form metal connections in the circuit.

[0170] Through the above steps, it can be ensured that each region and circuit connection are accurately formed on the wafer, ultimately achieving the expected circuit functions.

[0171] Base oxidation mainly includes the following steps.

[0172] The first step: Take out the boat for 15 minutes. In the standby state of the equipment, to maintain cleanliness, place the quartz boat in the furnace tube and take out the boat when making wafers.

[0173] The second step: Cool down for 10 minutes. Since the furnace tube temperature is 800 °C, it is still in a high-temperature state after taking out the boat, so it needs to be cooled to a certain temperature before loading the wafers.

[0174] The third step: Load wafers for 10 minutes. Load the wafers that need to form the oxide layer onto the quartz boat.

[0175] The fourth step: Insert the boat for 17 minutes. After loading the wafers, send the quartz boat into the furnace tube for processing.

[0176] The fifth step: Hold for 15 minutes to ensure that the temperature and gas atmosphere inside the furnace tube are in a stable state after inserting the boat.

[0177] The sixth step: Heat up for 50 minutes. The diffusion furnace heats up 5 °C per minute, and reaches the process required temperature of 1050 °C after 50 minutes.

[0178] The seventh step: Dry oxygen for 10 minutes, temperature: 1050 °C, oxygen flow rate 8 L / min, in order to obtain a dense silicon dioxide surface, thereby improving the ability to block impurities.

[0179] Step 8: Wet oxidation for 45 min, temperature 1050 °C, oxygen flow rate 7 L / min, hydrogen flow rate 10 L / min. Wet oxidation is mainly used to form the required thickness of the silicon dioxide film and improve production efficiency. If it is used as a masking film for impurity diffusion, its thickness is mainly determined by the junction depth formed by diffusion and the diffusion temperature. That is, first, the diffusion time required needs to be determined, and then the thickness of the oxide film required to block the diffusion of impurities in silicon dioxide under this diffusion time needs to be determined.

[0180] Step 9: Dry oxidation for 10 min, temperature: 1050 °C, oxygen flow rate 8 L / min. After wet oxidation, the presence of silanol on the surface reduces the adhesion between silicon dioxide and photoresist. Therefore, a second dry oxidation is required to improve the performance of the silicon dioxide and silicon interface, and at the same time, it can also dry the silicon dioxide surface and improve the adhesion between silicon dioxide and photoresist.

[0181] Step 10: DCE for 10 min, temperature 1050 °C, oxygen flow rate 8 L / min. At the same time, a small amount of nitrogen is used to carry trichloroethylene (DCE) with a flow rate of 0.1 L / min. Chlorine-doped oxidation is to add a certain amount of chlorine-containing gas, such as HCl, C2HCl3, etc. in the oxidation atmosphere. Chlorine-doped oxidation can reduce the contamination of sodium ions in silicon dioxide, inhibit oxidation stacking faults, and improve the quality of the oxide film, which is a commonly used oxidation method.

[0182] Step 11: Dry oxidation for 10 min, temperature: 1050 °C, oxygen flow rate 8 L / min. React most heavy metal atoms with chlorine to form volatile gaseous chlorides and discharge them outside the furnace tube to ensure the purity of the oxide layer.

[0183] Step 12: Cooling down for 83 min. The oxidation process is completed, and the temperature needs to be reduced to the standby temperature of the equipment. Generally, the cooling rate is 3 °C / min.

[0184] Step 13: Boat out for 15 min. After the temperature drops to the standby temperature, the equipment starts to take out the boat. Step 14: Cooling down for 10 min. Since the furnace tube temperature is 800 °C, it is still in a high-temperature state after the boat is taken out. Therefore, it needs to be cooled to a certain temperature before the wafer can be removed.

[0185] Step 15: Boat in for 17 min. In the standby state of the equipment, to maintain cleanliness, the quartz boat is placed in the furnace tube.

[0186] Step 16: The entire process flow is completed, and the equipment is in standby.

[0187] The base region pre-diffusion mainly includes the following steps.

[0188] Step 1: Boat out for 15 min. In the standby state of the equipment, to maintain cleanliness, the quartz boat is placed in the furnace tube and the boat is taken out when wafers need to be processed.

[0189] Step 2: Cool down for 10 min. Since the furnace tube temperature is 800 °C, it is still in a high-temperature state after taking out the boat. Therefore, it needs to be cooled down to a certain temperature before loading the wafers.

[0190] Step 3: Load wafers for 10 min. Load the wafers that need to have an oxide layer onto the quartz boat.

[0191] Step 4: Insert the boat for 17 min. After loading the wafers, send the quartz boat into the furnace tube to carry out the process.

[0192] Step 5: Hold for 15 min. Ensure that the temperature inside the furnace tube and the gas atmosphere are in a stable state after inserting the boat.

[0193] Step 6: Heat up for 27 min. The temperature of the diffusion furnace rises by 5 °C per minute during heating up. After 27 min, it reaches the process required temperature of 935 °C.

[0194] Step 7: Diffuse for 21 min. Diffuse the impurity source on the boron source wafer to the surface of the wafer to form a shallow junction.

[0195] Step 8: Cool down for 45 min. The process flow is completed, and the temperature needs to be cooled down to the equipment standby state temperature. Generally, the cooling rate is 3 °C / min.

[0196] Step 9: Take out the boat for 15 min. After the temperature drops to the standby temperature, the equipment starts to take out the boat. Step 10: Cool down for 10 min. Since the furnace tube temperature is 800 °C, it is still in a high-temperature state after taking out the boat. Therefore, it needs to be cooled down to a certain temperature before removing the wafers.

[0197] Step 11: Insert the boat for 17 min. In the equipment standby state, place the quartz boat in the furnace tube to keep it clean.

[0198] Step 12: The entire process flow is completed, and the equipment is on standby.

[0199] Removal of borosilicate glass: The borosilicate glass film will block diffusion, resulting in the base region junction depth not reaching the required value. Therefore, it needs to be removed here.

[0200] The main steps of the base region re-diffusion are as follows.

[0201] Step 1: Take out the boat for 15 min. In the equipment standby state, place the quartz boat in the furnace tube to keep it clean, and take out the boat when making wafers is needed.

[0202] Step 2: Cool down for 10 min. Since the furnace tube temperature is 800 °C, it is still in a high-temperature state after taking out the boat. Therefore, it needs to be cooled down to a certain temperature before loading the wafers.

[0203] Step 3: Load the wafers for 10 min. Load the wafers that need to have an oxide layer onto the quartz boat.

[0204] Step 4: Insert the boat for 17 min. After loading the wafers, insert the quartz boat into the furnace tube to perform the process.

[0205] Step 5: Hold for 15 min. Ensure that the temperature and gas atmosphere inside the furnace tube are stable after inserting the boat.

[0206] Step 6: Heat up for 66 min. The diffusion furnace heats up at a rate of 5 °C per minute. After 66 min, the temperature reaches the required process temperature of 1130 °C.

[0207] Step 7: Dry nitrogen for 90 min. Temperature: 1130 °C, nitrogen flow rate 8 L / min. The required base region junction depth can be achieved in 90 min.

[0208] Step 8: Dry oxygen for 5 min. Temperature: 1130 °C, oxygen flow rate 8 L / min. To obtain a dense silicon dioxide surface and thus improve the ability to block impurities.

[0209] Step 9: Wet oxygen for 10 min. Temperature 1130 °C, oxygen flow rate 7 L / min, hydrogen flow rate 10 L / min. Wet oxygen is mainly used to form the required thickness of the silicon dioxide film and improve production efficiency. If it is used as a masking film for impurity diffusion, its thickness is mainly determined by the junction depth formed by diffusion and the diffusion temperature. That is, first determine the required diffusion time, and then determine the thickness of the oxide film required to block the diffusion of impurities in silicon dioxide under this diffusion time.

[0210] Step 10: Dry oxygen for 5 min. Temperature: 1130 °C, oxygen flow rate 8 L / min. After wet oxygen oxidation, the presence of silanol on the surface reduces the adhesion between silicon dioxide and photoresist. Therefore, a second dry oxygen treatment is required to improve the performance of the silicon dioxide and silicon interface and at the same time dry the silicon dioxide surface to improve the adhesion between silicon dioxide and photoresist.

[0211] Step 12: Cool down for 110 min. After the oxidation process is completed, the temperature needs to be reduced to the standby temperature of the equipment. Generally, the cooling rate is 3 °C / min.

[0212] Step 13: Remove the boat for 15 min. After the temperature drops to the standby temperature, the equipment starts to remove the boat. Step 14: Cool down for 10 min. Since the furnace tube temperature is 800 °C, it is still at a high temperature after removing the boat, so it needs to be cooled to a certain temperature before the wafers can be removed.

[0213] Step 15: Insert the boat for 17 min. In the standby state of the equipment, to maintain cleanliness, place the quartz boat in the furnace tube.

[0214] Step 16: The entire process flow is completed, and the equipment is on standby.

[0215] The process of emitter lithography is HMDS, spin coating (using negative photoresist with a thickness of 19000 ± 2000 Å), soft bake (30 min), alignment, development, hard bake (30 min), wet etching (oxide layer etching: using BOE solution to etch for 10 min), and stripping (using stripping solution for 10 min).

[0216] The steps of emitter pre-diffusion are mainly as follows.

[0217] Step 1: Unload the boat for 15 min. In the standby state of the equipment, to maintain cleanliness, place the quartz boat in the furnace tube and unload the boat when wafers need to be processed.

[0218] Step 2: Cool down for 10 min. Since the furnace tube temperature is 800 °C, after unloading the boat, it is still in a high-temperature state, so it needs to be cooled to a certain temperature before loading the wafers.

[0219] Step 3: Load wafers for 10 min. Load the wafers that need to have the oxide layer processed onto the quartz boat.

[0220] Step 4: Load the boat into the furnace for 17 min. After loading the wafers, send the quartz boat into the furnace tube for processing.

[0221] Step 5: Hold for 15 min to ensure that the temperature and gas atmosphere inside the furnace tube are stable after loading the boat.

[0222] Step 6: Heat up for 46 min. The diffusion furnace heats up by 5 °C per minute. After 50 min, it reaches the process temperature of 1030 °C.

[0223] Step 7: Nitrogen-oxygen treatment for 3 min. Temperature: 1030 °C, nitrogen flow rate 6 L / min, oxygen flow rate 2 L / min.

[0224] Step 8: Source introduction for 20 min. Temperature 1030 °C, nitrogen flow rate 6 L / min, oxygen flow rate 2 L / min, small nitrogen carrying phosphorus oxychloride 0.4 L / min.

[0225] Step 9: Nitrogen-oxygen treatment for 3 min. Temperature: 1030 °C, nitrogen flow rate 6 L / min, oxygen flow rate 2 L / min.

[0226] Step 10: Cool down for 77 min. After the oxidation process is completed, the temperature needs to be reduced to the standby temperature of the equipment. Generally, the cooling rate is 3 °C / min.

[0227] Step 11: Unload the boat for 15 min. After the temperature is reduced to the standby temperature, the equipment starts to unload the boat. Step 12: Cool down for 10 min. Since the temperature of the furnace tube is 800 °C, it is still in a high-temperature state after taking out the boat. Therefore, it needs to be cooled down to a certain temperature before the wafer can be removed.

[0228] Step 13: Insert the boat for 17 min. In the standby state of the equipment, to maintain cleanliness, place the quartz boat in the furnace tube.

[0229] Step 14: The entire process flow is completed, and the equipment is in standby.

[0230] Phosphosilicate glass removal: The water absorption of the phosphosilicate glass film can cause device failure, so it needs to be removed here.

[0231] The re-diffusion of the emitter region mainly includes the following processes.

[0232] Step 1: Take out the boat for 15 min. In the standby state of the equipment, to maintain cleanliness, place the quartz boat in the furnace tube and take out the boat when making wafers.

[0233] Step 2: Cool down for 10 min. Since the temperature of the furnace tube is 800 °C, it is still in a high-temperature state after taking out the boat. Therefore, it needs to be cooled down to a certain temperature before loading the wafer.

[0234] Step 3: Load the wafer for 10 min. Load the wafers that need to form the oxide layer onto the quartz boat.

[0235] Step 4: Insert the boat for 17 min. After loading the wafers, send the quartz boat into the furnace tube for processing.

[0236] Step 5: Hold for 15 min to ensure that the temperature and gas atmosphere inside the furnace tube are stable after inserting the boat.

[0237] Step 6: Heat up for 44 min. The temperature of the diffusion furnace increases by 5 °C per minute during heating. After 44 min, it reaches the process temperature of 1020 °C.

[0238] Step 7: Dry oxygen for 5 min, temperature: 1020 °C, oxygen flow rate 8 L / min, to obtain a dense silicon dioxide surface and thus improve the blocking ability of impurities.

[0239] Step 8: Wet oxygen for 11 min, temperature 1130 °C, oxygen flow rate 7 L / min, hydrogen flow rate 10 L / min. Wet oxygen is mainly used to form the required thickness of the silicon dioxide film and improve production efficiency. If it is used as a masking film for impurity diffusion, its thickness is mainly determined by the junction depth formed by diffusion and the diffusion temperature, that is, first determine the diffusion time required, and then determine the thickness of the oxide film required to block the diffusion of impurities in silicon dioxide under this diffusion time.

[0240] Step 9: Dry oxidation for 5 min, temperature: 1020 °C, oxygen flow rate 8 L / min. After wet oxidation, the presence of surface silanols reduces the adhesion between silica and photoresist. Therefore, a second dry oxidation is carried out to improve the properties of the silica - silicon interface and also to dry the silica surface, thereby enhancing the adhesion between silica and photoresist.

[0241] Step 10: Cool down for 74 min. The oxidation process is completed, and the temperature needs to be reduced to the standby temperature of the equipment. Generally, the cooling rate is 3 °C / min.

[0242] Step 11: Unload the boat for 15 min. After the temperature drops to the standby temperature, the equipment starts to unload the boat. Step 12: Cool down for 10 min. Since the furnace tube temperature is 800 °C, the wafer is still at a high temperature after unloading the boat. Therefore, it needs to be cooled to a certain temperature before the wafer can be removed.

[0243] Step 13: Load the boat for 17 min. In the standby state of the equipment, to maintain cleanliness, the quartz boat is placed in the furnace tube.

[0244] Step 14: The entire process flow is completed, and the equipment is in standby.

[0245] The process of via - hole lithography is HMDS, coating (using negative photoresist with a thickness of 19000 ± 2000 Å), pre - baking (30 min), alignment, development, hard - baking (30 min), wet etching (oxide layer etching: using BOE solution for 10 min) and stripping (using stripping solution for 10 min).

[0246] During the metal sputtering process, the evaporation parameters for the front - side metal are Ti: 1500 Å, Al: 20000 Å, and the sheet resistance is 8.95 Ω / sq. Here, Ti acts as an adhesion layer, and Al acts as a metal lead.

[0247] The process of front - side metal lift - off is HMDS, coating (using negative photoresist with a thickness of 28000 ± 2000 Å), pre - baking (30 min), alignment, development, hard - baking (30 min), wet etching (metal layer etching: using stripping solution for 30 min) and plasma stripping (30 min).

[0248] Among them, the process parameters for the Al alloy are 400 °C and 30 min, and the gas flow rates are nitrogen: 8 L / min and hydrogen: 1 L / min. The purpose is to ensure a good ohmic contact between the front - side metal and the silicon wafer surface.

[0249] The process of passivation layer lithography is HMDS, spin coating (using a negative photoresist with a thickness of 28000±2000 Å), soft baking (30 min), alignment, development, hard baking (30 min), dry etching (passivation layer etching), and plasma ashing (30 min).

[0250] The manufacturing apparatus of the ER193 type dual differential comparator circuit provided by the present invention will be described below. The manufacturing apparatus of the ER193 type dual differential comparator circuit described below can be correspondingly referred to the manufacturing method of the ER193 type dual differential comparator circuit described above.

[0251] A manufacturing apparatus of an ER193 type dual differential comparator circuit according to an embodiment of the present invention mainly includes a first processing module 310, a second processing module 320, a third processing module 330, and a fourth processing module 340.

[0252] The first processing module 310 is configured to determine the removal of the surface oxide layer of the wafer after the wafer undergoes a lower isolation process. The second processing module 320 is configured to determine the formation of an epitaxial layer on the wafer and perform upper isolation oxidation on the wafer. The third processing module 330 is configured to determine the adjustment of the isolation lithography position of the wafer to correct the epitaxial layer drift during the upper isolation lithography. The fourth processing module 340 is configured to determine the pre-diffusion and re-diffusion of the wafer after correcting the epitaxial layer drift to obtain a target circuit on the wafer.

[0253] According to the manufacturing apparatus of the ER193 type dual differential comparator circuit of the embodiment of the present invention, by adjusting the isolation lithography position of the wafer, it is ensured that the epitaxial layer drift is corrected during the upper isolation lithography process. Even if the epitaxial layer drifts, the lithography pattern can still be accurately formed on the wafer, avoiding circuit malfunction or inconsistent electrical performance caused by alignment errors.

[0254] The embodiment of the present invention further provides an ER193 type dual differential comparator circuit, and the ER193 type dual differential comparator circuit is manufactured by using the manufacturing method of the ER193 type dual differential comparator circuit as described above.

[0255] Figure 4 An example of a schematic diagram of the physical structure of an electronic device is shown as Figure 4As shown in the figure, the electronic device may include: a processor 410, a communications interface 420, a memory 430, and a communication bus 440. Among them, the processor 410, the communications interface 420, and the memory 430 communicate with each other through the communication bus 440. The processor 410 may call the logical instructions in the memory 430 to execute the manufacturing method of the ER193 type double differential comparator circuit. The method includes: after performing lower isolation processing on the wafer, determining to remove the surface oxide layer of the wafer; determining that the wafer forms an epitaxial layer and performing upper isolation oxidation on the wafer; when performing upper isolation lithography, determining to adjust the isolation lithography position of the wafer to correct the epitaxial layer drift; determining to perform pre-diffusion and re-diffusion on the wafer after correcting the epitaxial layer drift to obtain a target circuit on the wafer.

[0256] In addition, when the logical instructions in the above-mentioned memory 430 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0257] On the other hand, the present invention also provides a computer program product. The computer program product includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the manufacturing method of the ER193 type double differential comparator circuit provided by the above-mentioned various methods. The method includes: after performing lower isolation processing on the wafer, determining to remove the surface oxide layer of the wafer; determining that the wafer forms an epitaxial layer and performing upper isolation oxidation on the wafer; when performing upper isolation lithography, determining to adjust the isolation lithography position of the wafer to correct the epitaxial layer drift; determining to perform pre-diffusion and re-diffusion on the wafer after correcting the epitaxial layer drift to obtain a target circuit on the wafer.

[0258] In another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the manufacturing method of the ER193 type double differential comparator circuit provided by the above-mentioned various methods. The method includes: after performing lower isolation processing on the wafer, determining to remove the surface oxide layer of the wafer; determining that the wafer forms an epitaxial layer and performing upper isolation oxidation on the wafer; when performing upper isolation lithography, determining to adjust the isolation lithography position of the wafer to correct the epitaxial layer drift; determining to perform pre-diffusion and re-diffusion on the wafer after correcting the epitaxial layer drift to obtain a target circuit on the wafer.

[0259] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative labor.

[0260] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disc, etc., and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0261] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A manufacturing method of an ER193 type double differential comparator circuit, characterized in that, Including: After performing lower isolation processing on the wafer, determine to remove the surface oxide layer of the wafer; Determine that the wafer forms an epitaxial layer and perform upper isolation oxidation on the wafer; When performing upper isolation lithography, determine to adjust the isolation lithography position of the wafer to correct the epitaxial layer drift; Determine to perform pre-diffusion and re-diffusion on the wafer after correcting the epitaxial layer drift to obtain a target circuit on the wafer.

2. The manufacturing method of the ER193 type dual differential comparator circuit according to claim 1, characterized in that The adjusting the isolation lithography position of the wafer to correct the epitaxial layer drift includes: When the alignment parameters of the lithography machine for upper isolation lithography are in an adjustable state, based on the drift direction and magnitude of the epitaxial layer on the wafer, adjust the alignment parameters of the lithography machine.

3. The manufacturing method of the ER193 type double differential comparator circuit according to claim 2, characterized in that, The adjusting the alignment parameters of the lithography machine based on the drift direction and magnitude of the epitaxial layer on the wafer includes: Adjust the alignment parameters of the lithography machine to drift the alignment position of the lithography machine in the opposite direction of the drift direction of the epitaxial layer by a length equal to the thickness of the epitaxial layer.

4. The manufacturing method of the ER193 type double differential comparator circuit according to claim 1, characterized in that, The adjusting the isolation lithography position of the wafer to correct the epitaxial layer drift includes: When the alignment parameters of the lithography machine for upper isolation lithography are in a non-adjustable state, based on the drift direction and magnitude of the epitaxial layer on the wafer, determine that the etch mark for etching the isolation region in the layout for upper isolation lithography deviates from the target offset direction by a target offset amount.

5. The manufacturing method of the ER193 type double differential comparator circuit according to claim 4, characterized in that, The target offset direction is the opposite direction of the drift direction of the epitaxial layer, and the target offset amount is the thickness size of the epitaxial layer.

6. The manufacturing method of the ER193 type double differential comparator circuit according to claim 1, characterized in that, Before determining to remove the surface oxide layer of the wafer after performing lower isolation processing on the wafer, the method further includes: Determine to perform buried layer oxidation on the wafer; After buried layer oxidation, determine to perform arsenic implantation and arsenic annealing on the wafer respectively; Determine to perform lower isolation oxidation, lower isolation lithography, lower isolation implantation, and lower isolation annealing on the wafer respectively.

7. The manufacturing method of the ER193 type double differential comparator circuit according to claim 1, characterized in that, After determining to perform pre-diffusion and re-diffusion on the wafer after correcting the epitaxial layer drift, the method includes: Determine to perform base region oxidation, base region pre-diffusion, boron silicate glass removal, and base region re-diffusion on the wafer respectively; Determine to perform emitter region lithography, emitter region pre-diffusion, phosphorus silicate glass removal, and emitter region re-diffusion on the wafer; Determine to perform via hole lithography and metal sputtering on the wafer.

8. A manufacturing apparatus for a manufacturing method of an ER193 type dual differential comparator circuit as described in any one of claims 1 to 7, characterized in that, Including: A first processing module, configured to determine to remove the surface oxide layer of the wafer after performing lower isolation processing on the wafer; A second processing module, configured to determine that the wafer forms an epitaxial layer and perform upper isolation oxidation on the wafer; A third processing module, configured to determine to adjust the isolation lithography position of the wafer to correct the epitaxial layer drift when performing upper isolation lithography; A fourth processing module, configured to determine to perform pre-diffusion and re-diffusion on the wafer after correcting the epitaxial layer drift to obtain a target circuit on the wafer.

9. An ER193 type dual differential comparator circuit, characterized in that, The ER193 type dual differential comparator circuit is manufactured by using the manufacturing method of the ER193 type dual differential comparator circuit according to any one of claims 1 to 7.

10. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the manufacturing method of the ER193 type dual differential comparator circuit according to any one of claims 1 to 7.

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