Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to increase contact resistance between a back contact structure and a source region and / or a drain region. The semiconductor device includes a semiconductor substrate, a transistor, and a back contact structure. The transistor is disposed on the semiconductor substrate. The transistor comprises a channel region, a source region, a drain region, a gate stack structure and a gate sidewall. And the back contact structure is arranged in the semiconductor substrate, and extends upwards from one side, close to the semiconductor substrate, of the source region and / or the drain region to cover at least partial regions of two side walls of the source region and / or the drain region along the width direction of the channel region. The manufacturing method of the semiconductor device comprises the following steps: forming a transistor on a semiconductor substrate, and forming a pre-formed structure in a part, below a source region and / or a drain region of the transistor, of the semiconductor substrate. And thinning the semiconductor substrate until the preformed structure is exposed. And removing the pre-formed structure and forming a contact hole. And forming a back contact structure arranged in the contact hole.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the continuous shrinking of chip processes, the challenges of interconnect technology have gradually exceeded the difficulty of shrinking transistors themselves. The increase in the number of interconnect layers, the improvement in the complexity of wiring design, and the problem of conductive resistance have greatly limited the improvement of performance and the optimization of power consumption. To solve these problems, the backside contact (BSC) technology has been proposed, which realizes the optimal area reduction and performance improvement by directly performing backside wiring under the source region and / or drain region of the transistor.

[0003] However, in existing semiconductor devices, the contact performance between the source region and / or drain region included in the transistor and the backside contact structure is poor, which is not conducive to improving the working performance of the semiconductor device. Summary of the Invention

[0004] The purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof, which are used to reduce the contact resistance between the backside contact structure and the source region and / or drain region, and are conducive to improving the electrical performance of the semiconductor device.

[0005] To achieve the above purpose, in a first aspect, the present invention provides a semiconductor device, which includes: a semiconductor substrate, a transistor, and a backside contact structure. The transistor is disposed on the semiconductor substrate. The transistor includes a channel region, a source region, a drain region, a gate stack structure, and a gate sidewall. The source region and the drain region are respectively disposed on two sides of the channel region along the length direction. The gate stack structure is disposed on the outer periphery of the channel region, and the gate sidewall is disposed at least on two sides of the gate stack structure along the length direction. The backside contact structure is disposed in the semiconductor substrate, and extends upward from the side of the source region and / or drain region close to the semiconductor substrate to cover at least a partial region on two sidewalls of the source region and / or drain region along the width direction of the channel region.

[0006] In the case of adopting the above technical solution, the contact structure in electrical contact with the source region and / or drain region included in the transistor is disposed in the semiconductor substrate below the transistor, rather than above the transistor facing away from the semiconductor substrate, which can reduce the design difficulty and manufacturing process difficulty of the front-side wiring. Moreover, a part of the back-side contact structure is disposed below the source region and / or drain region included in the transistor, which is conducive to shortening the wiring length of the back-side contact structure, reducing the conduction resistance, and improving the electrical performance of the transistor. Furthermore, compared with the prior art in which the back-side contact structure only contacts the bottom of the source region and drain region included in the transistor, in the semiconductor device provided by the present invention, the back-side contact structure also extends upward from the side of the source region and / or drain region close to the semiconductor substrate to cover at least a part of the two sidewalls of the source region and / or drain region along the width direction of the channel region, which can increase the contact area between the back-side contact structure and the source region and / or drain region included in the transistor, is conducive to reducing the contact resistance therebetween, improving the contact performance therebetween, improving the electrical performance of the transistor, and further improving the working performance of the semiconductor device.

[0007] In one example, along the length direction of the gate stack structure, the sidewall of the back-side contact structure close to the gate stack structure is aligned with the sidewall of the gate sidewall. The part of the two sidewalls of the source region and / or drain region along the width direction of the channel region that contacts the back-side contact structure is aligned with the sidewall of the channel region along the width direction.

[0008] In the case of adopting the above technical solution, when along the length direction of the gate stack structure, the sidewall of the back-side contact structure close to the gate stack structure is aligned with the sidewall of the gate sidewall, the sidewalls of the two are self-aligned, reducing the leakage risk between the back-side contact structure and other adjacent conductive contact structures, and being conducive to reducing the process difficulty and process precision requirements for forming the contact hole for filling the back-side contact structure, and being conducive to improving the yield of the semiconductor device. Moreover, the part of the two sidewalls of the source region and / or drain region along the width direction of the channel region that contacts the back-side contact structure is aligned with the sidewall of the channel region along the width direction. At this time, the width of the part where the source region and / or drain region is in direct contact with the back-side contact structure is small, which is conducive to reducing the layout area. Additionally, the space vacated by narrowing the source region and / or drain region can be used to fill part of the back-side contact structure, so that while increasing the contact area between the back-side contact structure and the source region and / or drain region, it is also conducive to the miniaturization of the semiconductor device and improves the integration degree of the semiconductor device.

[0009] In one example, the width of the part where the back-side contact structure covers the two sidewalls of the source region and / or drain region along the width direction of the channel region is greater than the width of the gate sidewall.

[0010] In one example, the height of the part where the back-side contact structure covers the two sidewalls of the source region and / or drain region along the width direction of the channel region is less than the height of the gate sidewall.

[0011] In one example, in the source region and / or drain region in electrical contact with the back contact structure, the width of the portion in direct electrical contact with the back contact structure is less than the maximum width of the portion not in direct electrical contact with the back contact structure.

[0012] In one example, in the source region and / or drain region in electrical contact with the back contact structure, the doping concentration on the side close to the semiconductor substrate is greater than or equal to the doping concentration on the side away from the semiconductor substrate.

[0013] In one example, the material of the source region and / or drain region in electrical contact with the back contact structure contains a first metal element, and the type of the first metal element is different from the type of the second metal element in the material of the back contact structure.

[0014] In one example, the back contact structure includes a first part and a second part in electrical contact. The first part penetrates through the semiconductor substrate and is in electrical contact with the bottom of the source region and / or drain region. The second part extends to the sidewalls of the source region and / or the drain region and is in electrical contact with the sidewalls of the source region and / or drain region.

[0015] In a second aspect, the present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: First, providing a semiconductor substrate. Next, forming a transistor on the semiconductor substrate, and forming a preformed structure in a portion of the semiconductor substrate below the source region and / or drain region included in the transistor. The gate sidewalls included in the transistor are disposed at least on both sides of the gate stack structure in the length direction, and on both sides of the source region and drain region in the width direction of the channel region. Next, thinning the semiconductor substrate until the preformed structure is exposed; and turning the bottoms of the source region and drain region upward. Next, sequentially removing the preformed structure, the semiconductor substrate on both sides of the preformed structure in the width direction of the channel region included in the transistor, and the gate sidewalls on both sides of the source region and / or drain region in the width direction of the channel region to form contact holes. Next, forming a back contact structure disposed in the contact holes.

[0016] In one example, forming the transistor and the preformed structure on the semiconductor substrate includes: forming a fin structure and a first mask structure on the semiconductor substrate. The first mask structure includes a sacrificial gate and gate sidewalls. The sacrificial gate straddles the fin structure, and the gate sidewalls are disposed at least on both sides of the sacrificial gate in the length direction, and on both sides of the fin structure in the width direction. Next, under the protection of the first mask structure, selectively etching the fin structure. And selectively etching a portion of the semiconductor substrate exposed on at least one side of the remaining fin structure to form a first opening in the semiconductor substrate. Next, forming a preformed structure in the first opening. Next, epitaxially forming the source region and the drain region. And making the remaining fin structure form a channel region. Next, forming a gate stack structure on the outer periphery of the channel region to obtain the transistor.

[0017] In one example, after forming a first opening and before epitaxially forming a source region and a drain region, a method for manufacturing a semiconductor device includes: forming a protective layer covering sidewalls of a gate and an inner wall of the first opening. Next, a preformed material covering the protective layer and filling the first opening is formed by a deposition process. Next, under the protection of the protective layer, the preformed material is selectively etched so that the remaining preformed material is only located within the first opening, obtaining a preformed structure. Next, a portion of the protective layer covering the sidewalls of the gate is removed.

[0018] In one example, when only one of the source region and the drain region included in a transistor is in electrical contact with a back contact structure, after selectively etching a fin structure and before forming a first opening, a method for manufacturing a semiconductor substrate further includes: forming at least a second mask structure on the semiconductor substrate. The second mask structure is used to cover one side of the semiconductor substrate exposed on both sides of the remaining fin structure. And, after forming a preformed structure within the first opening and before epitaxially forming a source region and a drain region, a method for manufacturing a semiconductor device further includes: removing the second mask structure.

[0019] In one example, after forming a transistor on a semiconductor substrate and before thinning the semiconductor substrate, a method for manufacturing a semiconductor device further includes: forming an insulating dielectric layer covering the transistor.

[0020] In one example, after sequentially removing a preformed structure and gate sidewalls located on both sides of a source region and / or a drain region along the width direction of a channel region and before forming a back contact structure disposed within a contact hole, a method for manufacturing a semiconductor device further includes: selectively etching the insulating dielectric layer to increase the width of the contact hole.

[0021] In one example, after forming a fin structure and a first mask structure on a semiconductor substrate and before epitaxially forming a source region and a drain region, a method for manufacturing a semiconductor device further includes: selectively etching gate sidewalls so that the height of gate sidewalls disposed on both sides of the fin structure along the width direction is less than the height of gate sidewalls disposed on both sides of a sacrificial gate along the length direction.

[0022] For the beneficial effects of the second aspect and its various implementation manners in the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0024] Figure 1Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure One ;

[0025] Figure 2 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Two ;

[0026] Figure 3 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Three ;

[0027] Figure 4 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Four ;

[0028] Figure 5 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Five ;

[0029] Figure 6 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Six ;

[0030] Figure 7 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Seven ;

[0031] Figure 8 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Eight ;

[0032] Figure 9 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Nine ;

[0033] Figure 10 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten ;

[0034] Figure 11 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten One;

[0035] Figure 12 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Two;

[0036] Figure 13 Schematic structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Three;

[0037] Figure 14 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Four;

[0038] Figure 15 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Five;

[0039] Figure 16 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Six;

[0040] Figure 17 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Seven;

[0041] Figure 18 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Eight;

[0042] Figure 19 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Nine;

[0043] Figure 20 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Two Ten;

[0044] Figure 21 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Two Eleven;

[0045] Figure 22 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Two Twelve;

[0046] Figure 23 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Two Thirteen;

[0047] Figure 24 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Two Fourteen;

[0048] Figure 25 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Two Fifteen;

[0049] Figure 26Structural schematic of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Two Sixteen;

[0050] Figure 27 Structural schematic of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Two Seventeen;

[0051] Figure 28 Structural schematic of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Two Eighteen;

[0052] Figure 29 Structural schematic of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Two Nineteen;

[0053] Figure 30 Structural schematic of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Three Ten.

[0054] Reference numerals: 11 is a semiconductor substrate, 12 is a transistor, 13 is a channel region, 14 is a source region, 15 is a drain region, 16 is a gate stack structure, 17 is a gate sidewall, 18 is a back contact structure, 181 is a first part, 182 is a second part, 19 is an insulating dielectric layer, 20 is a shallow trench isolation structure, 21 is a pre-formed structure, 22 is a contact hole, 23 is a fin structure, 24 is a first mask structure, 25 is a sacrificial gate, 26 is a first opening, 27 is a protective layer, 28 is a pre-formed material, 29 is a second mask structure. Detailed implementation manners

[0055] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present invention.

[0056] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and in order to express more clearly, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0057] In the context of the present invention, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clear and understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0058] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0059] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected" and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] As the chip process continues to shrink, the challenges of interconnect technology have gradually exceeded the difficulty of shrinking the transistors themselves. The increase in the number of interconnect layers, the improvement in the complexity of wiring design, and the problem of conductive resistance have greatly limited the improvement of performance and the optimization of power consumption. To solve these problems, the backside contact BSC technology has been proposed, which realizes the optimal area reduction and performance improvement by directly performing backside wiring under the source region and / or drain region of the transistor.

[0061] However, in existing semiconductor devices, the contact performance between the source region and / or drain region included in the transistor and the back contact structure is poor. Specifically, the back contact structure can only contact at least a part of the bottom surface of the source region and / or drain region located above it, resulting in a small contact area and a large contact resistance between the two. In addition, during the actual manufacturing process of the back contact structure, the bottoms of the source region and drain region included in the transistor are turned upward, and after forming a dielectric layer thereon, processes such as photolithography and etching are required to open contact holes in the dielectric layer to expose the source region and drain region. And processes such as physical vapor deposition are used to form the back contact structure filled in the contact holes. During the process of patterning the dielectric layer to form the contact holes, a high requirement for etching accuracy leads to a large process difficulty. If the etching accuracy is reduced, it is easy to cause large deviations in the size and / or opening position of the contact holes, resulting in problems such as poor contact performance between the back contact structure and the source / drain regions respectively and / or high leakage risk, which is not conducive to improving the working performance of the semiconductor device.

[0062] To solve the above technical problems, an embodiment of the present invention provides a semiconductor device and a manufacturing method thereof. Among them, in the manufacturing method of the semiconductor device provided by the embodiment of the present invention, the back contact structure extends upward from the side of the source region and / or drain region close to the semiconductor substrate to cover at least a part of the two side walls of the source region and / or drain region along the width direction of the channel region, so as to reduce the contact resistance between the two.

[0063] In a first aspect, an embodiment of the present invention provides a semiconductor device. As Figures 28 to 30 shown, the semiconductor device includes: a semiconductor substrate 11, a transistor 12, and a back contact structure 18. The transistor 12 is disposed on the semiconductor substrate 11. The transistor 12 includes a channel region 13, a source region 14, a drain region 15, a gate stack structure 16, and a gate sidewall 17. The source region 14 and the drain region 15 are respectively disposed on both sides of the channel region 13 along the length direction. The gate stack structure 16 is disposed on the outer periphery of the channel region 13, and the gate sidewall 17 is disposed at least on both sides of the gate stack structure 16 along the length direction. The back contact structure 18 is disposed in the semiconductor substrate 11, and extends upward from the side of the source region 14 and / or drain region 15 close to the semiconductor substrate 11 to cover at least a part of the two side walls of the source region 14 and / or drain region 15 along the width direction of the channel region 13.

[0064] In the case of adopting the above technical solution, as Figures 28 to 30As shown, the contact structure in electrical contact with the source region 14 and / or the drain region 15 included in the transistor 12 is disposed within the semiconductor substrate 11 beneath the transistor 12, rather than above the transistor 12 away from the semiconductor substrate 11, which can reduce the design difficulty and manufacturing process difficulty of the front-side wiring. Moreover, part of the back-side contact structure 18 is disposed beneath the source region 14 and / or the drain region 15 included in the transistor 12, which is conducive to shortening the wiring length of the back-side contact structure 18, reducing the conduction resistance, and improving the electrical performance of the transistor 12. Also, compared with the prior art where the back-side contact structure 18 only contacts the bottom of the source region 14 and the drain region 15 included in the transistor 12, in the semiconductor device provided by the embodiment of the present invention, the back-side contact structure 18 further extends upward from the side of the source region 14 and / or the drain region 15 close to the semiconductor substrate 11 to cover at least a partial region of both sidewalls of the source region 14 and / or the drain region 15 along the width direction of the channel region 13, which can increase the contact area between the back-side contact structure 18 and the source region 14 and / or the drain region 15 included in the transistor 12, is conducive to reducing the contact resistance therebetween, improving the contact performance therebetween, enhancing the electrical performance of the transistor 12, and further improving the working performance of the semiconductor device.

[0065] In the actual application process, the embodiment of the present invention does not specifically limit the device type of the semiconductor device, as long as it can include the above-mentioned semiconductor substrate, transistor, and back-side contact structure.

[0066] Exemplarily, the semiconductor device provided by the embodiment of the present invention can have only a single layer of transistors disposed on the semiconductor substrate, or can have multiple layers of transistors spaced along the thickness direction of the semiconductor substrate. Among them, the transistors located at the bottom layer can have only one or more of the above-mentioned transistors, or can additionally have one or more other transistors with different structures from the above-mentioned transistors (such as fin field-effect transistors or gate-all-around transistors, etc.). The distribution and types of different transistors in the remaining layer of transistors can be set according to actual needs, and are not specifically limited herein.

[0067] Exemplarily, the semiconductor device can further include an insulating isolation layer and upper-layer transistors. Along the thickness direction of the semiconductor substrate, the upper-layer transistors are disposed above the above-mentioned transistors (in this case, the above-mentioned transistors can be defined as lower-layer transistors for easy distinction). The insulating isolation layer is disposed between the source region and the drain region included in the lower-layer transistors and the source region and the drain region included in the upper-layer transistors respectively. In this case, the lower-layer transistors and the upper-layer transistors can form a CFET device, which can further improve the integration degree of the semiconductor device provided by the embodiment of the present invention.

[0068] Among them, the material of the above-mentioned insulating isolation layer can be any insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the insulating isolation layer can be set according to actual needs and is not specifically limited here. Additionally, in actual application scenarios, it can be that the source region included in the upper transistor is directly above the source region included in the lower transistor, or it can be that the drain region included in the upper transistor is directly above the source region included in the lower transistor. As for the conduction types of the lower transistor and the upper transistor, the conduction types of the upper transistor and the lower transistor can be opposite or the same. For example: the conduction type of the lower transistor can be N-type, and at this time, the conduction type of the upper transistor can be P-type or N-type. Another example: the conduction type of the lower transistor can also be P-type, and at this time, the conduction type of the upper transistor can be P-type or N-type.

[0069] In addition, as for the structure of the upper transistor, it can be set according to actual needs and is not specifically limited here. The upper transistor can be a gate-all-around transistor, a fin field-effect transistor, or other types of transistors, as long as it can be applied to the semiconductor device provided in the embodiment of the present invention. The type and specific structure of the lower transistor will be described in detail below.

[0070] As for the above-mentioned semiconductor substrate, it can be a substrate of any semiconductor material such as a silicon substrate, a silicon-germanium substrate, or a germanium substrate, as long as it can be applied to the semiconductor device provided in the embodiment of the present invention.

[0071] In some cases, as Figures 28 to 30 shown, the semiconductor device may further include an insulating dielectric layer 19 covering the transistor 12 to reduce the leakage risk of the transistor 12 and is conducive to improving the yield of the transistor 12. The material of the insulating dielectric layer 19 can include any insulating material such as silicon oxide or silicon nitride, as long as it can be applied to the semiconductor device provided in the embodiment of the present invention.

[0072] For the transistor, in terms of the device type, as Figure 30 shown, the above-mentioned transistor 12 can be a gate-all-around transistor. At this time, the gate stack structure 16 included in the transistor 12 surrounds the outer periphery of the channel region 13, having a strong gate control ability and being conducive to suppressing the short-channel effect. In the embodiment of the present invention, the number of layers and structure of the nanostructures provided in the channel region 13 included in the transistor 12 are not specifically limited.

[0073] Alternatively, the transistor can also be a fin field-effect transistor. At this time, the gate stack structure included in the transistor is only provided on the top and sidewalls of the channel region.

[0074] Of course, the above-mentioned transistor can also be other types of transistors, as long as the above-mentioned transistor is provided on the substrate.

[0075] For the source region and the drain region included in the above transistor, at least one of the source region and the drain region included in the transistor may be in electrical contact with the above back contact structure, and the contact structure to which the other is electrically connected may be led out from the side of the transistor facing away from the semiconductor substrate, or may also be led out from the diagonally lower part of the transistor. Secondly, among the source region and the drain region included in the transistor, both may also be in electrical contact with the corresponding back contact structure.

[0076] In addition, among the source region and / or the drain region included in the transistor in electrical contact with the back contact structure, the doping concentration on the side close to the semiconductor substrate may be greater than or equal to the doping concentration on the side facing away from the semiconductor substrate, so as to further reduce the contact resistance between the back contact structure and the source region and / or the drain region (specifically, it can be achieved by processes such as ion implantation or epitaxy after turning the bottoms of the source region and the drain region upwards and before forming the back contact structure); or the doping concentration on the side close to the semiconductor substrate may be less than the doping concentration on the side facing away from the semiconductor substrate. Among them, for the source region and / or the drain region included in the transistor in electrical contact with the back contact structure, the magnitude relationship between the doping concentration on the side close to the semiconductor substrate and the doping concentration on the side facing away from the semiconductor substrate may be determined according to the size of the contact area between the source region and / or the drain region included and the back contact structure, as well as the requirements for the contact performance between the back contact structure and the source region and / or the drain region included in the transistor in the actual application scenario, and no specific limitation is made here.

[0077] Exemplarily, among the source region and / or the drain region included in the transistor in electrical contact with the back contact structure, the doping concentration on the side close to the semiconductor substrate may be greater than or equal to 2E20 cm -3 .

[0078] In terms of materials, the source region and the drain region included in the transistor may be manufactured and formed using semiconductor materials. At this time, PN junctions are formed between the source region and the drain region and the channel region respectively. Or, the materials of the source region and / or the drain region included in the transistor may also contain a first metal element (such as copper, tungsten, titanium, gold, or aluminum, etc.; the first metal element may include one or more), and at this time, Schottky junctions may also be formed between the source region and / or the drain region and the channel region to improve the applicability of the semiconductor device in different application scenarios.

[0079] As for the type of the first metal element mentioned above, it can be set according to actual requirements and will not be specifically limited here. Among them, when the material of the source region and / or drain region in electrical contact with the back contact structure contains the first metal element, the type of the first metal element can be the same as or different from the type of the second metal element in the material of the back contact structure. When the first metal element is different from the second metal element, the material types of both can be determined respectively according to the source region and / or drain region, the functions of the back contact structure, and actual requirements, so as to improve the applicability of the semiconductor device in different application scenarios.

[0080] In addition, as Figures 28 to 30 shown, in the transistor 12, the portions of the sidewalls on both sides of the source region 14 and / or drain region 15 along the width direction of the channel region that are in contact with the back contact structure 18 can be aligned with the sidewalls of the channel region 13 along the width direction, so as to reduce the layout area of the transistor 12 and facilitate increasing the contact area between the back contact structure 18 and the source region 14 and / or drain region 15. Among them, as Figure 28 and Figure 30 shown, if the back contact structure 18 is in electrical contact with all partial regions of the sidewalls on both sides of the source region 14 and / or drain region 15 along the width direction of the channel region, the widths of the respective portions of the source region 14 and / or drain region 15 that are in electrical contact with the back contact structure 18 are equal to the width of the channel region 13.

[0081] Alternatively, as Figure 29 and Figure 30 shown, if the height of the portion of the back contact structure 18 covering the sidewalls on both sides of the source region 14 and / or drain region 15 along the width direction of the channel region is less than the height of the gate sidewall 17, then in the source region 14 and / or drain region 15 that is in electrical contact with the back contact structure 18, the width of the portion that is directly in electrical contact with the back contact structure 18 can be less than the maximum width of the portion that is not directly in electrical contact with the back contact structure 18. With such a setting, there is no need to pattern the epitaxial source region 14 and drain region 15 to reduce the layout area, simplifying the manufacturing process of the semiconductor device.

[0082] Of course, when the height of the portion of the back contact structure covering the sidewalls on both sides of the source region and / or drain region along the width direction of the channel region is less than the height of the gate sidewall, the width of the portion of the source region and / or drain region that is in electrical contact with the back contact structure and that is directly in electrical contact with the back contact structure can also be equal to the width of the portion that is not directly in electrical contact with the back contact structure.

[0083] It should be noted that, as Figures 28 to 30As shown, the portions of the sidewalls on both sides of the source region 14 and / or the drain region 15 along the width direction of the channel region 13 that are in contact with the back contact structure 18 are aligned with the sidewalls of the channel region 13 along the width direction. At this time, the width of the portion where the source region 14 and / or the drain region 15 are in direct contact with the back contact structure 18 is small, which is beneficial for reducing the layout area. At the same time, the space vacated by narrowing the source region 14 and / or the drain region 15 can be used to fill part of the back contact structure 18, so as to increase the contact area between the back contact structure 18 and the source region 14 and / or the drain region 15 while also being beneficial for the miniaturization of semiconductor devices and improving the integration degree of semiconductor devices.

[0084] In addition, in a transistor, the width of the portions of the sidewalls on both sides of the source region and / or the drain region along the width direction of the channel region that are in contact with the back contact structure can also be greater than the width of the channel region to improve the applicability of the semiconductor device provided by the embodiments of the present invention in different application scenarios. Specifically, after forming the contact holes for exposing the source region and / or the drain region, processes such as epitaxy can be used to further increase the width of the source region and / or the drain region.

[0085] For the back contact structure, as Figures 28 to 30 shown, along the length direction of the gate stack structure 16, the sidewall of the back contact structure 18 close to the gate stack structure 16 can be aligned with the sidewall of the gate sidewall 17. At this time, the sidewalls of the two are self-aligned, reducing the leakage risk between the back contact structure 18 and other adjacent conductive contact structures, and being beneficial for reducing the process difficulty and process precision requirements for forming the contact holes 22 for filling the back contact structure 18, and being beneficial for improving the yield of semiconductor devices.

[0086] In the actual application process, along the thickness direction of the semiconductor substrate, as Figure 29 shown, the back contact structure 18 can only extend and cover part of the regions on the sidewalls of the source region 14 and / or the drain region 15 along the width direction of the channel region; at this time, the height of the part of the back contact structure 18 covering the sidewalls of the source region 14 and / or the drain region 15 along the width direction of the channel region is less than the height of the gate sidewall 17, so as to reduce the process difficulty of filling the back contact structure 18 from the back side of the source region 14 and / or the drain region 15 and prevent the contact holes 22 for filling the back contact structure 18 from having unfilled voids due to an excessive aspect ratio, which is beneficial for the semiconductor device to have a high yield.

[0087] Or, as Figure 28 shown, the back contact structure 18 is in electrical contact with each part of the sidewalls of the source region 14 and / or the drain region 15 along both sides of the width direction of the channel region. At this time, the contact area between the back contact structure 18 and the source region 14 and / or the drain region 15 is large, and the contact resistance between the two can be further reduced.

[0088] As for the specific structure of the back contact structure, such as Figures 28 to 30 shown, the back contact structure 18 may include a first part 181 and a second part 182 in electrical contact. The first part 181 penetrates the semiconductor substrate 11 and is in electrical contact with the bottoms of the source region 14 and / or the drain region 15. The second part 182 extends to the sidewalls of the source region 14 and / or the drain region 15 and is in electrical contact with the sidewalls of the source region 14 and / or the drain region 15. Among them, the first part 181 and the second part 182 may be integrally continuous, that is, the two are formed simultaneously in the same operation step and based on the same material. Alternatively, the first part 181 and the second part 182 may also be non-integrally formed.

[0089] As for the width of the back contact structure (the width direction of the back contact structure is parallel to the width direction of the channel region), the width of the part of the back contact structure covering the two sidewalls of the source region and / or the drain region along the width direction of the channel region may be equal to the width of the gate sidewall. Alternatively, the width of the part of the back contact structure covering the two sidewalls of the source region and / or the drain region along the width direction of the channel region may also be greater than the width of the gate sidewall. In this case, the width of the part of the contact hole for filling the back contact structure located on both sides of the source region and / or the drain region is also larger, which can reduce the process difficulty of filling the back contact structure in the part of the contact hole located on both sides of the source region and / or the drain region, and is beneficial to the semiconductor device having a high yield.

[0090] As for the difference between the width of the part of the back contact structure covering the two sidewalls of the source region and / or the drain region along the width direction of the channel region and the width of the gate sidewall, it can be determined according to the manufacturing process precision and the height of the part of the back contact structure covering the two sidewalls of the source region and / or the drain region along the width direction of the channel region, and no specific limitation is made here.

[0091] As for the material of the back contact structure, it may include any one of conductive materials such as silver, aluminum, copper, nickel, titanium or tungsten, as long as it can be applied to the semiconductor device provided by the embodiment of the present invention.

[0092] In some cases, such as Figure 28 and Figure 29 shown, the semiconductor device provided by the embodiment of the present invention may further include a shallow trench isolation structure 20. Among them, the shallow trench isolation structure 20 is formed on the semiconductor substrate 11 and is used to define the active region of the semiconductor substrate 11, reduce the leakage risk, and further improve the yield and working performance of the semiconductor device.

[0093] As for the material of the shallow trench isolation structure, it may include any one of insulating materials such as silicon oxide, silicon oxynitride or silicon nitride oxynitride, and no specific limitation is made here.

[0094] Second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device. The following will be described according to Figures 1 to 30 the perspective view and cross-sectional view of the operations shown, the manufacturing process will be described. Specifically, the method for manufacturing the semiconductor device includes the following steps:

[0095] First, a semiconductor substrate is provided. The structure and material of the semiconductor substrate can refer to the foregoing, and will not be elaborated here.

[0096] Next, as Figures 1 to 21 shown, a transistor 12 is formed on the semiconductor substrate 11, and a preformed structure 21 is formed in a portion of the semiconductor substrate 11 below the source region 14 and / or drain region 15 included in the transistor 12. The gate sidewall 17 included in the transistor 12 is disposed at least on both sides of the gate stack structure 16 along the length direction, and on both sides of the source region 14 and drain region 15 along the channel region width direction.

[0097] Specifically, information such as the structure and material of the transistor can refer to the foregoing, and will not be elaborated here. As for the above-mentioned preformed structure, after forming the transistor and thinning the semiconductor substrate, a contact hole for filling the back contact structure is formed by removing the preformed structure and the portion of the gate sidewall disposed on both sides of the source region and drain region along the channel region width direction. Therefore, the morphology of the preformed structure can be determined according to the morphology of the portion of the back contact structure below the source region and / or drain region. In addition, the material of the preformed structure is different from the material of the semiconductor substrate.

[0098] In the actual manufacturing process, for example, as Figures 1 to 5 shown, when forming the transistor and the preformed structure on the semiconductor substrate 11, a fin structure 23 and a first mask structure 24 can be first formed on the semiconductor substrate 11. The first mask structure 24 includes a sacrificial gate 25 and a gate sidewall 17. The sacrificial gate 25 straddles the fin structure 23, and the gate sidewall 17 is disposed at least on both sides of the sacrificial gate 25 along the length direction, and on both sides of the fin structure 23 along the width direction.

[0099] It can be understood that the above-mentioned fin structure is used to manufacture the channel region included in the transistor. Therefore, the specific structure of the fin structure can be determined according to the device type of the manufactured transistor and the structure of the channel region included in the transistor.

[0100] Exemplarily, when the manufactured transistor is a fin field effect transistor, the fin structure can be a single-layer structure, or the specific structure of the fin structure can be determined according to the structure of the channel region included in the transistor along the thickness direction of the semiconductor substrate.

[0101] Exemplarily, in the case where the transistor is a gate-all-around transistor, as Figure 4 and Figure 5As shown, in the thickness direction of the semiconductor substrate 11, the fin structure 23 may include at least one layer of semiconductor stack. Each layer of semiconductor stack includes a sacrificial layer and a channel layer located on the sacrificial layer. Among them, the channel layer included in the fin structure 23 is used to fabricate the channel region included in the transistor. Therefore, the material and number of layers of the channel layer included in the fin structure 23 can be set according to the material of the channel region included in the transistor described above and the number of layers of the nanostructures included in the channel region, which will not be elaborated here. As for the sacrificial layer, the remaining sacrificial layer will be removed later to form a void for filling the gate stack structure. Therefore, the thickness of the sacrificial layer can be determined according to the thickness of the gate stack structure. The material of the sacrificial layer may include any semiconductor material different from the material of the channel layer. For example, when the material of the channel layer is silicon, the material of the sacrificial layer may include silicon germanium or germanium, etc. Another example is that when the material of the channel layer is silicon germanium or germanium, the material of the sacrificial layer may include silicon.

[0102] Regarding the above-mentioned first mask structure, the material and specific structure of the first mask structure can be set according to actual requirements as long as it can play a masking and protecting role in the subsequent process.

[0103] Exemplarily, the first mask structure may only include a sacrificial gate and gate sidewalls. The material of the sacrificial gate may include materials such as polysilicon that are easy to remove.

[0104] Exemplarily, the first mask structure may also include a gate oxide layer, a sacrificial gate located on the gate oxide layer, and gate sidewalls located on both sides of the sacrificial gate along the length direction. The material of the gate oxide layer may include materials such as silicon oxide.

[0105] In the actual manufacturing process, taking the transistor as a gate-all-around transistor as an example for illustration: As Figure 1 shown, processes such as epitaxy can be used to form sacrificial layers and channel layers that are alternately stacked in the thickness direction of the semiconductor substrate 11. Then, processes such as photolithography and etching are used to pattern the above-mentioned sacrificial layers, channel layers, and part of the semiconductor substrate to form fins. Next, as Figure 2 shown, processes such as deposition and etching can be used to form a shallow trench isolation structure 20 for defining the active region between adjacent fins. The top height of the shallow trench isolation structure 20 is less than or equal to the bottom height of the sacrificial layer located at the bottom layer. Among them, the part of the fin exposed outside the shallow trench isolation structure 20 is the fin structure 23. Next, a masking material covering the semiconductor substrate 11 can be formed by a deposition process. Then, as Figures 3 to 5 shown, processes such as photolithography and etching are used to selectively etch the masking material to form the above-mentioned first mask structure 24.

[0106] It should be noted that when the semiconductor device does not include the above-mentioned shallow trench isolation structure, only the sacrificial layer and the channel layer can be patterned. And a fin structure can be directly obtained after the patterning process.

[0107] Exemplarily, in the manufactured semiconductor device, if the height of the portion of the back contact structure covering the sidewalls of the source region and / or the drain region along the width direction of the channel region is less than the height of the gate sidewalls on both sides of the gate stack structure, after forming the fin structure and the first mask structure on the semiconductor substrate, processes such as photolithography and etching can be used to selectively etch the gate sidewalls (specifically, the gate sidewalls directly located on both sides of the fin structure along the width direction) so that the height of the gate sidewalls provided on both sides of the fin structure along the width direction is less than the height of the gate sidewalls provided on both sides of the sacrificial gate along the length direction.

[0108] In the manufactured semiconductor device, if the height of the portion of the back contact structure covering the sidewalls of the source region and / or the drain region along the width direction of the channel region is equal to the height of the gate sidewalls on both sides of the gate stack structure, the above-mentioned selective etching operation of the gate sidewalls can be not performed and the subsequent operations can be directly carried out.

[0109] Next, as Figure 6 and Figure 7 shown, processes such as dry etching or wet etching can be used to selectively etch the fin structure under the protection of the first mask structure 24.

[0110] It should be noted that if only one of the source region and the drain region included in the manufactured transistor is in electrical contact with the back contact structure, after selectively etching the fin structure, as Figure 8 shown, processes such as photolithography are used to form at least a second mask structure 29 on the semiconductor substrate 11. The second mask structure 29 is used to cover one side of the semiconductor substrate 11 exposed on both sides of the remaining fin structure.

[0111] If both the source region and the drain region included in the manufactured transistor are in electrical contact with the back contact structure, the second mask structure does not need to be formed and the subsequent operations can be directly carried out.

[0112] Next, as Figure 9 shown, processes such as dry etching or wet etching can be used to selectively etch at least a part of the semiconductor substrate 11 exposed on both sides of the remaining fin structure to form a first opening 26 in the semiconductor substrate 11. The etching depth of the first opening 26 can be determined according to the height of the portion of the back contact structure 18 located below the source region and / or the drain region, and no specific limitation is made here.

[0113] Next, as Figure 12As shown, processes such as deposition and etching can be used to form a pre - formed structure 21 within the first opening.

[0114] The material of the pre - formed structure can be any material different from the semiconductor substrate (in the case where the semiconductor device further includes a shallow trench isolation structure, the material of the pre - formed structure is also different from the material of the shallow trench isolation structure). For example, the material of the pre - formed structure can be an insulating dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0115] In the actual manufacturing process, as Figure 10 shown, after forming the first opening, a deposition process can be used to form a protective layer 27 covering the gate sidewall 17 and the inner wall of the first opening 26. The presence of the protective layer 27 can protect the gate sidewall 17 during the process of manufacturing the pre - formed structure 21, preventing the height of the gate sidewall 17 from becoming smaller, which may cause the coverage area of the subsequent - formed back - contact structure 18 on the sidewalls of the source region and / or drain region 15 to be smaller. This is beneficial for the back - contact structure 18 to have a larger contact area with the source region and / or drain region 15. The material of the protective layer 27 is different from the materials of the gate sidewall 17, the pre - formed structure 21, and the semiconductor substrate 11. For example, when the materials of the gate sidewall 17 and the pre - formed structure 21 are silicon nitride, the material of the protective layer 27 can include silicon oxide. Next, as Figure 11 shown, a deposition process can be used to form a pre - formed material 28 covering the protective layer 27 and filling the first opening. Next, as Figure 12 shown, under the protection of the protective layer 27, processes such as dry etching or wet etching are used to selectively etch the pre - formed material so that the remaining pre - formed material is only located within the first opening, obtaining the pre - formed structure 21. At this time, the portions of the protective layer 27 covering the gate sidewall 17 and the semiconductor substrate 11 are exposed. Next, as Figure 13 shown, processes such as dry etching or wet etching are used to remove the portion of the protective layer 27 covering the gate sidewall 17.

[0116] It should be noted that if a second mask structure is formed before forming the first opening, after forming the pre - formed structure within the first opening, processes such as dry etching or wet etching are required to remove the second mask structure.

[0117] Next, as Figure 14 and Figure 15 shown, the source region 14 and the drain region 15 are epitaxially formed. Alternatively, in the case where the source region 14 and / or drain region 15 includes a first metal element, processes such as physical vapor deposition and etching can be used to form the source region 14 and / or drain region 15 including the first metal element.

[0118] Next, as Figures 16 to 19As shown, processes such as deposition and planarization can be used to form an insulating dielectric layer 19 covering the transistor 12. The top of the insulating dielectric layer 19 is flush with the top of the first mask structure 24. The material of the insulating dielectric layer 19 can refer to the previous text.

[0119] As Figure 20 shown, so that the remaining fin structures form the channel region 13. Specifically, as Figure 20 shown, processes such as dry etching or wet etching can be used to at least remove the sacrificial gate (when the first mask structure also includes structures such as a gate oxide layer covering the channel region 13, the gate oxide layer and other structures covering the channel region 13 also need to be removed). Secondly, how to form the channel region 13 can be determined according to the device type of the transistor, and specific limitations are not made here.

[0120] For example: in the case where the transistor is a fin field-effect transistor, after at least removing the sacrificial gate and exposing the remaining fin structures, the remaining fin structures form the channel region.

[0121] Another example: in the case where the transistor is a gate-all-around transistor, after at least removing the sacrificial gate and exposing the remaining fin structures, as Figure 20 shown, processes such as dry etching or wet etching need to be used to etch and remove the remaining sacrificial layer so that the remaining channel layer forms the channel region 13.

[0122] Next, as Figure 21 shown, processes such as atomic layer deposition can be used to form a gate stack structure 16 on the outer periphery of the channel region 13 to obtain the transistor 12.

[0123] Among them, the gate stack structure can include a gate dielectric layer provided on the outer periphery of the channel region and a gate electrode located on the gate dielectric layer. The material of the gate dielectric layer can be an insulating material such as HfO2, ZrO2, TiO2, or Al2O3. The material of the above-mentioned gate electrode can be a conductive material such as TiN, TaN, or TiSiN.

[0124] Next, a temporary bonding process can be used to bond a carrier wafer on one side of the top of the transistor to prevent damage to the formed structure. Of course, this operation can also not be performed.

[0125] Next, as Figure 22 and Figure 23 shown, processes such as chemical mechanical polishing, wet etching, or dry etching can be used to thin the semiconductor substrate 11 until the pre-formed structure 21 is exposed; and make the bottoms of the source region 14 and the drain region 15 face upward.

[0126] Next, as Figures 24 to 26As shown, by using processes such as dry etching or wet etching, the pre-formed structure, the semiconductor substrate 11 on both sides of the pre-formed structure along the width direction of the channel region 13 included in the transistor 12, and the gate sidewalls 17 on both sides of the source region 14 and / or the drain region 15 along the width direction of the channel region are sequentially removed to form the contact hole 22.

[0127] It should be noted that if a protective layer is formed before manufacturing the pre-formed structure, this step of operation also requires removing the remaining protective layer. Additionally, if a shallow trench isolation structure is formed, selective etching of the shallow trench isolation structure is also required.

[0128] Furthermore, if the width of the portion of the manufactured back contact structure covering the sidewalls of the source region and / or the drain region is greater than the width of the gate sidewall, after sequentially removing the pre-formed structure and the gate sidewalls on both sides of the source region and / or the drain region along the width direction of the channel region, processes such as dry etching or wet etching can be used to selectively etch the insulating dielectric layer to increase the width of the contact hole, facilitating the formation of the back contact structure.

[0129] Next, as Figures 27 to 30 shown, at least by using processes such as physical vapor deposition, a back contact structure 18 disposed in the contact hole is formed. The material of the back contact structure 18 can refer to the foregoing, and will not be elaborated here.

[0130] For the beneficial effects of the second aspect and its various implementation manners in the embodiments of the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, and will not be elaborated here.

[0131] In the above description, technical details such as the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the desired shape. Additionally, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. Moreover, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0132] The above describes the embodiments of the present invention. However, these embodiments are merely for clearer illustration and not for limiting the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor substrate; A transistor disposed on the semiconductor substrate; the transistor includes a channel region, a source region, a drain region, a gate stack structure, and a gate sidewall; The source region and the drain region are respectively disposed on two sides of the channel region along the length direction; the gate stack structure is disposed on the outer periphery of the channel region, and the gate sidewall is disposed at least on two sides of the gate stack structure along the length direction; A back contact structure disposed in the semiconductor substrate and extending upward from a side of the source region and / or the drain region close to the semiconductor substrate to cover at least a partial region on two sidewalls of the source region and / or the drain region along the width direction of the channel region.

2. The semiconductor device according to claim 1, wherein, Along the length direction of the gate stack structure, a sidewall of the back contact structure close to the gate stack structure is aligned with a sidewall of the gate sidewall; in a portion of two sidewalls of the source region and / or the drain region along the width direction of the channel region that contacts the back contact structure, it is aligned with a sidewall of the channel region along the width direction.

3. The semiconductor device according to claim 1 or 2, characterized in that, A width of a portion of the back contact structure covering two sidewalls of the source region and / or the drain region along the width direction of the channel region is greater than a width of the gate sidewall.

4. The semiconductor device according to claim 1 or 2, characterized in that, A height of a portion of the back contact structure covering two sidewalls of the source region and / or the drain region along the width direction of the channel region is less than a height of the gate sidewall.

5. The semiconductor device according to claim 4, wherein In the source region and / or the drain region in electrical contact with the back contact structure, a width of a portion directly in electrical contact with the back contact structure is less than a maximum width of a portion not directly in electrical contact with the back contact structure.

6. The semiconductor device according to claim 1 or 2, characterized in that, In the source region and / or the drain region in electrical contact with the back contact structure, a doping concentration on a side close to the semiconductor substrate is greater than or equal to a doping concentration on a side away from the semiconductor substrate.

7. The semiconductor device according to claim 1 or 2, characterized in that, The material of the source region and / or the drain region in electrical contact with the back contact structure contains a first metal element, and a type of the first metal element is different from a type of a second metal element in the material of the back contact structure.

8. The semiconductor device according to claim 1 or 2, characterized in that, The back contact structure includes a first part and a second part in electrical contact; the first part penetrates through the semiconductor substrate and is in electrical contact with a bottom of the source region and / or the drain region; the second part extends to a sidewall of the source region and / or the drain region and is in electrical contact with the sidewall of the source region and / or the drain region.

9. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a semiconductor substrate; Forming a transistor on the semiconductor substrate and forming a preformed structure in a portion of the semiconductor substrate below the source region and / or the drain region included in the transistor; the gate sidewall included in the transistor is disposed at least on two sides of the gate stack structure along the length direction and two sides of the source region and the drain region along the width direction of the channel region; Thinning the semiconductor substrate until the preformed structure is exposed; and turning the bottom of the source region and the drain region upward; Remove the preformed structure, the semiconductor substrate on both sides of the preformed structure along the width direction of the channel region included in the transistor, and the gate sidewalls on both sides of the source region and / or the drain region along the width direction of the channel region in sequence to form a contact hole; Form a back contact structure disposed in the contact hole.

10. The manufacturing method of the semiconductor device according to claim 9, characterized in that, Form the transistor and the preformed structure on the semiconductor substrate, including: Form a fin structure and a first mask structure on the semiconductor substrate; the first mask structure includes a sacrificial gate and the gate sidewalls; the sacrificial gate straddles the fin structure, and the gate sidewalls are disposed at least on both sides of the sacrificial gate along the length direction and on both sides of the fin structure along the width direction; Selectively etch the fin structure under the protection of the first mask structure; and selectively etch a part of the semiconductor substrate exposed on at least one side of the remaining fin structure on both sides to form a first opening in the semiconductor substrate; Form the preformed structure in the first opening; Epitaxially form the source region and the drain region; and make the remaining fin structure form a channel region; Form a gate stack structure on the outer periphery of the channel region to obtain the transistor.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, After forming the first opening and before epitaxially forming the source region and the drain region, the manufacturing method of the semiconductor device includes: Form a protective layer covering the gate sidewalls and the inner wall of the first opening; Adopt a deposition process to form a preformed material covering the protective layer and filling the first opening; Selectively etch the preformed material under the protection of the protective layer so that the remaining preformed material is only located in the first opening to obtain the preformed structure; Remove the part of the protective layer covering the gate sidewalls.

12. The manufacturing method of the semiconductor device according to claim 10, characterized in that, In the case where only one of the source region and the drain region included in the transistor is in electrical contact with the back contact structure, after selectively etching the fin structure and before forming the first opening, the manufacturing method of the semiconductor substrate further includes: forming at least a second mask structure on the semiconductor substrate; the second mask structure is used to cover one side of the semiconductor substrate exposed on one side of the remaining fin structure on both sides; After forming the preformed structure in the first opening and before epitaxially forming the source region and the drain region, the manufacturing method of the semiconductor device further includes: removing the second mask structure.

13. The manufacturing method of the semiconductor device according to claim 9, characterized in that, After forming the transistor on the semiconductor substrate and before thinning the semiconductor substrate, the manufacturing method of the semiconductor device further includes: Form an insulating dielectric layer covering the transistor.

14. The manufacturing method of the semiconductor device according to claim 13, characterized in that, After sequentially removing the preformed structure and the gate sidewalls on both sides of the source region and / or the drain region along the width direction of the channel region and before forming the back contact structure disposed in the contact hole, the manufacturing method of the semiconductor device further includes: Selectively etch the insulating dielectric layer to increase the width of the contact hole.

15. The method for manufacturing a semiconductor device according to claim 10, characterized in that, After forming the fin structure and the first mask structure on the semiconductor substrate and before epitaxially forming the source region and the drain region, the manufacturing method of the semiconductor device further includes: Selectively etching the gate sidewall so that the height of the gate sidewalls disposed on both sides of the fin structure in the width direction is less than the height of the gate sidewalls disposed on both sides of the sacrificial gate in the length direction.

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