Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for reducing electrical interference between a first transistor and a second transistor and improving the working performance of the semiconductor device. The semiconductor device comprises a semiconductor substrate, a first transistor, a second transistor, a first isolation structure and a second isolation structure. The first transistor and the second transistor are sequentially arranged on the semiconductor substrate in the thickness direction of the semiconductor substrate. The first isolation structure is arranged between the source and drain regions included in the first transistor and the source and drain regions included in the second transistor. The second isolation structure is disposed between the gate stack structure included in the first transistor and the gate stack structure included in the second transistor. The second isolation structure comprises a first isolation part and second isolation parts located on the two sides of the first isolation part in the width direction of channel regions included in the first transistor and the second transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method thereof. Background Art

[0002] A three-dimensional stacked transistor includes two transistors vertically stacked, eliminating the lateral spacing between the two transistors, which allows for further increasing the effective channel width, thus facilitating the improvement of the working performance and integration degree of the semiconductor device.

[0003] However, in the existing three-dimensional stacked transistors, there is interference between the upper and lower transistors, which is not conducive to improving the working performance of the three-dimensional stacked transistors. Summary of the Invention

[0004] The purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof, which are used to reduce the electrical interference between the first transistor and the second transistor and improve the working performance of the semiconductor device.

[0005] To achieve the above purpose, in a first aspect, the present invention provides a semiconductor device, which includes: a semiconductor substrate, a first transistor, a second transistor, a first isolation structure, and a second isolation structure. Along the thickness direction of the semiconductor substrate, the first transistor and the second transistor are sequentially arranged on the semiconductor substrate. The first isolation structure is arranged between the source-drain regions included in the first transistor and the source-drain regions included in the second transistor. The second isolation structure is arranged between the gate stack structures included in the first transistor and the gate stack structures included in the second transistor. Along the width direction of the channel regions included in the first transistor and the second transistor, the second isolation structure includes a first isolation portion and second isolation portions located on both sides of the first isolation portion.

[0006] In the case of adopting the above technical solution, the first transistor and the second transistor included in the semiconductor device are spaced apart along the thickness direction of the semiconductor substrate, and the first isolation structure is arranged between the source-drain regions included in the second transistor and the source-drain regions included in the first transistor to prevent leakage. Obviously, in the semiconductor device provided by the present invention, the first transistor and the second transistor can form a three-dimensional stacked transistor (CFET device) to improve the integration degree of the semiconductor device.

[0007] In addition, the semiconductor device further includes a second isolation structure disposed between the gate stack structure included in the first transistor and the gate stack structure included in the second transistor. The first isolation portion and the second isolation portion included in the second isolation structure can isolate the portion of the gate stack structure in the first transistor disposed outside the channel region from the portion of the gate stack structure in the second transistor disposed outside the channel region, reducing the electrical interference therebetween. Moreover, the first isolation portion and the second isolation portion included in the second isolation structure are arranged at intervals along the width direction of the channel region. At this time, along the thickness direction of the semiconductor substrate, the portion of the gate stack structure in the first transistor disposed outside the channel region and the portion of the gate stack structure in the second transistor disposed outside the channel region support the first isolation portion and the second isolation portion having isolation characteristics, which is beneficial to improving the isolation effect of the second isolation structure, reducing the electrical interference between the first transistor and the second transistor, and improving the working performance of the semiconductor device.

[0008] In one example, there is an interface between the first isolation portion and the second isolation portion.

[0009] In one example, the materials of the first isolation portion and the second isolation portion are different.

[0010] In one example, the material of the second isolation portion includes an oxide of a semiconductor material. The semiconductor material is different from the materials of the channel regions included in the first transistor and the second transistor.

[0011] In one example, the germanium content in the semiconductor material is higher than the germanium content in the channel region materials included in the first transistor and the second transistor.

[0012] In one example, in the sidewalls of the first isolation portion and / or the second isolation portion along the length direction of the gate stack structure, the surfaces of different regions are substantially aligned.

[0013] In one example, the sidewall of the second isolation portion along the width direction of the channel region is arc-shaped and concave into the second isolation portion.

[0014] In one example, along the width direction of the channel region, the width of the second isolation portion is greater than or equal to one-sixth times the width of the channel region and less than or equal to one-half times the width of the channel region.

[0015] In one example, in the second isolation structure on the same layer, a single first isolation portion and / or second isolation portion is continuously distributed between the two interfaces of the second isolation structure along the thickness direction.

[0016] In one example, the semiconductor device includes multiple layers of second isolation structures disposed at intervals along the thickness direction of the semiconductor substrate.

[0017] In one example, the gate stack structure is filled between two adjacent layers of the second isolation structure.

[0018] In one example, the first transistor and / or the second transistor is a gate-all-around transistor.

[0019] In a second aspect, the present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: First, a fin structure is formed on a semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin structure includes a first fin portion, a semiconductor isolation portion, and a second fin portion arranged in sequence. The semiconductor isolation portion includes a first semiconductor isolation layer. The material of the first semiconductor isolation layer is different from the materials of the first fin portion and the second fin portion. Next, along a first direction, two side edge portions of the first semiconductor isolation layer are selectively removed; and first isolation portions are formed on both sides of the remaining first semiconductor isolation layer. Next, the remaining first semiconductor isolation layer is made to form a second isolation portion. Next, a first transistor is formed based on one of the first fin portion and the second fin portion; and a second transistor is formed based on the other of the first fin portion and the second fin portion. The first direction is parallel to the width direction of the channel regions included in the first transistor and the second transistor. Next, a first isolation structure is formed between the source-drain regions included in the first transistor and the source-drain regions included in the second transistor.

[0020] In one example, a selective oxidation process is used to make the remaining first semiconductor isolation layer form the second isolation portion.

[0021] In one example, after the first isolation portions are formed on both sides of the remaining first semiconductor isolation layer and before the first transistor is formed based on one of the first fin portion and the second fin portion, the method for manufacturing the semiconductor device includes: forming a mask structure spanning the fin structure. Next, the portions of the fin structure and the first isolation portions exposed outside the mask structure are removed. Next, the remaining first semiconductor isolation layer is selectively removed. Next, a second isolation portion is formed between the two first isolation portions.

[0022] In one example, the semiconductor isolation portion includes multiple layers of first semiconductor isolation layers spaced apart along the thickness direction of the semiconductor substrate. The semiconductor isolation portion further includes a second semiconductor isolation layer at least between adjacent two layers of the first semiconductor isolation layers. The material of the first semiconductor isolation layer is different from the material of the second semiconductor isolation layer. And, after the source-drain regions included in the first transistor and the second transistor are formed and before the gate stack structures included in the first transistor and the second transistor are formed, the second semiconductor isolation layer is removed.

[0023] In one example, forming the first transistor, the second transistor, and the first isolation structure includes: forming a mask structure across the fin structure. Next, at least remove the portions of the fin structure and the first isolation portion that are exposed outside the mask structure. Next, form the source / drain regions included in the first transistor on both sides of the remaining first fin portion. Next, form the first isolation structure on the source / drain regions included in the first transistor. Next, form the source / drain regions included in the second transistor on both sides of the remaining first fin portion. Next, form the channel region included in the first transistor based on the remaining first fin portion; and form the channel region included in the second transistor based on the remaining second fin portion. Next, form a gate stack structure at least on the outer periphery of the channel region included in the first transistor and on the outer periphery of the channel region included in the second transistor.

[0024] For the beneficial effects of the second aspect and its various implementations in the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementations, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings described herein are used to provide a further understanding of the present invention and form a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0026] Figure 1 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure One ;

[0027] Figure 2 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Two ;

[0028] Figure 3 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Three ;

[0029] Figure 4 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Four ;

[0030] Figure 5 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Five ;

[0031] Figure 6 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Six ;

[0032] Figure 7 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing processFigure Seven ;

[0033] Figure 8 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Eight ;

[0034] Figure 9 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Nine ;

[0035] Figure 10 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten ;

[0036] Figure 11 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten One;

[0037] Figure 12 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Two;

[0038] Figure 13 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Three;

[0039] Figure 14 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Four;

[0040] Figure 15 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Five;

[0041] Figure 16 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Six;

[0042] Figure 17 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Seven;

[0043] Figure 18 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Eight;

[0044] Figure 19 Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Ten Nine;

[0045] Figure 20 Structural schematic of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Two Ten;

[0046] Figure 21 Structural schematic of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Two Eleven;

[0047] Figure 22 Structural schematic of the semiconductor device provided by the embodiment of the present invention during the manufacturing process Figure Two Twelve.

[0048] Reference numerals: 11 is a semiconductor substrate, 12 is a first transistor, 13 is a second transistor, 14 is a first isolation structure, 15 is a second isolation structure, 16 is a source-drain region, 17 is a channel region, 18 is a gate stack structure, 19 is a first isolation portion, 20 is a second isolation portion, 21 is a channel layer, 22 is a gate sidewall, 23 is a shallow trench isolation structure, 24 is an interlayer dielectric layer, 25 is an inner sidewall, 26 is a fin structure, 27 is a first fin portion, 28 is a second fin portion, 29 is a semiconductor isolation portion, 30 is a first semiconductor isolation layer, 31 is a second semiconductor isolation layer, 32 is a mask structure, 33 is a sacrificial gate, 34 is a sacrificial layer. Detailed implementation manners

[0049] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present invention.

[0050] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, where in order to express more clearly, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0051] In the context of the present invention, when a layer / component is referred to as being "on" another layer / component, the layer / component may be directly on the other layer / component, or there may be an intermediate layer / component therebetween. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component may be "under" the other layer / component. In order to make the technical problems, technical solutions, and beneficial effects to be solved by the present invention more clear and understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0052] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0053] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0054] The three-dimensional stacked transistor includes two transistors stacked vertically, eliminating the lateral spacing between the two transistors, which allows for further increasing the effective channel width, thereby facilitating the improvement of the working performance and integration degree of the semiconductor device. However, in existing three-dimensional stacked transistors, the upper and lower layer transistors often have direct electrical contact, and there is interference between them, which is not conducive to improving the working performance of the three-dimensional stacked transistor.

[0055] To solve the above technical problems, embodiments of the present invention provide a semiconductor device and a manufacturing method thereof. Among them, in the semiconductor device provided by the embodiments of the present invention, the first transistor and the second transistor are spaced apart along the thickness direction of the semiconductor substrate, and a first isolation structure is disposed between the source-drain regions included in the second transistor and the source-drain regions included in the first transistor to prevent leakage. In addition, the semiconductor device further includes a second isolation structure disposed between the gate stack structure included in the first transistor and the gate stack structure included in the second transistor. The second isolation structure can isolate the part of the gate stack structure in the first transistor disposed outside the channel region from the part of the gate stack structure in the second transistor disposed outside the channel region, reducing the electrical interference therebetween.

[0056] In a first aspect, embodiments of the present invention provide a semiconductor device. As Figures 20 to 22 shown, the semiconductor device includes: a semiconductor substrate 11, a first transistor 12, a second transistor 13, a first isolation structure 14, and a second isolation structure 15. Along the thickness direction of the semiconductor substrate 11, the first transistor 12 and the second transistor 13 are sequentially disposed on the semiconductor substrate 11. The first isolation structure 14 is disposed between the source-drain regions 16 included in the first transistor 12 and the source-drain regions 16 included in the second transistor 13. The second isolation structure 15 is disposed between the gate stack structure 18 included in the first transistor 12 and the gate stack structure 18 included in the second transistor 13. Along the width direction of the channel regions 17 included in the first transistor 12 and the second transistor 13, the second isolation structure 15 includes a first isolation portion 19 and second isolation portions 20 located on both sides of the first isolation portion 19.

[0057] In the case of adopting the above technical solution, as Figures 20 to 22As shown, the first transistor 12 and the second transistor 13 included in the semiconductor device are spaced apart along the thickness direction of the semiconductor substrate 11, and a first isolation structure 14 is disposed between the source-drain regions 16 included in the second transistor 13 and the source-drain regions 16 included in the first transistor 12 to prevent leakage. Obviously, in the semiconductor device provided by the embodiment of the present invention, the first transistor 12 and the second transistor 13 can form a three-dimensional stacked transistor (CFET device) to improve the integration degree of the semiconductor device. In addition, the semiconductor device further includes a second isolation structure 15 disposed between the gate stack structure 18 included in the first transistor 12 and the gate stack structure 18 included in the second transistor 13. The first isolation portion 19 and the second isolation portion 20 included in the second isolation structure 15 can isolate the portion of the gate stack structure 18 in the first transistor 12 disposed outside the channel region 17 from the portion of the gate stack structure 18 in the second transistor 13 disposed outside the channel region 17, reducing the electrical interference therebetween. Moreover, the first isolation portion 19 and the second isolation portion 20 included in the second isolation structure 15 are spaced apart along the width direction of the channel region 17. At this time, along the thickness direction of the semiconductor substrate 11, the portion of the gate stack structure 18 in the first transistor 12 disposed outside the channel region 17 and the portion of the gate stack structure 18 in the second transistor 13 disposed outside the channel region 17 support the first isolation portion 19 and the second isolation portion 20 having isolation characteristics, which is beneficial to improving the isolation effect of the second isolation structure 15, reducing the electrical interference between the first transistor 12 and the second transistor 13, and improving the working performance of the semiconductor device.

[0058] In the actual application process, the embodiment of the present invention does not specifically limit the structure and material of the semiconductor substrate, which can be set according to actual needs. Exemplarily, the semiconductor substrate can be a substrate of any semiconductor material such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a silicon-on-insulator substrate.

[0059] For the first transistor and the second transistor, in terms of the device type, the embodiment of the present invention does not specifically limit the device types of the first transistor and the second transistor, as long as they can be formed on the semiconductor substrate.

[0060] Exemplarily, the first transistor and / or the second transistor can be a fin field-effect transistor or a gate-all-around transistor.

[0061] Optionally, as Figures 20 to 22 shown, the first transistor 12 and the second transistor 13 can both be gate-all-around transistors to improve their gate control ability and be beneficial to improving the driving performance of the semiconductor device.

[0062] In terms of the structure, the specific structures of the first transistor and the second transistor can be set according to their own device types and actual needs, and are not specifically limited herein.

[0063] Exemplarily, when the first transistor and / or the second transistor is a fin field-effect transistor, the fin field-effect transistor may include a channel region, source / drain regions, and a gate stack structure. The source / drain regions are disposed on two sides of the channel region along the length direction, and the gate stack structure is disposed on the top and sidewalls of the channel region.

[0064] Exemplarily, when the first transistor and / or the second transistor is a gate-all-around transistor, the gate-all-around transistor may include a channel region, source / drain regions, and a gate stack structure. The source / drain regions are disposed on two sides of the channel region along the length direction, and the gate stack structure surrounds the outer periphery of the channel region. Specifically, as Figures 20 to 22 shown, the channel region 17 may include only one layer of nanostructure; or, as Figures 20 to 22 shown, the channel region 17 may also include multiple layers of nanostructures distributed at intervals along the thickness direction of the semiconductor substrate 11. The embodiments of the present invention do not specifically limit the number of layers of nanostructures in the channel region 17 included in the first transistor 12 and the second transistor 13. Specifically, the materials of different layers of nanostructures included in the channel region 17 may be the same or different.

[0065] It should be noted that it may be that the source region included in the second transistor and the source region included in the first transistor are on the same side along the length direction of the gate stack structure; or, it may also be that the drain region included in the second transistor and the source region included in the first transistor are on the same side along the length direction of the gate stack structure.

[0066] In terms of materials, in the first transistor and the second transistor, the materials of the source / drain regions and the channel region may include any semiconductor material such as silicon, silicon-germanium, or germanium, which is not specifically limited herein. Among them, the material of the channel region included in the first transistor and / or the second transistor may be a germanium-containing semiconductor material or a germanium-free semiconductor material. It can be understood that when the material of the channel region is a germanium-free semiconductor material, the germanium content in the material of the channel region is 0. When the material of the channel region is a germanium-containing semiconductor material, the germanium content in the material of the channel region is greater than 0, and the specific germanium content can be set according to actual needs. Secondly, the material of the source / drain region may be the same as or different from the material of the channel region. In addition, the materials of the channel regions included in the first transistor and the second transistor may be the same or different. The materials of the source / drain regions included in the first transistor and the second transistor may be the same or different.

[0067] The gate stack structure included in the first transistor and the gate stack structure included in the second transistor may include: a gate dielectric layer disposed on the outer periphery of the channel region, and a gate electrode located on the gate dielectric layer. Among them, the material of the gate dielectric layer included in the first transistor and / or the second transistor may be an insulating material such as HfO2, ZrO2, TiO2 or Al2O3. The material of the gate electrode included in the first transistor and / or the second transistor may be a conductive material such as TiN, TaN or TiSiN. The materials of the gate stack structures included in the first transistor and the second transistor may be the same or different.

[0068] For the first isolation structure, the embodiments of the present invention do not specifically limit the material and thickness of the first isolation structure, as long as the first isolation structure can be disposed to electrically isolate the source / drain region included in the second transistor from the source / drain region and / or the channel region included in the first transistor.

[0069] For the second isolation structure, as Figure 20 and Figure 22 shown, along the width direction of the channel regions 17 included in the first transistor 12 and the second transistor 13, the second isolation structure 15 includes a first isolation portion 19 and second isolation portions 20 located on both sides of the first isolation portion 19. In terms of materials, the materials of the first isolation portion 19 and the second isolation portions 20 may include any non-conductive isolation material such as silicon oxide, silicon nitride or silicon oxynitride. Specifically, the materials of the first isolation portion 19 and the second isolation portions 20 may be the same or different.

[0070] The first isolation portion and / or the second isolation portions may be a single-layer structure or a multi-layer structure. Among them, when the first isolation portion is a laminated structure, the first isolation portion may include a plurality of nested "C"-shaped structures and a "one"-shaped structure located inside the innermost "C"-shaped structure. When the second isolation portions are a laminated structure, the second isolation portions may include a plurality of nested "square"-shaped structures and a solid columnar structure located inside the innermost "square"-shaped structure.

[0071] Exemplarily, the material of the second isolation portions includes an oxide of a semiconductor material. The type of the semiconductor material may be set according to actual needs as long as the isolation function can be achieved. For example: the semiconductor material may be different from the material of the channel regions included in the first transistor and the second transistor. In this case, during the actual application process, as Figure 7 and Figure 8As shown, after forming the first isolation structure 14, since the materials of the first semiconductor isolation layer are different from those of the first fin and the second fin respectively, only the remaining first semiconductor isolation layer can be selectively oxidized to form the second isolation structure 15, without etching away the remaining first semiconductor isolation layer and then forming the second isolation structure 15 through deposition and etching processes, which helps simplify the manufacturing process of semiconductor devices and improve the manufacturing efficiency of semiconductor devices.

[0072] Exemplarily, when the material of the second isolation portion includes an oxide of a semiconductor material, the germanium content in the semiconductor material can be higher than the germanium content in the channel region materials included in the first transistor and the second transistor. In this case, based on the difference in the higher germanium content in this semiconductor material, the second isolation portion can be formed by selective oxidation, and at the same time, the channel region can be reduced or even not affected by selective oxidation, improving the yield of semiconductor devices. Among them, the difference in the germanium content in the semiconductor material and the germanium content in the channel region materials included in the first transistor and the second transistor can be set according to actual needs, and no specific limitation is made here. In addition, the germanium content in the channel region materials included in the first transistor and the second transistor can be equal to 0 or greater than 0.

[0073] In addition, as Figures 20 to 22 shown, there can be an interface between the first isolation portion 19 and the second isolation portion 20. The specific morphology of the interface between the two can be determined according to the manufacturing processes of the first isolation portion 19 and the second isolation portion 20, and no specific limitation is made here.

[0074] Exemplarily, the sidewall of the second isolation portion along the width direction of the channel region can be arc-shaped and concave into the second isolation portion. Or, as Figure 21 shown, the sidewall of the second isolation portion 20 along the width direction of the channel region 17 can also be a plane-like shape substantially parallel to the thickness direction of the channel region 17.

[0075] As for the width direction along the channel region, the width of the second isolation portion can be set according to the specifications of the first transistor and the second transistor and actual needs, and no specific limitation is made here.

[0076] Exemplarily, the width of the second isolation portion can be greater than or equal to one-sixth times the width of the channel region and less than or equal to one-half times the width of the channel region. Among them, when the widths of the first transistor and the second transistor are different, the width of the second isolation portion can be greater than or equal to one-sixth times the width of the channel region included in the first transistor and less than or equal to one-half times the width of the channel region. Or, it can also be that the width of the second isolation portion is greater than or equal to one-sixth times the width of the channel region included in the second transistor and less than or equal to one-half times the width of the channel region. With such a setting, as Figures 4 to 6As shown, in the actual manufacturing process, before forming the mask structure, selective etching can be performed on the semiconductor isolation portion 29 in the fin structure 26 in the width direction to form a space for filling the first isolation portion 19. At this time, the remaining semiconductor isolation portion 29 needs to support the second fin portion 28 located above to prevent the fin structure 26 from tilting or collapsing. Based on this, within the above range of the width of the second isolation portion 20, it is possible to prevent the time required for selectively etching the remaining semiconductor isolation portion 29 from being too long after forming the mask structure 32 and etching the fin structure 26 subsequently, reduce the impact of the etchant on the channel layer 21, and improve the yield of the semiconductor device. In addition, it is also possible to prevent risks such as tilting or collapsing that are likely to occur due to the too small width of the second isolation portion 20, improve the yield of the semiconductor device, and at the same time, there is no need to etch too much isolation material during subsequent source-drain etching, reducing the etching difficulty.

[0077] As for the sidewall topography of the second isolation structure along the length direction of the gate stack structure, such as Figures 20 to 22 shown, in the sidewalls of the first isolation portion 19 and / or the second isolation portion 20 included in the second isolation structure 15 along the length direction of the gate stack structure 18, the surfaces of different regions can be substantially aligned so that each part of the second isolation structure 15 has a good isolation effect and further reduces electrical interference.

[0078] In addition, by way of example, as Figure 20 and Figure 22 shown, in the second isolation structure 15 on the same layer, a single first isolation portion 19 and / or a second isolation portion 20 can be continuously distributed between two interfaces of the second isolation structure 15 in the thickness direction so that each part of the second isolation structure 15 in the thickness direction has a good isolation effect and further reduces electrical interference.

[0079] In addition, the semiconductor device can include only a single layer of the second isolation structure. Or, as Figure 20 and Figure 22 shown, the semiconductor device also includes multiple layers of the second isolation structure 15 spaced apart in the thickness direction of the semiconductor substrate 11; at this time, as Figures 20 to 21As shown, the gate stack structure 18 can be filled between two adjacent layers of the second isolation structure 15. Alternatively, the semiconductor device may further include a third isolation structure (not shown in the figure) filled between two adjacent layers of the second isolation structure. In this case, the gate stack structures near the channel regions in the first transistor and the second transistor can be completely isolated from each other by the second isolation structure and the third isolation structure, so as to further reduce electrical interference. The material of the third isolation structure may include any non-conductive isolation material such as silicon oxide, silicon nitride, or silicon oxynitride. The material of the third isolation structure may be the same as or different from that of the first isolation portion or the second isolation portion.

[0080] In some cases, such as Figure 22 As shown, the semiconductor device provided by the embodiment of the present invention may further include a gate sidewall 22 and / or an inner sidewall 25. The gate sidewall 22 is disposed on both sides of the gate stack structure 18 included in the first transistor 12 and the second transistor 13 along the length direction, and is used to separate the gate stack structure 18 from other adjacent conductive structures, thereby reducing the risk of leakage. The inner sidewall 25 is disposed between the gate stack structure 18 and the source / drain region 16 to limit the length of the gate stack structure 18. The material of the inner sidewall 25 and / or the gate sidewall 22 may include any insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0081] In some cases, such as Figure 20 and Figure 22 As shown, the semiconductor device provided by the embodiment of the present invention may further include an interlayer dielectric layer 24. The interlayer dielectric layer 24 covers the second transistor 13. The top of the interlayer dielectric layer 24 is flush with the top of the gate stack structure 18 included in the second transistor 13, so as to protect the source / drain region 16 from the etching and cleaning operations for removing structures such as the sacrificial gate 33, and improve the yield of the semiconductor device. As for the material of the interlayer dielectric layer 24, it may include any insulating material such as silicon oxide, silicon oxynitride, or silicon nitride, and no specific limitation is made here.

[0082] In some cases, such as Figure 21 As shown, the semiconductor device provided by the embodiment of the present invention may further include a shallow trench isolation structure 23. The shallow trench isolation structure 23 is formed on the semiconductor substrate 11 and is used to define the active region of the semiconductor substrate 11, reduce the risk of leakage, and further improve the yield and working performance of the semiconductor device. As for the material of the shallow trench isolation structure 23, it may include any insulating material such as silicon oxide, silicon oxynitride, or silicon nitride, and no specific limitation is made here.

[0083] In a second aspect, the embodiment of the present invention provides a method for manufacturing a semiconductor device. The following will be based on Figures 1 to 22A perspective view or a cross-sectional view of the operations shown describes the manufacturing process. Specifically, the manufacturing method of the semiconductor device includes the steps: First, as Figures 1 to 3 shown, a fin structure 26 is formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the fin structure 26 includes a first fin portion 27, a semiconductor isolation portion 29, and a second fin portion 28 arranged in sequence. The semiconductor isolation portion 29 includes a first semiconductor isolation layer 30. The material of the first semiconductor isolation layer 30 is different from the materials of the first fin portion 27 and the second fin portion 28. Next, as Figures 4 to 6 shown, along a first direction, the two side edge portions of the first semiconductor isolation layer 30 are selectively removed; and first isolation portions 19 are formed on both sides of the remaining first semiconductor isolation layer 30. Next, as Figures 7 to 14 shown, the remaining first semiconductor isolation layer 30 is made to form a second isolation portion 20. Next, as Figures 15 to 22 shown, a first transistor 12 is formed based on one of the first fin portion 27 and the second fin portion 28; and a second transistor 13 is formed based on the other of the first fin portion 27 and the second fin portion 28. The first direction is parallel to the width direction of the channel regions 17 included in the first transistor 12 and the second transistor 13. Next, as Figure 16 shown, a first isolation structure 14 is formed between the source-drain regions 16 included in the first transistor 12 and the source-drain regions 16 included in the second transistor 13.

[0084] It should be noted that the structure of the semiconductor device formed by the manufacturing method provided in the second aspect of the embodiments of the present invention is the same as the structure of the semiconductor device provided in the first aspect. Therefore, for the beneficial effects of the second aspect and its various implementation manners in the embodiments of the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, and details are not described herein again.

[0085] In the actual manufacturing process, in the above fin structure, either the first fin portion or the second fin portion can be used to manufacture the first transistor. Therefore, the specific structure of the one of the first fin portion and the second fin portion used to manufacture the first transistor can be determined according to the device type and details of the first transistor.

[0086] Exemplarily, taking the first transistor as a fin field-effect transistor and the first fin portion being used to manufacture the first transistor as an example for illustration: The first fin portion can be a single-layer strip-shaped semiconductor structure; or, it can also be a strip-shaped semiconductor structure including multiple semiconductor layers. And, the material of the first fin portion is the same as the material of the channel region included in the first transistor.

[0087] Exemplarily, taking the first transistor as a gate-all-around transistor and the first fin being used to fabricate the first transistor as an example for illustration: The first fin may include at least one semiconductor stack. Each semiconductor stack includes sacrificial layers and channel layers stacked alternately. Among the alternately stacked sacrificial layers and channel layers, the bottom layer and the top layer are both sacrificial layers. Among them, the channel layers included in the first fin are used to fabricate nanostructures in the channel region included in the first transistor. Therefore, the material of the channel layers included in the first fin can be determined according to the material of the channel region included in the first transistor. As for the sacrificial layers included in the first fin, the sacrificial layers of the first fin covered by the mask structure need to be removed subsequently to release the channel region included in the first transistor. Moreover, when selectively removing the sacrificial layers included in the first fin, the second fin (or the channel layers included in the second fin) will be retained. Therefore, the material of the sacrificial layers included in the first fin can be any semiconductor material different from the channel layers included in the first fin and the second fin (or the channel layers included in the second fin). For example, when the materials of the channel layers included in the first fin and the second fin are silicon, the material of the sacrificial layers included in the first fin can be silicon germanium or germanium.

[0088] Similarly, the other of the first fin and the second fin is used to fabricate the second transistor. Therefore, the specific structure of the one of the first fin and the second fin used to fabricate the second transistor can be determined according to the device type and specific structure of the second transistor.

[0089] Exemplarily, taking the second transistor as a fin field-effect transistor and the second fin being used to fabricate the second transistor as an example for illustration: The second fin can be a single-layer strip-shaped semiconductor structure; or it can also be a strip-shaped semiconductor structure including multiple semiconductor layers. Moreover, the material of the second fin is the same as the material of the channel region included in the second transistor.

[0090] Exemplarily, taking the second transistor as a gate-all-around transistor and the second fin being used to fabricate the second transistor as an example for illustration: The second fin may include at least one layer of semiconductor stack. Each layer of semiconductor stack includes a sacrificial layer and a channel layer located on the sacrificial layer. Among them, the channel layer included in the second fin is used to fabricate the nanostructure in the channel region included in the second transistor. Therefore, the material of the channel layer included in the second fin can be determined according to the material of the channel region included in the second transistor. As for the sacrificial layer included in the second fin, subsequently, the sacrificial layer of the second fin covered by the mask structure needs to be removed to release the channel region included in the second transistor. And when selectively removing the sacrificial layer included in the second fin, the first fin (or the channel layer included in the first fin) will be retained. Therefore, the material of the sacrificial layer included in the second fin can be any semiconductor material different from the channel layer included in the second fin and the first fin (or the channel layer included in the first fin). Additionally, when both the first transistor and the second transistor are gate-all-around transistors, the materials of the sacrificial layers included in the first fin and the second fin can be the same to reduce the limitation of the epitaxial critical thickness and facilitate improving the formation quality of the semiconductor device; of course, the materials of the two can also be different.

[0091] As for the semiconductor isolation part included in the fin structure, this semiconductor isolation part plays a pre-occupation role. Subsequently, a first isolation structure located between the source / drain regions included in the first transistor and the source / drain regions included in the second transistor will be formed in the space where the semiconductor isolation part not covered by the mask structure is located. And a first isolation structure located between the gate stack structure included in the first transistor and the gate stack structure included in the second transistor will be formed in the space where the semiconductor isolation part corresponding to the gate formation region is located. Therefore, the thickness of the semiconductor isolation part can be determined according to the thickness requirements of the first isolation structure and the second isolation structure. The specific structure of the semiconductor isolation part is determined according to the specific structure of the second isolation structure. For example: When in the fabricated semiconductor device, the second isolation structure is a single-layer structure, as shown at this time, the semiconductor isolation part 29 can also be a single-layer structure (that is, the semiconductor isolation part 29 can only include one layer of the first semiconductor isolation layer). When the fabricated semiconductor device includes multiple layers of second isolation structures spaced along the thickness direction of the semiconductor substrate, as shown in and, the semiconductor isolation part 29 includes multiple layers of the first semiconductor isolation layers 30 spaced along the thickness direction of the semiconductor substrate 11. The semiconductor isolation part 29 further includes at least the second semiconductor isolation layer 31 located between adjacent two layers of the first semiconductor isolation layers 30. The material of the first semiconductor isolation layer 30 is different from the material of the second semiconductor isolation layer 31. Figure 2 shown, the semiconductor isolation part 29 can also be a single-layer structure (i.e., the semiconductor isolation part 29 can only include one layer of the first semiconductor isolation layer). When the fabricated semiconductor device includes multiple layers of second isolation structures spaced along the thickness direction of the semiconductor substrate, as shown in Figure 1 and Figure 3 shown, the semiconductor isolation part 29 includes multiple layers of the first semiconductor isolation layers 30 spaced along the thickness direction of the semiconductor substrate 11. The semiconductor isolation part 29 further includes at least the second semiconductor isolation layer 31 located between adjacent two layers of the first semiconductor isolation layers 30. The material of the first semiconductor isolation layer 30 is different from the material of the second semiconductor isolation layer 31.

[0092] As for the material of the semiconductor isolation part, it can be set according to the structure of the semiconductor isolation part and actual requirements. Specifically, the material of the first semiconductor isolation layer included in the semiconductor isolation part can be any semiconductor material different from that of the first fin part and the second fin part, and no specific limitation is made here. When the semiconductor isolation part further includes a second semiconductor isolation layer, the material of the second semiconductor isolation layer can be set according to actual requirements. For example: when in the manufactured semiconductor device, the substance between two adjacent second isolation parts is a gate stack structure, the material of the second semiconductor isolation layer can be substantially the same as that of the sacrificial layer. And when in the manufactured semiconductor device, the substance between two adjacent second isolation parts is a third isolation structure, the material of the second semiconductor isolation layer is any semiconductor material different from that of the first semiconductor isolation layer, the first fin part and the second fin part.

[0093] Exemplarily, taking the first transistor and the second transistor both being gate-all-around transistors as an example for illustration: The material of the channel region included in the first fin part and the second fin part can include silicon. The material of the sacrificial layer included in the first fin part and the second fin part can be silicon germanium. In the semiconductor isolation part, the materials of the first semiconductor isolation layer and the second semiconductor isolation layer can both be silicon germanium. The germanium content in the second semiconductor isolation layer can be the same as the germanium content in the sacrificial layer. The germanium content in the first semiconductor isolation layer can be higher than the germanium content in the second semiconductor isolation layer and the sacrificial layer.

[0094] Exemplarily, taking the first transistor and the second transistor both being gate-all-around transistors as an example for illustration: As Figure 1 shown, processes such as epitaxy can be adopted to form the sacrificial layer 34 and the channel layer 21 for manufacturing the first fin part and the second fin part along the thickness direction of the semiconductor substrate 11, and form the first semiconductor isolation layer 30 and the second semiconductor isolation layer 31. Then, processes such as photolithography and etching are adopted to pattern the above-mentioned sacrificial layer, channel layer, first semiconductor isolation layer, second semiconductor isolation layer, and part of the semiconductor substrate to form a Fin structure. Next, as Figure 2 and Figure 3 shown, processes such as deposition and etching can be adopted to form a shallow trench isolation structure 23 for defining an active region between adjacent Fin structures. The top height of the shallow trench isolation structure 23 is less than or equal to the bottom height of the sacrificial layer 34 at the bottom layer. Among them, the part of the Fin structure exposed outside the shallow trench isolation structure 23 is a fin structure 26.

[0095] It should be noted that when the manufactured semiconductor device does not include the above-mentioned shallow trench isolation structure, only the sacrificial layer, channel layer, first semiconductor isolation layer, and second semiconductor isolation layer can be patterned; and a fin structure can be directly obtained after the patterning process.

[0096] After forming the fin structure, asFigure 4 As shown, processes such as dry etching or wet etching can be used to selectively remove the edge portions on both sides of the first semiconductor isolation layer 30 along the first direction.

[0097] Next, processes such as deposition and etching can be successively used, as Figure 5 and Figure 6 shown, to form first isolation portions on both sides of the remaining first semiconductor isolation layer. The material of the first isolation portions can refer to the foregoing.

[0098] Next, as Figure 7 and Figure 8 shown, a selective oxidation process can be used to form the second isolation portion 20 from the remaining first semiconductor isolation layer 30. Alternatively, this step may not be performed and subsequent operations can be directly carried out.

[0099] Next, as Figure 9 and Figure 10 shown, deposition and etching processes can be used to form a mask structure 32 spanning across the fin structure 26. The specific structure and material of the mask structure 32 can be set according to actual requirements as long as it can play a masking and protecting role in the subsequent process.

[0100] Exemplarily, as Figure 9 and Figure 10 shown, the mask structure 32 can include a sacrificial gate 33. The material of the sacrificial gate 33 can include materials such as polysilicon that are easy to remove.

[0101] Exemplarily, the above mask structure can also include a gate oxide layer and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer can include materials such as silicon oxide.

[0102] Exemplarily, as Figure 9 and Figure 10 shown, the mask structure 32 can include a sacrificial gate 33 and gate sidewalls 22 located on both sides of the sacrificial gate 33 along the length direction. The material of the gate sidewalls 22 can refer to the foregoing.

[0103] Next, as Figure 11 shown, processes such as dry etching or wet etching can be used to remove the portions of the fin structure and the first isolation portion 19 that are exposed outside the mask structure 32.

[0104] It should be noted that, as Figure 12 shown, if the second isolation portion 20 has been formed by a selective oxidation process or the like before manufacturing the mask structure 32, this operation also needs to remove the portion of the second isolation portion 20 that is exposed outside the mask structure 32.

[0105] Next, as Figure 13As shown, if the second isolation portion 20 is not formed before manufacturing the mask structure 32, processes such as dry etching or wet etching need to be used to selectively remove the remaining first semiconductor isolation layer 30. Then, as Figure 14 shown, processes such as deposition and etching are used to form the second isolation portion 20 between the two first isolation portions 19. Of course, if the second isolation portion 20 has been formed before manufacturing the mask structure 32, this step does not need to be performed, and subsequent operations can be directly carried out.

[0106] Next, if the manufactured semiconductor device further includes a third isolation structure, processes such as dry etching or wet etching can be used to remove the second semiconductor isolation layer. Then, processes such as deposition and etching are used to form a third isolation structure that at least fills between adjacent two layers of the second isolation structure. If the manufactured semiconductor device does not include a third isolation structure, this step does not need to be performed, and subsequent operations can be directly carried out.

[0107] Next, if the first transistor and / or the second transistor in the manufactured semiconductor device is a gate-all-around transistor and the gate-all-around transistor further includes an inner sidewall, under the protection of the mask structure, after at least selectively etching the fin structure and the first isolation portion (or after forming the second isolation portion), before forming the source / drain regions, processes such as dry etching can be used to etch and remove the two side edge portions along the length direction of the remaining sacrificial layer. Then, processes such as deposition and etching are used to form inner sidewalls on the two sides along the length direction of the remaining sacrificial layer. The material of the inner sidewalls can refer to the previous text and will not be elaborated here.

[0108] Next, as Figure 15 shown, processes such as epitaxy can be used to form the source / drain regions 16 included in the first transistor on the two sides of the remaining first fin portion.

[0109] Next, as Figure 16 shown, processes such as deposition and etching can be used to form a first isolation structure 14 on the source / drain regions 16 included in the first transistor.

[0110] Next, as Figure 17 shown, processes such as epitaxy can be used to form the source / drain regions 16 included in the second transistor on the two sides of the remaining first fin portion.

[0111] Next, as Figure 18 shown, an interlayer dielectric layer 24 covering the formed structure can be formed. The top of the interlayer dielectric layer 24 is flush with the top of the mask structure 32. The material of the interlayer dielectric layer 24 can refer to the previous text and will not be elaborated here.

[0112] Next, as Figure 19As shown, a channel region 17 included in the first transistor is formed based on the remaining first fin portion; and a channel region 17 included in the second transistor is formed based on the remaining first fin portion.

[0113] Specifically, the formation process of the channel regions included in the first transistor and the second transistor can be determined according to the device types of the first transistor and the second transistor. For example: when the first transistor and / or the second transistor is a fin field-effect transistor, by using processes such as wet etching or dry etching to remove at least part of the mask structure and expose the remaining first fin portion or second fin portion, the channel region included in the fin field-effect transistor can be obtained. As Figure 19 shown, when the first transistor 12 and / or the second transistor 13 is a gate-all-around transistor, processes such as dry etching or wet etching can be first used to remove at least part of the mask structure and expose the remaining first fin portion or second fin portion; then, processes such as dry etching or wet etching are used to remove at least the remaining sacrificial layer (if the semiconductor isolation portion further includes a second semiconductor isolation layer and the semiconductor device does not include a third isolation structure, the remaining second semiconductor isolation layer also needs to be removed) so that the remaining channel layer forms the channel region 17.

[0114] It should be noted that whether to completely remove the mask structure can be determined according to the specific structure of the mask structure. For example: when the mask structure only includes a sacrificial gate, or only includes a sacrificial gate and a gate oxide layer, the mask structure can be completely removed. For example: when the mask structure includes a sacrificial gate and a gate sidewall, only the sacrificial gate can be removed, that is, part of the mask structure is removed.

[0115] Next, as Figures 20 to 22 shown, processes such as atomic layer deposition can be used to form a gate stack structure 18 at least on the outer periphery of the channel region 17 included in the first transistor 12 and on the outer periphery of the channel region 17 included in the second transistor 13. The specific structure and material of the gate stack structure 18 can refer to the foregoing, and will not be elaborated here.

[0116] It should be noted that the above-mentioned first transistor, second transistor, and first isolation structure can be formed in various ways. How to form the above-mentioned first transistor, second transistor, and first isolation structure is not the main feature of the present invention. Therefore, in this specification, only a brief introduction is given to enable those of ordinary skill in the art to easily implement the present invention. Those of ordinary skill in the art can fully conceive other ways to fabricate the above-mentioned first transistor, second transistor, and first isolation structure.

[0117] For the beneficial effects of the second aspect and its various implementation manners in the embodiments of the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, and will not be elaborated here.

[0118] In the above description, technical details such as the composition and etching of each layer are not elaborated in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the desired shape. Additionally, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. Moreover, although the embodiments are described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0119] The embodiments of the present invention have been described above. However, these embodiments are merely for the purpose of more clearly illustration, rather than for limiting the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor substrate; A first transistor and a second transistor sequentially disposed on the semiconductor substrate along the thickness direction of the semiconductor substrate; A first isolation structure disposed between the source-drain regions included in the first transistor and the source-drain regions included in the second transistor; A second isolation structure disposed between the gate stack structures included in the first transistor and the gate stack structures included in the second transistor; along the width direction of the channel regions included in the first transistor and the second transistor, the second isolation structure includes a first isolation portion and second isolation portions located on both sides of the first isolation portion.

2. The semiconductor device according to claim 1, wherein, There is an interface between the first isolation portion and the second isolation portions; And / or, the materials of the first isolation portion and the second isolation portions are different.

3. The semiconductor device according to claim 1, wherein The material of the second isolation portions includes an oxide of a semiconductor material; the semiconductor material is different from the materials of the channel regions included in the first transistor and the second transistor.

4. The semiconductor device according to claim 3, wherein The germanium content in the semiconductor material is higher than the germanium content in the materials of the channel regions included in the first transistor and the second transistor.

5. The semiconductor device according to claim 1, wherein In the sidewalls of the first isolation portion and / or the second isolation portions along the length direction of the gate stack structure, the surfaces of different regions are substantially aligned; And / or, the sidewalls of the second isolation portions along the width direction of the channel regions are arc-shaped and concave into the second isolation portions.

6. The semiconductor device according to claim 1, wherein Along the width direction of the channel regions, the width of the second isolation portions is greater than or equal to one-sixth times the width of the channel regions and less than or equal to one-half times the width of the channel regions.

7. The semiconductor device according to claim 1, wherein, In the second isolation structure located on the same layer, a single first isolation portion and / or second isolation portions are continuously distributed between two interfaces of the second isolation structure along the thickness direction.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The semiconductor device includes multiple layers of the second isolation structures spaced apart along the thickness direction of the semiconductor substrate.

9. The semiconductor device according to claim 8, wherein, The gate stack structures are filled between two adjacent layers of the second isolation structures.

10. The semiconductor device according to any one of claims 1 to 7, characterized in that, The first transistor and / or the second transistor is a gate-all-around transistor.

11. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a fin structure on a semiconductor substrate; Along the thickness direction of the semiconductor substrate, the fin structure includes a first fin portion, a semiconductor isolation portion, and a second fin portion sequentially disposed; the semiconductor isolation portion includes a first semiconductor isolation layer; the material of the first semiconductor isolation layer is different from the materials of the first fin portion and the second fin portion; Selectively removing the two side edge portions of the first semiconductor isolation layer along a first direction; and forming first isolation portions on both sides of the remaining first semiconductor isolation layer; Making the remaining first semiconductor isolation layer form second isolation portions; Forming a first transistor based on one of the first fin portion and the second fin portion; and forming a second transistor based on the other of the first fin portion and the second fin portion; the first direction is parallel to the width direction of the channel regions included in the first transistor and the second transistor; Forming a first isolation structure between the source-drain regions included in the first transistor and the source-drain regions included in the second transistor.

12. The manufacturing method of the semiconductor device according to claim 11, wherein, Using a selective oxidation process to make the remaining first semiconductor isolation layer form the second isolation portions.

13. The manufacturing method of the semiconductor device according to claim 11, characterized in that, After forming first isolation portions on both sides of the remaining first semiconductor isolation layer, before forming a first transistor based on one of the first fin portion and the second fin portion, a manufacturing method of the semiconductor device includes: Forming a mask structure spanning across the fin structure; Removing portions of the fin structure and the first isolation portions that are exposed outside the mask structure; Selectively removing the remaining first semiconductor isolation layer; Forming a second isolation portion between the two first isolation portions.

14. The manufacturing method of the semiconductor device according to claim 11, characterized in that, The semiconductor isolation portion includes multiple layers of first semiconductor isolation layers that are spaced apart along the thickness direction of the semiconductor substrate; the semiconductor isolation portion further includes a second semiconductor isolation layer that is at least located between adjacent two layers of the first semiconductor isolation layers; materials of the first semiconductor isolation layer are different from materials of the second semiconductor isolation layer; After forming source / drain regions included in the first transistor and the second transistor, before forming gate stack structures included in the first transistor and the second transistor, removing the second semiconductor isolation layer.

15. The manufacturing method of the semiconductor device according to any one of claims 11 to 14, characterized in that, Forming the first transistor, the second transistor, and the first isolation structure includes: Forming a mask structure spanning across the fin structure; Removing at least portions of the fin structure and the first isolation portions that are exposed outside the mask structure; Forming source / drain regions included in the first transistor on both sides of the remaining first fin portion; Forming the first isolation structure on the source / drain regions included in the first transistor; Forming source / drain regions included in the second transistor on both sides of the remaining first fin portion; Forming a channel region included in the first transistor based on the remaining first fin portion; and forming a channel region included in the second transistor based on the remaining second fin portion; Forming gate stack structures at least on the outer periphery of the channel region included in the first transistor and on the outer periphery of the channel region included in the second transistor.

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