Complementary field effect transistor, preparation method thereof and semiconductor device

Abstract

The invention provides a complementary field effect transistor, a preparation method thereof and a semiconductor device, which can be applied to the technical field of semiconductor devices. The complementary field effect transistor comprises a first field effect transistor and a second field effect transistor which are inversely stacked in the vertical direction; the first field effect transistor and the second field effect transistor share a substrate, the first field effect transistor comprises a first source / drain layer, a first channel and a second source / drain layer which are sequentially stacked in the direction away from the substrate, and a first grid electrode and a second grid electrode which are arranged at the two ends of the first channel in the first direction respectively. The cross sectional area of the first channel in the first direction is smaller than the cross sectional areas of the first source / drain layer and the first source / drain layer in the first direction, the first grid electrode and the second grid electrode are not connected, and the structure of the second field effect transistor and the structure of the first field effect transistor are in mirror symmetry relative to the substrate.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and more particularly, to a complementary field-effect transistor, a method for manufacturing the same, and a semiconductor device. Background Art

[0002] As a technical candidate for improving integration density, solving the wiring space of integrated circuits, and reducing the lateral arrangement pitch of p-n devices, the complementary field-effect transistor (CFET) can promote the continuous improvement of chip performance through size reduction, three-dimensional integration, and architecture innovation, and achieve an exponential increase in computing power, thereby improving the density of transistors and circuit performance.

[0003] In the process of implementing the concept of the present disclosure, the inventors found that in the related art, the CFET device technology is restricted by the large aspect ratio process and complex manufacturing process, and it is difficult to achieve multi-threshold regulation, facing certain challenges in practical applications. Summary of the Invention

[0004] In view of this, the present disclosure provides a complementary field-effect transistor, a method for manufacturing the same, and a semiconductor device.

[0005] One aspect of the present disclosure provides a complementary field-effect transistor, comprising:

[0006] A first field-effect transistor and a second field-effect transistor that are flip-chip stacked in the vertical direction; wherein, the first field-effect transistor and the second field-effect transistor share a common substrate, the first field-effect transistor includes a first source / drain layer, a first channel, and a second source / drain layer that are sequentially stacked along a direction away from the substrate, and a first gate and a second gate are respectively disposed at two ends of the first channel in a first direction, the cross-sectional area of the first channel in the first direction is smaller than the cross-sectional areas of the first source / drain layer and the second source / drain layer in the first direction, the first gate and the second gate are not connected to each other, and the structure of the second field-effect transistor is mirror-symmetrical with respect to the substrate to the structure of the first field-effect transistor.

[0007] According to an embodiment of the present disclosure, the thicknesses of the first gate and the second gate in the vertical direction are both 1 nm to 100 nm.

[0008] According to an embodiment of the present disclosure, a dielectric material is included between the first channel and the first gate and the second gate, and dielectric materials are included on a first surface of the first source / drain layer and on a surface of the second source / drain layer opposite to the first surface of the first source / drain layer.

[0009] According to an embodiment of the present disclosure, the second field-effect transistor includes a second channel, and one of the first channel and the second channel is doped with n-type and the other is doped with p-type.

[0010] Another aspect of the present disclosure provides a method for manufacturing a complementary field-effect transistor, including:

[0011] Forming a film layer on a first surface of a substrate, the film layer including a first source / drain layer, a channel layer, and a second source / drain layer vertically stacked in a direction away from the substrate; performing selective etching on the film layer, after the selective etching is completed, the etched channel layer is recessed relative to the first source / drain layer and the second source / drain layer and serves as a first channel between the first source / drain layer and the second source / drain layer; forming a gate material outside the first source / drain layer, the first channel, and the second source / drain layer; etching the gate material to obtain a first gate and a second gate located at two ends of the first channel in a first direction respectively, completing the preparation of the first field-effect transistor, wherein the first gate and the second gate are not connected to each other; filling an isolation layer along a direction away from the first surface of the substrate, so that the isolation layer covers the outer periphery of the first field-effect transistor, and bonding a layer of wafer on the top of the isolation layer; flipping the first field-effect transistor, the isolation layer, and the wafer along the first direction; thinning the substrate and forming a second field-effect transistor on a second surface of the thinned substrate, wherein the structure of the second field-effect transistor is mirror-symmetrical to the structure of the first field-effect transistor with respect to the substrate.

[0012] According to an embodiment of the present disclosure, the thickness of the first gate and the second gate is 1 nm to 100 nm.

[0013] According to an embodiment of the present disclosure, forming a gate material outside the first source / drain layer, the first channel, and the second source / drain layer includes: forming a gate material outside the first source / drain layer, the first channel, and the second source / drain layer by atomic layer deposition or selective epitaxy.

[0014] According to an embodiment of the present disclosure, a dielectric material is included between the first channel and the first gate and the second gate, and a dielectric material is included on a first surface of the first source / drain layer and a surface of the second source / drain layer opposite to the first surface of the first source / drain layer.

[0015] According to an embodiment of the present disclosure, etching the gate material to obtain a first gate and a second gate located at two ends of the first channel in a first direction respectively includes: etching the gate material, and only retaining the gate material in an annular structure formed by the first source / drain part, the second source / drain part, and the first channel; cutting off the connection of the gate material at two ends in a second direction intersecting the first direction to obtain a first gate and a second gate located at two ends of the first channel in the first direction respectively.

[0016] Another aspect of the present disclosure provides a semiconductor device, including:

[0017] A plurality of the above complementary field effect transistors, wherein the plurality of complementary field effect transistors share a common substrate, and a plurality of first field effect transistors and a plurality of second field effect transistors are arranged side by side at a predetermined pitch on a first surface and a second surface of the substrate, respectively.

[0018] According to an embodiment of the present disclosure, by designing a flip-chip complementary field effect transistor, a channel is provided between a first source / drain layer and a second source / drain layer of each field effect transistor, and a first gate and a second gate are formed at two ends of the channel in a first direction. Thus, a flip-chip vertical structure double-gate complementary field effect transistor is obtained without increasing the overall size of the chip. By applying different voltages to the two gates separated by the channel, the electric field distribution and carrier concentration in the channel can be adjusted, thereby realizing multi-threshold regulation of the complementary field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0020] Figure 1 Schematically shows a cross-sectional view of a complementary field effect transistor along a first direction according to an embodiment of the present disclosure.

[0021] Figure 2 Schematically shows a three-dimensional structure diagram of a first field effect transistor according to an embodiment of the present disclosure.

[0022] Figure 3 Schematically shows a flowchart of a method for manufacturing a complementary field effect transistor according to an embodiment of the present disclosure.

[0023] Figures 4A to 4I Schematically shows Figure 3 A cross-sectional view along a first direction of a structure after some operations in the shown method flow are executed.

[0024] Figures 5A to 5I Schematically shows Figure 3 A cross-sectional view along a second direction of a structure after some operations in the shown method flow are executed. Figure 6 Schematically shows a cross-sectional view of a semiconductor device along a first direction according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, for the sake of explanation, numerous specific details are set forth in order to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is obvious that one or more embodiments can be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0026] The terms used herein are merely for describing specific embodiments and are not intended to limit the present disclosure. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0027] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those of ordinary skill in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0028] In the case of using expressions such as "at least one of A, B, and C, etc.", generally, it should be interpreted according to the meaning commonly understood by those of ordinary skill in the art (for example, "a system having at least one of A, B, and C" should include, but is not limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0029] In the process of implementing the inventive concept of the present disclosure, through research, it is found that the current three-dimensional integration technology using flip-chip stacking in the related art overcomes the implementation difficulties of the large aspect ratio process faced by the current CFET technology, and improves the chip integration density and circuit design flexibility. However, in order to achieve multi-threshold regulation of CFETs, the traditional method of changing the film thickness of the gate metal work function layer is still used, and as the chip size continues to shrink, it is difficult to precisely control the film thickness of the gate metal work function layer. For example, at deep sub-micron or smaller scales, a small change in film thickness may cause a large fluctuation in the threshold voltage, and it is also difficult to achieve film thickness uniformity for transistor structures with a large aspect ratio.

[0030] In view of this, embodiments of the present disclosure provide a complementary field effect transistor, including:

[0031] A first field effect transistor and a second field effect transistor are flip-chip stacked in a vertical direction; wherein the first field effect transistor and the second field effect transistor share a substrate, the first field effect transistor comprises a first source / drain layer, a first channel, and a second source / drain layer stacked in sequence in a direction away from the substrate, and a first gate and a second gate are respectively arranged at both ends of the first channel in the first direction, the cross-sectional area of the first channel in the first direction is smaller than the cross-sectional area of the first source / drain layer and the first source / drain layer in the first direction, the first gate and the second gate are not connected to each other, and the structure of the second field effect transistor is mirror-symmetrical to the structure of the first field effect transistor relative to the substrate.

[0032] Figure 1 A cross-sectional view along a first direction of a complementary field effect transistor according to an embodiment of the present disclosure is schematically shown.

[0033] like Figure 1 As shown, the first direction is the horizontal direction, the first field effect transistor 110 and the second field effect transistor 120 are flipped and stacked in the vertical direction and share the same substrate, and the structure of the first field effect transistor 110 and the structure of the second field effect transistor 120 are mirror-symmetrical with respect to the substrate 111. The first field effect transistor 110 includes a first source / drain layer 112 and a second source / drain layer 114 stacked in sequence in a direction away from the substrate 111, and a first channel 113 (3), a first gate 113 (1) and a second gate 113 (2) located between the first source / drain layer 112 and the second source / drain layer 114, the first gate 113 (1) and the second gate 113 (2) are respectively located at two ends of the first channel 113 (3) in the first direction, the cross-sectional area of the first channel 113 (3) in the first direction is smaller than the cross-sectional area of the first source / drain layer 112 and the first source / drain layer 114 in the first direction, and the first gate 113 (1) and the second gate 113 (2) are not connected to each other. The interlayer between the first source / drain layer 112 , the first channel 113 ( 3 ) and the first source / drain layer 114 further includes a layer of dielectric material 115 .

[0034] According to an embodiment of the present disclosure, the material of the substrate may be silicon, and the material of the first source / drain layer and the second source / drain layer may also be silicon.

[0035] According to an embodiment of the present disclosure, a first gate and a second gate are respectively formed at two ends of a first channel. Compared with a single-gate structure, it is beneficial to regulate the electric field in the channel from different directions, thereby precisely controlling the number and motion state of carriers in the channel. In addition, by applying different voltage combinations to the two gates, the electric field distribution in the channel is changed, thereby flexibly adjusting the threshold voltage of the first field-effect transistor to achieve multiple threshold states. Therefore, for different application scenarios, the performance-power consumption ratio of the chip can be optimized through multi-threshold voltage regulation, so as to improve the performance of the first field-effect transistor without increasing the chip size.

[0036] Figure 2 Schematically shows a three-dimensional structural schematic diagram of a first field-effect transistor according to an embodiment of the present disclosure.

[0037] As Figure 2 shown, the first field-effect transistor 110 corresponds to Figure 1 The first field-effect transistor includes a first source / drain layer 112, a second source / drain layer 114, and a first gate 113(1), a second gate 113(2), and a first channel that are sequentially stacked in a direction away from the substrate 111. The first gate 113(1) and the second gate 113(2) are respectively located at two ends of the first channel in a first direction. The cross-sectional area of the first channel in the first direction is smaller than the cross-sectional areas of the first source / drain layer 112 and the first source / drain layer 114 in the first direction. The first gate 113(1) and the second gate 113(2) are not connected to each other. A layer of dielectric material 115 is further included in the interlayer between the first source / drain layer 112, the first channel, and the first source / drain layer 114. Since the cross-sectional area of the first channel in the first direction is smaller than the cross-sectional areas of the first source / drain layer 112 and the first source / drain layer 114 in the first direction, the first channel is surrounded by the dielectric material 115, the first gate 113(1), and the second gate 113(2).

[0038] Since the second field-effect transistor has the same structure as the first field-effect transistor, it has the same improvement relative to the overall chip and will not be elaborated here.

[0039] According to an embodiment of the present disclosure, by designing a flip-chip complementary field-effect transistor, a channel is provided between the source / drain layers of each field-effect transistor, and two gates are respectively provided in the interlayers formed between the two sides of the channel and the source and drain electrodes. Thus, a flip-chip vertical structure double-gate complementary field-effect transistor is obtained without increasing the overall size of the chip. By applying different voltages to the two gates separated by the channel, the electric field distribution and carrier concentration in the channel can be adjusted, thereby realizing multi-threshold regulation of the complementary field-effect transistor.

[0040] According to an embodiment of the present disclosure, a dielectric material is included between the first channel and the first gate and the second gate, and the first surface of the first source / drain layer and the surface of the second source / drain layer opposite to the first surface of the first source / drain layer include a dielectric material.

[0041] According to an embodiment of the present disclosure, the dielectric material should be a material with a high dielectric constant.

[0042] According to an embodiment of the present disclosure, the thickness of the first gate stack layer is 1 nm to 100 nm.

[0043] According to an embodiment of the present disclosure, the thickness of the first source / drain layer and the first source / drain layer can be 100 nm to 500 nm, and the thickness of the film layer where the dielectric material is located can be 1 nm to 10 nm.

[0044] According to an embodiment of the present disclosure, the second field-effect transistor includes a second channel, and one of the first channel and the second channel is n-type doped and the other is p-type doped.

[0045] According to an embodiment of the present disclosure, the thickness of the first channel and the second channel can be 100 nm to 500 nm.

[0046] Figure 3 A flowchart schematically showing a method for manufacturing a complementary field-effect transistor according to an embodiment of the present disclosure is shown.

[0047] As Figure 3 shown, this embodiment 300 includes operations S310 to S330.

[0048] In operation S310, a film layer is formed on the first surface of the substrate. Among them, the film layer includes a first source / drain layer, a channel layer, and a second source / drain layer vertically stacked in a direction away from the substrate.

[0049] For example, the source / drain material layer includes Si, and the channel material layer includes GeSi.

[0050] In operation S320, the film layer is selectively etched. After the selective etching is completed, the etched channel layer is recessed relative to the first source / drain layer and the second source / drain layer and serves as the first channel between the first source / drain layer and the second source / drain layer.

[0051] According to an embodiment of the present disclosure, using a photoresist as a mask, first etch the channel material layer and the source / drain material layer to the same width to obtain the first source / drain layer and the second source / drain layer, and then control the etching depth to completely remove the channel material layer in the non-channel region to form the first channel.

[0052] In operation S330, a gate material is formed outside the first source / drain layer, the first channel, and the second source / drain layer.

[0053] According to an embodiment of the present disclosure, after forming the first channel, the first source / drain layer, and the second source / drain layer, a layer of dielectric material needs to be formed on their respective outer surfaces, and then gate material is formed on the surface of the dielectric material.

[0054] In operation S340, the gate material is etched to obtain a first gate and a second gate located at both ends of the first channel in the first direction, completing the fabrication of the first field-effect transistor. Among them, the first gate and the second gate are not connected to each other.

[0055] In operation S350, an isolation layer is filled along the first surface away from the substrate, so that the isolation layer covers the outer periphery of the first field-effect transistor, and a layer of wafer is bonded on the top of the isolation layer.

[0056] According to an embodiment of the present disclosure, the material of the isolation layer is usually selected as silicon dioxide (SiO2) with good insulation performance, which is beneficial to isolate external interference and can prevent electrical crosstalk between different field-effect transistors for semiconductor devices.

[0057] According to an embodiment of the present disclosure, the material of the wafer is preferably a silicon wafer that matches the substrate material, and the bonding of the wafer can be direct bonding or adhesive bonding. For example, in direct bonding, the surfaces of the wafer and the isolation layer can be cleaned and pretreated more strictly to remove surface contaminants and oxide layers. Then, the wafer is placed on the top of the isolation layer, and under the combined action of the applied pressure and temperature, chemical bonds are formed between the atoms on the surface of the wafer and the isolation layer to achieve a firm bond.

[0058] In operation S360, the first field-effect transistor, the isolation layer, and the wafer are flipped along the first direction.

[0059] In operation S370, the substrate is thinned, and a second field-effect transistor is formed on the second surface of the thinned substrate. Among them, the structure of the second field-effect transistor is mirror-symmetrical to the structure of the first field-effect transistor with respect to the substrate.

[0060] According to an embodiment of the present disclosure, the thinning of the substrate can adopt mechanical grinding process and chemical mechanical polishing process. Chemical mechanical polish (CMP) grinds the upper surface of the substrate under a certain pressure and rotation speed, removes part of the unnecessary substrate material, makes the substrate thickness reach a predetermined thickness, and ensures the flatness and uniformity of the substrate surface.

[0061] According to an embodiment of the present disclosure, the fabrication of the second field-effect transistor is similar to that of the first field-effect transistor, which will not be elaborated here.

[0062] In addition to the above bonding stack preparation process, a monolithic integration process can also be used to form a p-type field-effect transistor and an n-type field-effect transistor on each of the two surfaces of the substrate, and specifically, a suitable preparation process can be selected according to different application scenarios.

[0063] It should also be noted that the preparation method part of the complementary field-effect transistor in the embodiments of the present disclosure corresponds to the complementary field-effect transistor part in the embodiments of the present disclosure. For the description of the preparation method part of the complementary field-effect transistor, specifically refer to the complementary field-effect transistor part, and details will not be elaborated here.

[0064] According to the embodiments of the present disclosure, in the flip-chip complementary field-effect transistor obtained by preparation, a gate stack layer is provided between the first source / drain layer and the second source / drain layer of each field-effect transistor, and a first gate and a second gate are formed at both ends of the channel in the first direction. Thus, a flip-chip vertical structure double-gate complementary field-effect transistor is obtained without increasing the overall size of the chip. By applying different voltages to the two gates separated by the channel, the electric field distribution and carrier concentration in the channel can be adjusted, and thus multi-threshold regulation of the complementary field-effect transistor can be achieved.

[0065] According to the embodiments of the present disclosure, etching the gate material to obtain the first gate and the second gate located at both ends of the first channel in the first direction includes: etching the gate material and only retaining the gate material in the annular structure composed of the first source / drain part, the second source / drain part, and the first channel; cutting off the connection of the gate material at both ends in the second direction intersecting the first direction to obtain the first gate and the second gate located at both ends of the first channel in the first direction respectively.

[0066] According to the embodiments of the present disclosure, the second direction is perpendicular to the first direction and is also the horizontal direction.

[0067] According to the embodiments of the present disclosure, the thickness of the first gate and the second gate is 1 nm to 100 nm.

[0068] According to the embodiments of the present disclosure, a dielectric material is included between the first channel and the first gate and the second gate, and the first surface of the first source / drain layer and the surface of the second source / drain layer opposite to the first surface of the first source / drain layer include a dielectric material.

[0069] According to the embodiments of the present disclosure, the dielectric material is used to isolate the first source / drain layer, the second source / drain layer, the first gate, or the second gate respectively to prevent leakage.

[0070] According to the embodiments of the present disclosure, forming a gate material around the first source / drain layer, the first channel, and the second source / drain layer includes: forming a gate material around the first source / drain layer, the first channel, and the second source / drain layer by atomic layer deposition or selective epitaxy.

[0071] To better understand the preparation process of the complementary field-effect transistor according to the embodiments of the present disclosure, the following will be in the first direction

[0072] Figures 4A to 4I schematically shows Figure 3 a cross-sectional view along the first direction of the structure after some operations in the shown method flow are performed.

[0073] Figures 5A to 5I schematically shows Figure 3 a cross-sectional view along the second direction of the structure after some operations in the shown method flow are performed.

[0074] As Figures 4A to 4I and Figures 5A to 5IAs shown, a film layer 410 is formed on the first surface of the substrate 111. The film layer 410 includes a first source / drain layer 411, a channel layer 412, and a second source / drain layer 413 that are vertically stacked in a direction away from the substrate. The film layer 410 is selectively etched, and the etched channel layer 412 is used as the first channel 113(3) of the first field-effect transistor 110, the etched first source / drain layer 411 is used as the first source / drain layer 112 of the first field-effect transistor 110, and the etched second source / drain layer 413 is used as the second source / drain layer 114 of the first field-effect transistor 110. The cross-sectional area of the first channel 113(3) in the first direction is smaller than the cross-sectional areas of the first source / drain layer 112 and the second source / drain layer 114 in the first direction. Therefore, whether viewed from a cross-section in the first direction or a cross-section in the second direction, the first channel 113(3) is located in the middle of the gate stack layer. A dielectric material 115 and a gate material 420 are sequentially formed outside the first source / drain layer 112, the first channel 113(3), and the second source / drain layer 114 by atomic layer deposition or epitaxial growth. The gate material 420 and the dielectric material 115 are etched to obtain a first gate 113(1) and a second gate 113(2) located at both ends of the first channel 113(3) in the first direction, completing the fabrication of the first field-effect transistor 110. Since the gate material 420 in the gate stack layer needs to be cut to ensure that the first gate 113(1) and the second gate 113(2) are not connected to each other, it can be seen from the cross-section in the second direction that the first gate 113(1) and the second gate 113(2) are located at both ends of the first channel 113(3) in the first direction. An isolation layer 430 is filled along the first surface away from the substrate 111 so that the isolation layer 430 covers the outer periphery of the first field-effect transistor 110. At this time, the height of the isolation layer 430 is higher than the height of the first field-effect transistor 110, and then a layer of wafer 440 is bonded on the top of the isolation layer 430. The first field-effect transistor 110, the isolation layer 430, and the wafer 440 are flipped along the first direction. Thinning is performed on the second surface of the substrate 111, and a second field-effect transistor 120 is formed on the second surface of the thinned substrate 111.

[0075] Another embodiment of the present disclosure provides a semiconductor device, including:

[0076] The above complementary field-effect transistors, wherein a plurality of complementary field-effect transistors share a substrate, and a plurality of first field-effect transistors and a plurality of second field-effect transistors are arranged side by side at a predetermined pitch on the first surface and the second surface of the substrate, respectively; an isolation layer covering the outer surfaces of the plurality of first field-effect transistors, wherein the thickness relative to the upper surface of the substrate exceeds the height of the first field-effect transistor; and a carrier wafer covering the surface of the isolation layer away from the substrate.

[0077] Figure 6A front view of the structure of a semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0078] As Figure 6 shown, the semiconductor device 600 of this embodiment includes a plurality of complementary field effect transistors 610, and a plurality of first field effect transistors 611 and a plurality of second field effect transistors 612 among the plurality of complementary field effect transistors 610 are arranged side by side at a predetermined pitch on the same substrate 613, an isolation layer 620 covers the outer surfaces of the plurality of first field effect transistors 611, and a carrier wafer 630 covers the surface of the isolation layer 620 away from the substrate.

[0079] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the above-mentioned module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and the combination of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions. Those skilled in the art can understand that the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0080] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in the respective embodiments cannot be used advantageously in combination. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A complementary field effect transistor, characterized in that, include: A first field effect transistor and a second field effect transistor flip-chip stacked in a vertical direction; Among them, the first field effect transistor and the second field effect transistor share a substrate, the first field effect transistor includes a first source / drain layer, a first channel, and a second source / drain layer stacked in sequence in a direction away from the substrate, and a first gate and a second gate are respectively arranged at both ends of the first channel in the first direction, the cross-sectional area of the first channel in the first direction is smaller than the cross-sectional area of the first source / drain layer and the first source / drain layer in the first direction, the first gate and the second gate are not connected to each other, and the structure of the second field effect transistor is mirror-symmetrical to the structure of the first field effect transistor relative to the substrate.

2. The transistor according to claim 1, characterized in that, The thickness of the first gate and the second gate in the vertical direction are both 1 nm to 100 nm.

3. The transistor according to claim 1, wherein A dielectric material is included between the first channel and the first gate and the second gate, and a first surface of the first source / drain layer and a surface of the second source / drain layer opposite to the first surface of the first source / drain layer include a dielectric material.

4. The transistor according to claim 1, wherein The second field effect transistor includes a second channel, and one of the first channel and the second channel is doped with n-type, and the other is doped with p-type.

5. A method for manufacturing a complementary field effect transistor, characterized in that, include: Forming a film layer on a first surface of the substrate, wherein the film layer includes a first source / drain layer, a channel layer, and a second source / drain layer vertically stacked in a direction away from the substrate; Selectively etching the film layer, wherein after the selective etching is completed, the etched channel layer is recessed relative to the first source / drain layer and the second source / drain layer, and serves as a first channel between the first source / drain layer and the second source / drain layer; forming a gate material outside the first source / drain layer, the first channel and the second source / drain layer; Etching the gate material to obtain a first gate and a second gate located at two ends of the first channel in the first direction, respectively, to complete the preparation of the first field effect transistor, wherein the first gate and the second gate are not connected to each other; Filling an isolation layer along a first surface away from the substrate so that the isolation layer covers the periphery of the first field effect transistor, and bonding a wafer layer on top of the isolation layer; flipping the first field effect transistor, the isolation layer and the wafer along the first direction; The substrate is thinned, and a second field effect transistor is formed on a second surface of the thinned substrate, wherein the structure of the second field effect transistor is mirror-symmetrical to the structure of the first field effect transistor relative to the substrate.

6. The method according to claim 5, wherein The thickness of the first gate and the second gate is 1 nm to 100 nm.

7. The method according to claim 5, wherein Forming a gate material outside the first source / drain layer, the first channel and the second source / drain layer, including: The gate material is formed outside the first source / drain layer, the first channel and the second source / drain layer by atomic layer deposition or selective epitaxy.

8. The method according to claim 5, wherein A dielectric material is included between the first channel and the first gate and the second gate, and dielectric materials are included on a first surface of the first source / drain layer and on a surface of the second source / drain layer opposite to the first surface of the first source / drain layer.

9. The method according to claim 5, characterized in that, Etching the gate material to respectively obtain a first gate and a second gate located at two ends of the first channel in a first direction includes: Etching the gate material to only retain the gate material within an annular structure formed by the first source / drain portion, the second source / drain portion, and the first channel; Cutting off connections of the gate material at two ends in a second direction intersecting with the first direction to respectively obtain the first gate and the second gate located at two ends of the first channel in the first direction.

10. A semiconductor device, characterized in that, Includes: Multiple complementary field-effect transistors according to any one of claims 1 to 4, wherein the multiple complementary field-effect transistors share a substrate, and multiple first field-effect transistors and multiple second field-effect transistors are respectively arranged side by side at a predetermined interval on a first surface and a second surface of the substrate.

Images