Three-dimensional semiconductor device

Abstract

A three-dimensional semiconductor device includes: a backside metal layer; a lower channel pattern and an upper channel pattern sequentially disposed on the backside metal layer; a gate electrode intersecting the lower channel pattern and the upper channel pattern in the first direction, and including a first gate electrode and a second gate electrode adjacent to each other in the first direction; a separation insulating pattern between the first gate electrode and the second gate electrode; and a conductive plate extending in the separation insulation pattern in each of a second direction intersecting the first direction and a third direction perpendicular to the first direction, in which the conductive plate includes a first conductive plate and a second conductive plate adjacent to each other in the first direction in the separation insulation pattern.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0006937, filed with the Korean Intellectual Property Office on January 16, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a three-dimensional semiconductor device and a method of manufacturing a three-dimensional semiconductor device, and more particularly, to a three-dimensional semiconductor device including a field-effect transistor and a method of manufacturing a three-dimensional semiconductor device. Background Art

[0003] A semiconductor device may include an integrated circuit including a metal-oxide-semiconductor field-effect transistor (MOSFET). As the size and design rules of semiconductor devices have decreased, the size of MOSFETs has also been reduced. The operating characteristics of semiconductor devices may be degraded by the reduction of MOSFETs. Accordingly, various studies are being conducted on semiconductor devices capable of overcoming the limitations caused by high integration and improving performance. Summary of the Invention

[0004] An object of the inventive concept is to provide a three-dimensional semiconductor device and a method of manufacturing a three-dimensional semiconductor device having improved integration.

[0005] An object of the inventive concept is to provide a three-dimensional semiconductor device and a method of manufacturing a three-dimensional semiconductor device having improved electrical characteristics and productivity.

[0006] Problems to be solved by the inventive concept are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0007] A three-dimensional semiconductor device according to some embodiments of the inventive concept includes: a backside metal layer; a first lower channel pattern and a first upper channel pattern sequentially disposed on the backside metal layer; a first gate electrode intersecting the first lower channel pattern and the first upper channel pattern; a second gate electrode adjacent to the first gate electrode in a first direction; a separation insulating pattern between the first gate electrode and the second gate electrode; a first conductive plate extending in the separation insulating pattern in each of a second direction and a third direction; and a second conductive plate extending in the separation insulating pattern in each of the second direction and the third direction. The second conductive plate is adjacent to the first conductive plate in the first direction. The first conductive plate and the second conductive plate are electrically separated from each other.

[0008] A three-dimensional semiconductor device according to some embodiments of the inventive concept includes: a backside metal layer; a first lower channel pattern and a first upper channel pattern sequentially disposed on the backside metal layer; a second lower channel pattern and a second upper channel pattern sequentially disposed on the backside metal layer; a first gate electrode intersecting the first lower channel pattern and the first upper channel pattern; and a second gate electrode intersecting the second lower channel pattern and the second upper channel pattern. The second gate electrode is adjacent to the first gate electrode in a first direction. The three-dimensional semiconductor device further includes: a separation insulating pattern between the first gate electrode and the second gate electrode; and a first conductive plate extending in the separation insulating pattern in each of a second direction and a third direction. The first conductive plate is adjacent to the first gate electrode. The three-dimensional semiconductor device further includes: a second conductive plate extending in the separation insulating pattern in each of the second direction and the third direction. The second conductive plate is adjacent to the second gate electrode. The first conductive plate and the second conductive plate are separated from each other. The first direction, the second direction, and the third direction are perpendicular to each other.

[0009] A three-dimensional semiconductor device according to some embodiments of the inventive concept includes: a backside metal layer; a first lower channel pattern and a first upper channel pattern sequentially disposed on the backside metal layer; a second lower channel pattern and a second upper channel pattern sequentially disposed on the backside metal layer; a first gate electrode intersecting the first lower channel pattern and the first upper channel pattern; a second gate electrode intersecting the second lower channel pattern and the second upper channel pattern, the second gate electrode being adjacent to the first gate electrode in a first direction; a separation insulating pattern between the first gate electrode and the second gate electrode; a first conductive plate extending in the separation insulating pattern in each of a second direction and a third direction, the first conductive plate being adjacent to the first gate electrode; and a second conductive plate extending in the separation insulating pattern in each of the second direction and the third direction. The second conductive plate is adjacent to the first gate electrode. The first conductive plate and the second conductive plate are separated from each other. The first direction, the second direction, and the third direction are perpendicular to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings represent non-limiting example embodiments as described herein.

[0011] Figure 1 is a plan view of a logic cell of a semiconductor device according to a comparative example of the inventive concept.

[0012] Figure 2 is a plan view of a logic cell of a semiconductor device according to an embodiment of the inventive concept.

[0013] Figure 3 is a plan view for explaining a three-dimensional semiconductor device according to some embodiments of the inventive concept.

[0014] Figure 4 is an enlarged view corresponding to a part "P1" in Figure 3 .

[0015] Figures 5A to 5E are respectively cross-sectional views taken along lines A-A', B-B', C-C', E-E' and F-F' of Figure 3 .

[0016] Figure 6 is an enlarged view corresponding to a part "P1" in Figure 3 .

[0017] Figures 7A to 7D are respectively cross-sectional views taken along lines B-B', D-D', E-E' and F-F' of Figure 3 .

[0018] Figure 8 is an enlarged view corresponding to a part "P1" in Figure 3 .

[0019] Figures 9A to 9D are respectively cross-sectional views taken along lines B-B', D-D', E-E' and F-F' of Figure 3 .

[0020] Figure 10 is a cross-sectional view taken along line B-B' of Figure 3 .

[0021] Figure 11A , Figure 11B , Figures 12A to 12C , Figure 13A , Figure 13B , Figures 14A to 14C , Figure 15A and Figure 15B are cross-sectional views for explaining a method of manufacturing a three-dimensional semiconductor device according to an embodiment of the inventive concept.

[0022] Figure 16 and Figure 17 are cross-sectional views for explaining a method of manufacturing a three-dimensional semiconductor device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0023] Hereinafter, for a detailed explanation of the inventive concept, embodiments according to the inventive concept will be described with reference to the accompanying drawings. It should be noted that, as can be seen in the various drawings from the context of the description of the various drawings, items described herein in the singular may be provided in the plural, and such a description should be considered applicable to each of the plurality unless the context indicates otherwise.

[0024] Throughout the specification, when a component is described as "comprising" a particular element or group of elements, it will be understood that, unless the context otherwise indicates, the component is formed only by that element or group of elements, or the element or group of elements may be combined with additional elements to form the component. On the other hand, the term "consisting of" indicates that the component is formed only by the listed element(s).

[0025] Figure 1 is a plan view of a logic unit of a semiconductor device that is a comparative example according to the inventive concept.

[0026] Referring to Figure 1 , a single height cell (SHC') can be set. As is conventional, a single height cell refers to a cell within a single row that is suitable for standard cell layout in a plan view (thus, the "height" in a single height cell refers to the row height and does not refer to the dimension that is generally considered to be vertical (i.e., perpendicular to the surface of the substrate)). Specifically, a first power line POR1 and a second power line POR2 can be set on the substrate 100. A drain voltage (VDD) (e.g., a power supply voltage) can be applied to one of the first power line POR1 and the second power line POR2. A source voltage (VSS) (e.g., a ground voltage) can be applied to the other of the first power line POR1 and the second power line POR2. As an example, the first power line POR1 and the second power line POR2 can be spaced apart from each other in a first direction D1 parallel to the lower surface of the substrate 100 and can be parallel to the lower surface of the substrate 100. Each of the first power line POR1 and the second power line POR2 can extend in a second direction D2 that intersects the first direction D1.

[0027] The single height cell SHC' can be defined between the first power line POR1 and the second power line POR2. The single height cell SHC' can include a first active region AR1 and a second active region AR2. One of the first active region AR1 and the second active region AR2 can be a p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOSFET) region, and the other of the first active region AR1 and the second active region AR2 can be an n-type MOSFET (NMOSFET) region. For example, the single height cell SHC' can have a CMOS (complementary metal oxide semiconductor) structure disposed between the first power line POR1 and the second power line POR2.

[0028] The semiconductor device according to the comparative example can be a two-dimensional device in which transistors of a front-end-of-line (FEOL) layer are arranged two-dimensionally. For example, the NMOSFET on the first active region AR1 can be formed to be spaced apart from the PMOSFET on the second active region AR2 in the first direction D1.

[0029] Each of the first active region AR1 and the second active region AR2 may have a first width AW1 in a first direction D1. The length of the single-height cell SHC' according to the comparative example in the first direction D1 may be defined as a first height CHT1. The first height CHT1 may be substantially equal to the distance (e.g., pitch) between the first power line POR1 and the second power line POR2.

[0030] The single-height cell SHC' may constitute a logic cell. In this description, a logic cell may represent a logic element that performs a specific function (e.g., AND gate, OR gate, XOR gate, XNOR gate, inverter, etc.). For example, a logic cell may include transistors for constituting the logic element and wiring lines connecting the transistors to each other.

[0031] Since two-dimensional devices are included in the single-height cell SHC' according to the comparative example, the first active region AR1 and the second active region AR2 may be arranged to be spaced apart from each other in the first direction D1 without overlapping each other. Therefore, it may be necessary to define the single-height cell SHC' to include all of the first active region AR1 and the second active region AR2 that are spaced apart from each other in the first direction D1. For example, the first height CHT1 of the single-height cell SHC' may have a size including at least two first widths AW1. As a result, the first height CHT1 of the single-height cell SHC' according to the comparative example may need to become relatively large. Therefore, the single-height cell SHC' according to the comparative example may have a relatively large area.

[0032] Figure 2 is a plan view of a logic cell of a semiconductor device according to an embodiment of the inventive concept.

[0033] Referring to Figure 2 , a single-height cell SHC including three-dimensional devices (e.g., stacked transistors) may be provided. Specifically, the first power line POR1 and the second power line POR2 may be provided on the substrate 100. The single-height cell SHC may be defined between the first power line POR1 and the second power line POR2.

[0034] The single-height cell SHC may include a lower active region LAR and an upper active region UAR. One of the lower active region LAR and the upper active region UAR may be a PMOSFET region, and the other of the lower active region LAR and the upper active region UAR may be an NMOSFET region.

[0035] The semiconductor device according to the present embodiment may be a three-dimensional device, and the transistors of the FEOL layer may be vertically stacked. For example, the lower active region LAR may be provided as part of the bottom layer of the FEOL layer on the substrate 100, and the upper active region UAR may be stacked on the lower active region LAR as part of the top layer of the FEOL layer. For example, the PMOSFETs in the lower active region LAR may be provided on the substrate 100, and the NMOSFETs in the upper active region UAR may be stacked on the PMOSFETs. The lower active region LAR and the upper active region UAR may be spaced apart from each other in the vertical direction (e.g., in the third direction D3 perpendicular to the lower surface of the substrate 100).

[0036] Each of the lower active region LAR and the upper active region UAR may have a second width AW2 in the first direction D1. The length of the single-height cell SHC according to the present embodiment in the first direction D1 may be defined as the second height CHT2.

[0037] Since the single-height cell SHC according to the present embodiment includes three-dimensional elements (e.g., stacked transistors), the lower active region LAR and the upper active region UAR may be vertically stacked on each other. Accordingly, the second height CHT2 of the single-height cell SHC may have a size including one of the above-described second widths AW2. As a result, the second height CHT2 of the single-height cell SHC according to the present embodiment may be smaller than the first height CHT1 of the single-height cell SHC' of the above-described Figure 1 . For example, the area of the single-height cell SHC according to the present embodiment may be relatively small. The area of the logic unit may be reduced, thereby improving the integration degree of the three-dimensional semiconductor device according to the present embodiment.

[0038] Figure 3 is a plan view for explaining a three-dimensional semiconductor device according to some embodiments of the inventive concept. Figure 4 is related to Figure 3 a magnified view corresponding to a part “P1” in Figures 5A to 5E are cross-sectional views taken along lines A-A', B-B', C-C', E-E', and F-F' of Figure 3 respectively.

[0039] Referring to Figure 3 , Figure 4 and Figures 5A to 5E , the single-height cell SHC may be provided on the substrate 100. In an embodiment of the inventive concept, the substrate 100 may be an insulating substrate including a silicon-based insulating material (e.g., silicon oxide and / or silicon nitride). In another embodiment of the inventive concept, the substrate 100 may be a semiconductor substrate including silicon, germanium, silicon germanium, etc.

[0040] As an example, the substrate 100 may include a first lower insulating layer LIL1 and a second lower insulating layer LIL2. The first lower insulating layer LIL1 may be disposed on the second lower insulating layer LIL2. The first lower insulating layer LIL1 may include a silicon-based insulating material (e.g., silicon oxide) and / or a semiconductor material (e.g., Si or SiGe). The second lower insulating layer LIL2 may include a silicon-based insulating material (e.g., silicon oxide, silicon oxynitride, or silicon nitride).

[0041] The device isolation layer ST may be disposed on the backside metal layer BSM. The device isolation layer ST may define a region for the lower source / drain pattern LSD of the single-height cell SHC. The device isolation layer ST may be disposed between the backside metal layer BSM and the first interlayer insulating layer 110, both of which will be described later. As an example, the device isolation layer ST may include a silicon-based insulating material (e.g., silicon oxide, silicon oxynitride, or silicon nitride).

[0042] In one embodiment of the inventive concept, each single-height cell SHC may be a logic cell constituting a logic circuit (e.g., a logic gate (such as a NAND gate, OR gate, XOR gate, NOT gate (inverter), NOR gate, or XNOR gate)). Each single-height cell SHC may be a logic cell including the three-dimensional elements described above with reference to Figure 2 the description. The single-height cells SHC may be repeatedly arranged in the first direction D1.

[0043] Each single-height cell SHC may include a lower active region LAR and an upper active region UAR sequentially stacked on the substrate 100. One of the lower active region LAR and the upper active region UAR may be a PMOSFET region, and the other of the lower active region LAR and the upper active region UAR may be an NMOSFET region. The lower active region LAR may be set as a part of the bottom layer of the FEOL layer, and the upper active region UAR may be set as a part of the top layer of the FEOL layer. The "bottom layer of the FEOL layer" or the "lower layer of the three-dimensional device" may refer to the lower channel pattern LCH and the lower source / drain pattern LSD described later. In addition, the "top layer of the FEOL layer" or the "upper layer of the three-dimensional device" may refer to the upper channel pattern UCH and the upper source / drain pattern USD described later. The NMOSFETs and PMOSFETs of the lower active region LAR and the upper active region UAR may be vertically stacked to form a three-dimensional stacked transistor. For example, the lower active region LAR may be a PMOSFET region, and the upper active region UAR may be an NMOSFET region. Each of the lower active region LAR and the upper active region UAR may have a bar shape or a linear shape extending in the second direction D2.

[0044] The lower active region LAR may include a lower channel pattern LCH and lower source / drain patterns LSD. The lower channel pattern LCH may be disposed between a pair of lower source / drain patterns LSD along a second direction. The lower channel pattern LCH may electrically connect the pair of lower source / drain patterns LSD to each other.

[0045] The lower channel pattern LCH may include a first semiconductor pattern SP1 and a second semiconductor pattern SP2 that are stacked and spaced apart from each other, but the number of semiconductor patterns is not limited thereto. For example, the lower channel pattern LCH may further include one or more additional semiconductor patterns that are stacked and spaced apart from the second semiconductor pattern SP2. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). Preferably, each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include crystalline silicon. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be in the form of a nanowire, a nanoribbon, or a nanosheet.

[0046] The lower source / drain pattern LSD may be disposed on the substrate 100. Each lower source / drain pattern LSD may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process.

[0047] The lower source / drain pattern LSD may be doped with an impurity to have a first conductivity type. The first conductivity type may be an N-type or a P-type. In this embodiment, the first conductivity type may be a P-type. The lower source / drain pattern LSD may include silicon (Si) and / or silicon germanium (SiGe).

[0048] The first interlayer insulating layer 110 may be disposed on the lower source / drain pattern LSD. The first interlayer insulating layer 110 may cover the lower source / drain pattern LSD.

[0049] The lower active contact LAC may be disposed under the lower source / drain pattern LSD. The lower active contact LAC may be electrically connected to the lower source / drain pattern LSD. Components described herein as “electrically connected” are configured such that an electrical signal may be transmitted from one component to another (although such an electrical signal may attenuate in strength as it is transmitted and may be selectively transmitted). The lower active contact LAC may be buried in the substrate 100. For example, the region where the lower active contact LAC is formed may be restricted to a recess in the substrate 100. The lower active contact LAC may include a conductive material (such as a metal).

[0050] The upper active region UAR may be disposed on the first interlayer insulating layer 110. The upper active region UAR may include an upper channel pattern UCH and upper source / drain patterns USD. The upper channel pattern UCH may be vertically stacked with the lower channel pattern LCH. The upper source / drain patterns USD may be vertically stacked with the lower source / drain patterns LSD. The upper channel pattern UCH may be disposed between a pair of upper source / drain patterns USD. The upper channel pattern UCH may electrically connect the pair of upper source / drain patterns USD to each other.

[0051] The upper channel pattern UCH may include a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 that are stacked and spaced apart from each other, but the number of semiconductor patterns is not limited thereto. As an example, the upper channel pattern UCH may further include one or more additional semiconductor patterns that are stacked while being spaced apart from the fourth semiconductor pattern SP4. The third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the upper channel pattern UCH may include the same semiconductor material as the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the lower channel pattern LCH described above. Each of the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 may be in the form of a nanowire, a nanoribbon, or a nanosheet.

[0052] At least one dummy channel pattern DSP may be disposed between the lower channel pattern LCH and the upper channel pattern UCH. A seed layer SDL may be disposed between the dummy channel pattern DSP and the upper channel pattern UCH. The dummy channel pattern DSP may be spaced apart from the lower source / drain pattern LSD and the upper source / drain pattern USD. For example, the dummy channel pattern DSP may not be connected to any source / drain pattern. The dummy channel pattern DSP may include a semiconductor material (such as silicon (Si), germanium (Ge), or silicon germanium (SiGe)), or may include a silicon-based insulating material (such as silicon oxide or silicon nitride). In an embodiment of the inventive concept, the dummy channel pattern DSP may include a silicon-based insulating material.

[0053] The upper source / drain pattern USD may be disposed on the upper surface of the first interlayer insulating layer 110. Each of the upper source / drain patterns USD may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process.

[0054] The upper source / drain pattern USD may be doped with impurities to have a second conductivity type. The second conductivity type may be different from the first conductivity type of the lower source / drain pattern LSD. The second conductivity type may be an N-type. The upper source / drain pattern USD may include silicon germanium (SiGe) and / or silicon (Si).

[0055] Multiple gate electrodes GE may be disposed on the stacked lower channel pattern LCH and upper channel pattern UCH. When viewed in a plan view, the gate electrode GE may have a bar shape extending in a first direction D1. The gate electrode GE may be vertically stacked with the stacked lower channel pattern LCH and upper channel pattern UCH, and may intersect the stacked lower channel pattern LCH and upper channel pattern UCH in the first direction D1. For example, in a plan view, multiple gate electrodes GE may be repeatedly disposed in the first direction D1. Multiple gate electrodes GE may surround the stacked lower channel pattern LCH and upper channel pattern UCH.

[0056] Multiple gate electrodes GE may extend from the upper surface of the substrate 100 to the lower surface of a gate capping pattern GP, which will be described later, in a third direction D3. Multiple gate electrodes GE may extend from the lower channel pattern LCH of the lower active region LAR to the upper channel pattern UCH of the upper active region UAR in the third direction D3.

[0057] The gate electrode GE may be disposed on the upper surface, bottom surface, and two sidewalls of each of the first semiconductor pattern SP1 to the fourth semiconductor pattern SP4. For example, the transistor according to the present embodiment may include a three-dimensional field-effect transistor in which the gate electrode GE three-dimensionally surrounds the channel (e.g., MBCFET (Multi-Bridge Channel MOSFET) or GAAFET (Gate-All-Around Field-Effect Transistor)).

[0058] Multiple gate electrodes GE may be provided. The gate electrodes GE may be spaced apart from each other in a first direction D1 and a second direction D2. For example, in a single-height cell SHC, the gate electrodes GE may be spaced apart from each other in the second direction D2.

[0059] The gate electrode GE may include a lower gate electrode LGE provided as a part of the lower layer of the FEOL layer, and an upper gate electrode UGE provided as a part of the upper layer of the FEOL layer. The lower gate electrode LGE and the upper gate electrode UGE may be vertically stacked with each other. In an embodiment of the inventive concept, the lower gate electrode LGE and the upper gate electrode UGE may be connected to each other. For example, the lower gate electrode LGE may be integrally formed with the upper gate electrode UGE, and the gate electrode GE according to the present embodiment may be a common gate electrode in which the lower gate electrode LGE on the lower channel pattern LCH and the upper gate electrode UGE on the upper channel pattern UCH are connected to each other.

[0060] The lower gate electrode LGE may include a first inner electrode PO1 disposed between the first lower insulating layer LIL1 and the first semiconductor pattern SP1, a second inner electrode PO2 disposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a third inner electrode PO3 disposed between the second semiconductor pattern SP2 and the dummy channel pattern DSP.

[0061] The upper gate electrode UGE may include a fourth inner electrode PO4 disposed between the dummy channel pattern DSP (or the seed layer SDL) and the third semiconductor pattern SP3, a fifth inner electrode PO5 disposed between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4, and an outer electrode PO6 on the fourth semiconductor pattern SP4.

[0062] A pair of gate spacers GS may be disposed on two sidewalls of the gate electrode GE. The pair of gate spacers GS may be respectively disposed on two sidewalls of the outer electrode PO6. The gate spacers GS may extend along the gate electrode GE in the first direction D1. As an example, the gate spacers GS may include at least one of SiCN (silicon carbonitride), SiCON (silicon carbon oxynitride), and SiN (silicon nitride). As another example, the gate spacers GS may include multiple layers made of at least two of SiCN, SiCON, and SiN.

[0063] The gate covering pattern GP may be disposed on the upper surface of the gate electrode GE. The gate covering pattern GP may extend along the gate electrode GE in the first direction D1. As an example, the gate covering pattern GP may include at least one of SiON (silicon oxynitride), SiCN, SiCON, and SiN.

[0064] The gate insulating layer GI may be disposed between the gate electrode GE and the first semiconductor pattern SP1 to the fourth semiconductor pattern SP4. The gate insulating layer GI may include a silicon oxide layer, a silicon oxynitride layer, and / or a high-k dielectric layer. As an example, the gate insulating layer GI may include a silicon oxide layer directly covering the surfaces of the semiconductor patterns SP1 to SP4 and a high-k dielectric layer on the silicon oxide layer. For example, the gate insulating layer GI may include multiple layers of a silicon oxide layer and a high-k dielectric layer. The high-k dielectric layer may include a high dielectric constant material having a dielectric constant higher than that of the silicon oxide layer.

[0065] The second interlayer insulating layer 120 and the third interlayer insulating layer 130 may be sequentially disposed on the lower source / drain pattern LSD and the first interlayer insulating layer 110. The second interlayer insulating layer 120 may cover the upper source / drain pattern USD. The third interlayer insulating layer 130 may cover the second interlayer insulating layer 120.

[0066] The upper active contact UAC may be disposed through the second inter-level dielectric layer 120 and the third inter-level dielectric layer 130, and electrically connected to the upper source-drain pattern USD, respectively. For example, the upper surface of the upper active contact UAC may be coplanar with the upper surface of the third inter-level dielectric layer 130. Terms such as "same", "symmetric", "equal", "coplanar", "parallel", and "perpendicular" as used herein encompass identity or approximate identity including variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize such meaning.

[0067] An upper gate contact UGC may be provided that penetrates the third inter-level dielectric layer 130 and the gate capping pattern GP and is electrically connected to the upper gate electrode UGE. The upper gate contact UGC may include a conductive material (such as the metal of the upper active contact UAC and the upper gate contact UGC).

[0068] The isolation trench STR may separate the gate electrodes GE adjacent to each other in the first direction D1 in the gate group. Thus, the adjacent gate electrodes GE may be spaced apart in the first direction D1 by the isolation trench STR. The isolation trench STR may extend in the second direction D2 and the third direction D3. The width of the isolation trench STR in the first direction D1 may become smaller as it goes downward in the third direction D3.

[0069] The isolation insulating pattern SI may fill the interior of the isolation trench STR. The isolation insulating pattern SI may extend in each of the second direction D2 and the third direction D3 in the isolation trench STR. The isolation insulating pattern SI may be disposed between a pair of gate electrodes GE adjacent to each other in the first direction D1. The isolation insulating pattern SI may include an insulating material (such as silicon oxide and silicon nitride).

[0070] The fourth inter-level dielectric layer 140 may be provided on the third inter-level dielectric layer 130. The first metal layer M1 may be provided in the fourth inter-level dielectric layer 140. The first metal layer M1 may include upper interconnects UMI. The first metal layer M1 may further include upper vias UVI. The upper vias UVI may electrically connect the upper interconnects UMI to the upper active contact UAC or the upper gate contact UGC. Each of the upper interconnects UMI and the upper vias UVI may include a conductive material (such as metal).

[0071] Additional metal layers (e.g., M2, M3, M4, etc.) may be stacked on the first metal layer M1. The first metal layer M1 and the metal layers on the first metal layer M1 (e.g., M2, M3, M4, etc.) may form the back-end-of-line (BEOL) layers of the semiconductor device. The metal layers on the first metal layer M1 (e.g., M2, M3, M4, etc.) may include routing interconnects for connecting logic units to each other.

[0072] The lower interlayer insulating layer 210 may be disposed below the lower surface of the substrate 100. A lower gate contact LGC electrically connected to the lower gate electrode LGE may be disposed between the lower interlayer insulating layer 210 and the lower gate electrode LGE. A backside metal layer BSM may be disposed in the lower interlayer insulating layer 210. The backside metal layer BSM may include a lower contact LC, a lower interconnect LMI, and a lower via LVI. The lower contact LC may be electrically connected to the lower source-drain pattern LSD through a lower active contact LAC. The lower via LVI may electrically connect the lower interconnect LMI to the lower active contact LAC, the lower contact LC, or the lower gate contact LGC. Each of the lower gate contact LGC, the lower contact LC, the lower interconnect LMI, and the lower via LVI may include a conductive material (such as metal).

[0073] An additional lower metal layer may be stacked below the backside metal layer BSM. In one embodiment of the invention, the lower metal layer may include a power transmission network. The power transmission network may include a line network for applying a source voltage (VSS) and a drain voltage (VDD) to the backside metal layer BSM.

[0074] The isolation trenches STR may include first isolation trenches STR1 and second isolation trenches STR2 alternately arranged in a first direction D1. As an example, a single-height cell SHC may be disposed between the first isolation trench STR1 and the second isolation trench STR2. The single-height cell SHC may include a first single-height cell SHC1, a second single-height cell SHC2, and a third single-height cell SHC3 arranged to be spaced apart from each other in the first direction D1. The first isolation trench STR1 may be disposed between the first single-height cell SHC1 and the second single-height cell SHC2, and the second isolation trench STR2 may be disposed between the second single-height cell SHC2 and the third single-height cell SHC3.

[0075] The isolation insulating pattern SI may include a first isolation insulating pattern SI1 filling the interior of the first isolation trench STR1 and a second isolation insulating pattern SI2 filling the interior of the second isolation trench STR2.

[0076] The first isolation insulating pattern SI1 may have a first width W1 in a first direction D1 in a plan view, and the second isolation insulating pattern SI2 may have a second width W2 in the first direction D1 in the plan view. A plurality of conductive plates CP, which will be described later, may be disposed in the first isolation insulating pattern SI1, and the plurality of conductive plates CP may not be disposed in the second isolation insulating pattern SI2. The second isolation insulating pattern SI2 may not require a space for the plurality of conductive plates CP to be disposed therein, and thus, the second width W2 of the second isolation insulating pattern SI2 may be smaller than the first width W1 of the first isolation insulating pattern SI1. As a result, the second height CHT2 of the single-height cell SHC may become relatively small, and thus the area of the single-height cell SHC may become relatively small. Accordingly, the integration degree of the three-dimensional semiconductor device may be improved.

[0077] The first isolation insulating pattern SI1 may include a liner insulating layer LN that conformally covers two sidewalls of the first isolation trench STR1 and a first fill pattern FL1 between the liner insulating layers LN. The liner insulating layer LN and the first fill pattern FL1 may be spaced apart from each other in the first direction D1. One liner insulating layer LN may be disposed between the first conductive plate CP1 and the first gate electrode GE1, which will be described later, and the other liner insulating layer may be between the second conductive plate CP2 and the second gate electrode GE2, which will be described later. The first fill pattern FL1 may be disposed between the first conductive plate CP1 and the second conductive plate CP2, which will be described later. Along a third direction D3, the widths of each of the liner insulating layers LN in the first direction D1 may be substantially the same. The width of the first fill pattern FL1 in the first direction D1 may become smaller as it goes downward in the third direction D3.

[0078] A plurality of conductive plates CP may be disposed in the first isolation insulating pattern SI1. The plurality of conductive plates CP may be disposed between gate electrodes GE adjacent to each other in the first direction D1. The first single-height cell SHC1 may include first gate electrodes GE1 arranged to be spaced apart from each other in a second direction D2, and the second single-height cell SHC2 may include second gate electrodes GE2 arranged to be spaced apart from each other in the second direction D2. The plurality of conductive plates CP may extend in each of the second direction D2 and the third direction D3 in the first isolation insulating pattern SI1. Specifically, the plurality of conductive plates CP may extend from the upper surface to the lower surface of the first isolation insulating pattern SI1. The plurality of conductive plates CP may include a conductive material (such as, metal).

[0079] A plurality of conductive plates CP may be provided. The conductive plates CP may be arranged adjacent to each other in a first direction D1 and a second direction D2. A conductive separation region CS may be defined between the conductive plates CP adjacent to each other along the second direction D2. The conductive plates CP may be spaced apart from each other in the second direction D2 through the conductive separation region CS. The first separation insulating pattern SI1 may further include a second filling pattern FL2 in the conductive separation region CS. The second filling pattern FL2 may include an insulating material, so that the conductive plates CP spaced apart from each other in the second direction D2 may be electrically insulated. For example, in a part of the first separation insulating pattern SI1, the liner insulating layer LN, the first filling pattern FL1, and the second filling pattern FL2 may form an integral shape without an interface therebetween.

[0080] The plurality of conductive plates CP may include a first conductive plate CP1 and a second conductive plate CP2 adjacent to each other in the first direction D1 in the first separation insulating pattern SI1. The first conductive plate CP1 may be closer to the first gate electrode GE1 than the second gate electrode GE2, and the second conductive plate CP2 may be closer to the second gate electrode GE2 than the first gate electrode GE1. The first conductive plate CP1 and the second conductive plate CP2 may be spaced apart from each other, and the first filling pattern FL1 is disposed between the first conductive plate CP1 and the second conductive plate CP2. As an example, each of the first conductive plate CP1 and the second conductive plate CP2 may have a shape of a plate extending in each of the second direction D2 and the third direction D3. When observed in a plan view, the liner insulating layer LN, the first conductive plate CP1, the first filling pattern FL1, and the second conductive plate CP2 may be sequentially arranged in the first separation trench STR1 in the first direction D1.

[0081] Each of the first conductive plate CP1 and the second conductive plate CP2 may be provided in plurality. The first conductive plates CP1 may be spaced apart from each other in the second direction D2 and are electrically insulated through the above-mentioned conductive separation region CS. The second conductive plates CP2 may be spaced apart from each other in the second direction D2 and are electrically insulated through the above-mentioned conductive separation region CS.

[0082] Each of the first conductive plate CP1 and the second conductive plate CP2 may conformally cover the sidewalls of each of the liner insulating layer LN. For example, along the third direction D3, the width of the first conductive plate CP1 in the first direction D1 may be substantially the same. Similarly, along the third direction D3, the width of the second conductive plate CP2 in the first direction D1 may be substantially the same. For example, the widths of the first conductive plate CP1 and the second conductive plate CP2 in the first direction D1 may be substantially the same along the third direction.

[0083] The liner insulating layer LN can conformally cover the sidewalls of the first isolation trench STR1. Thus, in the third direction D3, the distances between the first conductive plate CP1 and the first gate electrode GE1 can be substantially the same. Similarly, in the third direction D3, the distances between the second conductive plate CP2 and the second gate electrode GE2 can be substantially the same. The distances between the first conductive plate CP1 and the first gate electrode GE1 in the first direction are substantially the same along the third direction, and the distances between the second conductive plate CP2 and the second gate electrode GE2 in the first direction are substantially the same along the third direction. For example, at substantially the same level, the distance between the first conductive plate CP1 and the first gate electrode GE1 can be substantially the same as the distance between the second conductive plate CP2 and the second gate electrode GE2. As used herein, "level" refers to the height level with respect to the third direction D3.

[0084] Both sides of the first conductive plate CP1 can have profiles that slope in substantially the same direction. Both sides of the second conductive plate CP2 can have profiles that slope in substantially the same direction.

[0085] When viewed in a cross-sectional view, the first conductive plate CP1 and the second conductive plate CP2 can have profiles that are symmetric to each other. Specifically, when viewed in a cross-sectional view, the first conductive plate CP1 and the second conductive plate CP2 can have mirror symmetry with respect to the first filling pattern FL1.

[0086] The first distance DS1 and the second distance DS2 are the distances between the first conductive plate CP1 and the second conductive plate CP2. The first distance DS1 at a level substantially the same as the upper surface of the first isolation insulating pattern SI1 can be larger than the second distance DS2 at a level substantially the same as the lower surface of the first isolation insulating pattern SI1. For example, the first distance DS1 at the level of the upper surface of the first isolation insulating pattern SI1 can be larger than the second distance DS2 at the level of the lower surface of the first isolation insulating pattern SI1. The distance between the first conductive plate CP1 and the second conductive plate CP2 can decrease as it goes down in the third direction D3 (or decreases for the downward direction).

[0087] Hereinafter, although the scope of the invention is not limited thereto, reference will be made to Figure 4 and Figures 5A to 5E to describe in detail the adjacent components electrically connected to each of the first conductive plate CP1 and the second conductive plate CP2. Many modifications and changes to the arrangement of each of the first conductive plate CP1 and the second conductive plate CP2 and the adjacent components can be feasible.

[0088] Refer to Figure 4 and Figures 5A to 5E, the lower source-drain pattern LSD may include a first lower source-drain pattern LSD1 and a second lower source-drain pattern LSD2 spaced apart from each other in the second direction D2 in each of the single-height cells SHC1 and SHC2. The upper source-drain pattern USD may include a first upper source-drain pattern USD1 on the first lower source-drain pattern LSD1 and a second upper source-drain pattern USD2 on the second lower source-drain pattern LSD2.

[0089] The first lower source-drain pattern LSD1 and the second lower source-drain pattern LSD2 of the first single-height cell SHC1 may be adjacent to the first lower source-drain pattern LSD1 and the second lower source-drain pattern LSD2 of the second single-height cell SHC2 in the first direction D1, respectively. The first upper source-drain pattern USD1 and the second upper source-drain pattern USD2 of the first single-height cell SHC1 may be adjacent to the first upper source-drain pattern USD1 and the second upper source-drain pattern USD2 of the second single-height cell SHC2 in the first direction D1, respectively.

[0090] The lower active contact LAC may include a first lower active contact LAC1 below the first lower source-drain pattern LSD1 and a second lower active contact LAC2 below the second lower source-drain pattern LSD2. The upper active contact UAC may include a first upper active contact UAC1 on the first upper source-drain pattern USD1 and a second upper active contact UAC2 on the second upper source-drain pattern USD2.

[0091] The first conductive plate CP1 may be electrically connected to one of the first lower source-drain pattern LSD1 and the second lower source-drain pattern LSD2 in the first single-height cell SHC1 and the first upper source-drain pattern USD1 and the second upper source-drain pattern USD2 in the first single-height cell SHC1.

[0092] As an example, the first conductive plate CP1 may be electrically connected to the first upper source-drain pattern USD1 of the first single-height cell SHC1. In this case, the first upper contact UCa may be disposed on the upper surface of the first upper active contact UAC1. The first upper contact UCa may cover the upper surface of the first upper active contact UAC1 and may extend to cover the upper surface of the first conductive plate CP1. Thus, the first conductive plate CP1 and the first upper source-drain pattern USD1 may be electrically connected to each other through the first upper contact UCa and the first upper active contact UAC1. The first upper contact UCa may be spaced apart from the second conductive plate CP2 and may be electrically insulated.

[0093] As another example, although not shown in the drawings, the first upper contact UCa may not be provided, and the first upper active contact UAC1 may be in direct contact with the first conductive plate CP1 and electrically connected to each other.

[0094] The second conductive plate CP2 can be electrically connected to one of the first lower source-drain pattern LSD1 and the second lower source-drain pattern LSD2 in the second single-height cell SHC2, and the first upper source-drain pattern USD1 and the second upper source-drain pattern USD2 in the second single-height cell SHC2.

[0095] As an example, the second conductive plate CP2 can be electrically connected to the first lower source-drain pattern LSD1 of the second single-height cell SHC2. In this case, the lower contact LC can include a first lower contact LCa that covers the lower surface of the first lower active contact LAC1 and extends to cover the lower surface of the second conductive plate CP2. Therefore, the second conductive plate CP2 and the first lower source-drain pattern LSD1 can be electrically connected to each other through the first lower contact LCa and the first lower active contact LAC1. The first lower contact LCa can be spaced apart from the first conductive plate CP1 and may not be electrically connected to the first conductive plate CP1.

[0096] The first conductive plate CP1 can be electrically connected to the backside metal layer BSM or the first metal layer M1. For example, the first conductive plate CP1 is electrically connected to the first upper source-drain pattern USD1, and the first conductive plate CP1 can be electrically connected to the backside metal layer BSM. Specifically, the lower contact LC can include a second lower contact LCb that contacts the lower surface of the first conductive plate CP1. A lower via LVI can be disposed between the lower interconnect LMI and the second lower contact LCb. Therefore, the first conductive plate CP1 and the lower interconnect LMI can be electrically connected to each other through the second lower contact LCb and the lower via LVI. In summary, the lower interconnect LMI and the first upper source-drain pattern USD1 can be electrically connected to each other through the first conductive plate CP1.

[0097] The second lower contact LCb can be spaced apart from the first lower contact LCa and may not be electrically connected to the first lower contact LCa. For example, the second lower contact LCb can be adjacent to the first lower contact LCa in the first direction D1, but the invention is not limited thereto.

[0098] The second conductive plate CP2 can be electrically connected to the backside metal layer BSM or the first metal layer M1. For example, the second conductive plate CP2 is electrically connected to the first lower source-drain pattern LSD1, and the second conductive plate CP2 can be electrically connected to the first metal layer M1. Specifically, a second upper contact UCb can be provided on the upper surface of the second conductive plate CP2. An upper via UVI can be disposed between the upper interconnect UMI and the second upper contact UCb. Therefore, the second conductive plate CP2 and the upper interconnect UMI can be electrically connected to each other through the second upper contact UCb and the upper via UVI. In summary, the upper interconnect UMI and the first lower source-drain pattern LSD1 can be electrically connected to each other through the second conductive plate CP2.

[0099] The second upper contact UCb may be spaced apart from the first upper contact UCa and may not be electrically connected to the first upper contact UCa. For example, the second upper contact UCb may be adjacent to the first upper contact UCa in the first direction D1, but the invention is not limited thereto.

[0100] According to an embodiment of the invention, components of a logic element (e.g., the first single-height cell SHC1) and corresponding components of a second logic element (e.g., the second single-height cell SHC2) may be arranged to have a symmetric layout of a cell array in a plan view. For example, in an embodiment of the invention, components electrically connected to the bottom layer of the FEOL layer and corresponding components electrically connected to the top layer of the FEOL layer may be arranged symmetrically in the plan view with respect to a horizontal axis that intersects or overlaps with the first filling pattern FL1 and is parallel to the second direction. In an embodiment of the invention, components electrically connected to the first conductive plate CP1 and corresponding components electrically connected to the second conductive plate CP2 may be arranged symmetrically in the plan view with respect to a horizontal axis that intersects with the first filling pattern FL1 and is parallel to the second direction. For example, as Figure 4 shown in the plan view of, the lower vias LVI and the upper vias UVI may be arranged symmetrically with respect to a horizontal axis that intersects with the first filling pattern FL1 and is parallel to the second direction D2. In addition, as Figure 4 shown in the plan view of, the first upper contact UCa and the first lower contact LCa may be arranged symmetrically with respect to a horizontal axis that crosses the first filling pattern FL1 and is parallel to the second direction. In one embodiment, although not shown in the drawings, in the plan view, other components of the BEOL layer and corresponding components of the backside metal layer BSM may also be arranged symmetrically with respect to a horizontal axis that intersects with the first filling pattern FL1 and is parallel to the second direction. The symmetry described above may be achieved by utilizing the symmetric arrangement of the first conductive plate CP1 and the second conductive plate CP2 formed in the first separation insulating pattern SI1.

[0101] Hereinafter, referring to Figure 6 , Figures 7A to 7D , Figure 8 , Figures 9A to 9D and Figure 10 , other embodiments of the inventive concept will be described. To simplify the explanation, descriptions of content that is repeated with the above-mentioned content are omitted.

[0102] Figure 6 is an enlarged view corresponding to a part "P1" in Figure 3 . Figures 7A to 7D are cross-sectional views taken along lines B-B', D-D', E-E' and F-F' of Figure 3 , respectively.

[0103] Referring to Figure 6 and Figures 7A to 7D, various arrangements of adjacent components electrically connected to each of the first conductive plate CP1 and the second conductive plate CP2 will be described in detail.

[0104] Referring to Figure 6 and Figures 7A to 7D , as an example, the first conductive plate CP1 can be electrically connected to the second upper source-drain pattern USD2 of the first single-height cell SHC1. In this case, the first upper contact UCa can be disposed on the upper surface of the second upper active contact UAC2. The first upper contact UCa can extend to cover the upper surface of the second upper active contact UAC2 and the upper surface of the first conductive plate CP1. Thus, the first conductive plate CP1 and the second upper source-drain pattern USD2 can be electrically connected to each other through the first upper contact UCa and the second upper active contact UAC2. Therefore, the backside metal layer BSM and the second upper source-drain pattern USD2 can be electrically connected through the first conductive plate CP1.

[0105] The arrangement of adjacent components electrically connected to the second conductive plate CP2 can be the same / similar to the arrangement described with reference to Figure 3 , Figure 4 , Figures 5A to 5E .

[0106] The arrangement of adjacent components electrically connected to each of the first conductive plate CP1 and the second conductive plate CP2 is not limited to the arrangement described with reference to Figure 3 , Figure 6 and Figures 7A to 7D , and many modifications and changes can be feasible.

[0107] For example, the first conductive plate CP1 is electrically connected to the first metal layer M1 and the second upper contact UCb, and the first conductive plate CP1 can be electrically connected to one of the lower source-drain patterns LSD adjacent to the first conductive plate CP1 in the first direction D1 through the first lower contact LCa in the first single-height cell SHC1. In this case, one of the lower source-drain patterns LSD and the first metal layer M1 can be electrically connected through the first conductive plate CP1.

[0108] As an example, the first conductive plate CP1 is electrically connected to the backside metal layer BSM and the second lower contact LCb, and the first conductive plate CP1 can be electrically connected to one of the upper source-drain patterns USD adjacent to the first conductive plate CP1 in the first direction D1 through the first upper contact UCa in the first single-height cell SHC1. In this case, one of the upper source-drain patterns USD and the backside metal layer BSM can be electrically connected through the first conductive plate CP1.

[0109] For example, the second conductive plate CP2 is electrically connected to the first metal layer M1 and the second upper contact UCb, and the second conductive plate CP2 can be electrically connected to one of the lower source-drain patterns LSD adjacent to the second conductive plate CP2 in the first direction D1 through the first lower contact LCa in the second single-height cell SHC2. In this case, one of the lower source-drain patterns LSD and the first metal layer M1 can be electrically connected through the second conductive plate CP2.

[0110] As an example, the second conductive plate CP2 is electrically connected to the backside metal layer BSM and the second lower contact LCb, and the second conductive plate CP2 can be electrically connected to one of the upper source-drain patterns USD adjacent to the second conductive plate CP2 in the first direction D1 through the first upper contact UCa in the second single-height cell SHC2. In this case, one of the upper source-drain patterns USD and the backside metal layer BSM can be electrically connected through the second conductive plate CP2.

[0111] According to the inventive concept, the first conductive plate CP1 and the second conductive plate CP2 adjacent to each other in the first direction D1 can be disposed in a first separation trench STR1. Accordingly, the source-drain patterns LSD and USD of the two single-height cells SHC1 and SHC2 can be electrically connected to adjacent components (e.g., the backside metal layer BSM and the first metal layer M1) through the two conductive plates CP1 and CP2 disposed in a single separation trench STR1. As a result, the design freedom of the three-dimensional semiconductor device can be increased compared to disposing one conductive plate in a single separation trench.

[0112] According to an embodiment of the invention, components of a logic element (e.g., the first single-height cell SHC1) and corresponding components of a second logic element (e.g., the second single-height cell SHC2) can be arranged to have a symmetric layout of a cell array in a plan view. For example, in an embodiment of the invention, components electrically connected to the bottom layer of the FEOL layer and corresponding components electrically connected to the top layer of the FEOL layer can be symmetrically arranged in the plan view with respect to a symmetry point in the first fill pattern FL1. In an embodiment of the invention, components electrically connected to the first conductive plate CP1 and corresponding components electrically connected to the second conductive plate CP2 can be symmetrically arranged in the plan view with respect to a symmetry point in the first fill pattern FL1. For example, as Figure 6 shown in the plan view of, the lower vias LVI and the upper vias UVI can be symmetrically arranged with respect to a symmetry point in the first fill pattern FL1. Further, as Figure 4As shown in the plan view, the first upper contact UCa and the first lower contact LCa may be symmetrically arranged with respect to the symmetry point in the first filling pattern FL1. In one embodiment, although not shown in the drawings, other components of the BEOL layer and the corresponding components of the backside metal layer BSM may also be symmetrically arranged with respect to the symmetry point in the first filling pattern FL1 in the plan view. The symmetry described above may be achieved by utilizing the symmetric arrangement of the first conductive plate CP1 and the second conductive plate CP2 formed in the first separation insulating pattern SI1.

[0113] Figure 8 is an enlarged view corresponding to the part "P1" in Figure 3 the Figures 9A to 9D are cross-sectional views taken along the lines B-B', D-D', E-E' and F-F' of Figure 3 respectively.

[0114] Referring to Figure 8 and Figures 9A to 9D and referring to Figure 6 and Figures 7A to 7D each of the first conductive plate CP1 and the second conductive plate CP2 described may include an upper recessed region CUR and a lower recessed region CLR. The upper gap filling pattern UGP may fill the upper recessed region CUR, and the lower gap filling pattern LGP may fill the lower recessed region CLR. The upper gap filling pattern UGP and the lower gap filling pattern LGP may include an insulating material. As an example, the upper gap filling pattern UGP and the lower gap filling pattern LGP may include the same material as the first separation insulating pattern SI1. In this case, the upper gap filling pattern UGP and the lower gap filling pattern LGP may form an integral shape with the first separation insulating pattern SI1 without an interface therebetween.

[0115] Due to the upper recessed region CUR, each of the first conductive plate CP1 and the second conductive plate CP2 may have upper surfaces at different levels. Each of the first conductive plate CP1 and the second conductive plate CP2 may include a first upper surface Ca1 in contact with the fourth interlayer insulating layer 140 and a second upper surface Ca2 on the inner lower surface of the upper recessed region CUR. The first upper surface Ca1 may be located at a higher level than the second upper surface Ca2.

[0116] Due to the lower recessed region LUR, each of the first conductive plate CP1 and the second conductive plate CP2 may have lower surfaces at different levels. Each of the first conductive plate CP1 and the second conductive plate CP2 may include a first lower surface Cb1 in contact with the lower interlayer insulating layer 210 and a second lower surface Cb2 recessed by the lower recessed region LUR. The first lower surface Cb1 may be located at a lower level than the second lower surface Cb2.

[0117] When observed in a plan view, the upper recessed region CUR may be adjacent to the first upper contact UCa in a first direction D1. For example, the first conductive plate CP1 and the first upper contact UCa may be electrically connected, and when observed in a plan view, the upper recessed region CUR in the second conductive plate CP2 may be adjacent to the first upper contact UCa in the first direction D1. In this case, due to the misalignment of the first upper contact UCa, even if the first upper contact UCa extends onto the upper surface of the second conductive plate CP2, the first upper contact UCa and the second conductive plate CP2 may be spaced apart from each other by the upper recessed region CUR. In addition, the first upper contact UCa and the second conductive plate CP2 may be electrically insulated by the upper gap filling pattern UGP filling the upper recessed region CUR.

[0118] When observed in a plan view, the upper recessed region CUR may be adjacent to the second upper contact UCb in a first direction D1. For example, the second conductive plate CP2 and the second upper contact UCb may be electrically connected, and when observed in a plan view, the upper recessed region CUR in the first conductive plate CP1 may be adjacent to the second upper contact UCb in the first direction D1. In this case, due to the misalignment of the second upper contact UCb, even if the second upper contact UCb extends onto the upper surface of the first conductive plate CP1, the second upper contact UCb and the first conductive plate CP1 may be spaced apart from each other by the upper recessed region CUR. In addition, the second upper contact UCb and the first conductive plate CP1 may be electrically insulated by the upper gap filling pattern UGP filling the upper recessed region CUR.

[0119] When observed in a plan view, the lower recessed region CLR may be adjacent to the first lower contact LCa in a first direction D1. For example, the second conductive plate CP2 and the first lower contact LCa may be electrically connected, and when observed in a plan view, the lower recessed region CLR in the first conductive plate CP1 may be adjacent to the first lower contact LCa in the first direction D1. In this case, due to the misalignment of the first lower contact LCa, even if the first lower contact LCa extends onto the lower surface of the first conductive plate CP1, the first lower contact LCa and the first conductive plate CP1 may be spaced apart from each other by the lower recessed region CLR. In addition, the first lower contact LCa and the first conductive plate CP1 may be electrically insulated by the lower gap filling pattern LGP filling the lower recessed region CLR.

[0120] When observed in a plan view, the lower recessed region CLR may be adjacent to the second lower contact LCb in a first direction D1. For example, the first conductive plate CP1 and the second lower contact LCb may be electrically connected, and when observed in a plan view, the lower recessed region CLR in the second conductive plate CP2 may be adjacent to the second lower contact LCb in the first direction D1. In this case, due to the misalignment of the second lower contact LCb, even if the second lower contact LCb extends onto the lower surface of the second conductive plate CP2, the second lower contact LCb and the second conductive plate CP2 may be spaced apart from each other through the lower recessed region CLR. In addition, the second lower contact LCb and the second conductive plate CP2 may be electrically insulated by a lower gap filling pattern LGP filling the lower recessed region CLR.

[0121] According to the inventive concept, each of the first conductive plate CP1 and the second conductive plate CP2 may include an upper recessed region CUR and a lower recessed region CLR. Accordingly, unnecessary electrical connections between each of the first conductive plate CP1 and the second conductive plate CP2 and adjacent components may be prevented. As a result, process defects in the three-dimensional semiconductor device may be prevented, and the productivity of the three-dimensional semiconductor device may be improved.

[0122] Reference has been made Figure 8 and Figures 9A to 9D to the arrangement of each of the upper recessed region CUR and the lower recessed region CLR and adjacent components, but the invention is not limited thereto, and many modifications and changes may be feasible.

[0123] Figure 10 is a cross-sectional view taken along line B - B' in Figure 3 .

[0124] Referring to Figure 3 and Figure 10 , the first filling pattern FL1 of the first separation insulating pattern SI1 may include an air gap AG therein. Accordingly, the air gap AG may be disposed between the first conductive plate CP1 and the second conductive plate CP2. As a result, electrical interference between the first conductive plate CP1 and the second conductive plate CP2 may be reduced, and the electrical characteristics of the three-dimensional semiconductor device may be improved. It should be understood that the "air gap" may include a gap having air or other gases (e.g., gases such as those present during manufacturing), or may include a gap in which a vacuum is formed.

[0125] Figure 11A , Figure 11B , Figures 12A to 12C , Figure 13A , Figure 13B , Figures 14A to 14C , Figure 15A and Figure 15B are cross-sectional views for explaining a method of manufacturing a three-dimensional semiconductor device according to an embodiment of the inventive concept. Specifically,Figure 11A , Figure 12A , Figure 13A and Figure 14A are cross-sectional views taken along line A-A' of Figure 3 , respectively. Figure 11B , Figure 12B , Figure 13B , Figure 14B and Figure 15A are cross-sectional views taken along line B-B' of Figure 3 , respectively. Figure 12C and Figure 14C are cross-sectional views taken along line C-C' of Figure 3 , respectively. Figure 15B is a cross-sectional view taken along line E-E' of Figure 3 , respectively.

[0126] Hereinafter, a method of manufacturing a three-dimensional semiconductor device according to an embodiment of the inventive concept will be described. To simplify the explanation, descriptions of content that is repetitive with the above-mentioned content will be omitted.

[0127] Referring to Figure 3 , Figure 11A and Figure 11B , a semiconductor substrate 105 may be provided. The semiconductor substrate 105 may include any one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). For example, the semiconductor substrate 105 may be a single-crystalline silicon wafer.

[0128] A first lower insulating layer LIL1 may be formed on the semiconductor substrate 105. A first sacrificial layer SAL1 and a first active layer ACL1 may be alternately stacked on the first lower insulating layer LIL1. The first sacrificial layer SAL1 may include one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and the first active layer ACL1 may include another one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). For example, the first sacrificial layer SAL1 may include silicon germanium (SiGe), and the first active layer ACL1 may include silicon (Si).

[0129] A separation layer DSL may be formed on the uppermost first sacrificial layer SAL1. For example, the thickness of the separation layer DSL may be greater than the thickness of the first sacrificial layer SAL1. The separation layer DSL may include silicon (Si) or silicon germanium (SiGe). In one embodiment, the separation layer DSL includes silicon germanium (SiGe), and the concentration of germanium (Ge) in the separation layer DSL may be greater than the concentration of germanium (Ge) in the first sacrificial layer SAL1.

[0130] A seed layer SDL can be formed on the separation layer DSL. The seed layer SDL can include the same material as the first active layer ACL1. A second sacrificial layer SAL2 and a second active layer ACL2 can be alternately stacked on the seed layer SDL. Each of the second sacrificial layers SAL2 can include the same material as the first sacrificial layer SAL1, and each of the second active layers ACL2 can include the same material as the first active layer ACL1. The separation layer DSL can be disposed between the first sacrificial layer SAL1 and the seed layer SDL.

[0131] The stacked first sacrificial layer SAL1, second sacrificial layer SAL2, first active layer ACL1, second active layer ACL2, and separation layer DSL can be patterned to form a stacked pattern STP. Forming the stacked pattern STP can include: forming a hard mask pattern on the uppermost second active layer ACL2, and using the hard mask pattern as an etching mask to etch the layers SAL1, SAL2, ACL1, ACL2, SDL, and DSL stacked on the semiconductor substrate 105. While forming the stacked pattern STP, the upper portion of the semiconductor substrate 105 can be patterned to form a first trench TR1 that defines a region for the device isolation layer ST. The stacked pattern STP can have a bar shape or a linear shape extending in the second direction D2.

[0132] The stacked pattern STP can include a lower stacked pattern STP1 on the first lower insulating layer LIL1, an upper stacked pattern STP2 on the lower stacked pattern STP1, and a separation layer DSL between the lower stacked pattern STP1 and the upper stacked pattern STP2. The lower stacked pattern STP1 can include the first sacrificial layer SAL1 and the first active layer ACL1 alternately stacked. The upper stacked pattern STP2 can include the seed layer SDL and include the second sacrificial layer SAL2 and the second active layer ACL2 alternately stacked on the seed layer SDL. On the semiconductor substrate 105, a device isolation layer ST can be formed to fill the first trench TR1.

[0133] Referring to Figure 3 and Figures 12A to 12C , a plurality of sacrificial patterns PP can be formed across the stacked pattern STP. Each sacrificial pattern PP can be formed in a linear shape extending in the first direction D1. Specifically, forming the sacrificial pattern PP can include: forming a sacrificial layer on the entire surface of the semiconductor substrate 105, forming a hard mask pattern MP on the sacrificial layer, and using the hard mask pattern MP as an etching mask to pattern the sacrificial layer. The sacrificial layer can include amorphous silicon and / or polycrystalline silicon. A pair of gate spacers GS can be formed on the two sidewalls of the sacrificial pattern PP, respectively.

[0134] The gate spacer GS and the hard mask pattern MP can be used as an etch mask to perform an etching process on the stacked pattern STP. Through the etching process, a second trench TR2 can be formed between adjacent sacrificial patterns PP.

[0135] A sacrificial contact pattern PLH can be formed in the semiconductor substrate 105 exposed through the second trench TR2. The sacrificial contact pattern PLH can be repeatedly arranged in a first direction D1 and a second direction D2. The sacrificial contact pattern PLH can include a material (e.g., silicon germanium (SiGe)) having an etching selectivity with respect to the semiconductor substrate 105. The sacrificial contact pattern PLH can be formed using an epitaxial growth process. The second trench TR2 can expose the sacrificial contact pattern PLH.

[0136] In an embodiment of the invention, the isolation layer DSL can include silicon germanium (SiGe), and the isolation layer DSL can be replaced with a silicon-based insulating material. For example, the isolation layer DSL exposed by the second trench TR2 can be selectively removed, and a silicon-based insulating material (e.g., silicon nitride) can be filled in the region where the isolation layer DSL is removed.

[0137] Refer to Figure 3 、 Figure 13A and Figure 13B and

[0138] During the first SEG process, impurities can be in-situ introduced into the lower source / drain pattern LSD. As another example, after the lower source / drain pattern LSD is formed, impurities can be implanted into the lower source / drain pattern LSD. The lower source / drain pattern LSD can be doped to have a first conductivity type.

[0139] The first active layer ACL1 disposed between a pair of lower source / drain patterns LSD can constitute a lower channel pattern LCH. For example, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the lower channel pattern LCH can be constituted by the first active layer ACL1. The lower channel pattern LCH and the lower source / drain pattern LSD can constitute a lower active region LAR as a lower layer of a three-dimensional device.

[0140] A first interlayer insulating layer 110 may be formed to cover the lower source / drain pattern LSD. As an example, an etch stop layer may be further formed to conformally cover the lower source / drain pattern LSD before forming the first interlayer insulating layer 110. For example, the first interlayer insulating layer 110 may be a composite layer including a plurality of sub-insulating layers. A sub-insulating layer of the first interlayer insulating layer 110 may be formed under the lower source / drain pattern LSD before forming the lower source / drain pattern LSD, and another insulating layer of the first interlayer insulating layer 110 may be further formed after forming the lower source / drain pattern LSD.

[0141] An upper source / drain pattern USD may be formed on the sidewalls of the upper stacked pattern STP2. Specifically, the upper source / drain pattern USD may be formed by performing a second SEG process through a second trench TR2 using the exposed sidewalls of the upper stacked pattern STP2 as a seed layer. The upper source / drain pattern USD may be doped to have a second conductivity type different from the first conductivity type.

[0142] A second active layer ACL2 disposed between a pair of upper source / drain patterns USD may constitute an upper channel pattern UCH. For example, a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 of the upper channel pattern UCH may be constituted by the second active layer ACL2. The upper channel pattern UCH and the upper source / drain pattern USD may constitute an upper active region UAR as an upper layer of a three-dimensional device.

[0143] A second interlayer insulating layer 120 may be formed to cover the upper source / drain pattern USD. As an example, an etch stop layer may be further formed to conformally cover the upper source / drain pattern USD before forming the second interlayer insulating layer 120.

[0144] Thereafter, the second interlayer insulating layer 120 may be planarized until the upper surface of the sacrificial pattern PP is exposed. During the planarization process, all hard mask patterns MP on the sacrificial pattern PP may be removed.

[0145] Refer to Figure 3 and Figures 14A to 14C , the exposed sacrificial pattern PP may be selectively removed. By removing the sacrificial pattern PP, the first sacrificial layer SAL1 and the second sacrificial layer SAL2 may be exposed.

[0146] When removing, an etching process may be performed while maintaining the first semiconductor pattern SP1 to the fourth semiconductor pattern SP4 and the dummy channel pattern DSP intact to selectively etch the first sacrificial layer SAL1 and the second sacrificial layer SAL2.

[0147] The gate insulating layer GI can be conformally formed in the regions where the sacrificial pattern PP, the first sacrificial layer SAL1, and the second sacrificial layer SAL2 have been removed. The gate electrode GE can be formed on the gate insulating layer GI. The gate electrode GE can include first to fifth inner electrodes PO1 to PO5 between the first to fourth semiconductor patterns SP1 to SP4, and an outer electrode PO6 in the region where the sacrificial pattern PP has been removed.

[0148] A gate covering pattern GP can be formed to cover the upper surface of the outer electrode PO6 of the gate electrode GE. A third interlayer insulating layer 130 can be formed to cover the gate covering pattern GP and the second interlayer insulating layer 120.

[0149] A first isolation trench STR1 can be formed to intersect the gate electrode GE in the second direction D2. Accordingly, the gate electrode GE extending in the first direction D1 can be separated into gate electrodes GE spaced apart from each other in the first direction D1. The first isolation trench STR1 can be formed to extend to a level lower than the bottom surface STb of the device isolation layer ST. Correspondingly, the bottom surface STR1b of the first isolation trench STR1 can be located at a level lower than the bottom surface STb of the device isolation layer ST.

[0150] A liner insulating layer LN and a conductive plate layer CL can be formed to sequentially cover the sidewalls of the first isolation trench STR1 and the upper surface of the third interlayer insulating layer 130. Thereafter, a first filling pattern FL1 can be formed to fill the remaining portion of the first isolation trench STR1 and cover the upper surface of the third interlayer insulating layer 130. As an example, although not shown in the drawings, when the first filling pattern FL1 is formed, an air gap AG described with reference to Figure 10 may be formed in the first filling pattern FL1.

[0151] With reference to Figure 3 、 Figure 15A and Figure 15B , a planarization process can be performed on the liner insulating layer LN, the conductive plate layer CL, and the first filling pattern FL1. Accordingly, the liner insulating layer LN, the conductive plate layer CL, and the first filling pattern FL1 can be separated into a plurality of liner insulating layers LN, a plurality of conductive plates CP, and a plurality of first filling patterns FL1 adjacent to each other in the first direction D1 and each extending in the second direction D2. In each of the first isolation trenches STR1, a part of the liner insulating layer LN and a part of the first filling pattern FL1 can constitute the first isolation insulating pattern SI1 (in the final product).

[0152] Although not shown in the drawings, ( Figure 3 、 Figure 4 、 Figures 5A to 5EA second isolation trench STR2 (in the above) intersects the gate electrode GE in the second direction D2. Thus, the gate electrode GE extending in the first direction D1 can be separated into gate electrodes GE spaced apart from each other in the first direction D1. Thereafter, a second isolation insulating pattern SI2 can be formed to fill the second isolation trench STR2. Although the second isolation trench STR2 is shown as being formed by an additional process from the first isolation trench STR1, the inventive concept is not limited thereto. As another example, the first isolation trench STR1 and the second isolation trench STR2 can be formed simultaneously.

[0153] A second filling pattern FL2 can be formed in the conductive separation region CS.

[0154] Again, referring to Figure 3 、 Figure 4 、 Figures 5A to 5E ,the upper active contact UAC can be formed to pass through the second interlayer insulating layer 120 and the third interlayer insulating layer 130 and be connected to the upper source-drain pattern USD, respectively. An upper gate contact UGC can be formed to penetrate the second interlayer insulating layer 120 and the third interlayer insulating layer 130 and be electrically connected to the gate electrode GE.

[0155] A fourth interlayer insulating layer 140 can be formed on the third interlayer insulating layer 130. A first metal layer M1 including an upper interconnect UMI can be formed in the fourth interlayer insulating layer 140. An upper via UVI can be formed to electrically connect the first metal layer M1 to the gate contact GC and the upper active contact UAC. A BEOL layer including additional metal layers (e.g., M2, M3, M4, etc.) can be formed on the first metal layer M1. As an example, the first upper contact UCa can be formed to extend from the upper surface of the upper active contact UAC to the upper surface of the conductive plate CP. As an example, a second upper contact UCb can be formed on the upper surface of the conductive plate CP.

[0156] Thereafter, although not shown in the drawings, the semiconductor substrate 105 can be flipped so that the back surface of the semiconductor substrate 105 is exposed. The exposed semiconductor substrate 105 can be selectively removed. As a result, the sacrificial contact pattern PLH and the first lower insulating layer LIL1 can be exposed. In one embodiment, during the selective removal of the semiconductor substrate 105, the lower part of the conductive plate CP can also be removed, and the conductive plate CP can be separated into a first conductive plate CP1 and a second conductive plate CP2 adjacent to each other in the first direction D1. Similarly, a single liner insulating layer LN conformally covering the sidewalls of the first isolation trench STR1 can be separated into a pair of liner insulating layers LN adjacent to each other in the first direction D1.

[0157] A removal process may be performed on a part of the conductive plate CP and a part of the first separation insulating pattern SI1, thereby forming a conductive separation region CS in the first separation insulating pattern SI1.

[0158] The conductive plates CP1 and CP2 may form different electrical nodes and are not electrically connected to each other (at least not directly electrically connected such that they will each form a single electrical node). The conductive plates CP1 and CP2 may be electrically isolated from each other such that they may carry different electrical signals from each other.

[0159] According to an embodiment of the inventive concept, the conductive plate CP may be formed to conformally cover the first separation trench STR1 on the interlayer insulating layer LN. Without an additional lithography process, the preliminary conductive plate layer CL (and the conductive plate CP) may be separated into a plurality of conductive plates CP. Accordingly, the conductive plate CP may be easily formed and confined in the first separation trench STR1 without misalignment. Accordingly, the conductive plate CP may not make an undesired contact (e.g., an electrical short) with any adjacent component including a conductive material. In addition, since a lithography process is not involved, an additional mask manufactured according to the lithography process may not be required. Accordingly, the productivity of the three-dimensional semiconductor device may be increased.

[0160] In addition, the conductive plate CP may be formed to conformally cover the first separation trench STR1 on the interlayer insulating layer LN, and thus a seam or void may not be formed in the conductive plate CP. Accordingly, the resistance of the conductive plate CP may be reduced. As a result, the electrical characteristics of the three-dimensional semiconductor device may be improved.

[0161] A second lower insulating layer LIL2 may be formed on the exposed sacrificial contact pattern PLH and the exposed first lower insulating layer LIL1. A planarization process may be performed on the second lower insulating layer LIL2 until the sacrificial contact pattern PLH is exposed.

[0162] The sacrificial contact pattern PLH may be replaced with a lower active contact LAC. Specifically, the sacrificial contact pattern PLH may be selectively removed. An etching process may be further performed on the sacrificial contact pattern PLH from the region where it is removed to expose the lower source / drain pattern LSD. A lower active contact LAC connected to the exposed lower source / drain pattern LSD may be formed. The lower active contact LAC may be formed in a self-aligned manner using the sacrificial contact pattern PLH. A lower gate contact LGC penetrating the first lower insulating layer LIL1 and electrically connected to the gate electrode GE may be formed.

[0163] A backside metal layer BSM may be formed on the lower active contact LAC. The backside metal layer BSM may include a lower contact LC, a lower interconnect LMI, and a lower via LVI. An additional backside metal layer may be formed on the backside metal layer BSM. In one embodiment of the invention, the additional backside metal layer may include a power transmission network.

[0164] Figure 16 and Figure 17 are cross-sectional views for explaining a method of manufacturing a three-dimensional semiconductor device according to an embodiment of the inventive concept. More specifically, Figure 16 and Figure 17 are each a cross-sectional view taken along line B-B' of Figure 3 .

[0165] First, referring to Figure 3 and Figure 16 , during the formation of the first isolation trench STR1 described with reference to Figures 14A to 14C , the first isolation trench STR1 may be formed to extend to a level substantially the same as the lowermost surface STb of the device isolation layer ST. Accordingly, the lowermost end STR1b of the first isolation trench STR1 may be located at a level substantially the same as the lowermost surface STb of the device isolation layer ST.

[0166] Thereafter, a three-dimensional semiconductor device described with reference to Figure 3 , Figure 4 , Figures 5A to 5E may be formed using a semiconductor device manufacturing method the same as or similar to the semiconductor device manufacturing method described above.

[0167] Referring to Figure 3 and Figure 17 , during the formation of the first isolation trench STR1 described with reference to Figures 14A to 14C , the first isolation trench STR1 may be formed to extend to a level higher than the lowermost surface STb of the device isolation layer ST. Specifically, the lowermost end STR1b of the first isolation trench STR1 may be formed to be located between the upper surface and the lower surface of the sacrificial contact pattern PLH. Accordingly, the lowermost end STR1b of the first isolation trench STR1 may be located at a level higher than the lowermost surface STb of the device isolation layer ST.

[0168] Thereafter, a three-dimensional semiconductor device described with reference to Figure 3 , Figure 4 , Figures 5A to 5E may be formed using a semiconductor device manufacturing method the same as or similar to the semiconductor device manufacturing method described above.

[0169] According to an embodiment of the inventive concept, a first conductive plate and a second conductive plate adjacent to each other in a first direction may be disposed in a first isolation trench. Accordingly, source / drain patterns and adjacent components (e.g., a backside metal layer and a first metal layer) of each of two single-height units may be electrically connected to at least one of two conductive plates disposed in one isolation trench. As a result, the integration degree and design freedom of the three-dimensional semiconductor device may be improved.

[0170] According to the inventive concept, the conductive plate may be formed to conformally cover the first isolation trench on the interlayer insulating layer. Accordingly, the conductive plate may be easily formed in the first isolation trench without misalignment. As a result, the conductive plate may not be electrically short-circuited with an adjacent component including a conductive material undesirably. Accordingly, the productivity of the three-dimensional semiconductor device may be improved.

[0171] Although the embodiments have been described above, those skilled in the art will appreciate that many modifications and variations can be made without departing from the spirit and scope of the inventive concept defined in the appended claims. Accordingly, the exemplary embodiments of the inventive concept should be considered illustrative rather than restrictive in all respects, and the spirit and scope of the inventive concept are indicated by the appended claims.

Claims

1. A three-dimensional semiconductor device, comprising: A backside metal layer; A first lower channel pattern and a first upper channel pattern, sequentially disposed on the backside metal layer; A first gate electrode, intersecting the first lower channel pattern and the first upper channel pattern; A second gate electrode, adjacent to the first gate electrode in a first direction; An isolation insulating pattern, between the first gate electrode and the second gate electrode; A first conductive plate, extending in the isolation insulating pattern in each of a second direction and a third direction; And A second conductive plate, extending in the isolation insulating pattern in each of the second direction and the third direction, the second conductive plate being adjacent to the first conductive plate in the first direction, Wherein the first conductive plate and the second conductive plate are electrically separated from each other.

2. The three-dimensional semiconductor device according to claim 1, wherein, The width of the first conductive plate in the first direction is the same along the third direction.

3. The three-dimensional semiconductor device according to claim 1, wherein, The distance between the first conductive plate and the second conductive plate decreases for a downward direction.

4. The three-dimensional semiconductor device according to claim 1, wherein, When observed in a cross-sectional view, the first conductive plate and the second conductive plate are symmetric with respect to each other.

5. The three-dimensional semiconductor device according to claim 1, wherein, The isolation insulating pattern includes: an air gap, between the first conductive plate and the second conductive plate.

6. The three-dimensional semiconductor device according to claim 1, wherein, The isolation insulating pattern includes: A first liner insulating layer, between the first gate electrode and the first conductive plate, A second liner insulating layer, between the second gate electrode and the second conductive plate, and A filling pattern, between the first conductive plate and the second conductive plate.

7. The three-dimensional semiconductor device according to claim 1, wherein, The first conductive plate includes a recessed area on at least one of its upper and lower portions.

8. The three-dimensional semiconductor device according to claim 1, further comprising: A third conductive plate and a fourth conductive plate, Wherein: The third conductive plate is spaced apart from the first conductive plate in the second direction, The fourth conductive plate is spaced apart from the second conductive plate in the second direction, and The first conductive plate, the second conductive plate, the third conductive plate, and the fourth conductive plate are electrically separated from each other.

9. The three-dimensional semiconductor device according to claim 1 further comprises: A second isolation insulating pattern, wherein: The isolation insulating pattern is a first isolation insulating pattern, The first isolation insulating pattern and the second isolation insulating pattern are adjacent to each other in the first direction, The first conductive plate is disposed in the first isolation insulating pattern.

10. The three-dimensional semiconductor device according to claim 9, wherein, In the first direction, the width of the upper surface of the second isolation insulating pattern is smaller than the width of the upper surface of the first isolation insulating pattern.

11. The three-dimensional semiconductor device according to claim 1, further comprising: A first lower source / drain pattern and a second lower source / drain pattern, spaced apart from each other in the second direction; And A first upper source / drain pattern on the first lower source / drain pattern and a second upper source / drain pattern on the second lower source / drain pattern, Wherein: The first lower channel pattern is disposed between the first lower source / drain pattern and the second lower source / drain pattern, and The first conductive plate is electrically connected to one of the first lower source / drain pattern, the second lower source / drain pattern, the first upper source / drain pattern, and the second upper source / drain pattern.

12. A three-dimensional semiconductor device, comprising: A backside metal layer; A first lower channel pattern and a first upper channel pattern, sequentially disposed on the backside metal layer; A second lower channel pattern and a second upper channel pattern, sequentially disposed on the backside metal layer; A first gate electrode, intersecting the first lower channel pattern and the first upper channel pattern; A second gate electrode, intersecting the second lower channel pattern and the second upper channel pattern, the second gate electrode being adjacent to the first gate electrode in the first direction; An isolation insulating pattern, between the first gate electrode and the second gate electrode; A first conductive plate extends in a separated insulating pattern in each of a second direction and a third direction, and the first conductive plate is adjacent to a first gate electrode; And A second conductive plate extends in a separated insulating pattern in each of a second direction and a third direction, and the second conductive plate is adjacent to a second gate electrode, Wherein: The first conductive plate and the second conductive plate are separated from each other, and The first direction, the second direction, and the third direction are perpendicular to each other.

13. The three-dimensional semiconductor device according to claim 12, wherein, The first conductive plate and the second conductive plate are adjacent to each other in the first direction.

14. The three-dimensional semiconductor device according to claim 12, wherein, The distance between the first conductive plate and the second conductive plate decreases for a downward direction.

15. The three-dimensional semiconductor device according to claim 12, wherein, The width of the first conductive plate in the first direction is the same along the third direction.

16. The three-dimensional semiconductor device according to claim 12, wherein, When observed in a cross-sectional view, the first conductive plate and the second conductive plate are symmetric with respect to each other.

17. The three-dimensional semiconductor device according to claim 12, wherein, The distance between the first conductive plate and the first gate electrode in the first direction is the same along the third direction.

18. A three-dimensional semiconductor device, comprising: A backside metal layer; A first lower channel pattern and a first upper channel pattern, sequentially disposed on the backside metal layer; A second lower channel pattern and a second upper channel pattern, sequentially disposed on the backside metal layer; A first gate electrode intersecting the first lower channel pattern and the first upper channel pattern; A second gate electrode intersecting the second lower channel pattern and the second upper channel pattern, and the second gate electrode is adjacent to the first gate electrode in a first direction; A separated insulating pattern between the first gate electrode and the second gate electrode; A first conductive plate extending in the separated insulating pattern in each of a second direction and a third direction; And A second conductive plate extending in the separated insulating pattern in each of a second direction and a third direction, and the second conductive plate is adjacent to the first conductive plate in a first direction, Wherein: The first conductive plate and the second conductive plate are separated from each other, and The first direction, the second direction, and the third direction are perpendicular to each other.

19. The three-dimensional semiconductor device according to claim 18, wherein, The width of the first conductive plate in the first direction is the same along the third direction.

20. The three-dimensional semiconductor device according to claim 18, wherein, The distance between the first conductive plate and the second conductive plate decreases for a downward direction.

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