Semiconductor device including plug electrode with nanorods and method of manufacturing the same

Abstract

The invention relates to a semiconductor device including a plug electrode with nanorods and a method of manufacturing the same. A semiconductor device according to an embodiment of the present disclosure includes a lower electrode, a plug electrode disposed over the lower electrode and including a plurality of conductive nanorods, a resistance change layer disposed over the plug electrode, and an upper electrode disposed over the resistance change layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Application No. 10 - 2024 - 0009058, filed on January 19, 2024, which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure generally relates to a semiconductor device including a plug electrode, and more particularly, to a semiconductor device including a plug electrode having a plurality of nanorods and a method of manufacturing the same. Background art

[0004] Generally, a resistive - change material is a material whose resistance changes when an external stimulus such as heat, current, voltage, light, etc. is applied. Even after the external stimulus is removed, the resistive - change material can maintain the changed resistance. A resistive - change memory device utilizes the electrical characteristics of the above - mentioned resistive - change material to store signal information. The resistive - change memory device can switch the resistance state of the resistive - change material between a low - resistance state and a high - resistance state through a set operation and a reset operation.

[0005] According to the basis of the switching operation, resistive - change memory devices can be classified into resistive RAM devices, phase - change RAM devices, magnetic RAM devices, etc. In a resistive - change memory device, a resistive RAM device can be implemented by applying a voltage or current across both ends of a resistive - change layer and generating or removing an electric conduction path having a varying conductivity within the resistive - change layer to achieve multiple different resistance states. Summary of the invention

[0006] A semiconductor device according to an embodiment of the present disclosure may include: a lower electrode; a plug electrode disposed above the lower electrode and including a plurality of conductive nanorods; a resistive - change layer disposed above the plug electrode; and an upper electrode disposed above the resistive - change layer.

[0007] A method of manufacturing a semiconductor device is disclosed. In this method, a lower electrode may be formed on a substrate. An interlayer insulating layer including a hole pattern may be formed above the lower electrode. A plug electrode including a plurality of conductive nanorods and a non - conductive mold layer surrounding the plurality of conductive nanorods may be formed in the hole pattern. A resistive - change material layer and an upper - electrode material layer may be sequentially formed above the interlayer insulating layer including the plug electrode. The resistive - change material layer and the upper - electrode material layer may be patterned above the interlayer insulating layer to form a resistive - change layer and an upper electrode covering the plug electrode. Brief description of the drawings

[0008] Figure 1 is a cross - sectional view schematically showing a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 is a diagram showing the plug electrodes cut along line I-I' and displayed in the x-y plane. Figure 1

[0010] Figure 3 is a diagram showing the contact surface between the plug electrodes cut along line II-II' and the resistance change layer and displayed in the x-y plane. Figure 1

[0011] Figure 4 and Figure 5 is a diagram schematically showing an operation method of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 6 is a diagram schematically showing a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.

[0013] Figure 7A is a diagram schematically showing a cross-sectional view of a semiconductor device according to still another embodiment of the present disclosure.

[0014] Figure 7B is a diagram showing the plug electrodes cut along line III-III' and displayed in the x-y plane. Figure 7A

[0015] Figures 8 to 15 is a diagram schematically showing a cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 16 , Figure 17A , Figure 17B , Figure 18 and Figure 19 is a diagram schematically showing a cross-sectional view of a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. Detailed Description of the Embodiments

[0017] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, the dimensions (e.g., the width and thickness of the components) of the components are enlarged in order to clearly show each component. The terms used herein may correspond to words selected considering their functions in the embodiments, and according to those of ordinary skill in the art to which the embodiments belong, the meanings of these terms may be interpreted differently. If clearly and specifically defined, the terms may be interpreted according to the definition. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as those commonly understood by those of ordinary skill in the art to which the embodiments belong.

[0018] In addition, unless otherwise explicitly used in the context, the expression of the singular form of a word shall be understood to include the plural form of the word. It should be understood that the terms "comprising", "including" and "having" are intended to specify the presence of features, numbers, steps, operations, components, elements, parts or combinations thereof, but are not used to exclude the presence or possibility of adding one or more other features, numbers, steps, operations, components, elements, parts or combinations thereof.

[0019] The terms used in the specification of this application are terms selected in consideration of the functions in the presented embodiments, and the meanings of the terms may vary according to the intentions or habits of users or operators in the technical field. The meanings of the terms used follow the definitions defined when specifically defined in this article, and can be interpreted as the meanings generally recognized by those skilled in the art in the absence of specific definitions.

[0020] Embodiments of the present disclosure can be described by drawings using an x-y-z coordinate system. The x direction mentioned in this specification can represent a direction parallel to the x-axis. Similarly, the y direction and the z direction can respectively refer to directions parallel to the y-axis and the z-axis.

[0021] In addition, when describing a method or a manufacturing method, unless a specific order is clearly described in the context, each process constituting the method can be carried out in an order different from the specified order. That is, each process can be carried out in the same order as the specified order, can be carried out substantially simultaneously, or can be carried out in the reverse order.

[0022] Figure 1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment of the present disclosure. Figure 2 shows the plug electrode cut along line I-I' Figure 1 and shown in the x-y plane. Figure 3 shows the contact surface between the plug electrode 140 and the resistance change layer cut along line II-II' Figure 1 and shown in the x-y plane.

[0023] Referring to Figures 1 to 3 , the semiconductor device 1 may include a lower electrode 120, a plug electrode 140 disposed above the lower electrode 120, a resistance change layer 150 disposed above the plug electrode 140, an oxygen vacancy storage part 160 disposed above the resistance change layer 150, and an upper electrode 170 disposed above the oxygen vacancy storage part 160.

[0024] In an embodiment, the semiconductor device 1 may be a resistive RAM device, where the resistance state inside the resistance change layer 150 may reversibly change according to the magnitude or polarity of the voltage applied between the lower electrode 120 and the upper electrode 170. When the resistance state changes, after removing the applied voltage, the resistance change layer 150 may store the changed resistance state in a non-volatile manner. The semiconductor device 1 may have multiple different and measurable resistance states, and may also store multi-level signal information corresponding to the multiple resistance states.

[0025] Refer to Figure 1 , a substrate 101 may be provided. The substrate 101 may be made of various materials as long as the materials meet the conditions for performing semiconductor integration processes. The substrate 101 may include semiconductors, insulators, or conductors. The substrate 101 may include an integrated circuit (not shown). The integrated circuit may be a circuit for driving or controlling the semiconductor device 1. As an example, the integrated circuit may include multiple field effect transistors.

[0026] A first interlayer insulating layer 110 may be provided on the substrate 101. In Figure 1 this case, the first interlayer insulating layer 110 may electrically insulate the lower electrode 120 on the first interlayer insulating layer 110 from the substrate 101. The first interlayer insulating layer 110 may include, for example, oxides, nitrides, oxynitrides, or a combination of two or more of them.

[0027] The lower electrode 120 may be provided on the first interlayer insulating layer 110. The lower electrode 120 may include at least one layer of conductive material. For example, the conductive material layer may include doped semiconductor materials, metals, metal nitrides, metal carbides, metal silicides, or metal oxides. As an example, the conductive material layer may include n-type doped silicon (Si), platinum (Pt), gold (Au), palladium (Pd), molybdenum (Mo), nickel (Ni), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more of them. As an example, the lower electrode 120 may be a linear pattern layer extending in one direction.

[0028] In some embodiments, at least one conductive layer may be provided between the substrate 101 and the lower electrode 120. The conductive layer may be used as an interconnect for electrically connecting multiple integrated circuits of the substrate 101 to each other, or for electrically connecting the integrated circuit and the lower electrode 120 to each other. The conductive layer may be provided in, on, or under the first interlayer insulating layer 110.

[0029] The second interlayer insulating layer 130 may be disposed on the lower electrode 120. The second interlayer insulating layer 130 may include an insulating material. The insulating material may include, for example, silicon oxide, silicon nitride, silicon oxynitride, metal nitride, metal oxide, metal oxynitride, or a combination of two or more thereof. The second interlayer insulating layer 130 may be disposed to surround the plug electrode 140.

[0030] The plug electrode 140 may be disposed in the second interlayer insulating layer 130. The plug electrode 140 may include a plurality of conductive nanorods 142 and a non-conductive mold layer 144 surrounding the plurality of nanorods 142. The plurality of conductive nanorods 142 may be physically separated from each other.

[0031] In an embodiment, each of the plurality of conductive nanorods 142 may extend in a first direction (e.g., the z direction) perpendicular to the surface 120S of the lower electrode 120. Each of the plurality of conductive nanorods 142 may contact the lower electrode 120 and the resistive change layer 150. As Figure 1 shown, each of the plurality of conductive nanorods 142 may have a columnar shape having a predetermined width D and a predetermined height H1. As Figure 2 and Figure 3 shown, each of the plurality of conductive nanorods 142 may have a circular cross-section with a diameter of a predetermined width D10. In some embodiments, each of the plurality of conductive nanorods 142 may have an elliptical or polygonal cross-section having a predetermined width D10 in the major axis direction. As an example, the predetermined width D10 may be from 1 nanometer (nm) to 5 nm.

[0032] Reference Figures 1 to 3 , the plurality of conductive nanorods 142 may be disposed spaced apart from each other in a second direction (e.g., the x direction or the y direction) perpendicular to the first direction. The plurality of conductive nanorods 142 may be arranged at regular intervals in the second direction. As an example, each of the plurality of conductive nanorods 142 may be spaced apart by a pitch d1 of 1 nm to 50 nm. Here, the pitch d1 of the conductive nanorods 142 may represent the distance between the centers O of different adjacent conductive nanorods 142. As another example, the pitch d1 may be a multiple of the nanorod size, such as 1 to 10 times the predetermined width D10.

[0033] Each of the plurality of conductive nanorods 142 may include a conductive material. The conductive material may include, for example, a doped semiconductor material, a metal, a metal nitride, a metal carbide, a metal silicide, or a metal oxide. For example, the conductive material may include n-type doped silicon (Si), platinum (Pt), gold (Au), palladium (Pd), molybdenum (Mo), nickel (Ni), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

[0034] The non-conductive mold layer 144 may include a polymer material. The non-conductive mold layer 144 may electrically insulate the plurality of conductive nanorods 142 from each other. In an embodiment, the non-conductive mold layer 144 may be formed from one of different polymer blocks ( Figure 10 1400 in) that phase-separate from the block copolymer film ( Figure 10 1401 and 1402 in) as described in connection with Figure 10 and Figure 11 the manufacturing methods described below.

[0035] Referring again to Figure 1 , the resistive change layer 150 may be disposed on the second interlayer insulating layer 130 and the plug electrode 140. The resistive change layer 150 may include a resistive change material whose resistive state changes according to the application of an external voltage. For example, the resistive change material may include a metal oxide such as titanium oxide, aluminum oxide, nickel oxide, copper oxide, zirconium oxide, manganese oxide, hafnium oxide, tungsten oxide, tantalum oxide, niobium oxide, and iron oxide. The metal oxide may include oxygen vacancies.

[0036] In an embodiment, as will be described later with reference to Figure 4 and Figure 5 , the resistive change layer 150 may include a plurality of conductive filaments ( Figure 4 and Figure 5 155 in) generated internally by applying an external voltage. Each of the plurality of conductive filaments 155 may be connected to a corresponding one of the plurality of conductive nanorods 142. The plurality of conductive filaments 155 may include oxygen vacancies. As described above, the width of the plurality of conductive filaments 155 can be controlled by controlling the width D10 of the plurality of conductive nanorods 142.

[0037] Referring to Figure 1 and Figure 3 , the plug electrode 140 and the resistive change layer 150 may be disposed in contact with each other. As Figure 3As shown, in the plane 140I where the interface between the plug electrode 140 and the resistive change layer 150 is located, the cross-sectional area S1 of the plug electrode 140 can be located within the cross-sectional area S2 of the resistive change layer 150. That is to say, in the plane 140I, the entire cross-sectional area S1 of the plug electrode 140 can overlap with a part of the cross-sectional area S2 of the resistive change layer 150. Therefore, in the plane 140I, the area of the cross-sectional area S1 of the plug electrode 140 can be smaller than the area of the cross-sectional area S2 of the resistive change layer 150. In addition, in the plane 140I where the interface between the plug electrode 140 and the resistive change layer 150 is located, the cross-sectional areas of the plurality of conductive nanorods 142 can be located within the cross-sectional area S2 of the resistive change layer 150.

[0038] In an embodiment, in the plane 140I where the interface between the plug electrode 140 and the resistive change layer 150 is located, the pattern edge 140E of the plug electrode 140 can be separated from the adjacent pattern edge 150E of the resistive change layer 150 by a predetermined distance. As an example, the spacing distance d2 between the pattern edges 140E and 150E can be 5 nm or greater. Therefore, the plurality of conductive nanorods 142 far from the pattern edge 140E can be located at a distance of 5 nm or greater from the adjacent pattern edge 150E of the resistive change layer 150.

[0039] As will be referred to Figure 14 As described, the region of the resistive change layer 150 located at a distance less than 5 nm from the pattern edge 150E of the resistive change layer 150 can correspond to the etching damage region ( Figure 14 150R in). When at least a part of the etching damage region 150R overlaps with the plug electrode 140 in the z direction, leakage current can flow through the etching damage region 150R between the plug electrode 140 and the upper electrode 170, which may reduce the electrical reliability of the semiconductor device. However, according to the embodiment of the present disclosure, the etching damage region 150R of the resistive change layer 150 and the plug electrode 140 do not overlap with each other in the z direction. Therefore, the leakage current characteristics of the semiconductor device 1 can be improved.

[0040] Referring again to Figure 1 , the oxygen vacancy storage part 160 can be provided on the resistive change layer 150. The oxygen vacancy storage part 160 can have conductivity. In an embodiment, the oxygen vacancy storage part 160 can include a metal that is highly reactive with oxygen. For example, the oxygen vacancy storage part 160 can include tantalum (Ta), titanium (Ti), or a combination thereof. For example, the oxygen vacancy storage part 160 can include, for example, tantalum nitride, titanium nitride, or a combination thereof.

[0041] When a set voltage is applied, the oxygen vacancy storage unit 160 can receive oxygen ions from the resistive change layer 150, thereby generating oxygen vacancies in the resistive change layer 150. As will be described later, the oxygen vacancies generated inside the resistive change layer 150 can be arranged along the electric field formed by the set voltage, thereby forming a conductive filament.

[0042] See Figure 1 , the upper electrode 170 can be disposed on the oxygen vacancy storage unit 160. The upper electrode 170 can include at least one layer of conductive material. For example, the conductive material layer can include a doped semiconductor material, a metal, a metal nitride, a metal carbide, a metal silicide, or a metal oxide. As an example, the conductive material layer can include n-type doped silicon (Si), platinum (Pt), gold (Au), palladium (Pd), molybdenum (Mo), nickel (Ni), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

[0043] Refer to Figure 1 , the spacer 180 can be disposed on the sidewalls of the resistive change layer 150, the oxygen vacancy storage unit 160, and the upper electrode 170 and above the second interlayer insulating layer 130. The spacer 180 can be used as a barrier layer, which electrically insulates the resistive change layer 150, the oxygen vacancy storage unit 160, and the upper electrode 170 laterally and protects the resistive change layer 150, the oxygen vacancy storage unit 160, and the upper electrode 170 from material diffusion. The spacer 180 can include an insulating material, such as an oxide, a nitride, a nitrogen oxide, or a combination of two or more thereof.

[0044] As described above, the semiconductor device according to an embodiment of the present disclosure can include a plug electrode, which includes a plurality of nanorods physically separated from each other. The width of each of the plurality of conductive nanorods can be controlled. By controlling the width of each conductive nanorod, the width of each conductive filament generated in the resistive change layer and connected to the conductive nanorod can be controlled. In this way, as will be referred to later Figure 4 and Figure 5 described, the reliability of the write operation for storing signal information using a plurality of conductive filaments can be improved.

[0045] In the semiconductor device according to an embodiment of the present disclosure, in the plane where the interface between the plug electrode 140 and the resistive change layer 150 is located, the cross-sectional area of the plug electrode can be located within the cross-sectional area of the resistive change layer. In this way, the plug electrode can be arranged so as not to overlap with the etching damage area in the pattern edge of the resistive change layer 150. As a result, leakage current can be prevented from passing through the etching damage area.

[0046] Figure 4 andFigure 5 is a diagram schematically showing an operation method of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 1 described above with reference to Figures 1 to 3 can be used to describe Figure 4 and Figure 5 a method of operating the semiconductor device. In an embodiment, the semiconductor device 1 may be a resistive RAM device, and its resistance state depends on whether a conductive filament is formed in the resistance change layer 150.

[0047] Figure 4 is a diagram schematically showing a set operation, in which the resistance state of the resistance change layer 150 is switched from a high resistance state to a low resistance state. Figure 5 is a diagram schematically showing a reset operation, in which the resistance state of the resistance change layer 150 is switched from a low resistance state to a high resistance state.

[0048] Referring to Figure 4 , a set voltage can be applied between the lower electrode 120 and the upper electrode 170. The method of applying the set voltage may include applying a bias with a positive polarity to the upper electrode 170 and applying a bias with a negative polarity or a ground bias to the lower electrode 120.

[0049] By applying the set voltage, oxygen vacancies can be provided from the oxygen vacancy storage part 160 to the resistance change layer 150. Therefore, the concentration of oxygen vacancies can increase from the region of the resistance change layer 150 adjacent to the oxygen vacancy storage part 160 to the inner region of the resistance change layer 150. Subsequently, as the oxygen vacancies are aligned along the electric field formed by the set voltage, a plurality of conductive filaments 155 can grow from the interface between the oxygen vacancy storage part 160 and the resistance change layer 150 into the resistance change layer 150. The plurality of grown conductive filaments 155 can electrically connect the plug electrode 140 to the oxygen vacancy storage part 160, so that the resistance state of the resistance change layer 150 can be changed from a high resistance state to a low resistance state.

[0050] Referring to Figure 4, when the plug electrode 140 includes a plurality of conductive nanorods 142 that are electrically isolated from each other, a plurality of conductive filaments 155 can be respectively connected to the plurality of conductive nanorods 142. As an example, when a set voltage is applied, the electric field can be concentrated on the plurality of conductive nanorods 142 rather than on the non-conductive mold layer 144 in the plug electrode 140. Therefore, the conductive filaments 155 grown in the resistive change layer 150 can be connected to the conductive nanorods 142 in a one-to-one correspondence. At the same time, the electric field is not concentrated on the non-conductive mold layer 144 within the plug electrode 140. Therefore, the conductive filaments 155 may not be connected to the non-conductive mold layer 144, and the growth of the conductive filaments 155 in the lateral direction (e.g., the x-direction or the y-direction) after being connected to the conductive nanorods 142 can be restricted or inhibited. As a result, each of the conductive filaments 155 respectively connected to the conductive nanorods 142 can have a controlled width.

[0051] In addition, the number of the conductive filaments 155 connected to the conductive nanorods 142 can vary according to the magnitude of the set voltage. As an example, as the magnitude of the set voltage increases, the number of the conductive filaments 155 connected to the conductive nanorods 142 can increase. The resistance of the resistive change layer 150 can linearly decrease in proportion to the number of the conductive filaments 155 connected to the conductive nanorods 142. Therefore, by controlling the magnitude of the set voltage, a plurality of resistance states of the resistive change layer 150 can be linearly controlled.

[0052] In Figure 4 , the conductive filaments 155 are shown as being respectively connected to all of the plurality of conductive nanorods 142, but the present disclosure is not necessarily limited thereto. In some embodiments, the conductive filaments 155 can be connected to some of all of the plurality of conductive nanorods 142, and the conductive filaments 155 can be not connected to other conductive nanorods 142. Although not all of the conductive nanorods 142 are connected to the conductive filaments 155, the connected conductive nanorods are connected in a one-to-one correspondence.

[0053] In an embodiment, and with reference to Figure 2 and Figure 3 , at the contact portion between the conductive nanorods 142 and the conductive filaments 155, the width of the conductive filaments 155 can be less than 1 / 2 of the spacing d1 between the conductive nanorods 142. Therefore, it is possible to prevent the conductive filaments 155 respectively connected to adjacent conductive nanorods 142 from coming into contact with each other laterally.

[0054] In an embodiment, the width or cross-sectional area of the conductive filaments 155 can be equal to or less than the width D10 or the cross-sectional area π*(D10 / 2) of the conductive nanorods 142 2 (see Figure 1 and Figure 2)。In another embodiment, at the contact portion, the width or cross-sectional area of the conductive wire 155 may be greater than the width D10 or the cross-sectional area π*(D10 / 2) of the conductive nanorod 142 2 。However, even in this case, the width of the conductive wire 155 may be less than 1 / 2 of the pitch d1 between the conductive nanorods 142 to avoid lateral contact.

[0055] As described above, according to an embodiment of the present invention, the plug electrode 140 may include a plurality of mutually separated conductive nanorods 142, and conductive wires 155 respectively connected to the plurality of conductive nanorods 142 may be generated. The number of conductive wires 155 respectively connected to the plurality of conductive nanorods 142 may be controlled by controlling the magnitude of the set voltage. Therefore, the resistance state of the resistive change layer 150 may be controlled in linear proportion to the number of conductive wires 155 connected to the conductive nanorods 142.

[0056] In addition, in an embodiment of the present disclosure, since the plug electrode 140 includes a plurality of mutually separated conductive nanorods 142, when a set voltage is applied, the electric field may be concentrated on the plurality of conductive nanorods 142 of the plug electrode 140. Therefore, compared with the conventional case where the plug electrode 140 includes a single electrode pattern that is not mutually separated, filament formation may start at a relatively low set voltage, and conductive wires 155 having a relatively small width may be generated. Since filament formation starts at a relatively low set voltage, the width of the conductive wire 155 may be easily adjusted according to the applied set voltage. Therefore, the number of resistance states that can be achieved may increase in proportion to the variation range of the width of the conductive wire 155. In addition, a higher resistance state may be generated by forming a smaller number of conductive wires 155 by adjusting the set voltage. Therefore, multi-level signals can be effectively achieved using a plurality of mutually separated conductive wires 155. In addition, even if some of the plurality of conductive wires 155 are disconnected due to a failure during the set operation, the remaining conductive wires 155 are still connected to the conductive nanorods 142. Therefore, the number of set defects can be reduced compared with the conventional case of using a single or single electrode pattern.

[0057] Reference Figure 5 , a reset voltage may be applied between the lower electrode 120 and the upper electrode 170. As an example, the method of applying the reset voltage may be performed by applying a bias with a negative polarity to the upper electrode 170 and applying a bias with a positive polarity or a ground bias to the lower electrode 120.

[0058] Multiple conductive filaments 155 can be disconnected by a reset voltage. The reset voltage causes partial decomposition of the multiple conductive filaments 155 respectively and discharges oxygen vacancies from the conductive filaments 155 into the resistance change layer 150. In addition, the reset voltage can move the oxygen vacancies inside the resistance change layer 150 to the oxygen vacancy storage part 160. The disconnection of the multiple conductive filaments 155 can start or originate from the contact part between the conductive filaments 155 and the conductive nanorods 142.

[0059] As described above, compared with the conventional electrode, the resistance change layer 150 according to an embodiment of the present disclosure can include multiple conductive filaments 155, each conductive filament having a reduced width and arranged at a predetermined interval. Compared with the conventional case, each of the multiple conductive filaments 155 can have a reduced width, so that the conductive filaments can be disconnected with a relatively low reset voltage compared with the conventional case, while a higher voltage is required in the conventional case to disconnect a single conductive filament with a relatively large width. Therefore, the reliability of the reset operation of the semiconductor device 1 can be improved.

[0060] Figure 6 is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure. Compared with Figure 1 the semiconductor device 1, Figure 6 the semiconductor device 2 does not include an oxygen vacancy storage part.

[0061] Referring to Figure 6 , the oxygen vacancy storage part can be excluded, so that the upper electrode 270 can be directly disposed on the resistance change layer 150. The upper electrode 270 can also serve as an oxygen vacancy storage part. The upper electrode 270 can include a metal with strong reactivity with oxygen. For example, the upper electrode 270 can include tantalum (Ta), titanium (Ti), or a combination thereof. In an embodiment, the upper electrode 270 can include, for example, tantalum nitride, titanium nitride, or a combination thereof.

[0062] When a set voltage is applied to the upper electrode 270, an electric field is formed in the resistance change layer 150. As some oxygen ions in the resistance change layer 150 move to the upper electrode 270 due to the electric field, oxygen vacancies can be formed in the resistance change layer 150. The oxygen vacancies can be arranged to form conductive filaments along the electric field formed by the set voltage.

[0063] Figure 7A is a schematic cross-sectional view showing a semiconductor device according to still another embodiment of the present disclosure. Figure 7B is a view showing the plug electrode cut along line III-III' and displayed in the x-y plane of Figure 7A .

[0064] Referring to Figure 7A and Figure 7B , the semiconductor device 3 can have the same as Figure 1The plug electrode of the semiconductor device 1 has a different configuration compared to the plug electrode 240. The plug electrode 240 may include a plurality of conductive nanorods 242 and a non-conductive mold layer 244 surrounding the plurality of conductive nanorods 242. The configuration of the plurality of conductive nanorods 242 may be substantially the same as the configuration of the plurality of conductive nanorods 142 described above with reference to Figure 1 The non-conductive mold layer 244 may be a metal-organic framework layer.

[0065] In an embodiment, the metal-organic framework layer may be a thin film structure formed by sequentially stacking two-dimensional metal-organic frameworks each having a cavity V. The two-dimensional metal-organic framework may refer to a metal-organic framework having a single-layer structure in the form of a thin sheet with a thickness of several nanometers or less. As will be described later in connection with Figure 17A and 17B The plurality of two-dimensional metal-organic frameworks 2410a, 2410b, 2410c, and 2410d may be stacked in the z direction such that the cavities V of the plurality of two-dimensional metal-organic structures 2410a, 2410b, 2410c, and 2410d overlap each other. Therefore, Figure 17B The metal-organic framework layer 2410 shown in

[0066] See Figure 7A and Figure 7B The plurality of conductive nanorods 242 may be disposed in the channels formed by the cavities V of the metal-organic framework layer. Both the plurality of conductive nanorods 242 and the channels of the cavities V may extend in the z direction. The width D20 of each of the plurality of conductive nanorods 242 may be equal to or less than the width w1 of the cavity V. In an embodiment, the width w1 of the cavity V may be 10 nm to 100 nm. In an embodiment, the spacing w2 between the cavities V may be 1 / 10 to the width w1 of the cavity V.

[0067] As described above, according to an embodiment of the present disclosure, by adopting a metal-organic framework layer having channels with cavities V arranged at equal intervals, the plurality of conductive nanorods 242 included in the plug electrode 240 can be effectively realized, and the plurality of conductive nanorods 242 are respectively arranged within the cavities V.

[0068] Figures 8 to 15 is a cross-sectional view schematically showing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. In an embodiment, the method of manufacturing a semiconductor device may be applied to the method of manufacturing the semiconductor device 1 described above with reference to Figures 1 to 3 or the method of manufacturing the semiconductor device 2 described above with reference to Figure 6 The method described above.

[0069] See Figure 8, a substrate 101 can be provided. The substrate 101 can be made of various materials as long as the materials meet the conditions for performing semiconductor integration processes. The substrate 101 can include integrated circuits. The integrated circuits can be circuits for driving or controlling the semiconductor device 1.

[0070] A first interlayer insulating layer 110 can be formed on the substrate 101. The first interlayer insulating layer 110 can include, for example, oxides, nitrides, oxynitrides, or a combination of two or more of them. A lower electrode 120 can be formed on the first interlayer insulating layer 110. The lower electrode 120 can include at least one conductive material layer. The conductive material layer can include, for example, doped semiconductor materials, metals, metal nitrides, metal carbides, metal silicides, or metal oxides.

[0071] In some embodiments, at least one conductive layer can be provided between the substrate 101 and the lower electrode 120. The conductive layer can be used as an interconnect for electrically connecting a plurality of integrated circuits (not shown) of the substrate 101 or an interconnect for electrically connecting the integrated circuit and the lower electrode 120.

[0072] Next, an insulating material layer 1301 can be formed on the lower electrode 120. The insulating material layer 1301 can include, for example, oxides, nitrides, nitrogen oxides, or a combination of two or more of them.

[0073] Reference Figure 9 , the insulating material layer ( Figure 8 1301 therein) can be patterned to form a via pattern HP1. In an embodiment, the via pattern HP1 can expose the lower electrode 120. The via pattern HP1 can have a cross-sectional shape of a circle, an ellipse, or a polygon, but other embodiments are not limited to these examples. The insulating material layer 1301 can be patterned and converted into a second interlayer insulating layer 130 having the via pattern HP1.

[0074] Reference Figure 10 , a block copolymer layer 1400 can be formed to fill the via pattern HP1 and be disposed on the second interlayer insulating layer 130 outside the via pattern HP1. The block copolymer layer 1400 can include a polymer material in which a first polymer block and a second polymer block having different properties are linked by covalent bonds. As an example, one of the first polymer block and the second polymer block can exhibit hydrophilicity, while the other can exhibit hydrophobicity. As another example, one of the first polymer block and the second polymer block can exhibit relatively strong polarity, while the other can exhibit relatively weak polarity or no polarity.

[0075] For example, the block copolymer layer 1400 can be formed by dissolving the polymers of the first polymer block and the second polymer block in a solvent and spin-coating the dissolved polymers of the first polymer block and the second polymer block. The solvent can be removed by evaporation after coating. The first polymer block and the second polymer block can be randomly mixed with each other within the block copolymer layer 1400.

[0076] Next, the block copolymer layer 1400 can be heat-treated at a temperature equal to or higher than the glass transition temperature of the polymers of the first polymer block and the second polymer block. As a result, the block copolymer layer 1400 can be phase-separated into the first polymer blocks 1401 having a cylindrical shape and the second polymer blocks 1402 surrounding the first polymer blocks 1401.

[0077] See Figure 11 , the first polymer blocks 1401 can be selectively removed to form a polymer mold layer 1410 having a plurality of through-holes HP2. The polymer mold layer 1410 can include Figure 10 the second polymer blocks 1402. In an embodiment, the first polymer blocks 1401 can be selectively removed by an etching process using the etching selectivity between the first polymer blocks 1401 and the second polymer blocks 1402. The etching process can include wet development or dry development. In another embodiment, the first polymer blocks 1401 can be selectively removed using a plasma treatment method or a radiation irradiation method.

[0078] See Figure 12 , the plurality of through-holes HP2 of the polymer mold layer 1410 can be filled with a conductive material to form a plug material layer 1420. For example, the conductive material can include a doped semiconductor material, a metal, a metal nitride, a metal carbide, a metal silicide, or a metal oxide. As an example, the conductive material layer can include n-type doped silicon (Si), platinum (Pt), gold (Au), palladium (Pd), molybdenum (Mo), nickel (Ni), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

[0079] See Figure 13 , the polymer mold layer 1410 formed with the plug material layer 1420 can be planarized to expose the second interlayer insulating layer 130 and form a plug electrode 140. The upper surface 140S of the plug electrode 140 and the upper surface of the second interlayer insulating layer 130 can be located at substantially the same level in the z direction. The plug electrode 140 can include a plurality of conductive nanorods 142 formed by the plug material layer 1420 and a non-conductive mold layer 144 formed by the polymer mold layer 1410.

[0080] Subsequently, a resistive change material layer 1510, an oxygen vacancy storage part material layer 1610, and an upper electrode material layer 1710 may be sequentially formed on the second interlayer insulating layer 130. In an embodiment, the resistive change material layer 1510 may include a resistive change material whose resistance state changes according to an applied external voltage. For example, the resistive change material may include metal oxides such as titanium oxide, aluminum oxide, nickel oxide, copper oxide, zirconium oxide, manganese oxide, hafnium oxide, tungsten oxide, tantalum oxide, niobium oxide, and iron oxide. The metal oxide may include oxygen vacancies. The resistive change material layer 1510 may be formed, for example, by atomic layer deposition, chemical vapor deposition, or the like.

[0081] The oxygen vacancy storage part material layer 1610 may have conductivity. The oxygen vacancy storage part material layer 1610 may include a metal that is highly reactive with oxygen. For example, the metal may include tantalum (Ta), titanium (Ti), or a combination thereof. The oxygen vacancy storage part material layer 1610 may be formed, for example, by atomic layer deposition, chemical vapor deposition, or the like.

[0082] The upper electrode material layer 1710 may include a conductive material. The conductive material may include, for example, a doped semiconductor material, a metal, a metal nitride, a metal carbide, a metal silicide, or a metal oxide. As an example, the conductive material may include n-type doped silicon (Si), platinum (Pt), gold (Au), palladium (Pd), molybdenum (Mo), nickel (Ni), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. For example, the upper electrode material layer 1710 may be formed by atomic layer deposition, chemical vapor deposition, or the like.

[0083] Reference Figure 14 , the resistive change material layer 1510, the oxygen vacancy storage part material layer 1610, and the upper electrode material layer 1710 may be patterned on the second interlayer insulating layer 130 to form a resistive change layer 150, an oxygen vacancy storage part 160, and an upper electrode 170. A patterning process of the resistive change material layer 1510, the oxygen vacancy storage part material layer 1610, and the upper electrode material layer 1710 may be performed such that the plug electrode 140 formed under the resistive change layer 150 is not exposed. That is, a patterning process of the resistive change material layer 1510, the oxygen vacancy storage part material layer 1610, and the upper electrode material layer 1710 may be performed such that the plug electrode 140 is shielded by the resistive change layer 150 or overlaps with the resistive change layer 150 in the z direction.

[0084] Meanwhile, during the patterning process, an etching damage region 150R may be formed in an inner region at a predetermined width "a" from the sidewall 150SW of the resistance change layer 150. As an example, the width "a" may be less than 5 nm. In the etching damage region 150R, the resistance change material contained in the resistance change layer 150 may be in a heterogeneous state. Therefore, when an operating voltage such as a set voltage or a reset voltage is applied between the plug electrode 140 and the upper electrode 170, leakage current can pass through the etching damage region 150R.

[0085] According to an embodiment of the present disclosure, the pattern edge 140E of the plug electrode 140 may be located at a position at a predetermined distance from the adjacent pattern edge 150E of the resistance change layer 150 (see Figure 3 ). As an example, the spacing distance d2 between the pattern edges 140E and 150E may be 5 nm or greater. Therefore, the etching damage region 150R of the resistance change layer 150 and the plug electrode 140 may be configured not to contact each other in the z direction. As a result, leakage current that may occur through the etching damage region 150R can be prevented, thereby improving the electrical reliability of the semiconductor device.

[0086] Referring to Figure 15 , a spacer 180 may be formed on the second interlayer insulating layer 130 to surround the sidewalls of the resistance change layer 150, the oxygen vacancy storage part 160, and the upper electrode 170. The spacer 180 may electrically insulate the resistance change layer 150, the vacancy storage part 160, and the upper electrode 170 in the lateral direction, and may serve as a barrier layer to protect the resistance change layer 150, the oxygen vacancy storage part 160, and the upper electrode 170 from material diffusion. The spacer 180 may include, for example, an insulating material such as an oxide, a nitride, an oxynitride, or a combination of two or more thereof.

[0087] In some embodiments, in the process described with reference to Figure 13 , the process of forming the oxygen vacancy storage part material layer 1610 may be omitted. In this case, the upper electrode material layer 1710 may be directly formed on the resistance change material layer 1510. The upper electrode material layer 1710 may include a metal that is highly reactive with oxygen. For example, the upper electrode material layer 1710 may include tantalum (Ta), titanium (Ti), or a combination thereof. As an example, the upper electrode material layer 1710 may include tantalum nitride, titanium nitride, or a combination thereof. Subsequently, in the process described with reference to Figure 14 , the resistance change material layer 1510 and the upper electrode material layer 1710 may be patterned above the second interlayer insulating layer 130 to form the resistance change layer 150 and the upper electrode 170. Next, a spacer 180 may be formed on the sidewalls of the resistance change layer 150 and the upper electrode 170.

[0088] Figure 16 ,Figure 17A , Figure 17B , Figure 18 and Figure 19 are cross-sectional views schematically showing a method of manufacturing a semiconductor device according to another embodiment of the present disclosure. Figure 17B is Figure 17A an enlarged perspective view of region A of Figure 7A and Figure 7B . The manufacturing method can be applied to the semiconductor device 3 described above with reference to

[0089] Referring to Figure 16 , a process substantially the same as the process described with reference to Figure 8 and Figure 9 can be performed to form a first interlayer insulating layer 110 and a lower electrode 120 sequentially disposed on a substrate 101. Subsequently, a second interlayer insulating layer 130 having a hole pattern HP1 can be formed on the lower electrode 120.

[0090] Referring to Figure 17A and Figure 17B , an insulating metal-organic framework layer 2410 can be formed on the second interlayer insulating layer 130 to fill the hole pattern HP1 and can be disposed on the second interlayer insulating layer 130 outside the hole pattern HP1. The metal-organic framework layer 2410 can include channels of a plurality of cavities V.

[0091] Referring to Figure 17B , the metal-organic framework layer 2410 can be a thin film structure formed by sequentially stacking a plurality of two-dimensional metal-organic frameworks 2410a, 2410b, 2410c, and 2410d, each of the two-dimensional metal-organic frameworks 2410a, 2410b, 2410c, and 2410d having a cavity V. The plurality of two-dimensional metal-organic frameworks 2410a, 2410b, 2410c, and 2410d can be stacked in the z direction such that the cavities V of the plurality of two-dimensional metal-organic frameworks 2410a, 2410b, 2410c, and 2410d overlap each other. Accordingly, the metal-organic framework layer 2410 can include channels formed by the cavities V extending in the z direction. As an example, the metal-organic framework layer 2410 can be formed by methods such as atomic layer deposition, chemical vapor deposition, etc.

[0092] Referring to Figure 18, the channels of the cavities V of the metal-organic framework layer 2410 can be filled with a conductive material to form a plug material layer 2420. The conductive material can include, for example, a doped semiconductor material, a metal, a metal nitride, a metal carbide, a metal silicide, or a metal oxide. As an example, the conductive material layer can include n-type doped silicon (Si), platinum (Pt), gold (Au), palladium (Pd), molybdenum (Mo), nickel (Ni), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

[0093] Reference Figure 19 , the metal-organic framework layer 2410 formed with the plug material layer 2420 can be planarized to expose the second interlayer insulating layer 130 and form a plug electrode 240. The plug electrode 240 can include a plurality of conductive nanorods 242 formed by the plug material layer 2420 and a non-conductive mold layer 244 formed by the metal-organic framework layer 2410.

[0094] Subsequently, by performing a process substantially the same as the process described in reference Figure 14 and Figure 15 , the resistance change layer 150, the oxygen vacancy storage part 160, and the upper electrode 170 can be provided on the plug electrode 240. Next, spacers 180 can be formed on the sidewalls of the resistance change layer 150, the oxygen vacancy storage part 160, and the upper electrode 170.

[0095] As described above, the semiconductor device according to an embodiment of the present disclosure can be applied to a resistive RAM device. In addition, the semiconductor device according to an embodiment of the present disclosure can be applied to a memristor. A memristor is a compound word of a memory and a resistor, and can be a two-terminal device whose resistance state changes according to an external electrical stimulus. A memristor can simultaneously implement a memory function and a computing function through enhanced analog operation characteristics, and can simulate the role of a brain synapse. As an example, the semiconductor device can be applied to an oxide-based RAM (OxRAM) device, which generates a conductive path through oxygen vacancies.

[0096] Concepts have been disclosed in connection with some embodiments as described above. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered from a restrictive perspective, but from an illustrative perspective. The scope of the concepts is not limited to the above description, but is defined by the appended claims, and all distinguishing features within the equivalent scope should be understood to be included in the concepts.

Claims

1. A semiconductor device, comprising: A lower electrode; A plug electrode disposed above the lower electrode and including a plurality of conductive nanorods; A resistive change layer disposed above the plug electrode; And An upper electrode disposed above the resistive change layer.

2. The semiconductor device according to claim 1, wherein, The plug electrode includes a non-conductive mold layer surrounding the plurality of conductive nanorods.

3. The semiconductor device according to claim 2, wherein, Each of the plurality of conductive nanorods extends along a first direction substantially perpendicular to the surface of the lower electrode, and each of the plurality of conductive nanorods contacts the resistive change layer and the lower electrode.

4. The semiconductor device according to claim 3, wherein, Each of the plurality of conductive nanorods is spaced apart from each other in a second direction perpendicular to the first direction.

5. The semiconductor device according to claim 2, wherein, The non-conductive mold layer includes a polymer material or a metal-organic framework.

6. The semiconductor device according to claim 1, wherein, The plug electrode and the resistive change layer are arranged to contact each other.

7. The semiconductor device according to claim 6, wherein, In a plane at the interface between the plug electrode and the resistive change layer, a cross-sectional area of the plug electrode is located within a cross-sectional area of the resistive change layer.

8. The semiconductor device according to claim 7, wherein, In the plane, a pattern edge of the plug electrode is located at a position 5 nm or more away from an adjacent pattern edge of the resistive change layer.

9. The semiconductor device according to claim 6, wherein, In a plane at the interface between the plug electrode and the resistive change layer, a cross-sectional area of the plurality of conductive nanorods is located within a cross-sectional area of the resistive change layer.

10. The semiconductor device according to claim 9, wherein, In the plane, the plurality of conductive nanorods are located at a position 5 nm or more away from an adjacent pattern edge of the resistive change layer.

11. The semiconductor device according to claim 7, wherein, In the plane, a cross-sectional area of the plug electrode is smaller than a cross-sectional area of the resistive change layer.

12. The semiconductor device according to claim 1, wherein, The resistive change layer further includes a plurality of conductive filaments, and the plurality of conductive filaments are respectively connected to the plurality of conductive nanorods.

13. The semiconductor device according to claim 12, wherein, Each of the plurality of conductive filaments is respectively connected to the plurality of conductive nanorods in a one-to-one correspondence.

14. The semiconductor device according to claim 12, wherein, In a contact portion between each of the conductive nanorods and each of the conductive filaments, a width of the conductive filament is less than 1 / 2 of a spacing between the conductive nanorods.

15. The semiconductor device according to claim 1, wherein, The resistive change layer further includes conductive filaments connected to some of the plurality of conductive nanorods in a one-to-one correspondence.

16. The semiconductor device according to claim 1, Among them, Each of the plurality of conductive nanorods has a width of 1 nm to 5 nm, and wherein each of the plurality of conductive nanorods is spaced 1 nm to 50 nm apart from the nearest conductive nanorod.

17. The semiconductor device according to claim 1, wherein, The resistive change layer includes a metal oxide containing oxygen vacancies.

18. The semiconductor device according to claim 1, further comprising an oxygen vacancy storage portion located between the resistive change layer and the upper electrode.

19. A method of manufacturing a semiconductor device, the method comprising: Forming a lower electrode above a substrate; Forming an interlayer insulating layer including a via pattern above the lower electrode; Forming a plug electrode in the via pattern, the plug electrode including a plurality of conductive nanorods and a non-conductive mold layer surrounding the plurality of conductive nanorods; Sequentially forming a resistive change material layer and an upper electrode material layer above the interlayer insulating layer including the plug electrode; And The resistive change material layer and the upper electrode material layer are patterned over the interlayer insulating layer to form a resistive change layer and an upper electrode covering the plug electrode.

20. The method according to claim 19, wherein Forming the plug electrode includes: forming a block copolymer layer that fills the hole pattern and is disposed over the interlayer insulating layer outside the hole pattern; performing a heat treatment on the block copolymer layer to phase-separate the block copolymer layer into a first polymer block in the form of a cylinder and a second polymer block surrounding the first polymer block; selectively removing the first polymer block to form a polymer mold layer including a plurality of through holes; and filling the plurality of through holes with a conductive material to form the conductive nanorods.

21. The method according to claim 20, further comprising planarizing the polymer mold layer filled with the conductive material to expose the interlayer insulating layer.

22. The method according to claim 19, wherein, Forming the plug electrode includes: forming an insulating metal-organic framework layer that fills the hole pattern, is disposed over the interlayer insulating layer outside the hole pattern, and has channels with a plurality of cavities; and filling the channels of the cavities of the insulating metal-organic framework layer with a conductive material to form the conductive nanorods.

23. The method according to claim 19, wherein, Patterned the resistive change material layer and the upper electrode material layer includes: patterning the resistive change material layer and the upper electrode material layer to shield the plug electrode with the resistive change layer.

24. The method according to claim 23, wherein, Patterned the resistive change material layer and the upper electrode material layer includes: patterning the resistive change material layer and the upper electrode material layer such that the pattern edge of the plug electrode is at a distance of 5 nm or more from the adjacent pattern edge of the resistive change layer at the contact surface between the plug electrode and the resistive change layer.

25. The method according to claim 19, further comprising: forming an oxygen vacancy storage part material layer between the resistive change material layer and the upper electrode material layer; and patterning the oxygen vacancy storage part material layer to form an oxygen vacancy storage part between the resistive change layer and the upper electrode.

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