Load off boost converter

Abstract

A load disconnect technique for a boost converter. In one example, a power converter includes a driver circuit (106), a control circuit (M2, M3), and a comparator circuit (101). In a normal boost operation (VINlt; the comparator circuit (101) deactivates the control circuits (M2, M3) and activates the driver circuit (106) during a high-side on-phase (VOUT), which in turn fully conducts the high-side switching element (M1) during a high-side on-phase. Instead, during a start-up operation or an output short-to-ground condition (VIN > = VOUT), the comparator circuit (101) deactivates the driver circuit (106) and activates the control circuit (M2, M3), which in turn controls the gate voltage of the high-side switching element (M1), thus regulating the current through the switching element, and reducing the voltage of the high-side switching element (M1). And adjust the switch node voltage to about a threshold voltage higher than the VIN. In this manner, the comparator circuit (101) controls the driver circuit (106) and the control circuits (M2, M3), which in turn allows the boost converter to operate in a normal manner even when VIN is higher than VOUT.

Description

Technical Field

[0001] This specification relates to regulated power supplies, and more particularly, to a load-disconnect boost converter. Background Art

[0002] The direct current (DC) output voltage provided from a standard power supply can vary due to any number of factors such as transient conditions, environmental conditions, and varying load conditions. In such cases, a voltage regulator can be coupled between the power supply and the load and is used to provide a regulated DC output voltage to the load. In this way, the output voltage of the voltage regulator remains unaffected by sudden or otherwise transient changes in the input power supply voltage and load current. There are many types of DC-DC voltage regulators, including switching regulators and linear regulators. One feature that a boost converter can include is load disconnect. One way to implement the load disconnect function is to use a high-side p-channel metal oxide semiconductor field effect transistor (PMOS FET) to disconnect the input voltage of the boost converter from the output when the converter is disabled. There are still many important problems with such load-disconnect boost converters. Summary of the Invention

[0003] One example includes a power supply circuit that includes a first transistor and a second transistor and a comparator circuit. The comparator circuit has a comparator output and a first comparator input and a second comparator input. The first comparator input is coupled to an input voltage terminal, and the second comparator input is coupled to an output voltage terminal. The comparator circuit is configured to provide a voltage at the comparator output, where the provided voltage is the greater of the voltage at the first comparator input or the voltage at the second comparator input. The first transistor is coupled between the output voltage terminal and the input voltage terminal. The second transistor is coupled between a control terminal of the first transistor and the input voltage terminal, and the second transistor has a control terminal coupled to the comparator output.

[0004] Another example is a power supply circuit that includes a first transistor and a second transistor, a high-side switching transistor and a low-side switching transistor, a high-side driver circuit, a pulse width modulation (PWM) controller, and a comparator circuit. The comparator circuit has a first comparator input and a second comparator input, and a first comparator output and a second comparator output. The first comparator input is coupled to an input voltage terminal, and the second comparator input is coupled to an output voltage terminal. The comparator circuit is configured to provide a voltage at the first comparator output, where the provided voltage is the greater of the voltage at the first comparator input or the voltage at the second comparator input. The comparator circuit is further configured to provide a logic low signal at the second comparator output in response to the voltage at the first comparator input being less than the voltage at the second comparator input, and to provide a logic high signal at the second comparator output in response to the voltage at the first comparator input being greater than or equal to the voltage at the second comparator input. The high-side switching transistor has a drain terminal and a source terminal, the drain terminal being coupled to the output voltage terminal, and the source terminal being coupled to the input voltage terminal. The first transistor has a drain terminal, a source terminal, and a gate terminal, the drain terminal being coupled to the gate terminal of the high-side switching transistor via a diode, the source terminal being coupled to the input voltage terminal, and the gate terminal being coupled to the first comparator output. The anode of the diode is coupled to the drain terminal of the first transistor and its cathode is coupled to the gate terminal of the high-side switching transistor. The second transistor has a drain terminal, a source terminal, and a gate terminal, the drain terminal being coupled to the gate terminal of the high-side switching transistor via a resistor, the source terminal being coupled to the ground terminal, and the gate terminal being coupled to the second comparator output. The high-side driver circuit has a high-side driver circuit input, a high-side driver circuit output, and a high-side driver circuit enable input. The high-side driver circuit output is coupled to the cathode of the diode and the gate terminal of the high-side switching transistor, and the high-side driver circuit enable input is coupled to the second comparator output. The low-side transistor has a drain terminal and a source terminal, the drain terminal being coupled to the input voltage terminal, and the source terminal being coupled to the ground terminal. The PWM controller has a high-side output and a low-side output. The high-side output of the PWM controller is coupled to the high-side driver circuit input, and the low-side output of the PWM controller is coupled to the gate terminal of the low-side transistor. In some such cases, the high-side switching transistor is an n-channel power field effect transistor (FET), and its body terminal is coupled to its drain terminal via a resistor.

[0005] Another example is a comparator circuit. The comparator circuit includes a first input terminal and a second input terminal, where the first input terminal is for receiving the input voltage of a power supply circuit, and the second input terminal is for receiving the output voltage of the power supply circuit. The comparator circuit further includes a first output terminal and a second output terminal, where the first output terminal is for providing the larger of the input voltage or the output voltage, and the second output terminal is for providing a logic low signal in response to the input voltage being less than the output voltage, and for providing a logic high signal in response to the input voltage being greater than or equal to the output voltage. In one such example, the comparator circuit includes a first switch, a second switch, an inverter, and an amplifier. The non-inverting input of the amplifier is coupled to the first input terminal, its inverting input is coupled to the second input terminal, and its amplifier output is coupled to the second output terminal. The first switch is for switching the input voltage to the first output terminal and has a first switch control terminal coupled to the amplifier output. The second switch is for switching the output voltage to the first output terminal and has a second switch control terminal. The inverting input of the inverter is coupled to the amplifier output, and its inverter output is coupled to the second switch control terminal. In some cases, the comparator circuit is included in the power supply circuit, where the first input terminal is coupled to the input voltage terminal of the power supply circuit, and the second input terminal is coupled to the output voltage terminal of the power supply circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. shows a block diagram of a switched-mode power supply in one example.

[0007] Figure 2A FIG. shows a schematic diagram of a switched-mode power supply in one example.

[0008] Figure 2B FIG. shows a comparator circuit included in a switched-mode power supply in one example. Figure 2A FIG. shows a schematic diagram of a comparator circuit included in a switched-mode power supply in one example.

[0009] Figure 3A FIG. shows a signal and timing diagram of a switched-mode power supply in a first operating mode in one example.

[0010] Figure 3B FIG. shows a signal and timing diagram of a switched-mode power supply in a second operating mode in one example.

[0011] Figure 4A -B shows simulation results of a switched-mode power supply experiencing a short-to-ground on its output voltage terminal and recovering from the short-to-ground in one example.

[0012] Figure 5 FIG. shows a method for adaptively controlling a load-disconnect boost converter in one example. DETAILED DESCRIPTION

[0013] Load disconnect techniques for boost converters are described herein. The techniques can be used in any number of boost configurations, but are particularly well-suited to boost converter configurations having an NMOS FET for a high-side switching element. The boost converter can implement a load disconnect function and can withstand a short circuit to ground at the output terminals. In one such example, the boost power supply includes a driver circuit, a control circuit, and a comparator circuit. During normal boost operation (VIN < VOUT), the comparator circuit deactivates the control circuit and enables the driver circuit, which in turn fully conducts the high-side NMOS FET during the high-side conduction phase. During startup operation or a short circuit to ground condition at the output terminals (VIN ≥ VOUT), the comparator circuit deactivates the driver circuit and enables the control circuit, which in turn controls the gate voltage of the high-side NMOS FET, thus regulating the current through the NMOS FET. For example, during startup or a short circuit condition, the switch node voltage is regulated to be approximately the threshold voltage higher than VIN (e.g., VTH or VGS of approximately 1 volt), and the NMOS FET operates in saturation mode and the boost inductor current follows the volt-second balance rule, and the boost converter can operate similarly to normal conditions.

[0014] General Overview

[0015] In the case of no load disconnect in a boost converter, even when the converter is in a deactivated state, there may be a leakage current from the input power supply and through the rectifier diode to the output load (e.g., I = (VIN - VBE) / RLOAD, where I is the leakage current, VIN is the input power supply voltage, VBE is the voltage drop across the rectifier diode coupled between VIN and VOUT, and RLOAD is the load resistance). Additionally, without load disconnect, the converter may not be able to withstand a short circuit to ground at the output terminal, and there is no slope control during startup when VOUT ramps from 0 volts to VIN. As described above, load disconnect in a boost converter is typically implemented using a high-side PMOS FET to disconnect the input voltage of the converter from the output voltage when the converter is deactivated. In operation, the back gate of the PMOS FET can be switched to the switch node or the output terminal, so that when the converter is deactivated, the output load is disconnected from the input voltage supply. Additionally, during a short circuit to ground condition at the output, the PMOS FET can clamp the switch node to a lower voltage, thus allowing the converter to withstand the short circuit condition. However, using a PMOS power FET for the high-side switching element has a high cost and limits the power density of the boost converter. For example, the specific on-resistance of the PMOS power FET (Rsp, which is equal to RDSon * area) is larger than that of the NMOS power FET by a factor of about 2 to 5 times. Because of these limitations associated with using a PMOS power FET for the high side, some boost converters use an NMOS as the high-side FET. Unfortunately, such NMOS-based boost converter configurations cannot achieve load disconnect or withstand a short circuit to ground at the output terminal.

[0016] Accordingly, a boost converter is described herein that can achieve a load disconnect function and can withstand a short circuit to ground at the output terminal. The boost converter can be implemented using an NMOS power FET for the high-side switching element, thus facilitating significant space savings (e.g., up to 50% of the high-side FET die area). A comparator circuit controls the high-side driver circuit and the regulation loop, which in turn allows the boost converter to operate in a normal manner even when VIN is higher than VOUT.

[0017] Circuit Architecture

[0018] Figure 1A block diagram of a switching power supply in an example is shown. As shown, the power supply includes a comparator circuit 101, a pulse width modulation (PWM) controller 102, and a power converter circuit 103. The switching power supply receives a given input voltage (VIN) at its input voltage terminal and provides a regulated output voltage (VOUT) at its output voltage terminal. The values or ranges of VIN and VOUT may vary according to embodiments, but in some examples, both are in the range of 3.3 volts to 35 volts (e.g., such as an example case where VIN is equal to 5 volts or 12 volts and VOUT is equal to 5 volts or 8 volts).

[0019] The comparator circuit 101 has a first comparator input and a second comparator input, as well as a first comparator output (VMAX) and a second comparator output (VIN_HI). The first comparator input is coupled to the VIN terminal, and the second comparator input is coupled to the VOUT terminal. The comparator circuit 101 is configured to provide the larger of VIN or VOUT at the VMAX comparator output. The comparator circuit 101 is further configured to provide a logic low signal at the VIN_HI comparator output in response to VIN being less than VOUT, and to provide a logic high signal at the VIN_HI comparator output in response to VIN being greater than or equal to VOUT. Further details of the comparator circuit 101 are described below.

[0020] The PWM controller 102 is coupled to the switch node (SW) of the power converter circuit 103 and receives a reference voltage VREF and a feedback voltage FB representative of the output voltage VOUT as inputs, and is configured to generate a high-side gate drive signal HS_GT and a low-side gate drive signal LS_GT, which are provided to the input of the high-side bootstrap driver circuit and the control terminal of the low-side switching element of the power converter circuit 103, respectively. VREF can be provided, for example, by a bandgap voltage reference, and the feedback voltage FB can be provided by a voltage divider, for example, connected in series between VOUT and the ground terminal. The PWM controller 102 can be implemented with any suitable PWM control scheme and circuitry.

[0021] The power converter circuit 103 is configured with a boost converter topology (e.g., boost or buck-boost), and can both implement a load disconnect function and withstand a short circuit to ground at the VOUT terminal. In one example, the converter circuit 103 is implemented with an NMOS power FET for the high-side switching element. The converter circuit 103 can be implemented with any suitable boost converter circuitry, but it is further configured with a control circuit and a high-side driver circuit that respond to the outputs (VMAX and VIN_HI) of the comparator circuit 101. Further details of the converter circuit 103 are described below.

[0022] Figure 2A A schematic diagram of a switching power supply in one example is shown. As shown, according to one such example, the switching power supply is similar to Figure 1 the switching power supply shown in, but additional details of the power converter circuit 103 are shown. The above related discussions regarding the comparator circuit 101 and the PWM controller 102 apply equally here. In this example, the reference voltage VREF is provided to the PWM controller 102 by the VREF circuit 104, and the VREF circuit can be, for example, a bandgap voltage reference circuit (e.g., such as a Brokaw or Widlar bandgap voltage reference). As further shown, the feedback voltage FB provided to the PWM controller 102 is generated by a voltage divider including resistors R3 and R4, and the voltage divider is connected in series between VOUT and the ground terminal.

[0023] The power converter 103 is configured with a boost topology and includes an inductor L1 coupled between the VIN terminal and the switch node (SW). The high-side switch element M1 is coupled between the switch node and the VOUT terminal, and the low-side switch element M4 is coupled between the switch node and the ground terminal. The output capacitor COUT is coupled between VOUT and the ground terminal, such as for a load to be powered (in this example, it is a resistive load RLOAD). The control terminal of M1 is operatively coupled to a bootstrap driver circuit and a control circuit including an adjustment loop. The bootstrap driver circuit is further described below, but generally receives at its input the high-side drive signal HS_GT generated by the PWM controller 102 and applies a corresponding control signal to the control terminal of M1. The control terminal of M4 receives the low-side drive signal LS_GT generated by the PWM controller 102. In this example, each of M1 and M4 is implemented as an NMOS power FET, where the source of M1 is coupled to the VOUT terminal, the drain of M1 is coupled to the switch node, the gate of M1 is the control terminal of M1, the source of M4 is coupled to the ground terminal, the drain of M4 is coupled to the switch node, and the gate of M4 is the control terminal of M4. Other examples may be configured differently and still provide equivalent functionality.

[0024] The bootstrap diver circuit of this example includes a level shifter (LVL_SHIFT) 105, which is operatively coupled to a high-side gate driver (HS_DRVR) 106. The level shifter 105 receives at its input the high-side drive signal HS_GT generated by the PWM controller 102 and provides a level-shifted version of the signal, which is applied to the input of the high-side gate driver 106. The output of the high-side gate driver 106 is coupled to the gate of M1. The positive power rail of the high-side gate driver 106 is coupled to the bootstrap node, and the negative power rail of the driver 106 is coupled to a virtual ground. The driver 106 is configured with an enable (EN) input, which is coupled to the second comparator output VIN_HI. In this example, the driver 106 is enabled in response to VIN_HI being low and disabled in response to VIN_HI being high. The capacitor C1 is a bootstrap capacitor and is coupled between the switch node and the bootstrap node, and the anode of the diode D1 is coupled to the first comparator output VMAX and its cathode is coupled to the bootstrap node. With such a configuration, the first comparator output VMAX can charge the capacitor C1 in response to the switch node being low, and the charge of the capacitor C1 will rise as the switch node voltage rises. The diode D1 blocks the path from the bootstrap node to the switch node in response to the switch node being high and the bootstrap node voltage being higher than VMAX. Other examples may be configured differently and still provide equivalent functionality.

[0025] The control circuit for facilitating the regulation loop includes transistors M2 and M3, resistors R1 and R2, and diode D2. Transistor M2 is coupled between the switch node and the control terminal of transistor M1, and its control terminal is coupled to the first comparator output VMAX. Transistor M3 is coupled between the control terminal of transistor M1 and the ground terminal, and its control terminal is coupled to the second comparator output VIN_HI. In this example, transistor M2 is a PMOS FET, and transistor M3 is an NMOS FET, where the source of M2 is coupled to the switch node, the drain of M2 is coupled to the gate of M1 via diode D2, the gate of M2 is coupled to the first comparator output VMAX, the source of M3 is coupled to the ground terminal, the drain of M3 is coupled to the gate of M1 via resistor R2, and the gate of M3 is the control terminal of M3. The anode of diode D2 is coupled to the drain of M2 and its cathode is coupled to the gate of M1, and resistor R2 is coupled between the drain of M3 and the gate of M1. In response to VIN being less than VOUT (normal operation), the voltage at the gate of M1 is higher than the voltage on the switch node, which reverse-biases diode D2. In this way, diode D2 blocks the output voltage from transistor M2 and driver 106 of the switch node. In this example, resistor R1 is used to bias the back gate of M1, so that the back gate of M1 will not float. Resistor R2 controls the discharge rate (current) of the potential at the gate of M1 in response to VIN_HI being high (when VIN≥VOUT, such as during the startup of a switching power supply or a short-circuit condition on the VOUT terminal). Resistor R2 also provides a resistive load for the regulation loop. Other examples may be configured differently and still provide equivalent functionality.

[0026] Figure 2B FIG. shows a schematic diagram of the comparator circuit 101 in an example. As shown, the circuit 101 includes an amplifier (AMP) 107 and an inverter 108 arranged to control the states of the first switch S1 and the second switch S2. The non-inverting input of the amplifier 107 is coupled to the VIN terminal, and the inverting input of the amplifier 107 is coupled to the VOUT terminal. The switch S1 is coupled between the VIN terminal and the VMAX output, and the switch S2 is coupled between the VOUT terminal and the VMAX output. The output of the amplifier 107 is coupled to the VIN_HI output. The output of the amplifier 107 is also applied to the control terminal of the switch S1 and the input of the inverter 108. The output of the inverter 108 is applied to the control terminal of the switch S2. The amplifier 107 is configured to determine the larger of VIN and VOUT. Such a configuration allows the comparator circuit 101 to determine whether the boost converter is operating in the normal mode (characterized by VIN being less than VOUT) or in the startup or short-circuit condition (characterized by VIN being greater than or equal to VOUT), and configure the boost converter accordingly.

[0027] For example, if VIN is less than VOUT, amplifier 107 generates a logic low signal and applies the logic low signal to the VIN_HI output. The logic low signal is applied to the enable input of driver 106 and the M3 gate, thus enabling driver 106 and deactivating the regulation loop for normal operation. The logic low signal is also applied to the control terminal of switch S1, which places S1 in its open state, and to the input of inverter 108, which converts the low signal to a high signal, which in turn is applied to the control terminal of switch S2, which places S2 in its closed state. Thus, VOUT is provided at the VMAX output.

[0028] Conversely, if VIN is greater than or equal to VOUT, amplifier 107 generates a logic high signal and applies the logic high signal to the VIN_HI output. The logic high signal is applied to the enable input of driver 106 and the M3 gate, thus deactivating driver 106 and enabling the regulation loop for startup or short - circuit operation. The logic high signal is also applied to the control terminal of switch S1, which places S1 in its closed state, and to the input of inverter 108, which converts the high signal to a low signal, which is applied to the control terminal of switch S2, which places S2 in its open state. Thus, VIN is provided at the VMAX output.

[0029] Although the components and parameter values and sizes may vary according to the example, Table 1 shows a set of component and parameter values and sizes according to one such example.

[0030] Table 1: Example Values and Sizes

[0031]

[0032]

[0033] Thus, in one such example, a load - disconnect boost converter is provided that receives 5 volts at its VIN terminal and can generate up to 5.5 volts at its output terminal, and has an NMOS power FET as the high - side switching element (M1). The NMOS power FET has a back - gate (or a back - gate connected to VOUT through series resistor R1 as shown) that can be switched based on the voltage levels of VIN and VOUT, thus blocking the diode path from the switch node to VOUT. The boost converter can be in a deactivated state or an enabled state. In the deactivated state, the following applies: VIN is greater than VOUT; VMAX is equal to VIN; VIN_HI is equal to high; driver 106 is deactivated; HS_GT is equal to 0 volts; the M1 back - gate is equal to VOUT. Thus, in this deactivated state, load - disconnect is achieved and no current flows from VIN to the output terminal.

[0034] When enabled, the boost converter can be in normal operation mode or startup or short - circuit mode. In normal operation mode, the following applies: VIN is less than VOUT; VMAX is equal to VOUT; and VIN_HI is equal to low. Thus, the bootstrap driver circuit including driver 106 is enabled and fully conducts M1 during the boost converter high - side conduction phase, and the regulation loop is deactivated (VIN_HI is set to low). In startup and output - to - ground short - circuit operation modes, the following applies: VIN is greater than or equal to VOUT; VMAX is equal to VIN; and VIN_HI is equal to high. Thus, the bootstrap driver circuit including driver 106 is deactivated, and the regulation loop is enabled and regulates the switch - node voltage to about 1 volt higher than VIN (VMAX + VGS_M2), where M1 is in saturation mode. Thus, the current through inductor L1 follows the volt - second balance rule, and the boost - converter control circuit can operate similar to normal operation.

[0035] Figure 3A Shows the signals and timing diagram of a switched - mode power supply in normal operation mode in an example. In this example, it is assumed that: VIN is equal to 3.6 volts, VOUT is equal to 3.6 volts to 5.5 volts, VIN_HI is equal to 0 volts (low), and VMAX is equal to VOUT. As Figure 3A shown, during the low - side conduction phase: LS_CON is equal to VOUT (M4 conducts), HS_GT is equal to 0 volts (M1 is off), and the L1 inductor current (IL) ramps up with di / dt = VIN / L1. As Figure 3A further shown, during the high - side conduction phase: LS_CON is equal to 0 volts (M4 is off), HS_GT is equal to VBOOT (M1 conducts), the regulation loop is not working or otherwise enabled, and the L1 inductor current (IL) ramps down with di / dt = (VOUT - VIN) / L1. VBOOT is the voltage on the bootstrap node and is equal to VOUT+VSW. VSW is the voltage on the switch node and is equal to VOUT+(IL*RDSon_M1). RDSon_M1 is the drain - to - source on - resistance of M1.

[0036] Figure 3B Shows the signals and timing diagram of a switched - mode power supply in startup or short - circuit operation mode in an example. During startup, in this example, it is assumed that: VIN is equal to 3.6 volts, VOUT is equal to 0 volts to 3.6 volts, VIN_HI is equal to 3.6 volts (high), and VMAX is equal to VIN. As Figure 3B shown, during the low - side conduction phase: LS_CON is equal to VIN (M4 conducts), HS_GT is equal to 0 volts (M1 is off), and the L1 inductor current (IL) ramps up with di / dt = VIN / L1. As Figure 3BAs further shown, during the high-side conduction phase: LS_CON is equal to 0 volts (M4 is off), HS_GT is equal to VOUT + VGS_M1, and the switch-node voltage ramps up. VGS_M1 is the gate-to-source voltage of M1. In response to the switch-node voltage being higher than VMAX, the regulation loop conducts and regulates the inductor current through M1. The voltage on the switch node SW is equal to VIN + VGS_M2. VGS_M2 is the gate-to-source voltage of M2. The voltage across the inductor L1 is equal to SW - VIN = VGS_M2, and the L1 inductor current (IL) ramps down at di / dt = (VOUT + VGS_M1) / L1. In this way, the boost current limit can adapt to VIN - VOUT to reduce power dissipation during the startup of a load-disconnected boost converter. A similar adaptive current limit behavior is achieved to reduce power dissipation during an output-to-ground short circuit.

[0037] Example Simulation

[0038] Figure 4A -B shows the simulation results of a switching power supply in an example experiencing an output voltage terminal short circuit to ground and recovering from the short circuit to ground. Assume the following settings: VIN = 3.6 volts, VOUT = 5 volts, L1 = 1 uH; COUT = 5 uF. As Figure 4A shown, at startup, VOUT ramps linearly from 0 volts to 5 volts, and shortly thereafter (about 350 μs from t0), a short circuit to ground occurs on the VOUT terminal. At this time, the adaptive current limit functionality of the control circuit (regulation loop) comes into play, such that the inductor current IL remains relatively well controlled during the approximately 50 μs period when the short circuit persists. At this time, the short circuit condition is removed, and in the next approximately 75 μs, the regulation loop operates until VOUT ramps up to VIN (or slightly greater than VIN). At this time, normal boost converter operation continues.

[0039] Figure 4BIncludes further details of an expanded time base to show the simulated short circuit and inductor current, as well as the control or gate voltage (HS_GT) applied to the high-side NMOS FET (M1). As shown, in response to VOUT dropping below VIN, the high-side gate driver is deactivated and the regulation loop comes into play. As a result, the HS_GT voltage during the high-side conduction phase changes from approximately 8 volts (before the short circuit) to approximately 0.7 volts (during the short circuit duration). The ~0.7 volts corresponds to the gate-to-source voltage of the high-side NMOS FET, so other examples may have different HS_GT voltages depending on the VGS value of the high-side switching element used. As further shown in the example of Figure 4b, the inductor current before the short circuit condition remains in the range of approximately 100 mA to approximately 450 mA, and is then adaptively limited to the range of approximately 450 mA to approximately 750 mA during the short circuit condition through the operation of the control loop. In this way, when VIN > VOUT, the current limit of the boost converter is reduced, and the inductor current can be well controlled even when the VOUT terminal is shorted to ground.

[0040] Method

[0041] Figure 5 Shows a method for adaptively controlling a load-disconnect boost converter in one example. The method can be performed, for example, by Figure 1 the example boost converter shown in and 2, but any number of other boost converter configurations with an NMOS high-side switching element combined with load-disconnect and short-circuit withstand functionality can also be configured to perform the method.

[0042] As shown, the method includes comparing VIN with VOUT at 501. Based on the comparison, the method proceeds to 503 to determine whether VIN is greater than or equal to VOUT. In response to VIN being less than VOUT, normal boost converter operation begins. In the normal operating mode, the method proceeds to 504 to enable the driver of the high-side switching element and deactivate the control circuit (regulation loop). This enabling of the driver and deactivation of the control circuit can be achieved, for example, by setting VIN_HI low and setting VMAX to VOUT, as described above with reference to comparator circuit 101.

[0043] During the operation of the low-side conduction phase (LS_ON phase) at 506, the LS_CON signal applied to the control terminal of the low-side switching element is set to VOUT, the HS_GT signal applied to the control terminal of the high-side switching element is set to 0 volts, and the inductor current ramps up at di / dt = VIN / L. During the operation of the high-side conduction phase (HS_ON phase) at 508, the LS_CON signal applied to the control terminal of the low-side switching element is set to 0 volts, the HS_GT signal applied to the control terminal of the high-side switching element is set to the boost voltage (BOOT = VOUT + VSW, where VSW is the switching node voltage), and the inductor current ramps down at di / dt = (VOUT - VIN) / L.

[0044] In response to VIN being greater than or equal to VOUT, the adaptive current limit mode starts. In this mode, the method proceeds to 505, deactivating the driver of the high-side switching element and enabling the control circuit (regulation loop). This deactivation of the driver and activation of the control circuit can be achieved, for example, by setting VIN_HI high and setting VMAX to VIN, as described above with reference to the comparator circuit 101.

[0045] During the operation of the low-side conduction phase (LS_ON phase) at 507, the LS_CON signal applied to the control terminal of the low-side switching element is set to VIN, the HS_GT signal applied to the control terminal of the high-side switching element is set to 0 volts, and the inductor current ramps up at di / dt = VIN / L. During the operation of the high-side conduction phase (HS_ON phase) at 509, the LS_CON signal applied to the control terminal of the low-side switching element is set to 0 volts, the HS_GT signal is set to the sum of VOUT and the threshold voltage of the high-side switching element (e.g., VOUT + VTH_M1), and the inductor current ramps down at di / dt = (VOUT + VTH_M1) / L1. The switching node voltage VSW is equal to VIN + VTH_M2. VTH_M1 is the threshold voltage of M1, and VTH_M2 is the threshold voltage of M2. In some examples where M1 and M2 are implemented as FETs, the threshold voltage of each FET is the gate-to-source voltage (VTH = VGS). The voltage across the boost inductor is equal to VSW - VIN, which is equal to VTH_M2. In this way, the boost current limit can adapt to VIN - VOUT to reduce power dissipation during startup of the load-disconnected boost converter or output short-circuit operation.

[0046] Additional Examples

[0047] Example 1 is a power supply circuit, which includes: a comparator circuit having a comparator output, a first comparator input, and a second comparator input, where the first comparator input is coupled to an input voltage terminal, the second comparator input is coupled to an output voltage terminal, and the comparator circuit is configured to provide a voltage at the comparator output, where the provided voltage is the larger of the voltage at the first comparator input or the voltage at the second comparator input; a first transistor coupled between the output voltage terminal and the input voltage terminal; and a second transistor coupled between the control terminal of the first transistor and the input voltage terminal, the second transistor having a control terminal coupled to the comparator output. In some such examples, the comparator circuit may be similar to comparator circuit 101, and the first transistor and the second transistor may be FET M1 and M2, respectively.

[0048] Example 2 includes the power supply circuit according to Example 1, where the comparator output is a first comparator output, and the comparator circuit includes a second comparator output, and where the comparator circuit is further configured to provide a logic low signal at the second comparator output in response to the voltage at the first comparator input being less than the voltage at the second comparator input, and to provide a logic high signal at the second comparator output in response to the voltage at the first comparator input being greater than or equal to the voltage at the second comparator input. The power supply circuit includes: a third transistor coupled between the control terminal of the first transistor and a ground terminal, the third transistor having a control terminal coupled to the second comparator output. In some such examples, the first comparator output may be VMAX, the second comparator output may be VIN_HI, and the third transistor may be FET M3.

[0049] Example 3 includes the power supply circuit according to Example 2, where the third transistor is coupled to the control terminal of the first transistor via a resistor.

[0050] Example 4 includes the power supply circuit according to Example 2 or 3, and further includes a driver circuit having a driver circuit output and an enable input, the driver circuit output being coupled to the control terminal of the first transistor, and the enable input being coupled to the second comparator output.

[0051] Example 5 includes the power supply circuit according to any one of Examples 1 to 4, and further includes: a voltage divider circuit (e.g., R3 and R4), which has a voltage divider input and a voltage divider output, the voltage divider input being coupled to the output voltage terminal, wherein the voltage divider circuit is configured to provide a feedback signal at the voltage divider output, the feedback signal representing the voltage at the output voltage terminal; a reference voltage circuit (e.g., VREF 104), which has a reference voltage output, the reference voltage circuit being configured to provide a reference voltage at the reference voltage output; and a pulse width modulation (PWM) controller (e.g., PWM 102), which has a first PWM controller input, a second PWM controller input, and a PWM controller output, the first PWM controller input being coupled to the voltage divider output, the second input being coupled to the reference voltage output, and the PWM controller output being configured to provide a PWM control signal.

[0052] Example 6 includes the power supply circuit according to Example 5, and further includes: a driver circuit (e.g., level shifter 105 and driver 106), which has an input terminal and a power rail terminal, wherein the input terminal of the driver circuit is coupled to the PWM controller output; and a capacitor (e.g., C1), which is coupled between the input voltage terminal and the power rail terminal of the driver circuit.

[0053] Example 7 includes the power supply circuit according to any one of Examples 1 to 6, wherein the first transistor is a high-side switching transistor, and the power supply circuit further includes: a low-side switching transistor, which is coupled between the input voltage terminal and the ground terminal, and the low-side switching transistor has a control terminal coupled to the low-side output of the PWM controller.

[0054] Example 8 includes the power supply circuit according to any one of Examples 1 to 7, wherein the first transistor and the second transistor are field effect transistors, the control terminal of the first transistor is the gate terminal of the first transistor, the control terminal of the second transistor is the gate terminal of the second transistor, and the first transistor has a body terminal coupled to the drain terminal of the first transistor via a resistor, and wherein the second transistor has a drain terminal coupled to the gate terminal of the first transistor via a diode, the anode of the diode being coupled to the drain terminal of the second transistor and its cathode being coupled to the gate terminal of the first transistor.

[0055] Example 9 includes the power supply circuit according to any one of Examples 1 to 8, wherein the first transistor is an n-channel power field effect transistor (FET).

[0056] Example 10 is an integrated circuit package that includes: a power supply circuit according to any one of Examples 1 to 9; and an inductor (e.g., L1) coupled between the input voltage terminal and corresponding terminals of the first transistor and the second transistor.

[0057] Example 11 is a power supply circuit that includes: a comparator circuit having a first comparator input, a second comparator input, a first comparator output, and a second comparator output, the first comparator input being coupled to an input voltage terminal, the second comparator input being coupled to an output voltage terminal, wherein the comparator circuit is configured to provide a voltage at the first comparator output, wherein the provided voltage is the larger of the voltage at the first comparator input or the voltage at the second comparator input, and wherein the comparator circuit is further configured to provide a logic low signal at the second comparator output in response to the voltage at the first comparator input being less than the voltage at the second comparator input, and to provide a logic high signal at the second comparator output in response to the voltage at the first comparator input being greater than or equal to the voltage at the second comparator input; a high-side switching transistor (e.g., M1) having a drain terminal and a source terminal, the drain terminal being coupled to the output voltage terminal, the source terminal being coupled to the input voltage terminal; a first transistor (e.g., M2) having a drain terminal, a source terminal, and a gate terminal, the drain terminal being coupled to the gate terminal of the high-side switching transistor via a diode (e.g., D2), the source terminal being coupled to the input voltage terminal, the gate terminal being coupled to the first comparator output, the anode of the diode being coupled to the drain terminal of the first transistor and its cathode being coupled to the gate terminal of the high-side switching transistor; a second transistor (e.g., M3) having a drain terminal, a source terminal, and a gate terminal, the drain terminal being coupled to the gate terminal of the high-side switching transistor via a resistor (e.g., R2), the source terminal being coupled to a ground terminal, the gate terminal being coupled to the second comparator output; a high-side driver circuit having a high-side driver circuit input, a high-side driver circuit output, and a high-side driver circuit enable input, the high-side driver circuit output being coupled to the cathode of the diode (e.g., D2) and the gate terminal of the high-side switching transistor (e.g., M1), and the high-side driver circuit enable input being coupled to the second comparator output; a low-side transistor (e.g., M4) having a drain terminal and a source terminal, the drain terminal being coupled to the input voltage terminal, the source terminal being coupled to the ground terminal; and a pulse width modulation (PWM) controller having a high-side output and a low-side output, the high-side output being coupled to the high-side driver circuit input, and the low-side output being coupled to the gate terminal of the low-side transistor.

[0058] Example 12 includes the power supply circuit according to Example 11, wherein the high-side switching transistor is an n-channel power field effect transistor (FET), and its body terminal is coupled to its drain terminal via a resistor.

[0059] Example 13 includes the power supply circuit according to Example 11 or 12, wherein the power supply circuit is a DC-DC boost converter circuit.

[0060] Example 14 is an integrated circuit package that includes the power supply circuit according to any one of Examples 11 to 13.

[0061] Example 15 is a comparator circuit that includes: a first input terminal for receiving an input voltage of a power supply circuit; a second input terminal for receiving an output voltage of the power supply circuit; a first output terminal for providing the larger of the input voltage or the output voltage; and a second output terminal for providing a logic low signal in response to the input voltage being less than the output voltage, and providing a logic high signal in response to the input voltage being greater than or equal to the output voltage.

[0062] Example 16 includes the comparator circuit according to Example 15, and further includes: an amplifier having a non-inverting input, an inverting input, and an amplifier output, the non-inverting input being coupled to the first input terminal, the inverting input being coupled to the second input terminal, and the amplifier output being coupled to the second output terminal; a first switch for switching the input voltage to the first output terminal and having a first switch control terminal coupled to the amplifier output; a second switch for switching the output voltage to the first output terminal and having a second switch control terminal; and an inverter having an inverter input and an inverter output, the inverter input being coupled to the amplifier output, and the inverter output being coupled to the second switch control terminal.

[0063] Example 17 is a power supply circuit that includes the comparator circuit according to Example 15, wherein the first input terminal is coupled to an input voltage terminal of the power supply circuit, and the second input terminal is coupled to an output voltage terminal of the power supply circuit.

[0064] Example 18 includes the power supply circuit according to Example 17, and further includes: a power converter circuit, which includes a low-side switching element, a high-side switching element, and a high-side driver circuit, the low-side switching element has a low-side control terminal, and the high-side switching element has a high-side control terminal coupled to the output terminal of the high-side driver circuit, and the second output terminal of the comparator circuit is coupled to the enable input of the high-side driver circuit; and a PWM controller, which has a high-side output and a low-side output, the low-side output is coupled to the low-side control terminal of the low-side switching element, and the high-side output is coupled to the input terminal of the high-side driver circuit.

[0065] Example 19 includes the power supply circuit according to Example 18, wherein the power converter circuit further includes: a first transistor, which has a drain terminal, a source terminal, and a gate terminal, the drain terminal is coupled to the high-side control terminal of the high-side switching element via a diode, the source terminal is coupled to the input voltage terminal, the gate terminal is coupled to the first output terminal of the comparator circuit, the anode of the diode is coupled to the drain terminal of the first transistor and its cathode is coupled to the gate terminal of the high-side control terminal of the high-side switching element; and a second transistor, which has a drain terminal, a source terminal, and a gate terminal, the drain terminal is coupled to the high-side control terminal of the high-side switching element via a resistor, the source terminal is coupled to the ground terminal, and the gate terminal is coupled to the second output terminal of the comparator circuit.

[0066] Example 20 includes the power supply circuit according to any one of Examples 17 to 19, wherein the power supply circuit is a DC-DC boost converter circuit.

[0067] Example 21 is an integrated circuit package, which includes the comparator circuit according to Example 15 or 16, or the power supply circuit according to any one of Examples 17 to 20.

[0068] In this specification, the term "coupled" may cover a connection, communication, or signal path that enables a functional relationship to be consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, such that device B is controlled by device A through the control signal generated by device A.

[0069] A device “configured to” perform a task or function can be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function and / or can be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration can be done through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnects of the device, or a combination thereof.

[0070] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” can be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to denote the interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components or their ends.

[0071] A circuit or device described herein as including certain components can in fact be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) can in fact include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package) and can be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, e.g., by an end user and / or a third party.

[0072] Although the use of specific transistors is described herein, other transistors (or equivalent devices) can alternatively be used. For example, a p-channel field-effect transistor (PFET) can be used instead of an n-channel field-effect transistor (NFET) with little or no change to the circuit. Additionally, other types of transistors (e.g., bipolar junction transistors (BJTs)) can be used. Further, the device can be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0073] As used herein, a field-effect transistor (FET) being “on” means that there is a conductive channel in the FET and a drain current can flow through the FET. A FET being “off” as used herein means that there is no conductive channel and a drain current does not flow through the FET. However, an off FET can have a current flowing through the body diode of the transistor.

[0074] The circuits described herein can be reconfigured to include additional or different components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements that are coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0075] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about", "approximately", or "substantially" in front of a parameter means within + / - 10% of the stated parameter.

[0076] Within the scope of the claims, modifications may be made in the described embodiments, and other embodiments are possible.

Claims

1. A power supply circuit, comprising: A comparator circuit having a comparator output, a first comparator input, and a second comparator input, the first comparator input coupled to an input voltage terminal, the second comparator input coupled to an output voltage terminal, the comparator circuit configured to provide a voltage at the comparator output, wherein the provided voltage is the larger of the voltage at the first comparator input or the voltage at the second comparator input; A first transistor coupled between the output voltage terminal and the input voltage terminal; And A second transistor coupled between a control terminal of the first transistor and the input voltage terminal, the second transistor having a control terminal coupled to the comparator output.

2. The power supply circuit according to claim 1, wherein the comparator output is a first comparator output, and the comparator circuit includes a second comparator output, and wherein the comparator circuit is further configured to provide a logic low signal at the second comparator output in response to the voltage at the first comparator input being less than the voltage at the second comparator input, and to provide a logic high signal at the second comparator output in response to the voltage at the first comparator input being greater than or equal to the voltage at the second comparator input, the power supply circuit including: A third transistor coupled between the control terminal of the first transistor and a ground terminal, the third transistor having a control terminal coupled to the second comparator output.

3. The power supply circuit according to claim 2, wherein the third transistor is coupled to the control terminal of the first transistor via a resistor.

4. The power supply circuit according to claim 2, further comprising: A driver circuit having a driver circuit output and an enable input, the driver circuit output coupled to the control terminal of the first transistor, and the enable input coupled to the second comparator output.

5. The power supply circuit according to claim 1, further comprising: A voltage divider circuit having a voltage divider input and a voltage divider output, the voltage divider input coupled to the output voltage terminal, wherein the voltage divider circuit is configured to provide a feedback signal at the voltage divider output, the feedback signal representing the voltage at the output voltage terminal; A reference voltage circuit having a reference voltage output, the reference voltage circuit configured to provide a reference voltage at the reference voltage output; And A pulse width modulation (PWM) controller having a first PWM controller input, a second PWM controller input, and a PWM controller output, the first PWM controller input coupled to the voltage divider output, the second input coupled to the reference voltage output, and the PWM controller output configured to provide a PWM control signal.

6. The power supply circuit according to claim 5, further comprising: A driver circuit having an input terminal and a power rail terminal, wherein the input terminal of the driver circuit is coupled to the PWM controller output; And A capacitor, which is coupled between the input voltage terminal and the power rail terminal of the driver circuit.

7. The power supply circuit according to claim 1, wherein the first transistor is a high-side switching transistor, and the power supply circuit further includes: A low-side switching transistor, which is coupled between the input voltage terminal and the ground terminal, and the low-side switching transistor has a control terminal coupled to the low-side output of the PWM controller.

8. The power supply circuit according to claim 1, wherein the first transistor and the second transistor are field effect transistors, the control terminal of the first transistor is the gate terminal of the first transistor, the control terminal of the second transistor is the gate terminal of the second transistor, and the first transistor has a body terminal coupled to the drain terminal of the first transistor via a resistor, and wherein the second transistor has a drain terminal coupled to the gate terminal of the first transistor via a diode, the anode of the diode is coupled to the drain terminal of the second transistor and its cathode is coupled to the gate terminal of the first transistor.

9. The power supply circuit according to claim 1, wherein the first transistor is an n-channel power field effect transistor (FET).

10. An integrated circuit package, comprising: The power supply circuit according to claim 1; And an inductor, which is coupled between the input voltage terminal and the corresponding terminals of the first transistor and the second transistor.

11. A power supply circuit, which includes: A comparator circuit, which has a first comparator input, a second comparator input, a first comparator output, and a second comparator output, the first comparator input is coupled to the input voltage terminal, the second comparator input is coupled to the output voltage terminal, wherein the comparator circuit is configured to provide a voltage at the first comparator output, wherein the provided voltage is the larger of the voltage at the first comparator input or the voltage at the second comparator input, and wherein the comparator circuit is further configured to provide a logic low signal at the second comparator output in response to the voltage at the first comparator input being less than the voltage at the second comparator input, and to provide a logic high signal at the second comparator output in response to the voltage at the first comparator input being greater than or equal to the voltage at the second comparator input; A high-side switching transistor, which has a drain terminal and a source terminal, the drain terminal is coupled to the output voltage terminal, and the source terminal is coupled to the input voltage terminal; A first transistor, which has a drain terminal, a source terminal, and a gate terminal, the drain terminal is coupled to the gate terminal of the high-side switching transistor via a diode, the source terminal is coupled to the input voltage terminal, the gate terminal is coupled to the first comparator output, the anode of the diode is coupled to the drain terminal of the first transistor and its cathode is coupled to the gate terminal of the high-side switching transistor; A second transistor having a drain terminal, a source terminal, and a gate terminal, the drain terminal being coupled to the gate terminal of the high-side switching transistor via a resistor, the source terminal being coupled to a ground terminal, and the gate terminal being coupled to the second comparator output; A high-side driver circuit having a high-side driver circuit input, a high-side driver circuit output, and a high-side driver circuit enable input, the high-side driver circuit output being coupled to the cathode of the diode and the gate terminal of the high-side switching transistor, and the high-side driver circuit enable input being coupled to the second comparator output; A low-side transistor having a drain terminal and a source terminal, the drain terminal being coupled to the input voltage terminal and the source terminal being coupled to the ground terminal; And A pulse width modulation (PWM) controller having a high-side output and a low-side output, the high-side output being coupled to the high-side driver circuit input, and the low-side output being coupled to the gate terminal of the low-side transistor.

12. The power supply circuit according to claim 11, wherein the high-side switching transistor is an n-channel power field effect transistor (FET), and its body terminal is coupled to its drain terminal via a resistor.

13. The power supply circuit according to claim 11, wherein the power supply circuit is a DC-DC boost converter circuit.

14. An integrated circuit package including the power supply circuit according to claim 11.

15. A comparator circuit comprising: A first input terminal for receiving an input voltage of a power supply circuit; A second input terminal for receiving an output voltage of the power supply circuit; A first output terminal for providing the larger of the input voltage or the output voltage; And A second output terminal for providing a logic low signal in response to the input voltage being less than the output voltage, and providing a logic high signal in response to the input voltage being greater than or equal to the output voltage.

16. The comparator circuit according to claim 15, further comprising: An amplifier having a non-inverting input, an inverting input, and an amplifier output, the non-inverting input being coupled to the first input terminal, the inverting input being coupled to the second input terminal, and the amplifier output being coupled to the second output terminal; A first switch for switching the input voltage to the first output terminal and having a first switch control terminal coupled to the amplifier output; A second switch for switching the output voltage to the first output terminal and having a second switch control terminal; And An inverter having an inverter input and an inverter output, the inverter input being coupled to the amplifier output, and the inverter output being coupled to the second switch control terminal.

17. A power supply circuit including the comparator circuit according to claim 15, wherein the first input terminal is coupled to an input voltage terminal of the power supply circuit, and the second input terminal is coupled to an output voltage terminal of the power supply circuit.

18. The power supply circuit according to claim 17, further comprising: A power converter circuit, which includes a low-side switching element, a high-side switching element, and a high-side driver circuit. The low-side switching element has a low-side control terminal, and the high-side switching element has a high-side control terminal coupled to the output terminal of the high-side driver circuit. And the second output terminal of the comparator circuit is coupled to the enable input of the high-side driver circuit; And A pulse width modulation (PWM) controller, which has a high-side output and a low-side output. The low-side output is coupled to the low-side control terminal of the low-side switching element, and the high-side output is coupled to the input terminal of the high-side driver circuit.

19. The power supply circuit according to claim 18, wherein the power converter circuit further includes: A first transistor, which has a drain terminal, a source terminal, and a gate terminal. The drain terminal is coupled to the high-side control terminal of the high-side switching element via a diode. The source terminal is coupled to the input voltage terminal, and the gate terminal is coupled to the first output terminal of the comparator circuit. The anode of the diode is coupled to the drain terminal of the first transistor, and its cathode is coupled to the gate terminal of the high-side control terminal of the high-side switching element; And A second transistor, which has a drain terminal, a source terminal, and a gate terminal. The drain terminal is coupled to the high-side control terminal of the high-side switching element via a resistor. The source terminal is coupled to the ground terminal, and the gate terminal is coupled to the second output terminal of the comparator circuit.

20. The power supply circuit according to claim 17, wherein the power supply circuit is a DC-DC boost converter circuit.

21. An integrated circuit package, which includes the comparator circuit according to claim 15.

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