Three-dimensional memory devices including trench bridge structures having different volumes and methods of forming same

Abstract

A three-dimensional memory device includes: at least one alternating stack of insulating layers and conductive layers; a memory opening extending vertically through the at least one alternating stack; a memory opening filling structure in the memory opening; and a laterally extending trench filling structure contacting the at least one alternately stacked first longitudinal sidewall and comprising: a first type dielectric bridge structure having a first volume; a second type dielectric bridge structure having a second volume, the second volume being greater than the first volume; and a trench dielectric material portion.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of U.S. Non - Provisional Application No. 18 / 450,150, filed on August 15, 2023, entitled "THREE - DIMENSIONAL MEMORY DEVICE INCLUDING TRENCH BRIDGE STRUCTURES HAVING DIFFERENT VOLUMES AND METHODS OF FORMING THE SAME", and hereby incorporates by reference in its entirety the U.S. Non - Provisional Application for all purposes. The U.S. Non - Provisional Application claims the priority of U.S. Provisional Application No. 63 / 467,848, filed on May 19, 2023. Technical field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three - dimensional memory devices including trench bridge structures having different volumes and methods of forming the same. Background art

[0004] A three - dimensional vertical NAND string having one bit per cell is disclosed in the article by T. Endoh et al., entitled "Novel Ultra High Density Memory With A Stacked - Surrounding Gate Transistor (S - SGT) Structured Cell", Proceedings of the IEDM (2001), pages 33 - 36. Summary of the invention

[0005] According to one aspect of the present disclosure, a three-dimensional memory device includes: at least one alternating stack of insulating layers and conductive layers, the at least one alternating stack having a first longitudinal sidewall and a second longitudinal sidewall that extend laterally along a first horizontal direction; a memory opening that extends vertically through the at least one alternating stack; a memory opening fill structure located in the memory opening, wherein each memory opening fill structure in the memory opening fill structure includes a vertical semiconductor channel and a corresponding vertical stack of memory elements at respective levels of the conductive layer; and a first laterally extending trench fill structure that contacts the first longitudinal sidewall of the at least one alternating stack and includes: a first type of dielectric bridge structure having a first volume; a second type of dielectric bridge structure having a second volume, the second volume being greater than the first volume; and a first trench dielectric material portion.

[0006] According to another aspect of the present disclosure, a three-dimensional memory device includes: at least one alternating stack of insulating layers and conductive layers, the at least one alternating stack having a first longitudinal sidewall and a second longitudinal sidewall that extend laterally along a first horizontal direction; a memory opening that extends vertically through the at least one alternating stack; a memory opening fill structure located in the memory opening, wherein each memory opening fill structure in the memory opening fill structure includes a vertical semiconductor channel and a corresponding vertical stack of memory elements at respective levels of the conductive layer; and a first laterally extending trench fill structure that contacts the first longitudinal sidewall of the at least one alternating stack and includes: a first trench dielectric material portion; a plurality of the first type of dielectric bridge structures having a first volume and a first pitch; and a plurality of the second type of dielectric bridge structures having a second volume and a second pitch, the second volume being greater than the first volume, the second pitch being less than the first pitch.

[0007] According to another aspect of the present disclosure, a method of forming a three-dimensional memory device includes: forming at least one vertical alternating sequence of an insulating layer and a sacrificial material layer over a substrate; forming a memory opening through the at least one vertical alternating sequence; forming a memory opening fill structure in the memory opening, wherein each memory opening fill structure in the memory opening fill structure includes a vertical semiconductor channel and a corresponding vertical stack of memory elements; forming a laterally extending trench through the at least one vertical alternating sequence, the laterally extending trench including a first laterally extending trench and a second laterally extending trench; forming a first sacrificial laterally extending trench fill structure and a second sacrificial laterally extending trench fill structure in the first laterally extending trench and the second laterally extending trench, respectively; forming a first type of recess cavity having a first volume and a second type of recess cavity having a second volume by recessing portions of the first sacrificial laterally extending trench fill structure, wherein the second volume is greater than the first volume; forming a first type of dielectric bridge structure and a second type of dielectric bridge structure in the first type of recess cavity and the second type of recess cavity, respectively; removing the first sacrificial laterally extending trench fill structure and the second sacrificial laterally extending trench fill structure; and replacing a remaining portion of the sacrificial material layer with a conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a plan view of a configuration of an exemplary semiconductor die including a plurality of three-dimensional memory array regions according to an embodiment of the present disclosure.

[0009] Figures 2A to 2D are various views of an exemplary structure after forming a first vertical alternating sequence of a first insulating layer and a first sacrificial material layer, a first stepped surface, and a first backward stepped dielectric material portion according to an embodiment of the present disclosure. Figure 2A is a top-down view. Figure 2B is along Figure 2A vertical plane B-B' of Figure 2C is along Figure 2A vertical plane C-C' of Figure 2D is along Figure 2D vertical plane D-D' of

[0010] Figures 3A to 3E are various views of an exemplary structure after forming a first sacrificial memory opening fill structure according to an embodiment of the present disclosure. Figure 3A is a top-down view. Figure 3B is along Figure 3A vertical plane B-B' of Figure 3C is along Figure 3A vertical plane C-C' of Figure 3D is alongFigure 3D Vertical sectional view of the vertical plane D-D'. Figure 3E is along Figure 3E Vertical sectional view of the vertical plane E-E'.

[0011] Figures 4A to 4F Various views of an exemplary structure after forming a second vertical alternating sequence of a second insulating layer and a second sacrificial material layer, a second stepped surface, a second backward stepped dielectric material portion, and a second sacrificial memory opening filling structure according to an embodiment of the present disclosure. Figure 4A Is a top-down view. Figure 4B is along Figure 4A Vertical sectional view of the vertical plane B-B'. Figure 4C is along Figure 4A Vertical sectional view of the vertical plane C-C'. Figure 4D is along Figure 4D Vertical sectional view of the vertical plane D-D'. Figure 4E is along Figure 4E Vertical sectional view of the vertical plane E-E'. Figure 4F is along Figure 4F Vertical sectional view of the vertical plane F-F'.

[0012] Figures 5A to 5F Various views of an exemplary structure after forming a third vertical alternating sequence of a third insulating layer and a third sacrificial material layer, a third stepped surface, a third backward stepped dielectric material portion, and a third memory opening according to an embodiment of the present disclosure. Figure 5A Is a top-down view. Figure 5B is along Figure 5A Vertical sectional view of the vertical plane B-B'. Figure 5C is along Figure 5A Vertical sectional view of the vertical plane C-C'. Figure 5D is along Figure 5D Vertical sectional view of the vertical plane D-D'. Figure 5E is along Figure 5E Vertical sectional view of the vertical plane E-E'. Figure 5F is along Figure 5F Vertical sectional view of the vertical plane F-F'.

[0013] Figures 6A to 6F Various views of an exemplary structure after forming an interlayer memory opening according to an embodiment of the present disclosure. Figure 6A Is a top-down view. Figure 6B is along Figure 6A Vertical sectional view of the vertical plane B-B'. Figure 6C is along Figure 6AVertical sectional view of the vertical plane C-C'. Figure 6D is the vertical sectional view of the vertical plane D-D' along Figure 6D of. Figure 6E is the vertical sectional view of the vertical plane E-E' along Figure 6E of. Figure 6F is the vertical sectional view of the vertical plane F-F' along Figure 6F of.

[0014] Figures 7A to 7F Illustrates sequential vertical sectional views of a memory opening during formation of a memory opening fill structure according to an embodiment of the present disclosure.

[0015] Figures 8A to 8F Are various views of an exemplary structure after formation of a memory opening fill structure according to an embodiment of the present disclosure. Figure 8A Is a top-down view. Figure 8B is the vertical sectional view of the vertical plane B-B' along Figure 8A of. Figure 8C is the vertical sectional view of the vertical plane C-C' along Figure 8A of. Figure 8D is the vertical sectional view of the vertical plane D-D' along Figure 8D of. Figure 8E is the vertical sectional view of the vertical plane E-E' along Figure 8E of. Figure 8F is the vertical sectional view of the vertical plane F-F' along Figure 8F of.

[0016] Figures 9A to 9H Are various views of an exemplary structure after formation of a laterally extending trench according to an embodiment of the present disclosure. Figure 9A Is a top-down view. Figure 9B is the vertical sectional view of the vertical plane B-B' along Figure 9A of. Figure 9C is the vertical sectional view of the vertical plane C-C' along Figure 9A of. Figure 9D is the vertical sectional view of the vertical plane D-D' along Figure 9D of. Figure 9E is the vertical sectional view of the vertical plane E-E' along Figure 9E of. Figure 9F is the vertical sectional view of the vertical plane F-F' along Figure 9F of. Figure 9G is the vertical sectional view of the vertical plane F-F' along Figure 9G of. Figure 9H is the vertical sectional view of the vertical plane F-F' along Figure 9H of.

[0017] Figures 10A to 10H These are various views of an exemplary structure after forming a sacrificial laterally extending trench fill structure according to an embodiment of the present disclosure. Figure 10A This is a top-down view. Figure 10B This is a vertical cross-sectional view along the Figure 10A vertical plane B-B'. Figure 10C This is a vertical cross-sectional view along the Figure 10A vertical plane C-C'. Figure 10D This is a vertical cross-sectional view along the Figure 10D vertical plane D-D'. Figure 10E This is a vertical cross-sectional view along the Figure 10E vertical plane E-E'. Figure 10F This is a vertical cross-sectional view along the Figure 10F vertical plane F-F'. Figure 10G This is a vertical cross-sectional view along the Figure 10G vertical plane F-F'. Figure 10H This is a vertical cross-sectional view along the Figure 10H vertical plane F-F'.

[0018] Figures 11A to 11H These are various views of an exemplary structure after forming a recess cavity in a sacrificial laterally extending trench fill structure according to an embodiment of the present disclosure. Figure 11A This is a top-down view. Figure 11B This is a vertical cross-sectional view along the Figure 11A vertical plane B-B'. Figure 11C This is a vertical cross-sectional view along the Figure 11A vertical plane C-C'. Figure 11D This is a vertical cross-sectional view along the Figure 11D vertical plane D-D'. Figure 11E This is a vertical cross-sectional view along the Figure 11E vertical plane E-E'. Figure 11F This is a vertical cross-sectional view along the Figure 11F vertical plane F-F'. Figure 11G This is a vertical cross-sectional view along the Figure 11G vertical plane F-F'. Figure 11H This is a vertical cross-sectional view along the Figure 11H vertical plane F-F'.

[0019] Figures 12A to 12H These are various views of an exemplary structure after vertically extending a second type of recess cavity according to an embodiment of the present disclosure. Figure 12A This is a top-down view. Figure 12B This is a vertical cross-sectional view along the Figure 12A vertical plane B-B'. Figure 12C This is a vertical cross-sectional view along the Figure 12A vertical plane C-C'.Figure 12D is a vertical sectional view along the vertical plane D-D’ of Figure 12D . Figure 12E is a vertical sectional view along the vertical plane E-E’ of Figure 12E . Figure 12F is a vertical sectional view along the vertical plane F-F’ of Figure 12F . Figure 12G is a vertical sectional view along the vertical plane F-F’ of Figure 12G . Figure 12H is a vertical sectional view along the vertical plane F-F’ of Figure 12H .

[0020] Figures 13A to 13H are various views of an exemplary structure after vertically extending a third type of groove cavity according to an embodiment of the present disclosure. Figure 13A is a top-down view. Figure 13B is a vertical sectional view along the vertical plane B-B’ of Figure 13A . Figure 13C is a vertical sectional view along the vertical plane C-C’ of Figure 13A . Figure 13D is a vertical sectional view along the vertical plane D-D’ of Figure 13D . Figure 13E is a vertical sectional view along the vertical plane E-E’ of Figure 13E . Figure 13F is a vertical sectional view along the vertical plane F-F’ of Figure 13F . Figure 13G is a vertical sectional view along the vertical plane F-F’ of Figure 13G . Figure 13H is a vertical sectional view along the vertical plane F-F’ of Figure 13H .

[0021] Figures 14A to 14J are various views of an exemplary structure after forming a dielectric bridge structure according to an embodiment of the present disclosure. Figure 14A is a top-down view. Figure 14B is a vertical sectional view along the vertical plane B-B’ of Figure 14A . Figure 14C is a vertical sectional view along the vertical plane C-C’ of Figure 14A . Figure 14D is a vertical sectional view along the vertical plane D-D’ of Figure 14D . Figure 14E is a vertical sectional view along the vertical plane E-E’ of Figure 14E . Figure 14F is a vertical sectional view along the vertical plane F-F’ of Figure 14F . Figure 14G is a vertical sectional view along the vertical plane F-F’ of Figure 14G .

[0022] Figure 14H is a vertical cross-section along the Figure 14H vertical plane F-F'. Figure 14I and Figure 14J is a top-down view of an alternative embodiment of the exemplary structure.

[0023] Figures 15A to 15H are various views of the exemplary structure after removal of the sacrificial laterally-extending trench fill structure according to an embodiment of the present disclosure. Figure 15A is a top-down view. Figure 15B is along Figure 15A vertical plane B-B'. Figure 15C is along Figure 15A vertical plane C-C'. Figure 15D is along Figure 15D vertical plane D-D'. Figure 15E is along Figure 15E vertical plane E-E'. Figure 15F is along Figure 15F vertical plane F-F'. Figure 15G is along Figure 15G vertical plane F-F'. Figure 15H is along Figure 15H vertical plane F-F'.

[0024] Figures 16A to 16H are various views of the exemplary structure after formation of the lateral grooves according to an embodiment of the present disclosure. Figure 16A is a top-down view. Figure 16B is along Figure 16A vertical plane B-B'. Figure 16C is along Figure 16A vertical plane C-C'. Figure 16D is along Figure 16D vertical plane D-D'. Figure 16E is along Figure 16E vertical plane E-E'. Figure 16F is along Figure 16F vertical plane F-F'. Figure 16G is along Figure 16G vertical plane F-F'. Figure 16H is along Figure 16H vertical plane F-F'.

[0025] Figures 17A to 17HAre various views of an exemplary structure after forming a conductive layer according to an embodiment of the present disclosure. Figure 17A Is a top-down view. Figure 17B Is along Figure 17A Vertical sectional view of the vertical plane B-B'. Figure 17C Is along Figure 17A Vertical sectional view of the vertical plane C-C'. Figure 17D Is along Figure 17D Vertical sectional view of the vertical plane D-D'. Figure 17E Is along Figure 17E Vertical sectional view of the vertical plane E-E'. Figure 17F Is along Figure 17F Vertical sectional view of the vertical plane F-F'. Figure 17G Is along Figure 17G Vertical sectional view of the vertical plane F-F'. Figure 17H Is along Figure 17H Vertical sectional view of the vertical plane F-F'.

[0026] Figures 18A to 18H Are various views of an exemplary structure after forming a laterally extending trench filling structure according to an embodiment of the present disclosure. Figure 18A Is a top-down view. Figure 18B Is along Figure 18A Vertical sectional view of the vertical plane B-B'. Figure 18C Is along Figure 18A Vertical sectional view of the vertical plane C-C'. Figure 18D Is along Figure 18D Vertical sectional view of the vertical plane D-D'.

[0027] Figure 18E Is along Figure 18E Vertical sectional view of the vertical plane E-E'. Figure 18F Is along Figure 18F Vertical sectional view of the vertical plane F-F'. Figure 18G Is along Figure 18G Vertical sectional view of the vertical plane F-F'. Figure 18H Is along Figure 18H Vertical sectional view of the vertical plane F-F'.

[0028] Figures 19A to 19H Are various views of an exemplary structure after forming various contact via structures according to an embodiment of the present disclosure. Figure 19A Is a top-down view. Figure 19B Is along Figure 19A Vertical sectional view of the vertical plane B-B'. Figure 19C Is along Figure 19A Vertical sectional view of the vertical plane C-C'.Figure 19D is a vertical sectional view along the vertical plane D-D’ of Figure 19D . Figure 19E is a vertical sectional view along the vertical plane E-E’ of Figure 19E . Figure 19F is a vertical sectional view along the vertical plane F-F’ of Figure 19F . Figure 19G is a vertical sectional view along the vertical plane F-F’ of Figure 19G . Figure 19H is a vertical sectional view along the vertical plane F-F’ of Figure 19H .

[0029] Figure 20 is a vertical sectional view of an exemplary structure after forming a memory die and attaching a logic die to the memory die according to an embodiment of the present disclosure.

[0030] Figure 21 is a vertical sectional view of a first alternative configuration of an exemplary structure according to an embodiment of the present disclosure.

[0031] Figure 22 is a vertical sectional view of a second alternative configuration of an exemplary structure according to an embodiment of the present disclosure.

[0032] Figure 23 is a vertical sectional view of a second alternative configuration of an exemplary structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] As discussed above, the present disclosure relates to three-dimensional memory devices including trench bridge structures having different volumes (e.g., different thicknesses, lengths, and / or widths) and / or different spacings (i.e., bridge lengths and intervals between bridges) in different regions, and methods of forming the same, aspects of which are described below. Embodiments of the present disclosure can be used to form three-dimensional memory array devices including a plurality of NAND memory strings.

[0034] The drawings are not drawn to scale. Multiple instances of an element may be replicated in the case of illustrating a single instance of the element, unless otherwise explicitly described or clearly indicated that there is no replication of the element. Ordinal numbers such as “first,” “second,” and “third” are only used to identify similar elements, and different ordinal numbers may be used in the specification and claims of the present disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0035] Like reference numerals designate like or similar elements. Unless otherwise specified, elements with like reference numerals are considered to have the same composition and the same function. Unless otherwise specified, "contact" between elements means direct contact providing an edge or surface shared by the elements. If two or more elements do not contact each other directly or do not contact each other directly, the two elements are "separated" from each other or are "separated" from each other. As used herein, an element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, an element is "directly" located "on" a second element if there is physical contact between the surface of the element and the surface of the second element. As used herein, an element is "electrically connected to" a second element if there is an electrical conduction path composed of at least one conductive material between the element and the second element. As used herein, a "prototype" structure or a "work-in-progress" structure refers to a transient structure that is subsequently modified in shape or composition of at least one of its components.

[0036] As used herein, a "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure, or its extent may be less than the extent of the underlying or overlying structure. Additionally, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top surface and the bottom surface of a continuous structure or at the top surface and the bottom surface. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers on, above, and / or below it.

[0037] Generally, a semiconductor die or a semiconductor package may include memory chips. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (usually one or two). Despite some limitations, the same, concurrent operations can be performed on each plane. Each plane contains a plurality of blocks, which are the smallest units that can be erased in a single erase operation. Each block contains a plurality of pages, which are the smallest programmable units, i.e., the smallest units on which a read operation can be performed.

[0038] As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0x10 -5 S / m to 1.0x10 5 S / m. As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0x10 -5Materials in the range of 1.0 S / m to 1.0 S / m, and after being appropriately doped with an electrical dopant, can produce a doped material with a conductivity in the range of 1.0 S / m to 1.0x10 7 S / m. As used herein, an "electrical dopant" is a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, a "conductive material" is a material with a conductivity greater than 1.0x10 5 S / m. As used herein, an "insulating material" or "dielectric material" is a material with a conductivity less than 1.0x10 -5 S / m. As used herein, a "heavily doped semiconductor material" is a semiconductor material doped with an electrical dopant at a high enough atomic concentration to become a conductive material, which is formed as a crystalline material or transformed into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., providing a conductivity greater than 1.0x10 5 S / m. A "doped semiconductor material" can be a heavily doped semiconductor material or a semiconductor material including an electrical dopant (i.e., a p-type dopant and / or an n-type dopant), and the concentration of these electrical dopants provides a conductivity in the range of 1.0x10 -5 S / m to 1.0x10 7 S / m. An "intrinsic semiconductor material" is a semiconductor material not doped with an electrical dopant. Thus, a semiconductor material can be semiconductor or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconductor or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "metallic material" is a conductive material containing at least one metallic element. All conductivity measurements are performed under standard conditions.

[0039] According to one aspect of the present disclosure, a dielectric bridge structure with different vertical ranges is provided in a laterally extending trench to provide enhanced structural support to a stack of an insulating layer and a memory opening filling structure during replacement of a sacrificial material layer with a conductive layer.

[0040] Reference Figure 1, illustrates an exemplary semiconductor die according to an embodiment of the present disclosure, which exemplary semiconductor die may be a memory die 900. The memory die 900 includes a plurality of three-dimensional memory array regions and a plurality of inter-array regions. The memory die 900 may include a plurality of planes 300 (e.g., 300A, 300B), each of the plurality of planes including two memory array regions 100, such as a first memory array region 100A and a second memory array region 100B laterally spaced apart by a respective contact region 200. Generally, the memory die 900 may include a single plane 300 or a plurality of planes. The total number of planes in the memory die 900 may be selected based on the performance requirements of the memory die 900. A pair of memory array regions 100 in the plane 300 may be laterally spaced apart by the contact region 200 along a first horizontal direction hd1 (which may be a word line direction). A second horizontal direction hd2 (which may be a bit line direction) may be perpendicular to the first horizontal direction hd1.

[0041] Reference Figures 2A to 2D , illustrates an exemplary structure of the memory die 900 for forming Figure 1 at an initial stage of the manufacturing process. Figures 2A to 2D The illustrated region of Figure 1 corresponds to region M1 in

[0042] The exemplary structure may include a substrate 9, and optionally include at least one lower dielectric material layer 660 and a semiconductor material layer 110. The substrate 9 may be incorporated into the final device structure or may be a carrier substrate that is subsequently removed. In the case where the substrate 9 is incorporated into the final device structure, the substrate 9 may include a single crystal silicon substrate. In this case, optional semiconductor devices, such as field effect transistors and passive devices, may be formed on the top surface of the substrate 9. The semiconductor devices may be used as a first peripheral circuit for controlling the operation of the subsequently formed three-dimensional memory device. Alternatively, the substrate 9 may be a carrier substrate that is subsequently removed. In one embodiment, the substrate may include a commercially available silicon substrate. Optional peripheral circuitry 920 may be located on the substrate 9 and may include word line switching devices and / or bit line driver devices, such as sense amplifiers, configured to control the bias voltage to the respective word lines.

[0043] At least one lower dielectric material layer 660 may optionally be formed over the substrate 9. In the case where a semiconductor device is formed on the top surface of the substrate 9, a lower metal interconnect structure, such as a metal via structure and a metal line structure, may be formed in the at least one lower dielectric material layer 660. Although an embodiment is described in which the lower metal interconnect structure is formed in the at least one lower dielectric material layer 660, an alternative embodiment in which the lower metal interconnect structure is not formed in the at least one lower dielectric material layer 660 is clearly contemplated.

[0044] A semiconductor material layer 110 may optionally be formed over the at least one lower dielectric material layer 660. The semiconductor material layer 110 may include a single-crystalline semiconductor material or a polycrystalline semiconductor material, such as single-crystalline silicon or polycrystalline silicon. In one embodiment, the semiconductor material layer 110 may include a source-level material layer or an in-process source-level material layer, which are provided with a source contact layer or are at least partially replaced by a source contact layer. Alternatively, the semiconductor material layer 110 may at least partially serve as a horizontal channel layer. Yet alternatively, the semiconductor material layer 110 may be omitted or subsequently removed. Generally, for the combination of the substrate 9, the at least one lower dielectric material layer 660, and the at least one optional semiconductor material layer 110, various configurations may be employed, and each component in the combination may become a permanent component of the final device structure or may be removed from the final device structure.

[0045] A first vertical alternating sequence (i.e., a first alternating stack) of a first insulating layer 132 and a first sacrificial material layer 142 may be formed over the substrate 9 (e.g., over the semiconductor material layer 110 if present). As used herein, a "vertical alternating sequence" or "alternating stack" refers to a sequence of a plurality of instances of a first element and a plurality of instances of a second element, which are arranged such that instances of the second element are located between each pair of vertically adjacent instances of the first element, and instances of the first element are located between each pair of vertically adjacent instances of the second element.

[0046] The first insulating layer 132 may be composed of a first material, and the first sacrificial material layer 142 may be composed of a second material different from the first material. Each first insulating layer in the first insulating layer 132 is an insulating layer that continuously extends over the entire area of the substrate 9 and may have a uniform thickness over the entire area. Each first sacrificial material layer in the first sacrificial material layer 142 is a sacrificial material layer including a dielectric material and continuously extending over the entire area of the substrate 9 and may have a uniform thickness over the entire area. Insulating materials that can be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides generally referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0047] The second material of the first sacrificial material layer 142 is a sacrificial material that can be selectively removed relative to the first material of the first insulating layer 132. As used herein, if the removal process removes the first material at a rate that is at least twice the removal rate of the second material, the removal of the first material is "selective" relative to the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0048] The second material of the first sacrificial material layer 142 may subsequently be replaced with a conductive electrode. For example, these conductive electrodes may act as control gate electrodes of a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may be a material layer including silicon nitride. The first vertical alternating sequence of the first insulating layer 132 and the first sacrificial material layer 142 is used to form a first layer structure and may also be referred to as the first layer vertical alternating sequence (132, 142).

[0049] A step including the first stepped surface "S" may be formed within the stepped region of the contact region 200, and this stepped region will be filled with the first layer of back stepped dielectric material portion 165. For example, a combination of a sacrificial hard mask layer and a trimming mask layer may be used to form the first stepped surface. In one embodiment, a row of multiple first stepped regions may be formed within each region corresponding to a combination of a region of a pair of laterally adjacent first layer back stepped dielectric material portions 165 and an intermediate region. In this case, by subsequently performing a region trench etching process, the multiple first stepped regions may subsequently be vertically offset by different depths.

[0050] In an illustrative example, 2 MA first stepped surface of a group may be formed within a combination of regions and an intermediate region of a pair of laterally adjacent first layer back stepped dielectric material portions 165. M may be an integer in the range of 1 to 8. Each group of first stepped steps may include P steps such that sidewalls of P first consecutive spacer material layers are physically exposed with a lateral offset. P may be an integer from 2 to 64. An area trench etching process may be performed M times such that each area trench etching process vertically recesses P times 2 i A first insulating layer 132 and a first sacrificial material layer 142, where i is a different integer from 0 to (M - 1). For a first vertical alternating sequence of the first insulating layer 132 and the first sacrificial material layer 142, a total of up to 2 M xP stepped surfaces may be formed. The total number of stepped surfaces within each consecutive cavity covering the first stepped surface may be the same as the total number of the first sacrificial material layers 142 in the first vertical alternating sequence (132, 142). An alternative process sequence for forming the first stepped surface in the first region may also be employed.

[0051] A first dielectric fill material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) may be deposited in each first consecutive back stepped cavity. The first dielectric fill material may be planarized to remove an excess portion of the first dielectric fill material above a horizontal plane including the topmost surface of the first vertical alternating sequence (132, 142). Each remaining portion of the first dielectric fill material filling the corresponding first consecutive back stepped cavity constitutes a first layer back stepped dielectric material portion 165. Generally, the first layer back stepped dielectric material portion 165 may be formed in a contact region 200 located between a corresponding first memory array region 100A and a corresponding second memory array region 100B, and the corresponding first memory array region and the corresponding second memory array region are laterally spaced apart along a first horizontal direction hd1. The first stepped surface contacts a stepped bottom surface of the corresponding first back stepped dielectric material portion 165.

[0052] Reference Figures 3A to 3E, can pass through the first vertical alternating sequence (132, 142) and enter the semiconductor material layer 110 to form various first-layer openings. For simplicity, the optional peripheral circuit 920 is not illustrated in these figures and the subsequent figures. A photoresist layer (not shown) can be applied over the first vertical alternating sequence (132, 142), and it can be lithographically patterned to form various openings therethrough. The pattern of the openings in the photoresist layer can be transferred through the first vertical alternating sequence (132, 142) and into the semiconductor material layer 110 by a first anisotropic etching process to concurrently (i.e., during the first isotropic etching process) form various first-layer openings. The various first-layer openings can include first-layer memory openings formed in the memory array region 100 and first-layer support openings formed in the contact region 200. For simplicity, the first-layer support openings are not illustrated. Each cluster of the first-layer memory openings can be formed as a two-dimensional array of the first-layer memory openings. The first-layer support openings are openings formed in the contact region 200 and subsequently used to form support pillar structures. A subset of the first-layer support openings can be formed through the respective horizontal surfaces of the first stepped surface.

[0053] A sacrificial first-layer opening fill portion can be formed in the various first-layer openings. For example, a sacrificial first-layer fill material is concurrently deposited in each of the first-layer openings in the first-layer openings. The sacrificial first-layer fill material includes a material that can be subsequently selectively removed relative to the materials of the first insulating layer 132 and the first sacrificial material layer 142. In one embodiment, the sacrificial first-layer fill material can include a semiconductor material such as silicon (e.g., a-Si or polysilicon), a silicon-germanium alloy, germanium, a III-V group compound semiconductor material, or a combination thereof. Optionally, a thin etch stop liner (such as a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) can be used before depositing the sacrificial first-layer fill material. The sacrificial first-layer fill material can be formed by a non-conformal deposition method or a conformal deposition method.

[0054] In another embodiment, the sacrificial first-layer fill material can include a silicon oxide material having an etching rate higher than that of the material of the first insulating layer 132. For example, the sacrificial first-layer fill material can include borosilicate glass or porous organosilicate glass or non-porous organosilicate glass, the etching rate of which is at least 100 times higher than that of the densified TEOS oxide (i.e., the silicon oxide material formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and then densifying in an annealing process) in 100:1 diluted hydrofluoric acid. In this case, a thin etch stop liner (such as a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) can be used before depositing the sacrificial first-layer fill material. The sacrificial first-layer fill material can be formed by a non-conformal deposition method or a conformal deposition method.

[0055] In yet another embodiment, the first sacrificial fill material may include a carbon-containing material (such as amorphous carbon or diamond-like carbon) that can be subsequently removed by ashing, or a silicon-based polymer that can be subsequently selectively removed relative to the materials of the first vertical alternating sequence (132, 142).

[0056] Portions of the deposited first sacrificial fill material can be removed above the topmost layer of the first vertical alternating sequence (132, 142), such as above the topmost first insulating layer 132. For example, a planarization process can be used to recess the first sacrificial fill material into the top surface of the topmost first insulating layer 132. The planarization process can include trench etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the topmost first insulating layer 132 can be used as an etch stop layer or a planarization stop layer.

[0057] The remaining portions of the first sacrificial fill material include first sacrificial opening fill portions. Specifically, each remaining portion of the first sacrificial fill material in the first layer memory openings constitutes a first sacrificial layer memory opening fill portion 148. Each remaining portion of the first sacrificial fill material in the first layer support openings constitutes a first sacrificial layer support opening fill portion (not illustrated). The various first sacrificial opening fill portions are formed concurrently, i.e., during the same set of processes that include a deposition process of depositing the first sacrificial fill material and a planarization process of removing the first layer deposition process above the first vertical alternating sequence (132, 142), such as above the top surface of the topmost first insulating layer 132. The top surfaces of the first sacrificial opening fill portions can be coplanar with the top surface of the topmost first insulating layer 132. Each of the first sacrificial opening fill portions in the first sacrificial opening fill portions may or may not include a cavity therein. The set of all structures located between the bottommost surface and the topmost surface of the first vertical alternating sequence (132, 142) or embedded within the first vertical alternating sequence (132, 142) constitutes the first layer structure.

[0058] Reference Figures 4A to 4F , a second vertical alternating sequence of a second insulating layer 232 and a second sacrificial material layer 242 can be formed. Each second insulating layer in the second insulating layer 232 is an insulating layer that continuously extends above the entire region of the substrate 9 and can have a uniform thickness throughout the region. Each second sacrificial material layer in the second sacrificial material layer 242 includes a sacrificial material and continuously extends above the entire region of the substrate 9 and can have a uniform thickness throughout the region. The second insulating layer 232 can have the same material composition and the same thickness as the first insulating layer 132. The second sacrificial material layer 242 can have the same material composition and the same thickness as the first sacrificial material layer 142.

[0059] Typically, at least one additional vertical alternating sequence of an additional insulating layer and an additional sacrificial material layer may optionally be formed over the first vertical alternating sequence (132, 142) and the first layer back stepped dielectric material portion 165.

[0060] A second stepped surface may be formed within a stepped region of the contact region 200, which stepped region will be filled with a second layer back stepped dielectric material portion 265. For example, a combination of a sacrificial hard mask layer and a trimming mask layer may be used to form the second stepped surface. In one embodiment, a row of multiple second stepped regions may be formed within each region corresponding to a combination of regions of a pair of laterally adjacent second layer back stepped dielectric material portions 265 and an intermediate region. In such a case, by subsequently performing a regional recess etching process, the multiple second stepped regions may then be vertically offset by different depths. A set of process steps similar to the set of process steps used to form the first stepped surface may be used to form the second stepped surface. The second stepped surface may be laterally offset from the first stepped surface. The total number of stepped surfaces within each successive cavity covering the second stepped surface may be the same as the total number of second sacrificial material layers 242 in the second vertical alternating sequence (232, 242).

[0061] A second dielectric fill material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) may be deposited within each second successive back stepped cavity. The second dielectric fill material may be planarized to remove excess portions of the second dielectric fill material above a horizontal plane including the topmost surface of the second vertical alternating sequence (232, 242). Each remaining portion of the second dielectric fill material filling the corresponding second successive back stepped cavity constitutes a second layer back stepped dielectric material portion 265. The second stepped surface contacts the stepped bottom surface of the corresponding second back stepped dielectric material portion 265.

[0062] Typically, a second layer structure is formed that includes a second vertical alternating sequence of a second insulating layer 232 and a second sacrificial material layer 242, and a second layer back stepped dielectric material portion 265 covering the second stepped surface of the second vertical alternating sequence located within the contact region 200.

[0063] Various second layer openings may be formed through the second vertical alternating sequence (232, 242) and over the sacrificial first layer opening fill portions. A photoresist layer (not shown) may be applied over the second vertical alternating sequence (232, 242), and it may be lithographically patterned to form various openings therethrough. The opening pattern in the photoresist layer may be transferred through the second vertical alternating sequence (232, 242) to concurrently (i.e., during a second isotropic etching process) form various second layer openings.

[0064] The various second layer openings may include second layer memory openings formed in the memory array region 100 and second layer support openings (not illustrated) formed in the contact region 200. Each second layer opening may be formed within a corresponding region of the sacrificial first layer opening fill portion in the sacrificial first layer opening fill portion. Thus, the top surface of the sacrificial first layer opening fill portion may be physically exposed at the bottom of each second layer opening. Specifically, each second layer memory opening may be formed directly above a corresponding sacrificial first layer memory opening fill portion 148, and each second layer support opening (not illustrated) may be formed directly above a corresponding sacrificial first layer support opening fill portion (not illustrated). Each cluster of second layer memory openings may be formed as a two-dimensional array of second layer memory openings. The second layer support openings are openings formed in the contact region 200 and subsequently used to form support pillar structures. A subset of the second layer support openings may be formed through corresponding horizontal surfaces of the second stepped surface.

[0065] Sacrificial second layer opening fill portions may be formed in the various second layer openings. For example, sacrificial first layer fill material is concurrently deposited in each of the second layer openings in the second layer openings. The sacrificial second layer fill material may include any material that may be used for the sacrificial first layer fill material. Portions of the deposited sacrificial second layer fill material may be removed from above the topmost layer of the second vertical alternating sequence (232, 242). The remaining portions of the sacrificial second layer fill material include the sacrificial second layer opening fill portions. Specifically, each remaining portion of the sacrificial second layer fill material in the second layer memory openings constitutes a sacrificial second layer memory opening fill portion 248. Each remaining portion of the sacrificial second layer fill material in the first layer support openings constitutes a sacrificial second layer support opening fill portion (not illustrated). The top surface of the sacrificial second layer opening fill portion may be coplanar with the top surface of the topmost second insulating layer 232. Each sacrificial second layer opening fill portion in the sacrificial second layer opening fill portion may or may not include a cavity therein. The collection of all structures located between the bottommost surface of the second vertical alternating sequence (232, 242) and the topmost surface of the second vertical alternating sequence (232, 242) or embedded within the second vertical alternating sequence (232, 242) constitutes the second layer structure.

[0066] Reference Figures 5A to 5F, a third vertical alternating sequence of a third insulating layer 332 and a third sacrificial material layer 342 can be formed. Each third insulating layer in the third insulating layer 332 is an insulating layer that continuously extends over the entire area of the substrate 9 and can have a uniform thickness over the entire area. Each third sacrificial material layer in the third sacrificial material layer 342 includes a sacrificial material, continuously extends over the entire area of the substrate 9, and can have a uniform thickness over the entire area. The third insulating layer 332 can have the same material composition and the same thickness as the first insulating layer 132. The third sacrificial material layer 342 can have the same material composition and the same thickness as the first sacrificial material layer 142.

[0067] A third stepped surface can be formed within a stepped region of the contact region 200, and the stepped region will be filled with a third-layer back stepped dielectric material portion 365. For example, a combination of a sacrificial hard mask layer and a trimming mask layer can be used to form the third stepped surface. The third stepped surface can be laterally offset from the first stepped surface and the second stepped surface. A cavity can be formed above each region of the first stepped surface and the second stepped surface. It should be noted that the stepped direction can be reversed, with the lower portion of the step on the Figure 5B left side, and the upper portion of the step on the right side of this drawing.

[0068] In one embodiment, the stepped direction is symmetric across a plane extending in a second horizontal direction (e.g., bit line direction hd2). Thus, if the first step adjacent to the first memory array region 100A has a lower portion on one side (e.g., on the right side along the first horizontal direction (e.g., word line direction) hd1), the second step adjacent to the second memory array region 100B has a lower portion on the side opposite to the first step region (e.g., on the left side along the first horizontal direction hd1).

[0069] A third dielectric filling material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) can be deposited in each third continuous back stepped cavity. The third dielectric filling material can be planarized to remove the excess portion of the third dielectric filling material above the horizontal plane including the topmost surface of the third vertical alternating sequence (332, 342). Each remaining portion of the third dielectric filling material filling the corresponding third continuous back stepped cavity constitutes the third-layer back stepped dielectric material portion 365. The third stepped surface contacts the stepped bottom surface of the corresponding third back stepped dielectric material portion 365.

[0070] Typically, a third layer structure is formed, which includes a third vertical alternating sequence of a third insulating layer 332 and a third sacrificial material layer 342, and a third stepped-back dielectric material portion 365 covering the third stepped surface of the third vertical alternating sequence located in the contact region 200.

[0071] An insulating cap layer 370 can be formed over the third vertical alternating sequence and the third stepped-back dielectric material portion 365. The insulating cap layer 370 includes an insulating material such as silicon oxide and can have a thickness in the range of 20 nm to 100 nm, although smaller and larger thicknesses can also be employed.

[0072] Various third layer openings can be formed through the insulating cap layer 370 and the third vertical alternating sequence (332, 342) in the region of the second sacrificial layer opening filling portion. For example, a photoresist layer (not illustrated) can be applied over the insulating cap layer 370 and can be lithographically patterned to form various openings therethrough. The opening pattern in the photoresist layer can be transferred through the third vertical alternating sequence (332, 342) to concurrently (i.e., during a third isotropic etching process) form various third layer openings.

[0073] The various third layer openings can include third layer memory openings formed in the memory array region 100 and third layer support openings (not illustrated) formed in the contact region 200. Each third layer opening can be formed within the region of a corresponding second sacrificial layer opening filling portion in the second sacrificial layer opening filling portion. Thus, the top surface of the second sacrificial layer opening filling portion can be physically exposed at the bottom of each third layer opening. Specifically, each third layer memory opening 349 can be formed directly over a corresponding second sacrificial layer memory opening filling portion 248, and each third layer support opening (not illustrated) can be formed directly over a corresponding second sacrificial layer support opening filling portion (not illustrated). Each cluster of third layer memory openings 349 can be formed as a two-dimensional array of third layer memory openings 349. The third layer support openings (not shown) are openings formed in the contact region 200 and subsequently used to form support pillar structures. A subset of the third layer support openings can be formed through corresponding horizontal surfaces of the third stepped surface.

[0074] Reference Figures 6A to 6F, an etching process that selectively etches the second sacrificial fill material and the first sacrificial fill material with respect to the insulating layers (132, 232, 332) and the sacrificial material layers (142, 242, 342) can be used to remove the second sacrificial fill material in the second sacrificial opening fill portion 248 and the first sacrificial fill material in the first sacrificial opening fill portion 148. Memory openings (also referred to as interlayer memory openings 49) are formed in each combination of the third layer memory opening 349 and the volume from which the second sacrificial memory opening fill portion 248 and the first sacrificial memory opening fill portion 148 are removed. Support openings (not illustrated) (also referred to as interlayer support openings) are formed in each combination of the third layer support opening and the volume from which the second sacrificial support opening fill portion and the first sacrificial support opening fill portion are removed. The interlayer memory opening 49 extends through the third layer structure, the second layer structure, and the first layer structure. Generally, the memory opening 49 can be formed within each memory array region 100 in which there are layers of the first vertical alternating sequence (132, 142), the second vertical alternating sequence (232, 242), and the third vertical alternating sequence (332, 342).

[0075] Figures 7A to 7E An exemplary sequential vertical cross-section of the memory opening 49 during the formation of the memory opening fill structure 58 according to an embodiment of the present disclosure is illustrated.

[0076] Reference Figure 7A , an interlayer memory opening 49 at the process step of Figure 6C is illustrated.

[0077] Reference Figure 7B, a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and an optional sacrificial capping layer 57 can be sequentially deposited in the interlayer memory opening 49. The blocking dielectric layer 52 can include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer can include a dielectric metal oxide layer substantially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material including at least one metal element and at least oxygen. The dielectric metal oxide can be substantially composed of at least one metal element and oxygen, or can be substantially composed of at least one metal element, oxygen, and at least one non-metal element (such as nitrogen). In one embodiment, the blocking dielectric layer 52 can include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). The thickness of the dielectric metal oxide layer can be in the range of 1 nm to 20 nm, but smaller or larger thicknesses can also be used. The dielectric metal oxide layer is then used as a dielectric material portion that blocks the leakage of stored charge to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes alumina. Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0078] Subsequently, the charge storage layer 54 can be formed. In one embodiment, the charge storage layer 54 can be a continuous layer or a patterned discrete portion of a charge trapping material including a dielectric charge trapping material, which can be, for example, silicon nitride. Alternatively, the charge storage layer 54 can include a continuous layer or a patterned discrete portion of a conductive material (such as doped polysilicon or a metal material), which is patterned into a plurality of electrically isolated portions (e.g., floating gates) by, for example, being formed within lateral grooves in a sacrificial material layer (142, 242, 342). In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242, 342) and the insulating layer (132, 232, 332) can have vertically coincident sidewalls, and the charge storage layer 54 can be formed as a single continuous layer. Alternatively, the sacrificial material layer (142, 242, 342) can be laterally recessed with respect to the sidewalls of the insulating layer (132, 232, 332), and a combination of a deposition process and an anisotropic etching process can be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer 54 can be in the range of 2 nm to 20 nm, but smaller or larger thicknesses can also be used.

[0079] The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under appropriate electrical biasing conditions. Depending on the operating mode of the monolithic three-dimensional NAND string memory device to be formed, charge tunneling can be performed by hot carrier injection or by charge transfer induced by Fowler-Nordheim tunneling. The tunneling dielectric layer 56 can comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal nitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 can comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which stack is commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 can comprise a silicon oxide layer substantially free of carbon or a silicon oxynitride layer substantially free of carbon. The thickness of the tunneling dielectric layer 56 can be in the range of 2 nm to 20 nm, although smaller or larger thicknesses can also be used. The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes the memory film 50 that stores the memory bit.

[0080] The sacrificial capping layer 57 can comprise a sacrificial material that can subsequently be selectively removed relative to the material of the tunneling dielectric layer 56. For example, the sacrificial capping layer can comprise a semiconductor material (e.g., amorphous silicon), silicon oxide, or a carbon-based material (e.g., amorphous carbon or diamond-like carbon). The thickness of the sacrificial capping layer can be in the range of 1 nm to 10 nm, although smaller and larger thicknesses can also be employed.

[0081] Reference Figure 7C , an anisotropic etching process can be performed to remove the horizontal portions of the sacrificial capping layer 57, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52. The remaining cylindrical portion of the sacrificial capping layer 57 can be selectively removed relative to the material of the tunneling dielectric layer 56 during the anisotropic etching process or by an isotropic etching process (such as a wet etching process) or by ashing. Alternatively, if the sacrificial capping layer 57 comprises a semiconductor material (e.g., amorphous silicon), the sacrificial capping layer can be retained. In an alternative embodiment, the anisotropic etching process can be omitted. In these alternative embodiments, a horizontal source contact (e.g., a discrete strip contact) can be formed in contact with one side of the vertical semiconductor channel, or the substrate 9 can be removed, and a top source contact can be formed in contact with the exposed end portion of the vertical semiconductor channel.

[0082] Reference Figure 7D, the semiconductor channel material layer 60L can be deposited by a conformal deposition process. The semiconductor channel material layer 60L includes an intrinsic or doped semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L can have uniform doping. In one embodiment, the semiconductor channel material layer 60L has p-type doping, where a p-type dopant (such as a boron atom) is present at an atomic concentration in the range of 1.0x10 12 / cm 3 to 1.0x10 18 / cm 3 (such as 1.0x10 14 / cm 3 to 1.0x10 17 / cm 3 ). In one embodiment, the semiconductor channel material layer 60L includes boron-doped amorphous silicon or boron-doped polycrystalline silicon, and / or consists essentially of boron-doped amorphous silicon or boron-doped polycrystalline silicon. In another embodiment, the semiconductor channel material layer 60L has n-type doping, where an n-type dopant (such as a phosphorus atom or an arsenic atom) is present at an atomic concentration in the range of 1.0x10 12 / cm 3 to 1.0x10 18 / cm 3 (such as 1.0x10 14 / cm 3 to 1.0x10 17 / cm 3 ). The semiconductor channel material layer 60L can be formed by a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L can be in the range of 2 nm to 10 nm, but smaller and larger thicknesses can also be used. A cavity 49' is formed in the volume of each interlayer memory opening 49 that is not filled with the deposited material layers (52, 54, 56, 60L).

[0083] Reference Figure 7E, in the case where the cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer can be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer includes a dielectric material, such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD) or by a self-planarizing deposition process such as spin coating. The horizontal portion of the dielectric core layer covering the top of the semiconductor channel material layer 60L can be removed, for example, by trench etching. The trench etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface and the bottom surface of the insulating cap layer 370. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0084] Reference Figure 7F , doped semiconductor material of a second conductivity type can be deposited in the cavity covering the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The portions of the deposited doped semiconductor material, the semiconductor channel material layer 60L, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 that cover the horizontal plane including the top surface of the insulating cap layer 370 can be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0085] Each remaining portion of the doped semiconductor material of the second conductivity type constitutes a drain region 63. The dopant concentration in the drain region 63 can be in the range of 5.0x10 18 / cm 3 to 2.0x10 21 / cm 3 , but smaller or larger dopant concentrations can also be used. The doped semiconductor material can be, for example, doped polysilicon.

[0086] Each remaining portion of the semiconductor channel material layer 60L constitutes a vertical semiconductor channel 60 through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each set of adjacent blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 together constitutes a memory film 50 that can store charge for a macroscopic retention time. In some embodiments, in this step, the blocking dielectric layer 52 may not be present in the memory film 50, and the blocking dielectric layer can be formed subsequently after forming the lateral grooves. As used herein, the macroscopic retention time refers to the retention time suitable for the operation of the memory device as a permanent memory device, such as a retention time exceeding 24 hours.

[0087] Each combination of a memory film 50 within an interlayer memory opening 49 and a vertical semiconductor channel 60 (which is a vertical semiconductor channel) forms a memory stack structure 55. The memory stack structure 55 is a combination of a vertical semiconductor channel 60, a tunneling dielectric layer 56, multiple memory elements including portions of a charge storage layer 54, and an optional blocking dielectric layer 52. The memory stack structure 55 can be formed through a memory array region 100 of a first vertical alternating sequence and a second vertical alternating sequence, in which all layers of the first vertical alternating sequence and the second vertical alternating sequence are present. Each combination of the memory stack structure 55, a dielectric core 62, and a drain region 63 within the interlayer memory opening 49 forms a memory opening fill structure 58. Generally, the memory opening fill structure 58 is formed within the memory opening 49. Each memory opening fill structure within the memory opening fill structure 58 includes a corresponding memory film 50 and a corresponding vertical semiconductor channel 60.

[0088] In one embodiment, each memory stack structure within the memory stack structure 55 includes a vertical NAND string that includes a corresponding vertical stack of memory elements (including portions of the charge storage layer 54 at respective levels of a sacrificial material layer (142, 242, 342)) and a vertical semiconductor channel 60 that extends vertically through the sacrificial material layer (142, 242, 342) adjacent to the corresponding vertical stack of memory elements.

[0089] Reference Figures 8A to 8F , illustrates an exemplary structure after the process steps of Figure 7F (i.e., after forming the memory opening fill structure 58 in the memory opening 49). In one embodiment, a support pillar structure (not shown) can be formed within a support opening. Generally, each memory opening fill structure within the memory opening fill structure 58 includes a corresponding vertical stack of memory elements at respective levels of a conductive layer (146, 246, 346) within a plurality of layer structures, and also includes a corresponding vertical semiconductor channel 60 that extends vertically through the plurality of layer structures.

[0090] Although an embodiment has been described in which a three - layer device includes three vertical stacked vertical alternating sequences of insulating layers (132, 232, 332) and sacrificial material layers (142, 242, 342), the device can include one or more layers of a vertical alternating sequence of corresponding insulating layers and corresponding sacrificial material layers. Thus, the number of layers of the vertical alternating sequence can be 1, 2, 3, 4, etc. Additionally, the number of groups of stepped surfaces and the number of at least one backward - stepped dielectric material portion that can be vertically stacked can be the same as the number of layers, i.e., can be 1, 2, 3, 4, etc.

[0091] Generally, at least one vertical alternating sequence of insulating layers (132, 232, 332) and sacrificial material layers (142, 242, 342) can be formed over the substrate 9. A memory opening 49 can be formed through the at least one vertical alternating sequence. A memory opening fill structure 58 can be formed in the memory opening 49. Each memory opening fill structure in the memory opening fill structure 58 includes a corresponding vertical stack of memory elements (e.g., portions of the memory film 50) and a vertical semiconductor channel 60.

[0092] Reference Figures 9A to 9H , a contact-level dielectric layer 80 can be formed over the insulating capping layer 370, the memory opening fill structure 58, and a support pillar structure (not illustrated). The contact-level dielectric layer 80 includes a dielectric material such as silicon oxide and can have a thickness in the range of 50 nm to 400 nm, although smaller and larger thicknesses can also be employed.

[0093] Subsequently, a laterally extending trench 79 that extends laterally along a first horizontal direction hd1 can be formed through the contact-level dielectric layer 80, the insulating capping layer 370, and each vertical alternating sequence in the at least one vertical alternating sequence {(132, 142), (232, 242), (332, 342)}. The laterally extending trench 79 can be formed between clusters of memory opening fill structures 58 in the memory block such that an array of memory opening fill structures 58 exists in each portion of the memory array region 100 (e.g., within each memory block) located between a corresponding pair of adjacent laterally extending trenches 79.

[0094] Each vertical alternating sequence in the vertical alternating sequence is divided into a corresponding set of alternating stacks {(132, 142), (232, 242), (332, 342)} of insulating layers (132, 232, 332) and sacrificial material layers (142, 242, 342), and these alternating stacks are laterally spaced apart along a second horizontal direction (e.g., the bit line direction) hd2. For example, the third vertical alternating sequence of the third insulating layer 332 and the third sacrificial material layer 342 is divided into a set of third alternating stacks of the third insulating layer 332 (which is the patterned portion of the third insulating layer 332 of the third vertical alternating sequence) and the third sacrificial material layer 342 (which is the patterned portion of the third sacrificial material layer 342 of the third vertical alternating sequence); the second vertical alternating sequence of the second insulating layer 232 and the second sacrificial material layer 242 is divided into a set of second alternating stacks of the second insulating layer 232 (which is the patterned portion of the second insulating layer 232 of the second vertical alternating sequence) and the second sacrificial material layer 242 (which is the patterned portion of the second sacrificial material layer 242 of the second vertical alternating sequence); and the first vertical alternating sequence of the first insulating layer 132 and the first sacrificial material layer 142 is divided into a set of first alternating stacks of the first insulating layer 132 (which is the patterned portion of the first insulating layer 132 of the first vertical alternating sequence) and the first sacrificial material layer 142 (which is the patterned portion of the first sacrificial material layer 142 of the first vertical alternating sequence).

[0095] In one embodiment, the laterally extending trench 79 includes a first laterally extending trench 79A that divides a corresponding set of at least one backward stepped dielectric material portion (165, 265, 365) into two separated material portions that are laterally spaced apart along the second horizontal direction hd2. Each divided portion of the at least one backward stepped dielectric material portion (165, 265, 365) is also referred to as the at least one backward stepped dielectric material portion (165, 265, 365), although having a reduced area compared to before the formation of the laterally extending trench 79. The laterally extending trench 79 also includes a second laterally extending trench 79B that does not divide and does not contact any of the at least one backward stepped dielectric material portion (165, 265, 365). In other words, each first laterally extending trench 79A cuts through the at least one backward stepped dielectric material portion (165, 265, 365). In contrast, each second laterally extending trench 79B is laterally spaced apart from the at least one backward stepped dielectric material portion (165, 265, 365).

[0096] In one embodiment, the first laterally extending trench 79A and the second laterally extending trench 79B may be staggered along the second horizontal direction hd2 such that each first laterally extending trench 79A that is not the outermost laterally extending trench 79 is located between a pair of second laterally extending trenches 79B that are the two closest laterally extending trenches 79 to the respective first laterally extending trench 79A; and each second laterally extending trench 79B that is not the outermost laterally extending trench 79 is located between a pair of first laterally extending trenches 79A that are the two closest laterally extending trenches 79 to the respective second laterally extending trench 79B.

[0097] As Figure 9A shown, at least one alternating stack {(132, 142), (232, 242), (332, 342)} extending vertically between the patterned portions of the semiconductor material layer 110 and the insulating capping layer 370 includes a pair of longitudinal sidewalls that includes a first longitudinal sidewall LS1 physically exposed to the respective first laterally extending trench 79A and a second longitudinal sidewall LS2 physically exposed to the respective second laterally extending trench 79B.

[0098] At least one alternating stack {(132, 142), (232, 242), (332, 342)} is disposed between each pair of adjacent first laterally extending trenches 79A and second laterally extending trenches 79B. At least one alternating stack {(132, 142), (232, 242), (332, 342)} covers the substrate 9 and includes insulating layers (132, 232, 332) and sacrificial material layers (142, 242, 342) alternating along the vertical direction and has a first longitudinal sidewall LS1 and a second longitudinal sidewall LS2 extending laterally along the first horizontal direction (e.g., word line direction) hd1. At least one backward stepped dielectric material portion (165, 265, 365) is embedded within the alternating stack {(132, 142), (232, 242), (332, 342)} and includes a respective dielectric material.

[0099] In a case where the semiconductor material layer 110 is present in the exemplary structure and serves as a horizontal semiconductor channel, the semiconductor material layer 110 may be doped with a first conductivity type (i.e., the same conductivity type as that of the vertical semiconductor channel 60). In this case, an ion implantation process may be performed to implant dopants of a second conductivity type (i.e., opposite to the first conductivity type), thereby forming a source region 61 in a surface portion of the semiconductor material layer 110 (or in the substrate 9 if the layer 110 is omitted), which is located below the laterally extending trench 79. In some embodiments, the metal connection pad 680 may be provided as a subset of the lower metal interconnect structures in at least one lower dielectric material layer 660. The metal connection pad 680 may then be used to provide a vertical electrical connection through the insulating and conductive layers within the three-dimensional memory array.

[0100] Reference Figures 10A to 10H , optionally, an etch stop liner (such as a silicon oxide liner; not shown) may be formed in a peripheral region of the laterally extending trench 79. A sacrificial fill material may be deposited in the laterally extending trench 79. The excess portion of the sacrificial fill material may be removed from above a first horizontal plane HP1 including the top surface of the contact dielectric layer 80 by a planarization process. The planarization process may include a chemical mechanical polishing (CMP) process and / or a recess etching process. Each remaining portion of the sacrificial fill material filling the laterally extending trench 79 constitutes a sacrificial laterally extending trench fill structure 71. The sacrificial laterally extending trench fill structure 71 includes a first sacrificial laterally extending trench fill structure 71A filling the first laterally extending trench 79A and a second sacrificial laterally extending trench fill structure 71B filling the second laterally extending trench 79B. In embodiments where no etch stop liner is employed, each first longitudinal sidewall LS1 of at least one alternating stack {(132,142),(232,242),(332,342)} and the sidewalls of each at least one backward stepped dielectric material portion (165,265,365) contact the first sacrificial laterally extending trench fill structure 71A; and each second longitudinal sidewall LS2 of at least one alternating stack {(132,142),(232,242),(332,342)} contacts the second sacrificial laterally extending trench fill structure 71B.

[0101] The sacrificial fill material of the sacrificial laterally-extended trench fill structure 71 may include any material that can subsequently be selectively removed relative to an etch stop liner (if employed) or relative to the materials of the insulating layers (132, 232, 332), the sacrificial material layers (142, 242, 342), and the semiconductor material layer 110. For example, the sacrificial fill material may include carbon-based fill materials such as amorphous carbon, diamond-like carbon, or a mixture of carbon with at least one other element such as boron or silicon; semiconductor fill materials such as silicon-germanium alloys or amorphous silicon (in the case where an etch stop liner is employed); dielectric materials such as organosilicate glass or borosilicate glass; or polymeric materials.

[0102] Reference Figures 11A to 11H , a first photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and the sacrificial laterally-extended trench fill structure 71, and may be lithographically patterned to form a two-dimensional array of openings therein. Each row of openings in the first photoresist layer may cover a corresponding sacrificial laterally-extended trench fill structure in the sacrificial laterally-extended trench fill structure 71.

[0103] In one embodiment, the two-dimensional array of openings may be arranged as a two-dimensional periodic array of openings. Each opening in the first photoresist layer may have a width greater than the width of the underlying sacrificial laterally-extended trench fill structure 71. In one embodiment, the length of each opening in the first photoresist layer along a first horizontal direction hd1 may be greater than the width along a second horizontal direction hd2.

[0104] In one embodiment, at least one opening may be formed between the stepped bottom surfaces of a corresponding pair of adjacent first back stepped dielectric material layers 165 around each first sacrificial laterally-extended trench fill structure 71A in the first photoresist layer; at least one opening may be formed between the stepped bottom surfaces of a corresponding pair of adjacent second back stepped dielectric material layers 265 around each first sacrificial laterally-extended trench fill structure 71A in the first photoresist layer; and at least one opening may be formed between the stepped bottom surfaces of a corresponding pair of adjacent third back stepped dielectric material layers 365 around each first sacrificial laterally-extended trench fill structure 71A in the first photoresist layer.

[0105] A first selective recess etching process can be performed to vertically recess portions of the sacrificial laterally extending trench fill structure 71 that are not masked by the first photoresist layer. The first selective recess etching process can include an anisotropic etching process, such as a reactive ion etching process. The first selective recess etching process can selectively remove the unmasked portions of the sacrificial laterally extending trench fill structure 71 relative to the material of the contact-level dielectric layer 80. By the first selective recess etching process, a recess cavity 73 is formed in the volume of the sacrificial laterally extending trench fill structure 71.

[0106] The duration of the first selective recess etching process can be selected such that each recess cavity in the recess cavity 73 has a first depth D1 along the vertical direction, as Figure 11B shown. Thus, each recess cavity in the recess cavity 73 can have a corresponding flat bottom surface that is vertically offset from a first horizontal plane HP1 including the top surface of the contact-level dielectric layer 80 by the first depth D1. In one embodiment, the first depth D1 is less than the sum of the thickness of the contact-level dielectric layer 80 and the thickness of the insulating cap layer 370, and can be equal to, greater than, or less than the thickness of the contact-level dielectric layer 80. In one embodiment, the first depth D1 can be less than the thickness of the contact-level dielectric layer 80. Each sacrificial laterally extending trench fill structure in the sacrificial laterally extending trench fill structure 71 can be embedded in a corresponding row of recess cavities 73. The first photoresist layer can then be removed, for example, by ashing.

[0107] Referring Figures 12A to 12H , a second photoresist layer (not shown) can be applied over the contact-level dielectric layer 80 and the sacrificial laterally extending trench fill structure 71, and can be lithographically patterned to form openings therein. Each opening in the second photoresist layer can cover an area above the recess cavity 73 corresponding to the area between the stepped bottom surfaces of a corresponding pair of adjacent first backward stepped dielectric material layers 165, or above the area between the stepped bottom surfaces of a corresponding pair of adjacent second backward stepped dielectric material portions 265. All of the recess cavities 73 located in the memory array region 100 can be covered by the second photoresist layer. In addition, all of the recess cavities 73 that are not located between a pair of adjacent first backward stepped dielectric material portions 165 or between a pair of adjacent second backward stepped dielectric material portions 265 can be covered by the second photoresist layer.

[0108] A second selective recess etching process may be performed to vertically recess a subset of the recess cavities 73 that is not masked by the second photoresist layer. The second selective recess etching process may include an anisotropic etching process, such as a reactive ion etching process. The second selective recess etching process may vertically extend the unmasked subset of the recess cavities 73 to a depth below a horizontal plane including the top surface of the second backward stepped dielectric material portion 265. Each recess cavity 73 covered by the second photoresist layer is hereinafter referred to as a first type recess cavity 73A. Each recess cavity 73 vertically extended by the second selective recess etching process is hereinafter referred to as a second type recess cavity 73B.

[0109] The duration of the second selective recess etching process may be selected such that each of the second type recess cavities 73B in the second type recess cavities 73B has a second depth D2 along the vertical direction, as Figure 12B shown. Thus, each of the second type recess cavities 73B in the second type recess cavities 73B may have a corresponding flat bottom surface that is vertically offset from a first horizontal plane HP1 including the top surface of the contact level dielectric layer 80 by the second depth D2, which is greater than the first depth D1.

[0110] In one embodiment, the second depth D2 may be greater than the sum of the thickness of the contact level dielectric layer 80, the thickness of the insulating capping layer 370, and the thickness of the third alternating stack of the third insulating layer 332 and the third sacrificial material layer 342. Each first sacrificial laterally extending trench fill structure 71A in the first sacrificial laterally extending trench fill structures 71A is embedded in a corresponding set of first type recess cavities 73A and a corresponding set of second type recess cavities 73B. Each second sacrificial laterally extending trench fill structure 71B in the second sacrificial laterally extending trench fill structures 71B is embedded in a corresponding set of additional first type recess cavities 73A but not in any second type recess cavities 73B. The sidewalls of a pair of third backward stepped dielectric material portions 365 and the upper portions of the sidewalls of a pair of second backward stepped dielectric material portions 265 may be physically exposed to each second type recess cavity 73B. The second photoresist layer may then be removed, for example, by ashing.

[0111] Referring to Figures 13A to 13H, a third photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and the sacrificial laterally-extended trench fill structure 71, and may be lithographically patterned to form openings therein. Each opening in the third photoresist layer may cover an area of a corresponding second-type groove cavity 73B that is between the stepped bottom surfaces of a corresponding pair of adjacent first backward stepped dielectric material layers 165. All groove cavities 73 located in the memory array region 100 may be covered by the third photoresist layer. Additionally, all groove cavities 73 that are not located between a pair of adjacent first backward stepped dielectric material portions 165 may be covered by the third photoresist layer.

[0112] A third selective groove etching process may be performed to vertically recess a subset of the second-type groove cavities 73B that are not masked by the third photoresist layer. The third selective groove etching process may include an anisotropic etching process, such as a reactive ion etching process. The third selective groove etching process may vertically extend the unmasked subset of the second-type groove cavities 73B to a depth below a horizontal plane that includes the top surface of the first backward stepped dielectric material portion 165. Each second-type groove cavity 73B that is vertically extended during the third selective groove etching process is hereinafter referred to as a third-type groove cavity 73C.

[0113] The duration of the third selective groove etching process may be selected such that each third-type groove cavity 73C in the third-type groove cavities has a third depth D3 along the vertical direction, as Figure 13B shown. Thus, each third-type groove cavity 73C in the third-type groove cavities may have a corresponding flat bottom surface that is vertically offset from a first horizontal plane HP1 that includes the top surface of the contact-level dielectric layer 80 by the third depth D3, which is greater than the second depth D2 and the first depth D1.

[0114] In one embodiment, the third depth D3 can be greater than the sum of the thickness of the contact-level dielectric layer 80, the thickness of the insulating cap layer 370, the thickness of the third alternating stack of the third insulating layer 332 and the third sacrificial material layer 342, and the thickness of the second alternating stack of the second insulating layer 232 and the second sacrificial material layer 242. Each first sacrificial laterally-extending trench fill structure in the first sacrificial laterally-extending trench fill structures 71A is embedded in a corresponding set of first-type recess cavities 73A, at least one second-type recess cavity 73B, and at least one third-type recess cavity 73C. Each second sacrificial laterally-extending trench fill structure in the second sacrificial laterally-extending trench fill structures 71B is embedded in a corresponding set of additional first-type recess cavities 73A, but not in any second-type recess cavity 73B or any third-type recess cavity 73C. Upper portions of the sidewalls of a pair of third backward-stepped dielectric material portions 365, the sidewalls of a pair of second backward-stepped dielectric material portions 265, and the sidewalls of a pair of first backward-stepped dielectric material portions 165 can be physically exposed to each third-type recess cavity 73C. The third photoresist layer can then be removed, for example, by ashing.

[0115] Figures 11A to 13H Exemplary embodiments for forming the first-type recess cavities 73A, the second-type recess cavities 73B, and the third-type recess cavities 73C are illustrated. Generally, any combination of a photolithographic patterning step and a selective recess etching process can be employed to provide Figures 13A to 13H the exemplary structures illustrated in Figures 10A to 10H From Figures 13A to 13H In a non-limiting example of an alternating sequence of process steps for providing Figures 13A to 13H the exemplary structures illustrated in Figures 13A to 13H a first photolithographic patterning step and a first selective recess etching process for etching only the first-type recess cavities 73A illustrated in Figures 13A to 13H can be employed to form the first-type recess cavities 73A, a second photolithographic patterning step and a second selective recess etching process for etching only the second-type recess cavities 73B illustrated in Figures 13A to 13H can be employed to form the second-type recess cavities 73B, and a third photolithographic patterning step and a third selective recess etching process for etching only the third-type recess cavities 73C illustrated in

[0116] Reference Figures 14A to 14H, a dielectric filling material such as undoped silicate glass (i.e., silica) or doped silicate glass can be deposited in each of the trench cavities (73A, 73B, 73C). An optional reflow process can be performed to facilitate gap filling within each of the trench cavities (73A, 73B, 73C) by the dielectric filling material. A planarization process can be performed to remove portions of the dielectric filling material deposited outside the volume of the various trench cavities (73A, 73B, 73C). The planarization process can include a chemical mechanical polishing (CMP) process and / or a trench etching process. Each remaining portion of the dielectric filling material constitutes a dielectric bridge structure (72A, 72B, 72C).

[0117] The dielectric bridge structures (72A, 72B, 72C) include: a first type of dielectric bridge structure 72A formed in a first type of trench cavity 73A; a second type of dielectric bridge structure 72B formed in a second type of trench cavity 73B; and a third type of dielectric bridge structure 72C formed in a third type of trench cavity 73B. The top surface of the dielectric bridge structures (72A, 72B, 72C) can be formed within a first horizontal plane HP1 that includes the top surface of the contact-level dielectric layer 80. Each first type of dielectric bridge structure 72A can have a first vertical extent VE1 that is the same as the first depth D1 of the first type of trench cavity 73A; each second type of dielectric bridge structure 72B can have a second vertical extent VE2 that is the same as the second depth D2 of the second type of trench cavity 73B; and each third type of dielectric bridge structure 72C can have a third vertical extent VE3 that is the same as the third depth D3 of the third type of trench cavity 73C. Thus, the third vertical extent VE3 is greater than the first and second vertical extents (VE1, VE2), and the second vertical extent VE2 can be greater than the first vertical extent VE1. In other words, the third type of dielectric bridge structure 72C is thicker in the vertical direction than the first and second type of dielectric bridge structures (72A, 72B), and the second type of dielectric bridge structure 72B is thicker in the vertical direction than the first type of dielectric bridge structure 72A.

[0118] In Figure 14I In an alternative embodiment shown, as a supplement or alternative to the third type of dielectric bridge structure 72C being thicker than the first and second type of dielectric bridge structures (72A, 72B), the third type of dielectric bridge structure 72C is longer than the first and second type of dielectric bridge structures (72A, 72B) along a first horizontal direction (e.g., the word line direction) hd1. As a supplement or alternative to the second type of dielectric bridge structure 72B being thicker than the first type of dielectric bridge structure 72A, the second type of dielectric bridge structure 72B is longer than the first type of dielectric bridge structure 72A along the first horizontal direction hd1.

[0119] In Figure 14J In another alternative embodiment shown, as a supplement or alternative to the first type of dielectric bridge structure being thicker and / or longer than the second type of dielectric bridge structures (72A, 72B), the third type of dielectric bridge structure 72C is wider along the second horizontal direction (e.g., the bit line direction) hd2 than the first type of dielectric bridge structure and the second type of dielectric bridge structures (72A, 72B). As a supplement or alternative to the first type of dielectric bridge structure 72A being thicker and / or longer, the second type of dielectric bridge structure 72B is wider along the second horizontal direction hd2 than the first type of dielectric bridge structure 72A.

[0120] Generally, the third type of dielectric bridge structure 72C has a larger volume than the first type of dielectric bridge structure and the second type of dielectric bridge structures (72A, 72B). The second type of dielectric bridge structure 72B has a larger volume than the first type of dielectric bridge structure 72A. The larger volume may be due to any combination of at least one of a greater thickness, length, and / or width.

[0121] In one embodiment, each of the first type of dielectric bridge structure 72A, the second type of dielectric bridge structure 72B, and the third type of dielectric bridge structure 72C contacts a respective pair of sidewalls of the contact-level dielectric layer 80. The first type of dielectric bridge structure 72A may optionally contact the sidewall of the insulating cap layer 370. In one embodiment, the first type of dielectric bridge structure 72A does not contact any of the sacrificial material layers (142, 242, 342) or the insulating layers (132, 232, 332).

[0122] Each of the second type of dielectric bridge structure 72B and the third type of dielectric bridge structure 72C contacts a respective pair of sidewalls of the insulating cap layer 370, a respective pair of sidewalls of the third backward stepped dielectric material portion 365, and a respective pair of sidewalls of the second backward stepped dielectric material portion 265. The second type of dielectric bridge structure 72B does not contact any of the first backward stepped dielectric material portions in the first backward stepped dielectric material portion 165. Each of the third type of dielectric bridge structures in the third type of dielectric bridge structure 72C contacts a respective pair of sidewalls of the first backward stepped dielectric material portion 165.

[0123] Typically, the bottom surface of each first type of dielectric bridge structure 72A is formed above the horizontal plane of the top surface of the topmost sacrificial material layer including the sacrificial material layers (142, 242, 342). The bottom surface of each second type of dielectric bridge structure 72B is formed below the horizontal plane of the top surface of the topmost sacrificial material layer 242. The bottom surface of each third type of dielectric bridge structure 72C is formed below the horizontal plane of the top surface of the topmost sacrificial material layer 142. The first type of dielectric bridge structure 72A does not contact any of the at least one backward stepped dielectric material portion (165, 265, 365). The second type of dielectric bridge structure 72B and the third type of dielectric bridge structure 72C can be directly formed on the sidewalls of a pair of consecutive dielectric portions including the corresponding vertical stack of at least one backward stepped dielectric material portion (165, 265, 365), such as the first backward stepped dielectric material portion 165, the second backward stepped dielectric material portion 265, and the third backward stepped dielectric material portion 365.

[0124] In one embodiment, each first type of dielectric bridge structure 72A may have a first top surface located in a first horizontal plane HP1 and a first bottom surface vertically spaced from the first horizontal plane HP1 by a first vertical distance (such as a first vertical range VE1); each second type of dielectric bridge structure 72B may have a second top surface located in the first horizontal plane HP1 and a second bottom surface vertically spaced from the first horizontal plane HP1 by a second vertical distance (such as a second vertical range VE2), which is greater than the first vertical distance; and each third type of dielectric bridge structure 72C may have a third top surface located in the first horizontal plane HP1 and a third bottom surface vertically spaced from the first horizontal plane HP1 by a third vertical distance (such as a third vertical range VE3), which is greater than the first vertical distance and the second vertical distance.

[0125] Although three different types of dielectric bridge structures for a three - layer memory device are described in the above embodiments, in an alternative embodiment, the memory device may include only two types or more than three types of dielectric bridge structures. It should be noted that the boundaries between different types of dielectric bridge structures may vary and do not necessarily correspond to the boundaries of the stepped layers and may vary within each layer as long as the bottom of the surface does not extend above the active word line. In another embodiment, the spacing (e.g., bridge length and the spacing between bridges) may also vary.

[0126] Each sacrificial laterally extending trench fill structure 71 located within a first laterally extending trench 79A embeds a row of first type dielectric bridge structures 72A, at least one second type dielectric bridge structure 72B, and optionally at least one third type dielectric bridge structure 72C. Each first type dielectric bridge structure 72A is not in direct contact with any of the backward stepped dielectric material portions (165, 265, 365). Each sacrificial laterally extending trench fill structure 71 located within a second laterally extending trench 79B embeds a corresponding set of additional first type dielectric bridge structures 72A, but does not embed any second type dielectric bridge structures 72B or any third type dielectric bridge structures 72C. Each additional first type dielectric bridge structure 72A is not in direct contact with any of the backward stepped dielectric material portions (165, 265, 365).

[0127] Reference Figures 15A to 15H , the sacrificial fill material of the sacrificial laterally extending trench fill structure 71 can be selectively removed relative to the materials of various dielectric bridge structures (72A, 72B, 72C), alternating stacks {(132, 142), (232, 242), (332, 342)}, and the semiconductor material layer 110 (if present) (and the source region 61 (if present)) by performing an isotropic removal process. For example, if the sacrificial fill material includes a carbon-based material, the isotropic removal process can include an ashing process. If the sacrificial fill material includes a semiconductor material, a dielectric material, or a polymer material, the isotropic removal process can include an isotropic etching process, such as a wet etching process. For example, if the sacrificial laterally extending trench fill structure 71 includes a semiconductor material (such as amorphous silicon), the isotropic etching process can include a wet etching process using hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH). In one embodiment, the sacrificial laterally extending trench fill structure 71 can include an undoped semiconductor material or a lightly doped semiconductor material, and the wet etching process using hot TMY or TMAH can selectively etch the undoped semiconductor material or the lightly doped semiconductor material of the sacrificial laterally extending trench fill structure 71 relative to the heavily doped semiconductor material of the source region 61. A laterally extending cavity 79' exists within the volume of each laterally extending trench 79 that is not filled by the dielectric bridge structures (72A, 72B, 72C). The dielectric bridge structures (72A, 72B, 72C) are suspended above the laterally extending cavity 79'.

[0128] Reference Figures 16A to 16H, the sacrificial material layer (142, 242, 342) can be selectively isotropically etched relative to the insulating layer (132, 232, 332), the dielectric bridge structure (72A, 72B, 72C), and the backward stepped dielectric material portion (165, 265, 365) (as well as the semiconductor material layer 110 and the source region 61, if present) by supplying an isotropic etchant into the laterally extending trench 79.

[0129] For example, an isotropic etchant can be introduced into the laterally extending trench, for example, using an isotropic etching process that selectively etches the material of the sacrificial material layer (142, 242, 342) relative to the materials of the insulating layer (132, 232, 332), the backward stepped dielectric material portion (165, 265, 365), the dielectric bridge structure (72A, 72B, 72C), and the outermost layer of the memory film 50.

[0130] The isotropic etching process can be a wet etching process using a wet etching solution or can be a gas-phase (dry) etching process in which the etchant is introduced into the laterally extending trench in the gas phase. For example, if the sacrificial material layer (142, 242, 342) comprises silicon nitride and the materials of the insulating layer (132, 232, 332), the backward stepped dielectric material portion (165, 265, 365), the dielectric bridge structure (72A, 72B, 72C), and the outermost layer of the memory film 50 comprise silicon oxide, the etching process can be a wet etching process in which the exemplary structure is immersed in a wet etching bath comprising phosphoric acid that selectively etches silicon nitride relative to silicon oxide, silicon, and various other materials used in the art.

[0131] Lateral grooves (143, 243, 343) are formed in the volume from which the sacrificial material layers (142, 242, 342) are removed. The lateral grooves (143, 243, 343) include: a first lateral groove 143 formed in the volume from which the first sacrificial material layer 142 is removed; a second lateral groove 243 formed in the volume from which the second sacrificial material layer 242 is removed; and a third lateral groove 343 formed in the volume from which the third sacrificial material layer 342 is removed. Each of the lateral grooves (143, 243, 343) can be a laterally extending cavity whose lateral dimension is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the lateral grooves (143, 243, 343) can be greater than the height of the corresponding lateral groove. A plurality of lateral grooves (143, 243, 343) can be formed in the volume of the material from which the sacrificial material layers (142, 242, 342) are removed. Each of the lateral grooves (143, 243, 343) can extend substantially parallel to the top surface of the semiconductor material layer 110 (if present, or another underlying layer or substrate 9). The lateral grooves (143, 243, 343) can be vertically bounded by the top surface of the underlying insulating layer (132, 232, 332) and the bottom surface of the overlying insulating layer (132, 232, 332). In one embodiment, each of the lateral grooves (143, 243, 343) can have a uniform height throughout the region.

[0132] Dielectric bridge structures (72A, 72B, 72C) provide lateral structural support between pairs of adjacent continuous structures including the insulating layers (132, 232, 332) and the memory opening fill structure 58, which are laterally spaced from each other by respective laterally extending trenches 79. A smaller volume of a first type of dielectric bridge structure 72A provides lateral support at the level of the contact-level dielectric layer 80 along a second horizontal direction. In one embodiment, a larger volume of a second type of dielectric bridge structure 72B and a third type of dielectric bridge structure 72C directly contact the sidewalls of a respective pair of adjacent backward stepped dielectric material portions (165, 265, 365).

[0133] The larger volume of the second type of dielectric bridge structure 72B and the third type of dielectric bridge structure 72C provide additional structural support at the levels of the deeper portions of the stepped surface (i.e., the steps), where the insulating layers (132, 232, 332) are more likely to deflect and slope into the laterally extending trenches 79, especially at Figure 16AIn the asymmetric structure shown, the steps are located on both sides of some of the laterally extending grooves 79, rather than on both sides of other laterally extending grooves. Additionally, since the stress on the dielectric bridge structure may be greater at the deeper portions of the steps, the larger volume of the second type of dielectric bridge structure 72B and the third type of dielectric bridge structure 72C reduces the likelihood of such bridge structures breaking under stress. Further, since only the lower sacrificial material layer (e.g., 142) must be replaced with a conductive layer at the deeper portions of the steps, the larger volume of the second type of dielectric bridge structure 72B and the third type of dielectric bridge structure 72C does not significantly interfere with the replacement process.

[0134] Reference Figures 17A to 17H , an optional backside barrier dielectric layer (not shown) may optionally be deposited in the lateral grooves (143, 243, 343) and the laterally extending grooves. The backside barrier dielectric layer includes a dielectric material such as a dielectric metal oxide (e.g., alumina), silicon oxide, or a combination thereof.

[0135] The conductive layer (146, 246, 346) may be deposited in the remaining volume of the lateral grooves (143, 243, 343) by performing a conformal deposition process in which a precursor gas of the conductive material for the conductive layer (146, 246, 346) is supplied into the lateral grooves (143, 243, 343) through the laterally extending grooves 79. At least one conductive material may be deposited in the plurality of lateral grooves (143, 243, 343), on the sidewalls of the laterally extending grooves, and above the topmost layer structure. At least one conductive material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. At least one conductive material may include elemental metals, alloys of at least two elemental metals, conductive nitrides of at least one elemental metal, conductive metal oxides, conductive doped semiconductor materials, conductive metal-semiconductor compounds (such as metal silicides), and combinations or stacks thereof.

[0136] In one embodiment, at least one conductive material may include at least one metal element such as including tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, cobalt, or ruthenium. For example, at least one conductive material may include a conductive metal nitride liner that includes a conductive metal nitride material (such as TiN, TaN, WN, MoN, or a combination thereof) and a conductive fill material (such as W, Co, Ru, Mo, Cu, or a combination thereof). In one embodiment, at least one conductive material for filling the lateral grooves (143, 243, 343) may be a combination of a titanium nitride layer and a tungsten fill material.

[0137] A plurality of first conductive layers 146 may be formed in a plurality of first lateral grooves 143, a plurality of second conductive layers 246 may be formed in a plurality of second lateral grooves 243, a plurality of third conductive layers 346 may be formed in a plurality of third lateral grooves 343, and a continuous conductive material layer (not shown) may be formed on the sidewalls of each laterally extending trench and above the topmost layer structure. Each of the conductive layers (146, 246, 346) may include a respective conductive metal nitride liner and a respective conductive fill material. Thus, the sacrificial material layers (142, 242, 342) may be replaced by the conductive layers (146, 246, 346), respectively. Specifically, each first sacrificial material layer 142 may be replaced by an optional portion of the backside barrier dielectric layer and the first conductive layer 146, each second sacrificial material layer 242 may be replaced by an optional portion of the backside barrier dielectric layer and the second conductive layer 246, and each third sacrificial material layer 342 may be replaced by an optional portion of the backside barrier dielectric layer and the third conductive layer 346. A back cavity exists in the portion of each laterally extending trench that is not filled with the continuous metal material layer.

[0138] Residual conductive material may be removed from inside the laterally extending trenches 79 and from above the plurality of layer structures. Specifically, the deposited conductive material may be etched back from the sidewalls of each laterally extending trench and from above the topmost layer structure, for example, by performing an isotropic etching process. Each remaining portion of the conductive material deposited in the first lateral groove constitutes the first conductive layer 146. Each remaining portion of the conductive material deposited in the second lateral groove constitutes the second conductive layer 246. Each remaining portion of the conductive material deposited in the third lateral groove constitutes the third conductive layer 346. The sidewalls of the conductive layers (146, 246, 346) may be physically exposed to the respective laterally extending trenches 79.

[0139] Each conductive layer (146, 246, 346) may be a conductive sheet including openings therein. A first subset of the openings through each conductive layer (146, 246, 346) may be filled with a memory opening fill structure 58. A second subset of the openings through each conductive layer (146, 246, 346) may be filled with a support pillar structure 20.

[0140] At least one topmost conductive layer 346 may include a drain-side select gate electrode, and at least one bottommost conductive layer 146 may include a source-side select gate electrode. An intermediate subset of the conductive layers (146, 246, 346) located between the select gate electrodes may include word lines for memory elements (e.g., memory cells). If the peripheral circuit 920 is located on the substrate 9 below or beside the memory-level assembly, the peripheral circuit may include word line switching devices and / or bit line driver devices, such as sense amplifiers, configured to control the bias voltage to the respective word lines. The memory-level assembly is located above the substrate semiconductor layer 9. The memory-level assembly includes at least one alternating stack {(132, 146), (232, 246), (332, 346)} of insulating layers (132, 232, 332) and conductive layers (146, 246, 346), and a memory stack structure 55 extending vertically through at least one alternating stack {(132, 146, 232, 246, 332, 346)}. Each memory stack structure in the memory stack structure 55 includes a vertical stack of memory elements (e.g., portions of the memory film 50) at each level of the conductive layers (146, 246, 346).

[0141] Reference Figures 18A to 18H , a dielectric material portion may be formed in each of the laterally extending trenches 79. The dielectric material portion formed in the first laterally extending trench 79A is referred to herein as the first trench dielectric material portion, and the dielectric material portion formed in the second laterally extending trench 79B is referred to herein as the second trench dielectric material portion. In one embodiment, the dielectric material portion may include a dielectric liner 74. In this case, the dielectric liner 74 may be formed by conformally depositing a dielectric liner material (such as silicon oxide, silicon nitride, and / or dielectric metal oxide) having a thickness less than the width of each laterally extending trench 79 along the second horizontal direction hd2, and performing an anisotropic etching process to remove the unmasked horizontally extending portions of the conformally deposited dielectric liner material. The anisotropic etching process removes the exposed horizontal portions of the dielectric liner 74 from the lower horizontal surface and exposes portions of the source region 61 that are not located below the dielectric bridge structures (72A, 72B, 72C). In an alternative embodiment, the dielectric liner 74 may be removed below the dielectric bridge structures (72A, 72B, 72C).

[0142] Each sidewall of the laterally extending trench 79 and each sidewall of the dielectric bridge structures (72A, 72B, 72C) may be covered by a respective vertically extending portion of the dielectric liner 74. Additionally, each bottom surface of the dielectric bridge structures (72A, 72B, 72C) and each segment of the top surface of the source region 61 that is located below the respective dielectric bridge structure in the dielectric bridge structures (72A, 72B, 72C) may be covered by a horizontally extending portion of the respective dielectric liner 74. The thickness of the dielectric liner 74 may be in the range of 5 nm to 100 nm (such as 10 nm to 50 nm), but smaller or larger thicknesses may also be employed.

[0143] At least one conductive material (such as at least one metallic material) may be deposited in the remaining volume of the laterally extending trench 79. The excess portion of the at least one conductive material may be removed from above a first horizontal plane HP1 that includes the top surface of the contact dielectric layer 80 by a planarization process (such as a chemical mechanical polishing process). Each remaining portion of the at least one conductive material in the respective laterally extending trench 79 constitutes a via structure, which is referred to herein as a trench-fill via structure 76. In an alternative embodiment, if the dielectric liner 74 is removed below the dielectric bridge structures (72A, 72B, 72C), the conductive material of the structure 76 extends along the entire trench 79. Each trench-fill via structure 76 may extend vertically from the first horizontal plane HP1 to the top surface of a respective top surface segment of the source region 61 between each pair of adjacent dielectric bridge structures (72A, 72B, 72C). Each trench-fill via structure 76 may extend vertically from below the dielectric bridge structures (72A, 72B, 72C) to the top surface of the horizontally extending portion of the dielectric liner 74 that contacts the top surface segment of the source region 61 within the region of the dielectric bridge structures (72A, 72B, 72C).

[0144] At least one alternating stack {(132, 146), (232, 246), (332, 346)} of an insulating layer (132, 232, 332) and a conductive layer (146, 246, 346) is disposed between each pair of adjacent first laterally extending trenches 79A and second laterally extending trenches 79B. A first laterally extending trench fill structure (72A, 72B, 72C, 74, 76) may be formed within each first laterally extending trench 79A. The first laterally extending trench fill structure (72A, 72B, 72C, 74, 76) contacts a first longitudinal sidewall LS1 of at least one alternating stack {(132, 146), (232, 246), (332, 346)}. In one embodiment, the first laterally extending trench fill structure (72A, 72B, 72C, 74, 76) includes a first trench dielectric material portion, which may include a dielectric liner 74 having a thickness less than half of the lateral dimension of the first laterally extending trench fill structure {72A, 72B, 72C, (74, 76)} along a second horizontal direction hd2 that is perpendicular to a first horizontal direction hd1. Additionally, the first laterally extending trench fill structure (72A, 72B, 72C, 74, 76) may further include a trench fill via structure 76 that extends vertically from a first horizontal plane HP1 to a top surface of the semiconductor material layer 110 (such as the top surface of the source region 61).

[0145] In one embodiment, the first type of dielectric bridge structure 72A does not contact any of the backward stepped dielectric material portions (165, 265, 365). In one embodiment, the second type of dielectric bridge structure 72B and an optional third type of dielectric bridge structure 72C contact the topmost backward stepped dielectric material portion (such as the third backward stepped dielectric material portion 365), and optionally contact another backward stepped dielectric material portion (such as the second backward stepped dielectric material portion 265). In one embodiment, the first trench dielectric material portion (such as the first dielectric liner 74) contacts each of the backward stepped dielectric material portions within two or more vertically stacked backward stepped dielectric material portions (165, 265, 365).

[0146] A second laterally extending trench fill structure (72A, 74, 76) may be formed within the second laterally extending trench 79B. The second laterally extending trench fill structure (72A, 74, 76) may contact at least one second longitudinal sidewall LS2 of an alternating stack {(132, 146), (232, 246), (332, 346)}. The second laterally extending trench fill structure (72A, 74, 76) may include additional dielectric bridge structures (such as additional first type dielectric bridge structure 72A). Each dielectric bridge structure within the second laterally extending trench fill structure (72A, 74, 76) has a vertical extent (such as a first vertical extent VE1) that is the same as the first vertical distance. In one embodiment, the second laterally extending trench fill structure {72A, (74, 76)} includes a second trench dielectric material portion (e.g., second dielectric liner 74) that contacts each of the additional dielectric bridge structures within the additional dielectric bridge structures and has the same material composition as the first trench dielectric material portion (e.g., first dielectric liner 74).

[0147] Reference Figures 19A to 19H , a layer contact via structure (86A, 86B, 86C) may pass through the contact level dielectric layer 80 and through at least one backward stepped dielectric material portion (165, 265, 365) and be formed directly on the top surface of a corresponding conductive layer {(146, 246, 346)} within at least one alternating stack {(132, 146), (232, 246), (332, 346)}. The layer contact via structure (86A, 86B, 86C) may include a first layer contact via structure 86A that contacts the corresponding first conductive layer 146, a second layer contact via structure 86B that contacts the corresponding second conductive layer 246, and a third layer contact via structure 86C that contacts the corresponding third conductive layer 346. A drain contact via structure 88 may be formed through the contact level dielectric layer 80 on the top surface of a corresponding drain region 63.

[0148] In some embodiments, a through-memory-level connection via structure 486 may pass through the alternating stack {(132, 146), (232, 246), (332, 346)} and be formed on the top surface of a corresponding metal connection pad 680. In such a case, the through-memory-level connection via structure 486 may be electrically isolated from the alternating stack {(132, 146), (232, 246), (332, 346)} by a tubular dielectric liner 484. In an alternative embodiment, such as where the peripheral circuit 720 is formed in a separate logic die 700 bonded to the memory die 900, the through-memory-level connection via structure 486 and the tubular dielectric liner 484 may be omitted.

[0149] Reference Figure 20, an additional dielectric material layer and an additional metal interconnect structure can be formed over the contact-level dielectric layer 80. The additional dielectric material layer can include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and / or at least one additional line and via-level dielectric layer. The additional metal interconnect structure can include a metal via structure, a metal line structure, and / or an integrated metal line and via structure. The additional dielectric material layer formed over the contact-level dielectric layer 80 is referred to herein as the memory-side dielectric material layer 960. The additional metal interconnect structures are collectively referred to as the memory-side dielectric material layer 960. The memory-side dielectric material layer 960 includes a bit-line-level dielectric material layer embedding bit lines, which are a subset of the memory-side metal interconnect structure 980.

[0150] A metal bonding pad (which is referred to herein as the upper bonding pad 988) can be formed at the topmost level of the memory-side dielectric material layer 960. The upper bonding pad 988 can be electrically connected to the memory-side metal interconnect structure 980 and respective nodes of the three-dimensional memory array, and the respective nodes include an alternating stack of insulating layers (132, 232, 332) and conductive layers (146, 246, 346) and a memory opening fill structure 58. Thus, a memory die 900 can be provided.

[0151] The memory-side dielectric material layer 960 is formed over the alternating stack {(132, 146), (232, 246), (332, 346)}. The memory-side metal interconnect structure 980 is embedded in the memory-side dielectric material layer 960. The memory-side bonding pad 988 can be embedded within the memory-side dielectric material layer 960, and specifically within the topmost layer of the memory-side dielectric material layer 960. The memory-side bonding pad 988 can be electrically connected to the memory-side metal interconnect structure 980.

[0152] Generally, a memory die 900 is provided, which includes a memory array, a memory-side metal interconnect structure 980, and a memory-side bonding pad 988 embedded within the memory-side dielectric material layer 960. The memory die 900 includes memory devices, which can include a three-dimensional memory array including an alternating stack of insulating layers (132, 232, 332) and conductive layers (146, 246, 346), and the memory devices further include a two-dimensional array of NAND strings extending vertically through the alternating stack {(132, 146), (232, 246), (332, 346)}. In one embodiment, the conductive layers (146, 246, 346) include word lines of the two-dimensional array of NAND strings. In one embodiment, the memory-side metal interconnect structure 980 includes bit lines of the two-dimensional array of NAND strings.

[0153] In one embodiment, a logic die 700 may be provided. The logic die 700 includes a peripheral circuit 720 formed on a logic-side substrate 709. According to one aspect of the present disclosure, the peripheral circuit 720 may be configured to control the operation of a memory array within a memory die 900. For example, the peripheral circuit 720 may include a word line driver region, a bit line driver region, a sense amplifier region, an input / output buffer region, and the like. Logic-side metal interconnect structures 780 embedded within a logic-side dielectric material layer 760 may be formed above the peripheral circuit 720. The logic die 700 includes logic-side bond pads 788 embedded within the logic-side dielectric material layer 760.

[0154] In Figures 2B to 2D In one embodiment shown, a first peripheral circuit 920 may be disposed on a top surface of a substrate 9, and the peripheral circuit 720 in the logic die 700 may include a second peripheral circuit that is used in combination with the first peripheral circuit to control the operation of a three-dimensional memory array in the memory die 900. Alternatively, if the substrate 9 is a carrier substrate, or if no peripheral circuit 920 is disposed on the top surface of the substrate 9, the peripheral circuit 720 may be the sole control circuit for controlling the operation of the three-dimensional memory device in the memory die 900. Alternatively, the logic die 700 may not be employed, and a peripheral circuit 920 disposed on the top surface of the substrate 9 may be used to control the operation of the three-dimensional memory device in the memory die 900. The peripheral circuit disposed on the top surface of the substrate 9 may be located below and / or beside at least one alternating stack [{(132,146),(232,246),(332,346)},(32,46)].

[0155] Subsequently, a bonded assembly may be formed by bonding the logic die 700 to the memory die 900. The logic die 700 may be attached to the memory die 900, for example, by bonding the logic-side bond pads 788 to memory-side bond pads 988. The bonding between the memory die 900 and the logic die 700 may be performed using a wafer-to-wafer bonding process (in which a two-dimensional array of the memory die 900 is bonded to a two-dimensional array of the logic die 700), by a die-to-bond process, or by a die-to-die bonding process. The logic-side bond pads 788 within each logic die 700 may be bonded to the memory-side bond pads 988 within the corresponding memory die 900.

[0156] Referring Figure 21 , a first alternative configuration of an exemplary structure according to an embodiment of the present disclosure may be obtained from Figure 20derived from the exemplary structure illustrated therein (or its derivative structure as described above). In this case, a single vertical alternating sequence of the insulating layer 32 and the sacrificial material layer is formed, and a laterally extending trench is formed through the single vertical alternating sequence. A single backward stepped dielectric material portion 65 may be formed to replace each vertical stack of the first backward stepped dielectric material portion 165, the second backward stepped dielectric material portion 265, and the third backward stepped dielectric material portion 365.

[0157] An alternating stack of the insulating layer 32 and the sacrificial material layer may be formed between each pair of adjacent first laterally extending trenches 79A and second laterally extending trenches 79B. The sacrificial lateral isolation trench filling structure 71 may be formed as described above, and a first type of groove cavity 73A having a first depth D1 and a second type of groove cavity 73B having a second depth D2 may be formed. Optionally, a third type of groove cavity 73C having a third depth D3 may be formed. The first depth D1 is less than the sum of the thickness of the contact-level dielectric layer 80 and the thickness of the insulating cap layer 370; the second depth is greater than the sum of the thickness of the contact-level dielectric layer 80 and the thickness of the insulating cap layer 370; and the third depth D3 is greater than the second depth D3. In one embodiment, the first type of dielectric bridge structure 72A does not contact the backward stepped dielectric material portion 65, and the second type of dielectric bridge structure 72B (and the third type of dielectric bridge structure 72C) contacts the sidewalls of the corresponding backward stepped dielectric material portion 65 but does not contact the sacrificial material layer or the conductive layer 46.

[0158] Reference Figure 22 , a second alternative configuration of the exemplary structure according to an embodiment of the present disclosure may be derived from Figure 20 or Figure 21 the exemplary structure illustrated therein (or its derivative structure as described above). In this case, the trench dielectric material portion may include a dielectric trench filling material portion 176. The volume of the lateral isolation trench 79 is not used for the source interconnect local interconnect. In this case, the formation of the source region 61 may be omitted, and a horizontally discrete strip contact (e.g., the source region) including a doped semiconductor material of the second conductivity type may contact a lower portion of the sidewall of the corresponding vertical semiconductor channel 60.

[0159] Reference Figure 23 , a third alternative configuration of the exemplary structure according to an embodiment of the present disclosure may be derived from Figures 19A to 19H , Figure 20 or Figure 21derived from the exemplary structures illustrated therein (or derivative structures thereof as described above). For example, the first type of dielectric bridge structure 72A may have a first pitch, and the second type of dielectric bridge structure 72B may have a second pitch that is different from the first pitch. If present, the third type of dielectric bridge structure 72C may have a third pitch that is different from the first and second pitches.

[0160] In one configuration, compared to the first type of dielectric bridge structure 72A, the second type of dielectric bridge structure 72B may be located laterally adjacent to a deeper portion of the step. Compared to both the first type of dielectric bridge structure 72A and the second type of dielectric bridge structure 72B, the third type of dielectric bridge structure 72C (if present) may be located laterally adjacent to a deeper portion of the step. In other words, compared to the second type of dielectric bridge structure 72B located laterally adjacent to the intermediate depth portion of the step, the third type of dielectric bridge structure 72C located laterally adjacent to the deepest portion of the step (which includes the bottommost stepped surface (e.g., the stepped surface of the first conductive layer 146)) may be closer to each other (i.e., laterally spaced apart by a smaller distance along the first horizontal direction hd1). Compared to the first type of dielectric bridge structure 72A located laterally adjacent to the shallowest portion of the step, the second type of dielectric bridge structure 72B may be closer to each other (i.e., laterally spaced apart by a smaller distance along the first horizontal direction hd1). Thus, compared to dielectric bridge structures having a larger pitch, dielectric bridge structures having a smaller pitch are located laterally adjacent to a deeper portion of the step.

[0161] In this embodiment, the first type of dielectric bridge structure 72A, the second type of dielectric bridge structure 72B, and the third type of dielectric bridge structure 72C may have the same volume (i.e., the same length, width, and thickness). Alternatively, the first type of dielectric bridge structure 72A, the second type of dielectric bridge structure 72B, and the third type of dielectric bridge structure 72C may have different volumes from each other. For example, the third type of dielectric bridge structure 72C may have a larger volume (e.g., a larger length, width, and / or thickness) and a smaller pitch than the second type of dielectric bridge structure 72B. The second type of dielectric bridge structure 72B may have a larger volume (e.g., a larger length, width, and / or thickness) and a smaller pitch than the first type of dielectric bridge structure 72A.

[0162] Referring to all of the accompanying drawings and in accordance with various embodiments of the present disclosure, a three-dimensional memory device includes: at least one alternating stack [{(132, 146), (232, 246), (332, 346)}, (32, 46)] of an insulating layer {(132, 232, 332), 32} and a conductive layer {(146, 246, 346), 46}, the at least one alternating stack having a first longitudinal sidewall LS1 and a second longitudinal sidewall LS2 that extend laterally along a first horizontal direction hd1; a memory opening 49 that extends vertically through the at least one alternating stack [{(132, 146), (232, 246), (332, 346)}, (32, 46)]; a memory opening fill structure 58 that is located in the memory opening 49, wherein each memory opening fill structure in the memory opening fill structure 58 includes a vertical semiconductor channel 60 and a corresponding vertical stack of memory elements (e.g., portions of a memory film 50) at respective levels of the conductive layer {(146, 246, 346), 46}; and a first laterally extending trench fill structure {72A, 72B, 72C and (74, 76) or 176} that contacts the first longitudinal sidewall LS1 of the at least one alternating stack [{(132, 146), (232, 246), (332, 346)}, (32, 46)]. The first laterally extending trench fill structure {72A, 72B, 72C and (74, 76) or 176} includes: a first type dielectric bridge structure 72A having a first volume; a second type dielectric bridge structure 72B having a second volume that is greater than the first volume; and a first trench dielectric material portion {(74, 76) or 176}.

[0163] In Figures 14A to 14H one embodiment shown, the second type dielectric bridge structure 72B has a greater vertical thickness (i.e., height) than the first type dielectric bridge structure 72A. In Figure 14I and Figure 14J an alternative embodiment shown, as an alternative or in addition to the greater vertical thickness, the second type dielectric bridge structure 72B has at least one of a greater horizontal length along the first horizontal direction hd1 or a greater horizontal width along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1, as compared to the first type dielectric bridge structure 72A.

[0164] In one embodiment, the first type of dielectric bridge structure 72A has a first top surface located in a first horizontal plane HP1 and has a first bottom surface vertically spaced apart from the first horizontal plane HP1 by a first vertical distance (such as a first vertical extent VE1). The second type of dielectric bridge structure 72B has a second top surface located in the first horizontal plane HP1 and has a second bottom surface vertically spaced apart from the first horizontal plane HP1 by a second vertical distance (such as a second vertical extent VE2), the second vertical distance being greater than the first vertical distance VE1.

[0165] In one embodiment, the first trench dielectric material portion (74 or 176) includes a topmost surface segment located between the first type of dielectric bridge structure 72A and the second type of dielectric bridge structure 72B in the first horizontal plane HP1, a first recessed surface segment contacting the first bottom surface, and a second recessed surface segment contacting the second bottom surface.

[0166] In Figure 23 In the embodiment shown, the first laterally extending trench fill structure {72A, 72B, 72C and (74, 76) or 176} includes a plurality of first type dielectric bridge structures 72A having a first volume and a first pitch; and a plurality of second type dielectric bridge structures 72B having a second volume and a second pitch, the second volume being greater than the first volume and the second pitch being less than the first pitch.

[0167] In one embodiment, the three-dimensional memory device further includes at least one backward stepped dielectric material portion {(165, 265, 365), 65} embedded in at least one alternating stack [{(132, 146), (232, 246), (332, 346)}, (32, 46)] and including a corresponding dielectric material, wherein one of the at least one backward stepped dielectric material portion {(165, 265, 365), 65} contacts each of the first type dielectric bridge structure 72A, the second type dielectric bridge structure 72B, and the first trench dielectric material portion (74 or 176).

[0168] In one embodiment, at least one alternating stack [{(132, 146), (232, 246), (332, 346)}, (32, 46)] includes a step having a stepped surface “S”. The stepped surface S contacts the stepped bottom surface of at least one backward stepped dielectric material portion {(165, 265, 365), 65}. The step includes corresponding longitudinal sidewalls LS1 that contact a first laterally extending trench fill structure {72A, 72B, 72C and (74, 76) or 176}. A memory opening fill structure 58 is located in a first memory array region 100A and a second memory array region 100B. The step is located between the first memory array region 100A and the second memory array region 100B. A conductive layer {(146, 246, 346), 46} extends continuously from the first memory array region 100A to the second memory array region 100B (e.g., along a first horizontal direction hd1 corresponding to the word line direction). A first type of dielectric bridge structure 72A is located laterally adjacent to an upper portion of the step; and a second type of bridge structure 72B is located laterally adjacent to a lower portion of the step, the lower portion of the step being closer to the substrate 9 than the upper portion of the step.

[0169] In one embodiment, the three-dimensional memory device further includes a layer contact via structure 86 that extends vertically through at least one backward stepped dielectric material portion {(165, 265, 365), 65} and contacts the top surface of a corresponding conductive layer {(146, 246, 346), 46} within at least one alternating stack [{(132, 146), (232, 246), (332, 346)}, (32, 46)].

[0170] In one embodiment, at least one backward stepped dielectric material portion {(165, 265, 365), 65} is laterally spaced apart from a second longitudinal sidewall LS2.

[0171] In one embodiment, the first laterally extending trench fill structure {72A, 72B, 72C, (74, 76) or 176} further includes an additional first type of dielectric bridge structure 72A that is laterally spaced apart from the first type of dielectric bridge structure 72A and the second type of dielectric bridge structure 72B and does not directly contact any conductive layer {(146, 246, 346), 46} within at least one alternating stack [{(132, 146), (232, 246), (332, 346)}, (32, 46)] or at least one backward stepped dielectric material portion {(165, 265, 365), 65}.

[0172] In one embodiment, at least one backward stepped dielectric material portion {(165, 265, 365), 65} includes two or more backward stepped dielectric material portions (165, 265, 365), and the two or more backward stepped dielectric material portions include: a bottommost backward stepped dielectric material portion 165; and a topmost backward stepped dielectric material portion (265 or 365, depending on the number of layers), which covers the bottommost backward stepped dielectric material portion 165 and contacts each of the first type of dielectric bridge structure 72A, the second type of dielectric bridge structure 72B, and the first trench dielectric material portion (74 or 176).

[0173] In one embodiment, the first type of dielectric bridge structure 72A does not contact any of the two or more backward stepped dielectric material portions (165, 265, 365); and the second type of dielectric bridge structure 72B contacts the topmost backward stepped dielectric material portion (265 or 365). In one embodiment, the first trench dielectric material portion (74 or 176) contacts each of the two or more backward stepped dielectric material portions (165, 265, 365).

[0174] In one embodiment, the first laterally extending trench filling structure further includes a third type of dielectric bridge structure 72C, which has a third volume greater than the second volume of the second type of dielectric bridge structure 72B.

[0175] In one embodiment, the three-dimensional memory device includes a second laterally extending trench filling structure {72A, (74, 76) or 176}, which contacts at least one second longitudinal sidewall LS2 of an alternating stack [{(132, 146), (232, 246), (332, 346)}, (32, 46)] and includes additional dielectric bridge structures. Each of the additional dielectric bridge structures in the second laterally extending trench filling structure {72A, (74, 76) or 176} has a first volume. In one embodiment, each of the additional dielectric bridge structures 72A has the same vertical thickness, horizontal length, and horizontal width as each of the first type of dielectric bridge structures 72A; and the second laterally extending trench filling structure {72A, (74, 76) or 176} includes a second trench dielectric material portion (74 or 176), which contacts each of the additional dielectric bridge structures and has the same material composition as the first trench dielectric material portion (74 or 176).

[0176] Although the foregoing relates to specific preferred embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art can envision various modifications to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. If publications, patent applications, and / or patents are cited herein, each such document is incorporated herein by reference in its entirety.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising: At least one alternating stack of insulating layers and conductive layers, the at least one alternating stack having a first longitudinal sidewall and a second longitudinal sidewall that extend laterally along a first horizontal direction; Memory openings that extend vertically through the at least one alternating stack; Memory opening fill structures located in the memory openings, wherein each memory opening fill structure in the memory opening fill structures includes a vertical semiconductor channel and a corresponding vertical stack of memory elements at each level of the conductive layer; And A first laterally extending trench fill structure that contacts the first longitudinal sidewall of the at least one alternating stack and includes: A first type dielectric bridge structure having a first volume; A second type dielectric bridge structure having a second volume, the second volume being greater than the first volume; and A first trench dielectric material portion.

2. The three-dimensional memory device according to claim 1, wherein the second type dielectric bridge structure has a greater vertical thickness than the first type dielectric bridge structure.

3. The three-dimensional memory device according to claim 2, wherein: The first type dielectric bridge structure has a first top surface located in a first horizontal plane and a first bottom surface that is vertically spaced from the first horizontal plane by a first vertical distance; The second type dielectric bridge structure has a second top surface located in the first horizontal plane and a second bottom surface that is vertically spaced from the first horizontal plane by a second vertical distance, the second vertical distance being greater than the first vertical distance; and The first trench dielectric material portion includes a topmost surface segment located in the first horizontal plane between the first type dielectric bridge structure and the second type dielectric bridge structure, a first recessed surface segment that contacts the first bottom surface, and a second recessed surface segment that contacts the second bottom surface.

4. The three-dimensional memory device according to claim 1, wherein the first laterally extending trench fill structure includes: A plurality of the first type dielectric bridge structures having the first volume and a first pitch; And A plurality of the second type dielectric bridge structures having a second volume and a second pitch, the second volume being greater than the first volume, the second pitch being different from the first pitch.

5. The three-dimensional memory device according to claim 1, wherein the second type dielectric bridge structure has at least one of a greater horizontal length along the first horizontal direction or a greater horizontal width along a second horizontal direction compared to the first type dielectric bridge structure, the second horizontal direction being perpendicular to the first horizontal direction.

6. The three-dimensional memory device according to claim 1, the three-dimensional memory device further comprising at least one backward stepped dielectric material portion, the at least one backward stepped dielectric material portion being embedded within the at least one alternating stack and comprising a respective dielectric material, wherein one of the at least one backward stepped dielectric material portions contacts each of the first type of dielectric bridge structure, the second type of dielectric bridge structure, and the first trench dielectric material portion.

7. The three-dimensional memory device according to claim 6, wherein: the at least one alternating stack includes a step having a stepped surface; the stepped surface contacts the stepped bottom surface of the at least one backward stepped dielectric material portion; the step includes respective longitudinal sidewalls that contact the first laterally extending trench fill structure; the memory opening fill structure is located in a first memory array region and a second memory array region; the step is located between the first memory array region and the second memory array region; the conductive layer extends continuously from the first memory array region to the second memory array region; the first type of dielectric bridge structure is located laterally adjacent to an upper portion of the step; and the second type of bridge structure is located laterally adjacent to a lower portion of the step.

8. The three-dimensional memory device according to claim 6, the three-dimensional memory device further comprising a layer contact via structure that extends vertically through the at least one backward stepped dielectric material portion and contacts a top surface of a respective conductive layer within the at least one alternating stack.

9. The three-dimensional memory device according to claim 6, wherein the at least one backward stepped dielectric material portion is laterally spaced apart from the second longitudinal sidewall.

10. The three-dimensional memory device according to claim 6, wherein the first laterally extending trench fill structure further includes an additional first type of dielectric bridge structure that is laterally spaced apart from the first type of dielectric bridge structure and the second type of dielectric bridge structure and does not directly contact any conductive layer within the at least one alternating stack or the at least one backward stepped dielectric material portion.

11. The three-dimensional memory device according to claim 6, wherein the at least one backward stepped dielectric material portion includes two or more backward stepped dielectric material portions, the two or more backward stepped dielectric material portions including: a bottommost backward stepped dielectric material portion; and a topmost backward stepped dielectric material portion that covers the bottommost backward stepped dielectric material portion and contacts each of the first type of dielectric bridge structure, the second type of dielectric bridge structure, and the first trench dielectric material portion.

12. The three-dimensional memory device according to claim 11, wherein: The first type of dielectric bridge structure does not contact any of the two or more backward stepped dielectric material portions; The second type of dielectric bridge structure contacts the topmost backward stepped dielectric material portion; and The first trench dielectric material portion contacts each of the two or more backward stepped dielectric material portions.

13. The three-dimensional memory device according to claim 1, wherein the first laterally extending trench fill structure further comprises a third type of dielectric bridge structure having a third volume greater than the second volume.

14. The three-dimensional memory device according to claim 1, the three-dimensional memory device further comprising a second laterally extending trench fill structure that contacts the at least one alternating stack of the second longitudinal sidewalls and includes additional dielectric bridge structures, wherein each of the additional dielectric bridge structures within the second laterally extending trench fill structure has the first volume, wherein: Each of the additional dielectric bridge structures has the same vertical thickness, horizontal length, and horizontal width as each of the first type of dielectric bridge structures; and The second laterally extending trench fill structure includes a second trench dielectric material portion that contacts each of the additional dielectric bridge structures and has the same material composition as the first trench dielectric material portion.

15. A three-dimensional memory device, the three-dimensional memory device comprising: At least one alternating stack of insulating layers and conductive layers having first and second longitudinal sidewalls extending laterally along a first horizontal direction; Memory openings extending vertically through the at least one alternating stack; Memory opening fill structures located within the memory openings, wherein each of the memory opening fill structures includes a vertical semiconductor channel and a corresponding vertical stack of memory elements at respective levels of the conductive layers; and A first laterally extending trench fill structure that contacts the first longitudinal sidewall of the at least one alternating stack and includes: A first trench dielectric material portion; A plurality of the first type of dielectric bridge structures having a first volume and a first pitch; and A plurality of the second type of dielectric bridge structures having a second volume and a second pitch, the second volume being greater than the first volume, the second pitch being different from the first pitch.

16. A method of forming a three-dimensional memory device, the method comprising: Forming at least one vertical alternating sequence of an insulating layer and a sacrificial material layer over a substrate; Forming memory openings through the at least one vertical alternating sequence; A memory opening fill structure is formed in the memory opening, wherein each memory opening fill structure in the memory opening fill structure includes a vertical semiconductor channel and a corresponding vertical stack of memory elements; A laterally extending trench is formed through the at least one vertical alternating sequence, the laterally extending trench including a first laterally extending trench and a second laterally extending trench; A first sacrificial laterally extending trench fill structure and a second sacrificial laterally extending trench fill structure are respectively formed in the first laterally extending trench and the second laterally extending trench; By recessing portions of the first sacrificial laterally extending trench fill structure, a first type of groove cavity having a first volume and a second type of groove cavity having a second volume are formed, wherein the second volume is greater than the first volume; A first type of dielectric bridge structure and a second type of dielectric bridge structure are respectively formed in the first type of groove cavity and the second type of groove cavity; The first sacrificial laterally extending trench fill structure and the second sacrificial laterally extending trench fill structure are removed; And The remaining portion of the sacrificial material layer is replaced with a conductive layer.

17. The method according to claim 16, wherein the first type of groove cavity has a first depth, and the second type of groove cavity has a second depth, the second depth being greater than the first depth.

18. The method according to claim 17, the method further comprising: Forming an additional groove cavity by recessing portions of the second sacrificial laterally extending trench fill structure; And Forming an additional dielectric bridge structure in the additional groove cavity, wherein each dielectric bridge structure formed within the second laterally extending trench has a vertical extent equal to the first depth.

19. The method according to claim 17, wherein: The bottommost surface of the first type of dielectric bridge structure is formed above a horizontal plane including the top surface of the topmost sacrificial material layer in the sacrificial material layer; And The bottommost surface of the second type of dielectric bridge structure is formed below the horizontal plane including the top surface of the topmost sacrificial material layer.

20. The method according to claim 16, the method further comprising: Forming at least one set of stepped surfaces by patterning the at least one vertical alternating sequence; And Forming at least one backward stepped dielectric material portion above the at least one set of stepped surfaces, Wherein: The first laterally extending trench cuts through the at least one backward stepped dielectric material portion; The second laterally extending trench is laterally spaced apart from the at least one backward stepped dielectric material portion; The first type of dielectric bridge structure does not contact any of the backward stepped dielectric material portions in the at least one backward stepped dielectric material portion; and The second type of dielectric bridge structure is directly formed on the sidewall of the at least one backward stepped dielectric material portion.

Images