Semiconductor device

Abstract

Provided is a semiconductor device occupying a small area. The semiconductor device includes a first insulating layer, a second insulating layer, and a transistor. The transistor is disposed on the first insulating layer and includes a semiconductor layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode. The second insulating layer includes an opening to the first insulating layer. The source electrode and the drain electrode are arranged on the second insulating layer. The semiconductor layer is provided so as to be in contact with a side surface of the second insulating layer in the opening, a top surface of the first insulating layer in the opening, and side surfaces of the source electrode and the drain electrode. The gate insulating layer is located on the semiconductor layer, the source electrode and the drain electrode. The gate electrode overlaps the opening and is located on the gate insulating layer.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same. One aspect of the present invention relates to a transistor and a method for manufacturing the same. One aspect of the present invention relates to a display device including a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. As an example of the technical field of one aspect of the present invention, semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and driving methods or manufacturing methods of the above devices can be cited.

[0003] Note that in this specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.), and a device including such a circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips having integrated circuits, and electronic components in which chips are housed in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices themselves are semiconductor devices, and sometimes all include semiconductor devices. Background Art

[0004] Semiconductor devices including transistors are widely used in electronic devices. In recent years, the uses of display devices have been diversifying. For example, display devices are used in portable information terminals, television devices (also referred to as television receivers), digital signage (electronic bulletin boards), and PIDs (public information displays). As display devices, for example, display devices including organic EL (electro luminescence) elements or light-emitting diodes (LEDs: light-emitting diodes), display devices including liquid crystal elements, and electronic paper that performs display by electrophoresis are cited.

[0005] In a display device, by reducing the occupied area of a transistor, the pixel size can be reduced, and thus the definition can be improved. In addition, by reducing the occupied area of a transistor, the aperture ratio can be increased. Therefore, micro transistors are in demand.

[0006] Devices that require high-definition display devices, such as those for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR), are actively being developed.

[0007] A high-definition display device using an organic EL element is disclosed in Patent Document 1. [Prior Art Documents] [Patent Documents]

[0008] [Patent Document 1] International Patent Application Publication No. 2016 / 038508 Summary of the Invention Technical Problem to be Solved by the Invention

[0009] One of the objects of one aspect of the present invention is to provide a micro transistor. One of the objects of one aspect of the present invention is to provide a transistor with a long channel length. One of the objects of one aspect of the present invention is to provide a transistor with a long channel length and a transistor with a short channel length. One of the objects of one aspect of the present invention is to provide a transistor with good electrical characteristics. One of the objects of one aspect of the present invention is to provide a semiconductor device with a small occupied area. One of the objects of one aspect of the present invention is to provide a semiconductor device with low wiring resistance. One of the objects of one aspect of the present invention is to provide a semiconductor device or a display device with low power consumption. One of the objects of one aspect of the present invention is to provide a transistor, a semiconductor device, or a display device with high reliability. One of the objects of one aspect of the present invention is to provide a high-definition display device. One of the objects of one aspect of the present invention is to provide a manufacturing method for a semiconductor device or a display device with high productivity. One of the objects of one aspect of the present invention is to provide a novel transistor, semiconductor device, display device, or a manufacturing method thereof.

[0010] Note that the description of these objects does not preclude the existence of other objects. One aspect of the present invention does not need to achieve all of the above objects. Objects other than the above can be extracted from the description of the specification, drawings, and claims. Means for Solving the Technical Problem

[0011] One aspect of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, and a transistor. The transistor is provided on the first insulating layer. The transistor includes a semiconductor layer, a gate insulating layer, a first gate electrode, a source electrode, and a drain electrode. The second insulating layer includes an opening reaching the first insulating layer. The source electrode and the drain electrode are provided on the second insulating layer. The semiconductor layer is provided in contact with the side surface of the second insulating layer in the opening and the side surfaces of the source electrode and the drain electrode. The gate insulating layer is located on the semiconductor layer, the source electrode, and the drain electrode. The first gate electrode overlaps with the opening and is located on the gate insulating layer.

[0012] One aspect of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, and a transistor. The transistor is provided on the first insulating layer. The transistor includes a semiconductor layer, a gate insulating layer, a first gate electrode, a source electrode, and a drain electrode. The second insulating layer includes an opening reaching the first insulating layer. The source electrode and the drain electrode are provided on the second insulating layer. The semiconductor layer has a first region in contact with the side surface of the second insulating layer in the opening, a second region in contact with the side surface of the source electrode, and a third region in contact with the side surface of the drain electrode in the opening. In the semiconductor layer, the first region is located between the second region and the third region. The gate insulating layer is located on the semiconductor layer, the source electrode, and the drain electrode. The first gate electrode overlaps with the opening and is located on the gate insulating layer.

[0013] One aspect of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, and a transistor. The transistor is provided on the first insulating layer and includes a semiconductor layer, a gate insulating layer, a first gate electrode, a source electrode, and a drain electrode. The second insulating layer includes an opening reaching the first insulating layer. The source electrode and the drain electrode are provided on the second insulating layer. The semiconductor layer is provided in contact with the side surface of the second insulating layer in the opening, the top surface of the first insulating layer in the opening, and the side surfaces of the source electrode and the drain electrode. The gate insulating layer is located on the semiconductor layer, the source electrode, and the drain electrode. The first gate electrode overlaps with the opening and is located on the gate insulating layer.

[0014] In the above semiconductor device, the semiconductor layer preferably contacts one or both of the top surfaces of the source electrode and the drain electrode.

[0015] In the above semiconductor device, the first insulating layer and the gate insulating layer preferably have a portion in contact at the bottom of the opening.

[0016] In the above semiconductor device, the semiconductor layer preferably has a portion in contact with the top surface of the second insulating layer.

[0017] In the above semiconductor device, a second gate electrode is preferably further included. The second gate electrode is preferably covered by the second insulating layer. A part of the second insulating layer is preferably located between the side surface of the second gate electrode and the semiconductor layer.

[0018] In the above semiconductor device, a third insulating layer is preferably included between the first insulating layer and the second gate electrode.

[0019] In the above semiconductor device, the contour shape of the opening is preferably any shape such as a circle, an ellipse, a quadrangle with rounded corners, a regular polygon, a polygon other than a regular polygon, a concave polygon, an ellipse, a polygon with rounded corners, or a closed curve combining a straight line and a curve.

[0020] In the above semiconductor device, the opening preferably includes a plurality of extending portions and one or more bending portions. The extending portion preferably has a shape extending in one direction in a top view. One extending portion is preferably connected to another extending portion through a bending portion.

[0021] One aspect of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, a first transistor, and a second transistor. The first transistor is provided on the first insulating layer and includes a first semiconductor layer, a gate insulating layer, a first gate electrode, a first source electrode, and a first drain electrode. The second insulating layer includes a first opening reaching the first insulating layer. The first source electrode and the first drain electrode are provided on the second insulating layer. The first semiconductor layer is provided in contact with the side surface of the second insulating layer in the first opening, the top surface of the first insulating layer in the first opening, and the side surfaces of the first source electrode and the first drain electrode. The gate insulating layer is located on the first semiconductor layer, the first source electrode, and the first drain electrode. The first gate electrode overlaps with the first opening and is located on the gate insulating layer. The second transistor includes a second semiconductor layer, a gate insulating layer, a second gate electrode, a second source electrode, and a second drain electrode. The second source electrode and the second drain electrode are at different heights. The second insulating layer includes a second opening reaching one of the second source electrode and the second drain electrode. The other of the second source electrode and the second drain electrode is provided on the second insulating layer. The second semiconductor layer is provided in contact with the side surface of the second insulating layer in the second opening, the top surface of one of the second source electrode and the second drain electrode, and the side surface of the other of the second source electrode and the second drain electrode. The gate insulating layer is located on the second semiconductor layer, the second source electrode, and the second drain electrode. The second gate electrode overlaps with the second opening and is located on the gate insulating layer.

[0022] In the above semiconductor device, the first semiconductor layer preferably contacts one or both of the top surfaces of the first source electrode and the first drain electrode.

[0023] In the above semiconductor device, the first insulating layer and the gate insulating layer preferably have a portion in contact with the bottom of the first opening.

[0024] In the above semiconductor device, the first semiconductor layer preferably has a portion in contact with the top surface of the second insulating layer.

[0025] In the above semiconductor device, the contour shape of the first opening is preferably any shape such as a circle, an ellipse, a quadrangle with rounded corners, a regular polygon, a polygon other than a regular polygon, a concave polygon, an ellipse, a polygon with rounded corners, or a closed curve combining a straight line and a curve.

[0026] In the above semiconductor device, the first opening preferably includes a plurality of extension portions and one or more bending portions. The extension portions preferably have a shape extending in one direction in a top view. One extension portion is preferably connected to another extension portion through a bending portion. Advantages of the Invention

[0027] According to one aspect of the present invention, a micro transistor can be provided. According to one aspect of the present invention, a transistor with a long channel length can be provided. According to one aspect of the present invention, a transistor with a long channel length and a transistor with a short channel length can be provided. According to one aspect of the present invention, a transistor with good electrical characteristics can be provided. According to one aspect of the present invention, a semiconductor device with a small occupied area can be provided. According to one aspect of the present invention, a semiconductor device with a low wiring resistance can be provided. According to one aspect of the present invention, a semiconductor device or a display device with low power consumption can be provided. According to one aspect of the present invention, a transistor, a semiconductor device, or a display device with high reliability can be provided. According to one aspect of the present invention, a high-definition display device can be provided. According to one aspect of the present invention, a manufacturing method of a semiconductor device or a display device with high productivity can be provided. According to one aspect of the present invention, a novel transistor, semiconductor device, display device, or their manufacturing methods can be provided.

[0028] Note that the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have all of the above effects. Effects other than the above can be extracted from the descriptions in the specification, drawings, and claims. Brief Description of the Drawings

[0029] Figure 1A is a perspective schematic diagram of a transistor. Figure 1B is a cross-sectional schematic diagram of a transistor. Figure 2A and Figure 2B is a perspective schematic diagram of a transistor. Figures 3A to 3C is a perspective schematic diagram of a transistor. Figure 4A and Figure 4B is a perspective schematic diagram of a transistor. Figure 5A is a perspective schematic diagram of a transistor. Figure 5B is a cross-sectional schematic diagram of a transistor. Figure 6It is a three-dimensional schematic diagram of a transistor. Figure 7A and Figure 7B It is a three-dimensional schematic diagram of a transistor. Figure 8A and Figure 8B It is a three-dimensional schematic diagram of a transistor. Figure 9A It is a top view schematic diagram of a transistor. Figure 9B It is a cross-sectional schematic diagram of a transistor. Figure 10A It is a three-dimensional schematic diagram of a transistor. Figure 10B It is a top view schematic diagram of a transistor. Figures 11A to 11E It is a top view schematic diagram of a transistor. Figure 12A It is a top view showing an example of a semiconductor device. Figure 12B It is a cross-sectional view showing an example of a semiconductor device. Figure 13A It is a top view showing an example of a semiconductor device. Figure 13B It is a cross-sectional view showing an example of a semiconductor device. Figure 14A It is a top view showing an example of a semiconductor device. Figure 14B It is a cross-sectional view showing an example of a semiconductor device. Figure 15A It is a top view showing an example of a semiconductor device. Figure 15B It is a cross-sectional view showing an example of a semiconductor device. Figure 16A It is a top view showing an example of a semiconductor device. Figure 16B It is a cross-sectional view showing an example of a semiconductor device. Figure 17A It is a top view showing an example of a semiconductor device. Figure 17B It is a cross-sectional view showing an example of a semiconductor device. Figure 18A It is a top view showing an example of a semiconductor device. Figure 18B It is a cross-sectional view showing an example of a semiconductor device. Figure 19A and Figure 19B It is a cross-sectional view showing an example of a semiconductor device. Figures 20A to 20E It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figures 21A to 21D It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Figures 22A to 22DIt is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 23A And Figure 23B It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 24A And Figure 24B It is a top view showing an example of a method for manufacturing a semiconductor device. Figure 25A And Figure 25B It is a top view showing an example of a method for manufacturing a semiconductor device. Figures 26A to 26D It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figures 27A to 27D It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figures 28A to 28D It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 29A And Figure 29B It is a top view showing an example of a method for manufacturing a semiconductor device. Figure 30A And Figure 30B It is a top view showing an example of a method for manufacturing a semiconductor device. Figure 31A It is a perspective view showing an example of a display device. Figure 31B It is a block diagram showing an example of a display device. Figure 32A It is a circuit diagram of a latch circuit. Figure 32B It is a circuit diagram of an inverter circuit. Figure 33A And Figure 33B It is a circuit diagram of a pixel circuit. Figure 33C It is a cross-sectional view showing an example of a pixel circuit. Figure 34 It is a cross-sectional view showing an example of a pixel circuit. Figure 35 It is a schematic cross-sectional view showing an example of the structure of a display device. Figure 36A And Figure 36B It is a diagram for explaining an example of the structure of an electronic device. Figure 37A And Figure 37B It is a diagram for explaining an example of the structure of an electronic device. Figure 38A And Figure 38B It is a diagram for explaining an example of the structure of a display device. Figure 39 It is a diagram for explaining an example of the structure of a display device. Figures 40A to 40C It is a perspective view of the display module. Figure 41A and Figure 41B It is a diagram showing an example of the structure of the display device. Figures 42A to 42D It is a diagram showing an example of the structure of the display device. Figures 43A to 43D It is a diagram showing an example of the structure of the display device. Figure 44A and Figure 44B It is a diagram showing an example of the structure of the display device. Figures 45A to 45D It is a diagram showing an example of the structure of the display device. Figures 46A to 46C It is a diagram showing an example of the structure of the display device. Figures 47A to 47F It is a diagram showing an example of the electronic device. Figures 48A to 48G It is a diagram showing an example of the electronic device. Figure 49A It is a diagram explaining the sub-display unit. Figures 49B1 to 49B7 It is a diagram showing an example of the structure of the pixel. Figures 50A to 50G It is a diagram showing an example of the structure of the pixel. Figures 51A to 51D It is a diagram showing an example of the structure of the light-emitting device. Embodiment

[0030] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and it is easily understood by those of ordinary skill in the art that the modes and details thereof can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the contents described in the following embodiments.

[0031] Note that in the structure of the invention described below, the same parts or parts having the same functions are denoted by the same reference numerals in different drawings, and repeated description is omitted. In addition, when indicating parts having the same functions, the same hatching is sometimes used, and reference numerals are not particularly added.

[0032] In addition, in this specification and the like, when the same symbol is used for multiple elements and it is necessary to distinguish them, sometimes symbols for identification such as "_1", "[n]", "[m, n]" are attached to the symbol. In addition, in the drawings and the like, in the case where symbols for identification such as "_1", "[n]", "[m, n]" are attached to the symbol, if it is not necessary to distinguish them in this specification and the like, sometimes symbols for identification such as "_1", "[n]", "[m, n]" are not attached.

[0033] For ease of understanding, sometimes the positions, sizes, ranges, etc. of the respective components shown in the drawings do not represent their actual positions, sizes, ranges, etc. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings.

[0034] In this specification and the like, for convenience, ordinal numbers such as "first" and "second" are attached, but they do not limit the number of components or the order of the components (for example, the process order or the stacking order). In addition, the ordinal numbers attached to a component in a certain part of this specification may sometimes be inconsistent with the ordinal numbers attached to the same component in other parts of this specification or in the claims.

[0035] In addition, depending on the situation or state, "film" and "layer" can be interchanged with each other. For example, "conductive layer" can be changed to "conductive film". In addition, "insulating film" can be changed to "insulating layer".

[0036] A transistor is a type of semiconductor device, and can achieve functions such as amplifying current or voltage, and switching operations for controlling conduction or non-conduction. The transistors in this specification and the like include IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs: Thin Film Transistors).

[0037] In cases where transistors with different polarities are used or the direction of the current changes during the operation of the circuit, etc., the functions of the source and drain sometimes interchange with each other. Therefore, in this specification and the like, "source" and "drain" can be used interchangeably. Note that depending on the situation, the source and drain of the transistor can be appropriately renamed as source terminal and drain terminal or source electrode and drain electrode, etc.

[0038] In addition, "gate" and "back gate" can be interchanged. Therefore, in this specification and the like, "gate" and "back gate" can be used interchangeably. Note that depending on the situation, the gate and back gate of the transistor can be appropriately renamed as gate electrode and back gate electrode, etc.

[0039] In this specification and the like, "electrically connected" includes cases where connection is made through "elements having certain electrical functions". Here, the "elements having certain electrical functions" are not particularly limited as long as they can transmit and receive electrical signals between the connection targets. For example, the "elements having certain electrical functions" include switching elements such as transistors, resistive elements, coils, and other elements having various functions, in addition to electrodes or wirings.

[0040] In this specification and the like, in the absence of special instructions, the off-state current refers to the leakage current between the source and the drain when the transistor is in the off state (also referred to as the non-conducting state, the cut-off state). In the absence of special instructions, in an n-channel transistor, the off state refers to the voltage V between the gate and the source gs being lower than the threshold voltage V th (in a p-channel transistor, V gs being higher than V th ).

[0041] In this specification and the like, "substantially the same top surface shape" means that at least a part of the edges of each layer in the stack overlap. For example, it includes cases where the upper layer and the lower layer are processed by the same mask pattern or a part of the same mask pattern. However, in practice, there are cases where the edges do not overlap, and sometimes the upper layer is inside the lower layer or the upper layer is outside the lower layer, and this case can also be said to have "substantially the same top surface shape". When the top surface shapes are the same or substantially the same, it can also be said that the ends are aligned or substantially aligned.

[0042] In this specification and the like, the conical shape means a shape in which at least a part of the side surface of the constituent element is inclined with respect to the substrate surface or the surface to be formed. For example, it preferably has a region where the angle (also referred to as the conical angle) formed by the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Here, the side surface of the constituent element, the substrate surface, and the surface to be formed do not necessarily have to be completely flat, and may be an approximately planar shape with a small curvature or an approximately planar shape with fine irregularities.

[0043] In this specification and the like, sometimes a device manufactured using a metal mask or an FMM (Fine Metal Mask, high-precision metal mask) is referred to as a device having an MM (Metal Mask) structure. In addition, in this specification and the like, sometimes a device not manufactured using a metal mask or an FMM is referred to as a device having an MML (MetalMask Less) structure. Note that since a device with an MML structure can be manufactured without using a metal mask, it can exceed the upper limit of the resolution due to the alignment accuracy of the metal mask. In addition, a device with an MML structure does not require the equipment and the washing process of the metal mask for manufacturing. In addition, a device with an MML structure can reduce the manufacturing cost, so it is suitable for mass production.

[0044] In this specification and the like, a structure in which light-emitting layers are separately formed in light-emitting devices (also referred to as light-emitting elements) having different light-emitting wavelengths is sometimes referred to as an SBS (Side By Side) structure. Since the SBS structure allows the materials and structure to be optimized for each light-emitting device, the degree of freedom in the selection of materials and structure is increased, and it is possible to easily improve the luminance and reliability.

[0045] In this specification and the like, holes or electrons are sometimes referred to as "carriers". Specifically, a hole injection layer or an electron injection layer is sometimes referred to as a "carrier injection layer", a hole transport layer or an electron transport layer is sometimes referred to as a "carrier transport layer", and a hole blocking layer or an electron blocking layer is sometimes referred to as a "carrier blocking layer". Note that the above carrier injection layer, carrier transport layer, and carrier blocking layer cannot sometimes be clearly distinguished based on their cross-sectional shape or characteristics, etc. In addition, sometimes one layer has the functions of two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0046] In this specification and the like, a light-emitting device includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Here, as the layers (also referred to as functional layers) included in the EL layer, a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier blocking layer (hole blocking layer and electron blocking layer) can be cited. In this specification and the like, a light-receiving element (also referred to as a light-receiving device) includes at least an active layer serving as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, sometimes one of the pair of electrodes is referred to as a pixel electrode, and the other is referred to as a common electrode.

[0047] In this specification and the like, a sacrificial layer (which may also be referred to as a mask layer) is at least located above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers constituting the EL layer), and has a function of protecting the light-emitting layer in the manufacturing process.

[0048] In this specification and the like, disconnection refers to a phenomenon in which a layer, film, or electrode is disconnected due to the shape of the formation surface (for example, a step, etc.).

[0049] (Embodiment 1) In this embodiment, a structural example of a semiconductor device according to one aspect of the present invention will be described. Here, in particular, a structure including a transistor will be described.

[0050] <Structural Example 1> Figure 1A A perspective schematic view of the transistor 20 is shown. Figure 1B A cross-sectional schematic view of a cross-section along the Figure 1A dashed line A-B in is shown. Figure 11AA plan view (also known as a top view) of transistor 20 is shown. Note that in Figure 1A and Figure 11A , some components (such as gate electrode 23, gate insulating layer 22, etc.) are omitted.

[0051] Transistor 20 is disposed on insulating layer 31 and includes a semiconductor layer 21, a gate insulating layer 22, a gate electrode 23, a source electrode 24a, and a drain electrode 24b.

[0052] An insulating layer 32 is provided on insulating layer 31. Insulating layer 32 includes an opening 30 reaching insulating layer 31. Source electrode 24a and drain electrode 24b are provided on insulating layer 32. Semiconductor layer 21 is disposed along the sidewall of insulating layer 32 in opening 30. Gate insulating layer 22 is disposed so as to cover semiconductor layer 21, insulating layer 31, source electrode 24a, drain electrode 24b, etc. Gate electrode 23 overlaps with opening 30 and is disposed so as to cover gate insulating layer 22. Semiconductor layer 21 is disposed so as to be in contact with source electrode 24a and drain electrode 24b respectively. Here, an example is shown in which semiconductor layer 21 is disposed so as to be in contact with the sidewalls and a part of the top surfaces of source electrode 24a and drain electrode 24b.

[0053] As Figure 1A and Figure 1B shown, semiconductor layer 21 is disposed along the sidewall of opening 30 (sometimes referred to as the side surface of opening 30 or the sidewall of insulating layer 32 in opening 30). Semiconductor layer 21 can also be said to be disposed along the sidewall of opening 30 in a sidewall shape. Here, the channel length L in transistor 20 corresponds to the distance along the sidewall of opening 30 between source electrode 24a and drain electrode 24b. In Figure 1A , the channel length L is indicated by a double arrow. On the other hand, the channel width W in transistor 20 is the width of semiconductor layer 21 along the depth direction of opening 30. Therefore, the channel width W can be controlled according to the thickness of insulating layer 32 and the depth of opening 30, so that a transistor with an extremely small channel width can be realized. For example, a transistor with an extremely small channel width that cannot be realized by a mass-production exposure device can be realized. In addition, a transistor with a channel width less than 10 nm can be realized without using a very expensive exposure device used in the most advanced LSI technology. In Figure 1A and Figure 1B , the channel width W is indicated by a double arrow.

[0054] The more complex the contour shape of the opening 30 (also referred to as the top surface shape, planar shape), the greater the channel length L can be increased. Here, the contour shape of the opening 30 is a rectangular shape with rounded corners, but it is not limited thereto and can be various shapes. For example, it can be a circular shape, an elliptical shape, a quadrangle with rounded corners, etc. In addition, it can be a regular polygon such as an equilateral triangle, a square, a regular pentagon, or a polygon other than a regular polygon. In addition, when it is a concave polygon such as a star polygon where at least one interior angle exceeds 180 degrees, the channel length L can be increased. In addition, an elliptical shape, a polygon with rounded corners, a closed curve combining a straight line and a curve, etc. can also be adopted.

[0055] By adopting such a structure, the channel width W of the transistor can be precisely controlled according to the thickness of the insulating layer 32, so the deviation of the channel width W can be made extremely small. And a transistor with an extremely small channel width W can be realized.

[0056] Here, as an index showing the characteristics of the transistor, the ratio of the channel width W to the channel length L (W / L ratio) is sometimes used. In existing transistors, the minimum values of the channel length and the channel width depend on the exposure limit of the exposure apparatus, so when trying to reduce the W / L ratio, it is necessary to increase L, and there is a problem that the occupied area of the transistor increases. However, in the transistor of one embodiment of the present invention, the channel width W can be made smaller than the exposure limit of the exposure apparatus, so a transistor with an extremely small W / L ratio can be realized without increasing the occupied area of the transistor.

[0057] Figure 2A An example is shown in which the semiconductor layer 21 is provided not only on the sidewalls of the opening 30 but also on the top surface of the insulating layer 32 and the top surface of the insulating layer 31 located within the opening 30. In Figure 2A In the structure shown, the channel width W of the transistor is the length of the sum of the width of the portion of the semiconductor layer 21 located on the sidewalls of the opening 30, the width of the portion located on the insulating layer 32, and the width of the portion located on the top surface of the insulating layer 31.

[0058] Note that in Figure 1A , Figure 1B and Figure 2A , the semiconductor layer 21 covers both the source electrode 24a and the drain electrode 24b, and the semiconductor layer 21 is in contact with the top surfaces of the source electrode 24a and the drain electrode 24b, but the present invention is not limited thereto. For example, a structure in which the semiconductor layer 21 covers one of the source electrode 24a and the drain electrode 24b and the semiconductor layer 21 is in contact with one of the top surfaces of the source electrode 24a and the drain electrode 24b can also be adopted. Or, for example, the semiconductor layer 21 may not cover the source electrode 24a and the drain electrode 24b and may not be in contact with the top surfaces of the source electrode 24a and the drain electrode 24b.

[0059] Figure 2B An example is shown where the semiconductor layer 21 is in contact with the side surfaces of the source electrode 24a and the drain electrode 24b, but not in contact with the top surfaces of the source electrode 24a and the drain electrode 24b. For example, when processing the semiconductor film that will become the semiconductor layer 21, the semiconductor layer 21 can be formed along the side walls of the opening 30 by using an anisotropic etching method.

[0060] Figure 3A An example is shown where the source electrode 24a and the drain electrode 24b are arranged adjacent to each other. Figure 11B A top view schematic is shown. By adopting this structure, the channel length L of the transistor can be made close to the perimeter of the opening 30, thereby enabling a transistor with a long channel length L to be realized. For example, more than 70%, preferably more than 80%, and more preferably more than 90% of the perimeter of the opening 30 is the channel length L.

[0061] Figure 3B An example is shown of the case where two transistors are arranged in one opening 30. Here, the semiconductor layer 21a and the semiconductor layer 21b are arranged without contact along the side walls of the opening 30. Thus, the transistor 20a including the semiconductor layer 21a and the transistor 20b including the semiconductor layer 21b share one opening 30. The channel widths W of the transistor 20a and the transistor 20b are equal. Note that the channel lengths L of the transistor 20a and the transistor 20b can also be different. Note that although an example of arranging two transistors in one opening 30 is shown here, three or more transistors can also be arranged.

[0062] Figure 3C An example is shown when a ring-shaped semiconductor layer 21 is provided on the entire side wall of the opening 30. Figure 11C A top view schematic is shown. The source electrode 24a is arranged in contact with a part of the ring-shaped semiconductor layer 21, and the drain electrode 24b is arranged in contact with another part. At this time, as Figure 3C shown, the semiconductor layer 21 has two paths connecting the source electrode 24a and the drain electrode 24b, one of which can have a length of the channel length L1 and the other can have a length of the channel length L2. In particular, it is preferable to symmetrically arrange the source electrode 24a and the drain electrode 24b with respect to the opening 30 such that the channel length L1 is equal to the channel length L2.

[0063] Figure 4A and Figure 4B Structural examples are shown where the shape of the opening 30 is different from the above.

[0064] Figure 4A An example is shown when a part of the contour of the opening 30 has a wavy shape. Thereby, the channel length L can be increased without increasing the occupied area of the opening 30.

[0065] Figure 4B An example is shown in which the contour shape of the opening 30 is substantially circular. Thereby, the occupied area of the transistor can be reduced. In addition, since the shape of the opening 30 is simple, its shape non-uniformity can be reduced, and thus the non-uniformity of the electrical characteristics of the transistor can be suppressed.

[0066] Figure 4A and Figure 4B An example is shown in which the source electrode 24a and the drain electrode 24b are provided so as to be embedded in the upper part of the insulating layer 32 and their top surfaces are on the same plane as the top surface of the insulating layer 32.

[0067] <Structural Example 2> Figure 5A and Figure 5B A structural example different from Structural Example 1 is shown. Figure 5A is a perspective view of the transistor 20A, Figure 5B is Figure 5A a schematic cross-sectional view of a cross-section along the dotted line A - B shown.

[0068] The main difference between the transistor 20A and the transistor shown in Structural Example 1 is that in the transistor 20A, the semiconductor layer 21 is also provided at the bottom of the opening 30.

[0069] The semiconductor layer 21 is provided in contact with the side surface of the insulating layer 32 in the opening 30, the top surface of the insulating layer 31, and the top surface of the insulating layer 32 outside the opening 30.

[0070] As Figure 5A shown, in the transistor 20A, there are mainly three paths for the current flowing through the semiconductor layer 21 between the source electrode 24a and the drain electrode 24b. One is the path RB from the source electrode 24a through the part of the semiconductor layer 21 on the side wall of the opening 30, the part at the bottom of the opening 30, and the part on the side wall of the opening 30 to the drain electrode. The second is the path RS from the source electrode 24a through the part of the semiconductor layer 21 on the side wall of the opening 30 to the drain electrode. The third is the path RT from the source electrode 24a through the part of the semiconductor layer 21 on the insulating layer 32 to the drain electrode 24b.

[0071] The path through which the current of the transistor 20A most easily flows varies depending on the shape, thickness, etc. of each component. More specifically, among the paths with the shortest distance among the above three paths, the current easily flows and the current density increases. For example, in order to achieve a structure in which more current flows through the path RS, the depth of the opening 30 is increased to extend the distance of the path RB, and the widths of the source electrode 24a and the drain electrode 24b are made smaller than the width of the opening 30 to extend the distance of the path RT.

[0072] Thus, by adopting a structure with multiple current paths, the current that can flow in the on state can be increased.

[0073] Note that the structure of the semiconductor layer 21 shown here can also be used in other structural examples.

[0074] Figure 6 An example is shown when two transistors are arranged in one opening 30. Here, the semiconductor layer 21a and the semiconductor layer 21b are arranged in contact with the side wall and bottom of the opening 30 and the top surface of the insulating layer 32 without contacting each other. The semiconductor layer 21a and the semiconductor layer 21b can be formed using the same semiconductor film. Note that although an example of arranging two transistors in one opening 30 is shown here, three or more transistors can also be arranged.

[0075] Figure 7A and Figure 7B An example is shown in a case where the shape of the opening 30 is different from the above.

[0076] As above Figure 4A Similarly, Figure 7A An example is shown when a part of the contour of the opening 30 has a wavy shape. Thereby, the channel length can be increased.

[0077] As above Figure 4B Similarly, Figure 7B An example is shown when the shape of the opening 30 is substantially circular. Thereby, the occupied area of the transistor can be reduced. In addition, since the shape of the opening 30 is simple, its shape unevenness can be reduced, and thus the electrical characteristic unevenness of the transistor can be suppressed.

[0078] Note that the structure of the opening 30 shown here can also be used in other structural examples.

[0079] <Structural Example 3> Figure 8A , Figure 8B , Figure 9A and Figure 9B An example of a structural example different from Structural Example 1 is shown. Figure 8A and Figure 8B is a perspective schematic diagram of the transistor 20B, Figure 9A is a top view schematic diagram of the transistor 20B. Figure 9B is along Figure 8A , Figure 8B and Figure 9A The cross-sectional schematic diagram of the cross-section along the dotted line A - B shown. Note that in Figure 8A , Figure 8B and Figure 9A Some constituent elements (gate electrode 23, gate insulating layer 22, etc.) are omitted. In addition, in Figure 8BIn [the figure], the insulating layer 32 is shown in perspective by a dashed line to indicate the outline of the insulating layer 32.

[0080] As Figure 8A , Figure 8B and Figure 9A shown, the main difference between the transistor 20B and the transistor 20 shown in the structural example 1 is that the opening 30 has a contour shape including an extension part and a bent part. Here, the contour shape of the opening 30 formed by combining the extension part and the bent part can be referred to as a meandering shape, a tortuous shape, a zigzag shape, or a bent shape.

[0081] As Figure 9A shown, the opening 30 includes an extension part 26a, an extension part 26b, an extension part 26c, a bent part 28a, and a bent part 28b. It can be considered that the contour shape of the opening 30 is such that the extension part 26a is connected to the extension part 26b through the bent part 28a and the extension part 26b is connected to the extension part 26c through the bent part 28b.

[0082] As Figure 9B shown, the semiconductor layer 21 is disposed along the side surface of the insulating layer 32 in the opening 30. Furthermore, the semiconductor layer 21 has a region in contact with the source electrode 24a and a region in contact with the drain electrode 24b. In addition, in the opening 30, the semiconductor layer 21 is disposed opposite to the gate electrode 23 with the gate insulating layer 22 therebetween.

[0083] Figure 9A etc. show examples in which the semiconductor layer 21 is in contact with the source electrode 24a in the extension part 26a and in contact with the drain electrode 24b in the extension part 26c. In addition, a structure in which the semiconductor layer 21 is in contact with the source electrode 24a or the drain electrode 24b in the bent part can also be adopted. For example, a structure in which the semiconductor layer 21 is in contact with the source electrode 24a in the bent part 28a and in contact with the drain electrode 24b in the bent part 28b can also be adopted.

[0084] By connecting two extension parts with one bent part, a folded structure can be formed in the opening 30. By forming one or more of the above-mentioned folded shapes, the length of the opening 30 can be made significantly larger than the distance between the source electrode 24a and the drain electrode 24b. Therefore, the channel length L can be increased without increasing the occupied area of the transistor. By increasing the channel length L, a transistor with high saturation can be realized. In addition, a transistor with an extremely small ratio of the channel width W to the channel length L (W / L ratio) can be realized.

[0085] Note that in this specification, etc., the case where the current change in the saturation region of the Id-Vd characteristics of the transistor is small is sometimes expressed as "high saturation".

[0086] Note that the structure of the opening 30 shown here can also be used in other structural examples.

[0087] Figure 10A and Figure 10B shows a structural example in which a semiconductor layer 21 is not provided on a part of the side wall of the opening 30. Figure 10A is a perspective view of the transistor 20B, Figure 10B is a top view.

[0088] Figure 10A and Figure 10B shows a structural example in which the source electrode 24a and the drain electrode 24b are provided adjacent to each other and the semiconductor layer 21 is not provided on the side wall of the opening 30 between the source electrode 24a and the drain electrode 24b. By adopting such a structure, the channel length L of the transistor can be made close to the perimeter of the opening 30, thereby increasing the channel length L.

[0089] Although Figure 10A etc. show examples in which the semiconductor layer 21 contacts the source electrode 24a and the drain electrode 24b in the extension portion 26a, one embodiment of the present invention is not limited thereto. The semiconductor layer 21 may also have a structure in which it contacts the source electrode 24a and the drain electrode 24b in the bent portion. Alternatively, a structure in which the semiconductor layer 21 contacts one of the source electrode 24a and the drain electrode 24b in the bent portion and contacts the other of the source electrode 24a and the drain electrode 24b in the extension portion may also be adopted.

[0090] In Figure 9A and Figure 10B etc. show a structure in which the opening 30 includes an extension portion 26a, an extension portion 26b, an extension portion 26c, a bent portion 28a, and a bent portion 28b, but the present invention is not limited thereto. The opening 30 only needs to include a plurality of extension portions and at least one bent portion. Here, the number of bent portions is preferably one less than the number of extension portions. For example, as Figure 11D shown, the opening 30 may also have two extension portions and one bent portion. In addition, for example, the opening 30 may also have four or more extension portions and three or more bent portions. In addition, as Figure 11E shown, the contour shape of the opening 30 may also be roller-shaped.

[0091] Note that in Figure 9A etc., the contour shape of the opening 30 is a shape with rounded corners, but one embodiment of the present invention is not limited thereto, and a shape in which the corners of the extension portion and the bent portion are angular may also be adopted. At this time, the contour shape of the opening 30 may also be referred to as a sawtooth shape.

[0092] Note that the structure of the semiconductor layer 21 shown here can also be used in other structural examples.

[0093] At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0094] (Embodiment 2) In this embodiment, with reference to FIGS. 12 to Figure 19B a semiconductor device according to one aspect of the present invention will be described.

[0095] <Structural Example 1> Figure 12A A top view (also referred to as a plan view) of the semiconductor device 10 is shown. Figure 12B A cross-sectional view of a cross-section along the Figure 12A indicated dotted line A1 - A2 is shown. Note that in Figure 12A , some constituent elements (such as an insulating layer) of the semiconductor device 10 are omitted. Regarding the top view of the semiconductor device, Figure 12A similarly, some constituent elements are also omitted in the following drawings.

[0096] The semiconductor device 10 includes a transistor 100, a transistor 200, and an insulating layer 110. The transistor 100, the transistor 200, and the insulating layer 110 are provided on a substrate 102. In addition, an insulating layer that will become a base film may be provided on the substrate 102. In this case, the transistor 100, the transistor 200, and the insulating layer 110 are formed on the insulating layer that will become a base film. Therefore, hereinafter, the top surface of the substrate 102 also includes the top surface of the insulating layer that will become a base film on the substrate 102.

[0097] The transistor 100 and the transistor 200 have different structures. In addition, the transistor 100 and the transistor 200 can be formed using a part of the processes in common. Note that when the semiconductor device 10 is applied to a display device, it is preferable to use the transistor 100 as a selection transistor for a pixel and the transistor 200 as a driving transistor. More specifically, since the saturation of the driving transistor is preferably high, it is suitable to use the transistor 200 with a long channel length. Thus, in the semiconductor device according to one aspect of the present invention, the following excellent effects are exhibited: By utilizing the thickness and pattern formation of the insulating layer, transistors with different channel lengths can be freely designed on the same substrate.

[0098] The structure of the transistor 200 will be described below. Here, an example in which the structure of the above-described transistor 20 is used for the transistor 200 is shown.

[0099] The transistor 200 includes a conductive layer 204, conductive layers 212a and 212b, an insulating layer 106, and a semiconductor layer 208. In the transistor 200, the conductive layer 204 is used as a gate electrode, and a part of the insulating layer 106 is used as a gate insulating layer. One of the conductive layers 212a and 212b is used as a source electrode, and the other is used as a drain electrode. Each layer constituting the transistor 200 may have a single-layer structure or a laminated structure. The conductive layer 204, the conductive layers 212a and 212b, the insulating layer 106, and the semiconductor layer 208 may refer to the descriptions of the above-mentioned gate electrode 23, source electrode 24a, drain electrode 24b, gate insulating layer 22, and semiconductor layer 21.

[0100] The insulating layer 110 includes an opening 145. The conductive layers 212a and 212b are provided on the insulating layer 110. Preferably, partial end portions of the conductive layers 212a and 212b are aligned with the end portion of the insulating layer 110 on one side of the opening 145. The conductive layers 212a and 212b may use the same material. In addition, the conductive layer 212a may be formed by the same process as the conductive layer 212b. For example, by forming a film that will become the conductive layers 212a and 212b and processing the film, the conductive layers 212a and 212b can be formed. The insulating layer 110 and the opening 145 may refer to the descriptions of the above-mentioned insulating layer 32 and opening 30.

[0101] The semiconductor layer 208 is provided in a sidewall shape in contact with the sidewall of the opening 145 (sometimes referring to the side surface of the opening 145 or the side surface of the insulating layer 110 in the opening 145). The semiconductor layer 208 is provided in contact with the side surfaces of the conductive layer 212a, the conductive layer 212b, and the insulating layer 110. In addition, as Figure 12B shown, the bottom surface of the semiconductor layer 208 may also be in contact with the top surface of the substrate 102. Note that the semiconductor layer 208 is not formed to cover the substrate 102 at the bottom of the opening 145. That is, there is a region in the bottom of the opening 145 where the semiconductor layer 208 is not formed, and in this region, the top surface of the substrate 102 is in contact with the insulating layer 106.

[0102] In the semiconductor layer 208, the region in contact with the conductive layer 212a is used as one of the source region and the drain region, and the region in contact with the conductive layer 212b is used as the other of the source region and the drain region. In the semiconductor layer 208, a channel formation region is provided between the source region and the drain region.

[0103] The insulating layer 106 is disposed so as to cover the opening 145. The insulating layer 106 is disposed on the semiconductor layer 208, the conductive layer 212a, the conductive layer 212b, and the insulating layer 110. The insulating layer 106 has regions in contact with the top surface and side surfaces of the semiconductor layer 208, the top surface and side surfaces of the conductive layer 212a, the top surface and side surfaces of the conductive layer 212b, the side surface of the insulating layer 110, and the top surface of the substrate 102. The insulating layer 106 has a shape along the top surface and side surfaces of the semiconductor layer 208, the top surface and side surfaces of the conductive layer 212a, the top surface and side surfaces of the conductive layer 212b, the side surface of the insulating layer 110, and the top surface of the substrate 102.

[0104] The conductive layer 204 is disposed on the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106. The conductive layer 204 includes a region overlapping the semiconductor layer 208 with the insulating layer 106 therebetween. The conductive layer 204 has a shape along the top surface and side surfaces of the insulating layer 106.

[0105] The structure of the transistor 100 will be described below.

[0106] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. In the transistor 100, the conductive layer 104 is used as a gate electrode (also referred to as a first gate electrode), and a part of the insulating layer 106 is used as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 112a is used as one of a source electrode and a drain electrode, and the conductive layer 112b is used as the other of the source electrode and the drain electrode. Each layer constituting the transistor 100 may have a single-layer structure or a stacked structure.

[0107] The conductive layer 112a is disposed on the substrate 102, and the insulating layer 110 is disposed on the conductive layer 112a. The insulating layer 110 may be disposed so as to cover the top surface and side surfaces of the conductive layer 112a. The insulating layer 110 includes an opening 141 reaching the conductive layer 112a. It can also be said that the conductive layer 112a is exposed in the opening 141.

[0108] The conductive layer 112b is disposed on the insulating layer 110. The conductive layer 112b includes a region overlapping the conductive layer 112a with the insulating layer 110 therebetween. The conductive layer 112b includes an opening 143 in the region overlapping the conductive layer 112a. The opening 143 is disposed in the region overlapping the opening 141. The conductive layer 112b may use the same material as the conductive layer 212a and the conductive layer 212b. In addition, the conductive layer 112b may be formed by the same process as the conductive layer 212a and the conductive layer 212b. For example, by forming a film that will become the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b and processing the film, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b can be formed.

[0109] The semiconductor layer 108 is disposed so as to cover the opening 141 and the opening 143. The same material as that of the semiconductor layer 208 can be used as the semiconductor layer 108. The semiconductor layer 108 can be formed by the same process as that of the semiconductor layer 208. For example, by forming a film that will become the semiconductor layer 108 and the semiconductor layer 208 and processing the film, the semiconductor layer 108 and the semiconductor layer 208 can be formed.

[0110] The semiconductor layer 108 includes regions that contact the top surface and the side surfaces of the conductive layer 112b, the side surfaces of the insulating layer 110, and the top surface of the conductive layer 112a. The semiconductor layer 108 is electrically connected to the conductive layer 112a through the opening 141 and the opening 143. The semiconductor layer 108 has a shape along the top surface and the side surfaces of the conductive layer 112b, the side surfaces of the insulating layer 110, and the top surface of the conductive layer 112a. The semiconductor layer 108 has a region that overlaps the conductive layer 112a with the insulating layer 110 interposed therebetween. It can also be said that the insulating layer 110 has a region sandwiched between the conductive layer 112a and the semiconductor layer 108.

[0111] In the semiconductor layer 108, the region in contact with the conductive layer 112a is used as one of the source region and the drain region, and the region in contact with the conductive layer 112b is used as the other of the source region and the drain region. In the semiconductor layer 108, a channel formation region is provided between the source region and the drain region.

[0112] The insulating layer 106 is disposed so as to cover the opening 141 and the opening 143. The insulating layer 106 is disposed on the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110. The insulating layer 106 includes regions that contact the top surface and the side surfaces of the semiconductor layer 108, the top surface and the side surfaces of the conductive layer 112b, and the top surface of the insulating layer 110. The insulating layer 106 has a shape along the top surface and the side surfaces of the semiconductor layer 108, the top surface and the side surfaces of the conductive layer 112b, and the top surface of the insulating layer 110.

[0113] The conductive layer 104 is disposed on the insulating layer 106 and has a region that contacts the top surface of the insulating layer 106. The conductive layer 104 includes a region that overlaps the semiconductor layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 104 has a shape along the top surface and the side surfaces of the insulating layer 106. The same material as that of the conductive layer 204 can be used as the conductive layer 104. In addition, the conductive layer 104 can be formed by the same process as that of the conductive layer 204. For example, by forming a film that will become the conductive layer 104 and the conductive layer 204 and processing the film, the conductive layer 104 and the conductive layer 204 can be formed.

[0114] The transistor 100 is a so-called top-gate transistor having a gate electrode above the semiconductor layer 108. Furthermore, since the bottom surface of the semiconductor layer 108 is in contact with the conductive layers 112a and 112b serving as the source electrode and the drain electrode, it can be said to be a TGBC (Top Gate Bottom Contact) type transistor. In addition, in the transistor 100, the heights of the source electrode and the drain electrode with respect to the surface of the substrate 102 of the formed surface are different from each other, and the drain current flows in a direction perpendicular or substantially perpendicular to the surface of the substrate 102. It can also be said that in the transistor 100, the drain current flows in the longitudinal direction or substantially longitudinal direction. Therefore, the transistor according to one embodiment of the present invention can be said to be a longitudinal-channel transistor or a VFET (Vertical Field Effect Transistor). In addition, since the transistor 200 has a structure in which current flows in both the longitudinal direction and the lateral direction, it can be said to be a VLFET (Vertical Lateral Field Effect Transistor).

[0115] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 (specifically, the insulating layer 110b) provided between the conductive layer 112a and the conductive layer 112b. Therefore, a transistor having a channel length shorter than the limit resolution of the exposure apparatus used to manufacture the transistor can be manufactured with high precision. In addition, the characteristic non-uniformity between the plurality of transistors 100 can be reduced. Therefore, the operation of the semiconductor device including the transistor 100 is stable, and the reliability can be improved. In addition, when the characteristic non-uniformity is reduced, the degree of freedom in circuit design is increased, and the operating voltage of the semiconductor device can also be reduced. As a result, the power consumption of the semiconductor device can be reduced.

[0116] In the transistor 100, the source electrode, the layer having the channel formation region, and the drain electrode can be stacked in the vertical direction, so that the occupied area can be significantly reduced compared to a so-called planar transistor in which the layer having the channel formation region is arranged in a planar shape.

[0117] The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can all be used as wirings, and the transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 100 and the wirings, the occupied area of the transistor 100 and the wirings can be reduced. Therefore, the occupied area of the circuit can be reduced to realize a small semiconductor device.

[0118] A transistor 100 with a short channel length and a transistor 200 with a long channel length can be formed on the same substrate in a manner where a part of the processes is common. For example, by using the transistor 100 for a transistor that requires a large on-state current and the transistor 200 for a transistor that requires high saturation, a high-performance semiconductor device can be achieved.

[0119] Conductive layers 112a and 112b serving as the source electrode and drain electrode of the transistor 100 are provided on different surfaces. Specifically, the conductive layer 112a is provided on the substrate 102, and the conductive layer 112b is provided on the insulating layer 110, and the insulating layer 110 is sandwiched between the conductive layer 112a and the conductive layer 112b. On the other hand, conductive layers 212a and 212b serving as the source electrode and drain electrode of the transistor 200 are provided on the same surface. Specifically, the conductive layers 212a and 212b are provided on the insulating layer 110. It can also be said that one of the source electrode and drain electrode of the transistor 100 is provided on a surface different from the source electrode and drain electrode of the transistor 200, and the other of the source electrode and drain electrode of the transistor 100 is provided on the same surface as the source electrode and drain electrode of the transistor 200.

[0120] For example, when the semiconductor device according to one embodiment of the present invention is used in a pixel circuit of a display device, the occupied area of the pixel circuit can be reduced, and a high-definition display device can be achieved. In addition, for example, when the semiconductor device according to one embodiment of the present invention is used in a driving circuit of a display device (for example, one or both of a gate line driving circuit and a source line driving circuit), the occupied area of the driving circuit can be reduced, and thus a narrow-bezel display device can be achieved.

[0121] An insulating layer 195 is provided so as to cover the transistor 100 and the transistor 200. The insulating layer 195 is used as a protective layer for the transistor 100 and the transistor 200.

[0122] Next, the detailed structures of the transistor 100 and the transistor 200 will be described.

[0123] There is no particular limitation on the semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208. For example, a semiconductor composed of a single element or a compound semiconductor can be used. Examples of the semiconductor composed of a single element include silicon and germanium. Examples of the compound semiconductor include gallium arsenide and silicon germanium. In addition, examples of the compound semiconductor include an organic semiconductor, a nitride semiconductor, and an oxide semiconductor (OS: Oxide Semiconductor). Note that these semiconductor materials may also contain impurities as dopants.

[0124] There is no particular limitation on the crystallinity of the semiconductor materials for the semiconductor layer 108 and the semiconductor layer 208, and amorphous semiconductors, single-crystalline semiconductors, or semiconductors having crystallinity other than single crystal (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors having a crystalline region in a part thereof) can be used. When a single-crystalline semiconductor or a semiconductor having crystallinity is used, deterioration of the characteristics of the transistor can be suppressed, which is preferable.

[0125] Silicon can be used for both the semiconductor layer 108 and the semiconductor layer 208. Examples of silicon include single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. As polycrystalline silicon, for example, low-temperature polycrystalline silicon (LTPS: Low Temperature PolySilicon) can be cited. A transistor using amorphous silicon as a channel formation region can be formed on a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon in the channel formation region has a high field-effect mobility and can operate at high speed. In addition, compared with a transistor using amorphous silicon, a transistor using microcrystalline silicon in the channel formation region has a high field-effect mobility and can operate at high speed.

[0126] It is preferable that both the semiconductor layer 108 and the semiconductor layer 208 contain a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics.

[0127] The band gap of the metal oxide for the semiconductor layer 108 and the semiconductor layer 208 is preferably 2.0 eV or more, and more preferably 2.5 eV or more.

[0128] Compared with a transistor using amorphous silicon, a transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has a very high field-effect mobility. In addition, the off-state current of the OS transistor is extremely small, and the charge stored in a capacitor connected in series with the transistor can be maintained for a long period. In addition, by using an OS transistor, the power consumption of the semiconductor device can be reduced.

[0129] The insulating layer 110 preferably has one or more inorganic insulating films. Examples of materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitrogen oxides. As oxides, for example, silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate can be cited. As nitrides, for example, silicon nitride and aluminum nitride can be cited. As oxynitrides, for example, silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride can be cited. As nitrogen oxides, for example, silicon oxynitride and aluminum oxynitride can be cited.

[0130] Note that in this specification and the like, an oxynitride refers to a material in which the oxygen content is more than the nitrogen content in its composition. A nitride oxide refers to a material in which the nitrogen content is more than the oxygen content in its composition. For example, when it is described as "silicon oxynitride", it refers to a material in which the oxygen content is more than the nitrogen content in its composition, and when it is described as "silicon nitride oxide", it refers to a material in which the nitrogen content is more than the oxygen content in its composition.

[0131] In the transistor 200, the region of the semiconductor layer 208 that contacts the insulating layer 110 is used as a channel formation region. In the transistor 100, the region of the semiconductor layer 108 that contacts the insulating layer 110 is used as a channel formation region. When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110 and the interface characteristics between the semiconductor layer 208 and the insulating layer 110, at least a part of the region of the insulating layer 110 that contacts the semiconductor layer 108 and at least a part of the region of the insulating layer 110 that contacts the semiconductor layer 208 preferably contain oxygen. Specifically, the regions of the insulating layer 110 that contact the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208 preferably contain oxygen. The regions of the insulating layer 110 that contact the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208 are suitable for using one or more of an oxide and an oxynitride.

[0132] The insulating layer 110 preferably has a stacked structure. In Figure 12B etc., an example is shown in which the insulating layer 110 has an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b.

[0133] Figure 13A and Figure 13B show Figure 12A and Figure 12B an enlarged view of the transistor 200 shown. Figure 14A and Figure 14B show an enlarged view of the transistor 100.

[0134] The insulating layer 110b preferably contains oxygen and is preferably made of any one or more of the above-mentioned oxides and oxynitrides. Specifically, the insulating layer 110b is suitable for using one or both of silicon oxide and silicon oxynitride. Thus, at least the regions of the semiconductor layer 208 and the semiconductor layer 108 that contact the insulating layer 110b can be used as channel formation regions.

[0135] The insulating layer 110b more preferably uses a film that releases oxygen by heating. Since the insulating layer 110b releases oxygen due to the heat applied in the manufacturing process of the transistor 100, oxygen can be supplied to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, especially to the channel formation region of the semiconductor layer 108, oxygen vacancies (V O ) are filled, whereby oxygen vacancies (V O ) can be reduced. Furthermore, by supplying oxygen, the defect of hydrogen entering the oxygen vacancy (V O ), hereinafter also denoted as V O H, can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be achieved.

[0136] For example, by performing a heat treatment in an oxygen-containing atmosphere or a plasma treatment in an oxygen-containing atmosphere, oxygen can be supplied to the insulating layer 110b. In addition, an oxide film can also be formed on the top surface of the insulating layer 110b by sputtering in an oxygen-containing atmosphere to supply oxygen. Then, this oxide film can also be removed. In Embodiment 3 described later, an example of forming a metal oxide layer 137 to supply oxygen to the insulating layer 110b will be shown.

[0137] The insulating layer 110b is preferably formed by a deposition method such as sputtering or plasma enhanced chemical vapor deposition (PECVD: Plasma Enhanced Chemical Vapor Deposition). In particular, by forming using a deposition method that does not use a hydrogen-containing gas as a deposition gas by sputtering, a film with an extremely low hydrogen content can be formed. Thereby, the supply of hydrogen to the channel formation region can be suppressed and the electrical characteristics of the transistor 100 can be stabilized.

[0138] In the insulating layer 110b, it is preferable that substances (for example, atoms, molecules, and ions) are easily diffused. In other words, the diffusion coefficient of substances in the insulating layer 110b is preferably large. In particular, it is preferable that oxygen is easily diffused in the insulating layer 110b. That is, the oxygen diffusion coefficient in the insulating layer 110b is preferably large. The oxygen contained in the insulating layer 110b diffuses in the insulating layer 110b and is supplied to the semiconductor layer 108 through the interface between the insulating layer 110b and the semiconductor layer 108, and is also supplied to the semiconductor layer 208 through the interface between the insulating layer 110b and the semiconductor layer 208.

[0139] Here, by using a material with high conductivity for the semiconductor layer 108 and the semiconductor layer 208, a transistor with a large on-state current can be achieved. However, when using a material with high conductivity, oxygen vacancies (V O ) are easily formed, and due to the increase in oxygen vacancies (V O ) in the channel formation region, V OAs H increases, the threshold voltage of the transistor drifts. Sometimes, the drain current flowing when the gate voltage is 0V (hereinafter, also referred to as the cut-off current) becomes large. For example, in an n-channel transistor, the threshold voltage sometimes drifts to the negative side and the cut-off current increases. By providing the insulating layer 110b, oxygen is supplied at least to the region of the semiconductor layer 108 in contact with the insulating layer 110b and the region of the semiconductor layer 208 in contact with the insulating layer 110b, that is, the channel formation regions of the transistor 100 and the transistor 200. Thus, oxygen vacancies (V O ) and V O H in the channel formation region can be reduced. Thereby, the drift of the threshold voltage is suppressed, and a transistor that can achieve both a small cut-off current and a large on-state current can be obtained. Therefore, a semiconductor device with low power consumption and high performance can be realized.

[0140] In the semiconductor layer 108, the region in contact with the conductive layer 112a is used as one of the source region and the drain region of the transistor 100, and the region in contact with the conductive layer 112b is used as the other of the source region and the drain region. The source region and the drain region are regions where the resistance is lower than that of the channel formation region. The source region and the drain region can also be said to be regions with a higher carrier concentration and a higher oxygen vacancy density than the channel formation region.

[0141] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b. The insulating layer 110a and the insulating layer 110c preferably have a small amount of impurities (e.g., hydrogen and water) released from themselves and are not easily permeable to impurities. Thereby, the diffusion of impurities contained in the insulating layer 110a and the insulating layer 110c into the channel formation region can be suppressed. Therefore, a transistor with good electrical characteristics and high reliability can be realized.

[0142] The insulating layer 110a and the insulating layer 110c preferably use a film that is not easily permeable to oxygen. Thereby, the oxygen contained in the insulating layer 110b can be suppressed from diffusing through the insulating layer 110a to the conductive layer 112a. Similarly, the oxygen contained in the insulating layer 110b can be suppressed from diffusing through the insulating layer 110c to the conductive layer 112b. Thereby, the oxidation of the conductive layer 112a and the conductive layer 112b and the increase in resistance can be suppressed. At the same time, the diffusion of the oxygen contained in the insulating layer 110b to the insulating layer 110a side and the insulating layer 110c side is suppressed, so that the amount of oxygen supplied from the insulating layer 110b to the channel formation region increases, and oxygen vacancies (V O ) and V O H in the channel formation region can be reduced.

[0143] By using a film that is not easily diffusible to oxygen for both the insulating layer 110a and the insulating layer 110c, oxygen can be effectively supplied from the insulating layer 110b to the channel formation region. In addition, one or both of the insulating layer 110a and the insulating layer 110c may not be provided.

[0144] The insulating layer 110a and the insulating layer 110c preferably both contain nitrogen, and preferably any one or more of the above-mentioned nitrides and oxynitrides are used. For example, both the insulating layer 110a and the insulating layer 110c are suitable for using silicon nitride or silicon oxynitride. Alternatively, any one or more of oxides and oxynitrides may be used for one or both of the insulating layer 110a and the insulating layer 110c. For example, both the insulating layer 110a and the insulating layer 110c are suitable for using aluminum oxide. Note that the insulating layer 110a may use the same material or a different material from the insulating layer 110c.

[0145] Note that in this specification, etc., different materials refer to materials in which part or all of the constituent elements are different or materials in which the constituent elements are the same but the composition is different.

[0146] The thickness T110a of the insulating layer 110a can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 20 nm or more, 50 nm or more, or 70 nm or more and less than 1 μm, 500 nm or less, 400 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, or 120 nm or less. As Figure 14B shown, the thickness T110a can be the shortest distance between the formed surface of the insulating layer 110a (here, the top surface of the conductive layer 112a) and the top surface of the insulating layer 110a in a cross-sectional view.

[0147] When the thickness T110a of the insulating layer 110a is relatively thick, sometimes the amount of impurities released from the insulating layer 110a increases, and the amount of impurities diffusing into the channel formation region increases. On the other hand, when the thickness T110a is relatively thin, sometimes the oxygen contained in the insulating layer 110b diffuses to the side of the conductive layer 112a through the insulating layer 110a, and the amount of oxygen supplied to the channel formation region decreases. By setting the thickness T110a within the above range, oxygen vacancies (V O ) and V O H in the channel formation region can be reduced. In addition, it is possible to suppress the increase in the resistance of the conductive layer 112a due to the oxidation of the conductive layer 112a caused by the oxygen contained in the insulating layer 110b.

[0148] The thickness T110c of the insulating layer 110c can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 15 nm or more, or 20 nm or more and 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, 120 nm or less, or 100 nm or less. As Figure 14BAs shown, the thickness T110c can be the shortest distance between the formed surface of the insulating layer 110c (here, the top surface of the insulating layer 110b) and the top surface of the insulating layer 110c when viewed in cross section.

[0149] When the thickness T110c of the insulating layer 110c is relatively thick, sometimes the amount of impurities released from the insulating layer 110c increases, and the amount of impurities diffusing into the channel formation region increases. On the other hand, when the thickness T110c is relatively thin, sometimes the oxygen contained in the insulating layer 110b diffuses through the insulating layer 110c to the conductive layer 112b side, and the amount of oxygen supplied to the channel formation region decreases. By setting the thickness T110c within the above range, oxygen vacancies (V O ) and V O H in the channel formation region can be reduced. In addition, oxidation of the conductive layer 112b due to oxygen contained in the insulating layer 110b can be suppressed, and the resistance of the conductive layer 112b can be prevented from increasing.

[0150] At least one of the regions of the semiconductor layer 108 that are in contact with the insulating layer 110a and the insulating layer 110c can also be a region with a lower resistance than the channel formation region (hereinafter, also referred to as a low-resistance region). This region can also be said to be a region with a higher carrier concentration and a higher oxygen vacancy density than the channel formation region. By using a material that releases impurities (e.g., water and hydrogen) for the insulating layer 110a, the region of the semiconductor layer 108 that is in contact with the insulating layer 110a can be used as a low-resistance region. The semiconductor layer 108 can have a structure that includes a low-resistance region between the region in contact with the conductive layer 112a (one of the source region and the drain region) and the channel formation region. Similarly, by using a material that releases impurities as the insulating layer 110c, the region of the semiconductor layer 108 that is in contact with the insulating layer 110c can be made into a low-resistance region. The semiconductor layer 108 can have a structure that includes a low-resistance region between the region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel formation region. The low-resistance region can be used as a buffer region for alleviating the drain electric field. These low-resistance regions can also be used as the source region or the drain region.

[0151] By providing a low-resistance region between the drain region and the channel formation region, a high electric field is not easily generated near the drain region, generation of hot carriers can be suppressed, and thus degradation of the transistor can be suppressed. For example, in the case where the conductive layer 112a is used as the drain electrode and the conductive layer 112b is used as the source electrode, by setting the region of the semiconductor layer 108 in contact with the insulating layer 110a as the low-resistance region, a high electric field is not easily generated near the drain region, generation of hot carriers can be suppressed, and thus degradation of the transistor can be suppressed. In the case where the conductive layer 112a is used as the source electrode and the conductive layer 112b is used as the drain electrode, by setting the region of the semiconductor layer 108 in contact with the insulating layer 110c as the low-resistance region, a high electric field is not easily generated near the drain region, generation of hot carriers can be suppressed, and thus degradation of the transistor can be suppressed.

[0152] As described above, when the amount of impurities released from the insulating layer 110a and the insulating layer 110c is excessive, there is a concern that the impurities diffuse into the channel formation region. Even when a material that releases impurities is used as the insulating layer 110a and the insulating layer 110c, the amount of impurities released is preferably small.

[0153] The insulating layer 110 preferably includes at least the insulating layer 110b. For example, it may not include one or both of the insulating layer 110a and the insulating layer 110c. In addition, the insulating layer 110 may have a stacked structure of two or four or more layers or a single-layer structure.

[0154] There is no limitation on the top surface shape of the opening 145, the opening 141, and the opening 143. For example, it may be circular, elliptical, triangular, quadrangular (including rectangular, rhombic, square), pentagonal, or other polygonal shapes or rounded shapes of these polygonal shapes. The polygonal shape may also be a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As Figure 12A shown, etc., the top surface shapes of the opening 141 and the opening 143 are preferably both circular. By making the top surface shape of the opening circular, the processing accuracy when forming the opening can be improved, and a fine opening can be formed. Note that in this specification, etc., the circular shape is not limited to a perfect circle.

[0155] In this specification, etc., the top surface shape of the opening 145 refers to the shape of the top surface end portion on the opening 145 side of the insulating layer 110. The top surface shape of the opening 141 refers to the shape of the top surface end portion on the opening 141 side of the insulating layer 110. In addition, the top surface shape of the opening 143 refers to the shape of the bottom surface end portion on the opening 143 side of the conductive layer 112b.

[0156] As Figure 12A shown, etc., the top surface shape of the opening 141 and the top surface shape of the opening 143 can be made the same or substantially the same. At this time, as Figure 12BAs shown in etc., the bottom end portion on one side of the opening 143 of the conductive layer 112b preferably coincides with or is substantially coincident with the top end portion on one side of the opening 141 of the insulating layer 110. The bottom surface of the conductive layer 112b refers to the surface on the side of the insulating layer 110. The top surface of the insulating layer 110 refers to the surface on the side of the conductive layer 112b.

[0157] In addition, the top surface shape of the opening 141 and the top surface shape of the opening 143 may also be different. In addition, when the top surface shapes of the openings 141 and 143 are circular, the openings 141 and 143 may be concentric or may not be concentric.

[0158] Refer to Figure 13A and Figure 13B to illustrate the channel length and channel width of the transistor 200.

[0159] In Figure 13A , the channel length L200 of the transistor 200 is indicated by a double arrow of a solid line. The channel length L200 corresponds to the distance between the conductive layer 212a and the conductive layer 212b along the side wall of the opening 145. In Figure 13B , the channel width W200 of the transistor 200 is indicated by a double arrow of a dashed line. The channel width W200 is the width of the semiconductor layer 208 along the depth direction of the opening 145.

[0160] Refer to Figure 14A and Figure 14B to illustrate the channel length and channel width of the transistor 100.

[0161] Figure 14B In, the channel length L100 of the transistor 100 is indicated by a double arrow of a dashed line. The channel length L100 of the transistor 100 corresponds to the length of the side surface on the side of the opening 141 of the insulating layer 110b during cross-section. That is, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ110 formed by the side surface on the side of the opening 141 of the insulating layer 110b and the formed surface of the insulating layer 110b (here, the top surface of the insulating layer 110a). Therefore, for example, the channel length L100 can be set to a value smaller than the limit resolution of the exposure apparatus, and a fine transistor can be realized. Specifically, a transistor with an extremely short channel length that cannot be realized in an exposure apparatus (for example, with a minimum line width of about 2 μm or 1.5 μm) used in the mass production of conventional flat panel displays can be realized. In addition, a transistor with a channel length less than 10 nm can be realized without using a very expensive exposure apparatus used in the most advanced LSI technology.

[0162] The channel length L100 can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 can be set to 100 nm or more and 1 μm or less.

[0163] By reducing the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of operating at high speed can be fabricated. Furthermore, the occupied area of the circuit can be reduced. Therefore, a small semiconductor device can be realized. For example, in the case where the semiconductor device according to one embodiment of the present invention is used for a large display device or a high-definition display device, even when the number of wirings increases, the signal delay of each wiring can be reduced, thereby suppressing display unevenness. In addition, since the occupied area of the circuit can be reduced, the bezel of the display device can be reduced.

[0164] By adjusting the thickness T110b and the angle θ110 of the insulating layer 110b, the channel length L100 can be controlled. In Figure 14B the thickness T110b of the insulating layer 110b is indicated by a double-headed dotted line.

[0165] The thickness T110b of the insulating layer 110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.

[0166] The side surface on the opening 141 side of the insulating layer 110 preferably has a vertical shape or a tapered shape. The angle θ110 is preferably 90 degrees or less. By reducing the angle θ110, the coverage of the layer formed on the insulating layer 110 (for example, the semiconductor layer 108) can be improved. In addition, the smaller the angle θ110, the longer the channel length L100 can be, and the larger the angle θ110, the shorter the channel length L100 can be.

[0167] The angle θ110 can be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more and 90 degrees or less, 85 degrees or less, or 80 degrees or less. The angle θ110 can also be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less.

[0168] Note that in Figure 14BThe structure in which the shape of the side surface on the opening 141 side of the insulating layer 110 is a straight line when viewed in cross-section is shown in etc., but one embodiment of the present invention is not limited thereto. When viewed in cross-section, the shape of the side surface on the opening 141 side of the insulating layer 110 may also be a curve, or may have both a region where the shape of the side surface is a straight line and a region where the shape is a curve.

[0169] Here, the conductive layer 112b is preferably not provided inside the opening 141. Specifically, the conductive layer 112b preferably does not have a region in contact with the side surface on the opening 141 side of the insulating layer 110. When the conductive layer 112b is also provided inside the opening 141, the channel length L100 of the transistor 100 is shorter than the length of the side surface of the insulating layer 110b, so that the control of the channel length L100 may sometimes become difficult. Therefore, preferably, the top surface shape of the opening 143 is the same as the top surface shape of the opening 141, or the opening 143 includes the opening 141 when viewed from above (also referred to as viewing from a plane).

[0170] In Figure 14A and Figure 14B the double-headed arrow with a dashed line represents the width D141 of the opening 141. Figure 14A An example in which the top surface shape of the opening 141 is a circle is shown. At this time, the width D141 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100 corresponds to the length of the circumference of the circle. That is, the channel width W100 is π×D141. Thus, when the top surface shape of the opening 141 is a circle, a transistor with a smaller channel width W100 can be realized compared with other shapes.

[0171] The width D141 of the opening 141 may vary in the depth direction. As the width D141 of the opening 141, for example, the average value of the diameter at the highest position, the diameter at the lowest position, and the diameter at the midpoint position of the insulating layer 110b (or the insulating layer 110) when viewed in cross-section can be used. Alternatively, as the diameter of the opening 141, for example, any one of the diameter at the highest position, the diameter at the lowest position, and the diameter at the midpoint position of the insulating layer 110b (or the insulating layer 110) when viewed in cross-section can also be used.

[0172] When the opening 141 is formed by photolithography, the width D141 of the opening 141 is above the limit resolution of the exposure apparatus. The width D141 can be, for example, 200 nm or more, 300 nm or more, 400 nm or more, or 500 nm or more and less than 5 μm, 4.5 μm or less, 4 μm or less, 3.5 μm or less, 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, or 1 μm or less.

[0173] Note that when reducing the channel length L100 of the transistor 100, it is preferable to use materials that release less hydrogen from themselves for the insulating layer 110a and the insulating layer 110c. When the insulating layer 110a and the insulating layer 110c use materials that also release a small amount of hydrogen, their thicknesses are preferably small. For example, when the channel length L100 is 100 nm or less, the thickness T110a of the insulating layer 110a and the thickness T110c of the insulating layer 110c are preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. Thereby, the amount of impurities diffused into the channel formation region can be reduced, and thus a transistor with good electrical characteristics and high reliability can be achieved even when the channel length L100 is short.

[0174] Note that here, a structure in which the region of the semiconductor layer 108 in contact with the insulating layer 110b is used as the channel formation region is described as an example, but one aspect of the present invention is not limited thereto. The region of the semiconductor layer 108 in contact with the insulating layer 110a may also be used as the channel formation region. Similarly, the region in contact with the insulating layer 110c may also be used as the channel formation region.

[0175] Figure 12B Examples such as show that in the transistor 100, the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 cover the openings 141 and 143, but one aspect of the present invention is not limited thereto, and a structure in which the insulating layer 110 and the conductive layer 112a form a step and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are provided along the step may also be adopted.

[0176] Next, refer to Figure 13A and Figure 13B to describe the detailed structure of the transistor 200. Figure 13A and Figure 13B are Figure 12A and Figure 12B an enlarged view of the transistor 200 shown.

[0177] As described above, the channel length L100 of the transistor 100 can be set to a value smaller than the limit resolution of the exposure apparatus, and the channel length L200 of the transistor 200 can be set to a value equal to or greater than the limit resolution of the exposure apparatus. For example, by using the transistor 100 for a transistor that requires a large on-state current and using the transistor 200 for a transistor that requires high saturation, a high-performance semiconductor device 10 that exhibits the advantages of each transistor can be achieved. Furthermore, a part of the processes can be used in common to form the transistor 100 and the transistor 200. Specifically, the semiconductor layer 108 and the semiconductor layer 208 can be formed by the same process. A part of the insulating layer 106 is used as the gate insulating layer of the transistor 100, and the other part of the insulating layer 106 is used as the gate insulating layer of the transistor 200. The conductive layer 104 and the conductive layer 204 can be formed by the same process. The conductive layer 112b, the conductive layer 212a, and the conductive layer 212b can be formed by the same process. Therefore, the productivity of the semiconductor device 10 can be improved and the manufacturing cost can be reduced.

[0178] [Semiconductor layer 108, semiconductor layer 208] The metal oxides that can be used for the semiconductor layer 108 and the semiconductor layer 208 will be specifically described. As the metal oxides, for example, indium oxide, gallium oxide, and zinc oxide can be cited. The metal oxide preferably contains at least indium or zinc. In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Note that element M is a metal element or a metalloid element having a high bonding energy with oxygen, for example, a metal element or a metalloid element having a higher bonding energy with oxygen than indium. Specifically, as element M, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony, etc. can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably one or more of gallium and tin. Note that in this specification, etc., metal elements and metalloid elements are sometimes collectively referred to as "metal elements", and the "metal elements" described in this specification, etc. sometimes include metalloid elements.

[0179] The semiconductor layer 108 and the semiconductor layer 208 can be made of, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide, also denoted as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also denoted as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also denoted as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO, IGZAO or IAGZO), etc. Alternatively, indium tin oxide containing silicon (also denoted as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0180] When the proportion of the number of indium atoms to the sum of the number of atoms of all metal elements in the metal oxide is increased, the field-effect mobility of the transistor can be increased. In addition, a transistor with a large on-state current can be realized.

[0181] Note that the metal oxide can also replace indium or contain one or more metal elements with a large period number in the periodic table in addition to indium. There is a tendency that the greater the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including metal elements with a large period number, the field-effect mobility of the transistor can sometimes be increased. Examples of metal elements with a large period number include metal elements belonging to the 5th period and metal elements belonging to the 6th period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0182] The metal oxide can also contain one or more non-metal elements. When the metal oxide contains non-metal elements, the field-effect mobility of the transistor can sometimes be increased due to an increase in the carrier concentration or a narrowing of the bandgap, etc. Examples of non-metal elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0183] When the ratio of the number of zinc atoms to the sum of the number of atoms of all metal elements in the metal oxide is increased, the metal oxide has high crystallinity, and impurity diffusion in the metal oxide can be suppressed. Therefore, variations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0184] In addition, when the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements in the metal oxide is increased, formation of oxygen vacancies (V O ) in the metal oxide can be suppressed. O ) Therefore, generation of carriers due to the oxygen vacancies (V

[0185] The electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for the semiconductor layer 108 and the semiconductor layer 208. Therefore, by varying the composition of the metal oxide according to the required electrical characteristics and reliability of the transistor, a semiconductor device having both excellent electrical characteristics and high reliability can be realized.

[0186] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of element M. Examples of the atomic ratios of the metal elements in such an In-M-Zn oxide include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. In addition, the vicinity of the composition includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0187] The atomic ratio of In in the In-M-Zn oxide can also be less than the atomic ratio of element M. As the atomic ratio of the metal elements in such an In-M-Zn oxide, for example, In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, and compositions in the vicinity thereof can be cited. By increasing the proportion of the number of atoms of M in the metal oxide, the generation of oxygen vacancies (V O ) can be suppressed.

[0188] Note that when multiple metal elements are included as element M, the total of the atomic ratios of these metal elements can be the atomic ratio of element M.

[0189] In the present specification and the like, the atomic ratio of indium to the sum of the numbers of atoms of all the contained metal elements is sometimes referred to as the indium content rate. The same applies to other metal elements.

[0190] By using a material with a high indium content rate for the semiconductor layer 108 and the semiconductor layer 208, the on-state current or the field-effect mobility of the transistor can be increased. Also, by including element M, the generation of oxygen vacancies (V O ) can be suppressed. The content rate of element M (the ratio of the number of atoms of element M to the sum of the numbers of atoms of all the contained metal elements) is preferably 0.1% or more and 3% or less, more preferably 0.1% or more and 2% or less. Thereby, a transistor with good electrical characteristics can be realized. For example, it is preferable to use a metal oxide such as In:M:Zn = 40:1:10 and its vicinity. Element M is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, it is suitable to use a metal oxide such as In:Sn:Zn = 40:1:10 and its vicinity. Alternatively, it is suitable to use a metal oxide such as In:Al:Zn = 40:1:10 and its vicinity.

[0191] Here, when a polycrystalline metal oxide is used as the semiconductor layer 108 and the semiconductor layer 208, grain boundaries become recombination centers and carriers are trapped, whereby the on-state current of the transistor sometimes becomes small. When using a metal oxide having a composition that easily becomes a polycrystalline structure, it is preferable to contain an element that inhibits crystallization. For example, indium tin oxide containing silicon (ITSO) is less likely to have a polycrystalline structure compared to indium tin oxide (ITO), and thus can be applied to the semiconductor layer 108 and the semiconductor layer 208. When using ITSO, the content rate of silicon (the ratio of the number of silicon atoms to the sum of the number of atoms of all the contained metal elements) is preferably 1% or more and 20% or less, more preferably 3% or more and 20% or less, further preferably 3% or more and 15% or less, and still more preferably 5% or more and 15% or less. Specifically, metal oxides such as In:Sn:Si = 45:5:4, In:Sn:Si = 95:5:8 and those near them are suitably used.

[0192] Analysis of the composition of the semiconductor layer 108 and the semiconductor layer 208 can be performed, for example, using energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, multiple of the above methods can be combined for analysis. Note that elements with low content rates are sometimes affected by the analysis accuracy, and the actual content rate is different from the content rate obtained by analysis. For example, when the content rate of element M is low, the content rate of element M obtained by analysis is sometimes lower than the actual content rate.

[0193] The metal oxide is suitably formed by a sputtering method or an atomic layer deposition (ALD) method. Note that when the metal oxide is formed by the sputtering method, the composition of the formed metal oxide is sometimes different from the composition of the sputtering target. In particular, the content rate of zinc in the formed metal oxide sometimes decreases to about 50% of the content rate of zinc in the sputtering target.

[0194] The semiconductor layer 108 and the semiconductor layer 208 may also have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer 108 and the semiconductor layer 208 may be the same as or substantially the same as each other. By adopting a stacked structure of metal oxide layers having the same composition, for example, it can be formed using the same sputtering target, so the manufacturing cost can be reduced.

[0195] The compositions of the two or more metal oxide layers included in the semiconductor layer 108 and the semiconductor layer 208 may also be different from each other. For example, a stacked structure of a first metal oxide layer having a composition of In:M:Zn = 1:3:4 [atomic ratio] or near it and a second metal oxide layer having a composition of In:M:Zn = 1:1:1 [atomic ratio] or near it provided on the first metal oxide layer is suitably used. In addition, gallium, aluminum, or tin is particularly preferably used as the element M. The element M in the first metal oxide layer and the second metal oxide layer may be the same or different. For example, the first metal oxide layer and the second metal oxide layer may also be IGZO layers having different compositions.

[0196] For example, a stacked structure of a first metal oxide layer having a composition of In:Zn = 4:1 [atomic ratio] or near it and a second metal oxide layer having a composition of In:M:Zn = 1:1:1 [atomic ratio] or near it provided on the first metal oxide layer is suitably used.

[0197] For example, a stacked structure selected from any one of indium oxide, indium gallium oxide, and IGZO and any one of IAZO, IAGZO, and ITZO (registered trademark) can be used.

[0198] In addition, in the case of adopting a stacked structure of a first metal oxide layer containing a first metal oxide and a second metal oxide layer containing a second metal oxide and the composition of the first metal oxide is the same as or substantially the same as the composition of the second metal oxide, sometimes the boundary (interface) between the first metal oxide layer and the second metal oxide layer cannot be clearly confirmed.

[0199] The semiconductor layer 108 and the semiconductor layer 208 preferably use a crystalline metal oxide. As the structure of the crystalline metal oxide, for example, a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a microcrystalline (nc: nano-crystal) structure can be cited. By using a crystalline metal oxide for the semiconductor layer 108 and the semiconductor layer 208, the density of defect states in the semiconductor layer 108 and the semiconductor layer 208 can be reduced, and thus a highly reliable semiconductor device can be realized.

[0200] The semiconductor layer 108 and the semiconductor layer 208 preferably use CAAC-OS or nc-OS.

[0201] CAAC-OS has a plurality of layered crystals. The c-axis of the crystal is oriented in the normal direction of the formation surface. The semiconductor layer 108 and the semiconductor layer 208 preferably each have layered crystals parallel to or substantially parallel to the formation surface. For example, the semiconductor layer 108 preferably has layered crystals parallel to or substantially parallel to the top surface in the region in contact with the top surface of the conductive layer 112b, and has layered crystals parallel to or substantially parallel to the side surface in the region in contact with the side surface of the conductive layer 112b. In particular, the semiconductor layer 108 preferably has layered crystals parallel to or substantially parallel to the side surface of the insulating layer 110 as the formation surface in the opening 141. By adopting such a structure, the layered crystals of the semiconductor layer 108 are substantially parallel to the channel length direction of the transistor 100, so the on-state current of the transistor can be increased. Similarly, the semiconductor layer 208 preferably has layered crystals parallel to or substantially parallel to the formation surface (here, the side surfaces of the insulating layer 110, the conductive layer 212a, and the conductive layer 212b). In particular, the semiconductor layer 208 preferably has layered crystals parallel to or substantially parallel to the side surface of the insulating layer 110 as the formation surface in the region overlapping with the conductive layer 204.

[0202] By using a metal oxide with high crystallinity for the channel formation region, the density of defect states in the channel formation region can be reduced. On the other hand, by using a metal oxide with low crystallinity, a transistor capable of flowing a large current can be realized.

[0203] The higher the substrate temperature during the formation of the metal oxide, the higher the crystallinity of the metal oxide that can be formed. When forming the metal oxide by sputtering, the higher the substrate temperature during the formation, the higher the crystallinity of the metal oxide that can be formed. In addition, the higher the flow ratio of oxygen gas to the total deposition gas used during the formation (hereinafter, also referred to as the oxygen flow ratio) or the oxygen partial pressure in the processing chamber, the higher the crystallinity of the metal oxide that can be formed.

[0204] The crystallinity of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed, for example, by X-ray diffraction (XRD: X-Ray Diffraction), transmission electron microscope (TEM: Transmission Electron Microscope), or electron diffraction (ED: Electron Diffraction). Alternatively, multiple of the above methods can also be combined for analysis.

[0205] When using a metal oxide as the semiconductor layer 108 and the semiconductor layer 208, it is preferable to minimize the V of the channel formation region OH so as to make it high-purity intrinsic or substantially high-purity intrinsic. Thus, in order to obtain a metal oxide with sufficiently reduced V O H, it is important to remove impurities such as water and hydrogen in the metal oxide (sometimes referred to as dehydration and dehydrogenation treatment); and supply oxygen to the metal oxide to repair oxygen vacancies (V O ). By using a metal oxide with sufficiently reduced impurities such as V O H in the channel formation region of a transistor, stable electrical characteristics can be imparted. Note that the treatment of supplying oxygen to the metal oxide to repair oxygen vacancies (V O ) is sometimes referred to as oxidation treatment.

[0206] When a metal oxide is used as the semiconductor layer 108 and the semiconductor layer 208, the carrier concentration in the channel formation region is preferably 1×10 18 cm -3 or less, more preferably less than 1×10 17 cm -3 , further preferably less than 1×10 16 cm -3 , more preferably less than 1×10 13 cm -3 , further preferably less than 1×10 12 cm -3 . There is no limitation on the lower limit value of the carrier concentration in the channel formation region. For example, it can be set to 1×10 -9 cm -3 .

[0207] The electrical characteristics of the OS transistor change little due to radiation irradiation, that is, it has high tolerance to radiation. Therefore, it can be appropriately used in an environment where radiation may be incident. The OS transistor can also be said to have high reliability for radiation. For example, it is suitable to use the OS transistor in the pixel circuit of an X-ray flat panel detector. In addition, the OS transistor is suitable for semiconductor devices used in space. Examples of radiation include electromagnetic radiation (e.g., X-rays and γ-rays) and particle radiation (e.g., α-rays, β-rays, proton radiation, and neutron radiation).

[0208] The semiconductor layer 108 and the semiconductor layer 208 may also include a layered material used as a semiconductor. The layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds weaker than covalent bonds and ionic bonds such as van der Waals bonds. The layered material has high conductivity in the unit layer, that is, it has high two-dimensional conductivity. By using a material used as a semiconductor and having high two-dimensional conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0209] As the above-mentioned layered material, for example, graphene, silicene, chalcogenide, etc. can be cited. Chalcogenide is a compound containing chalcogen elements (elements belonging to Group 16). In addition, as chalcogenide, transition metal chalcogenide, Group 13 chalcogenide, etc. can be cited. As the transition metal chalcogenide that can be used as the channel formation region of a transistor, specifically, molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited.

[0210] [Conductive layer 112a, conductive layer 112b, conductive layer 104, conductive layer 204, conductive layer 212a, conductive layer 212b] The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b may have a single-layer structure or a stacked structure of two or more layers. As the materials that can be used for the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium and alloys containing one or more of the above metals as components can be cited. A low-resistance conductive material containing one or more of copper, silver, gold, and aluminum can be appropriately used for the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b. Among them, copper or aluminum is particularly advantageous in terms of mass productivity and is therefore preferred.

[0211] The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can use a conductive metal oxide (oxide conductor). As the oxide conductor (OC: Oxide Conductor), for example, indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (ITO containing silicon, also called ITSO), zinc oxide added with gallium, and In-Ga-Zn oxide can be cited. In particular, an oxide conductor containing indium is preferably used because of its high conductivity.

[0212] Oxygen vacancies are formed in a metal oxide having semiconductor characteristics, and hydrogen is added to the oxygen vacancies to form donor energy levels near the conduction band. As a result, the conductivity of the metal oxide increases and it becomes a conductor. The metal oxide that has become a conductor may be referred to as an oxide conductor.

[0213] As the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b, a laminated structure of a conductive film containing the above oxide conductor (metal oxide) and a conductive film containing a metal or an alloy may also be used. By using a conductive film containing a metal or an alloy, the wiring resistance can be reduced.

[0214] As the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b, a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may also be applied. By using a Cu-X alloy film, it can be processed by a wet etching method, and thus the manufacturing cost can be reduced.

[0215] Note that the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b may use the same material or different materials from each other.

[0216] The conductive layer 112a and the conductive layer 112b have regions in contact with the semiconductor layer 108. The conductive layer 212a and the conductive layer 212b have regions in contact with the semiconductor layer 208. When a metal oxide is used as the semiconductor layer 108, there is a concern that when a metal that is easily oxidized (for example, aluminum) is used as the conductive layer 112a and the conductive layer 112b, an insulating oxide (for example, aluminum oxide) is formed between the conductive layer 112a and the semiconductor layer 108 and between the conductive layer 112b and the semiconductor layer 108, hindering their conduction. Similarly, when a metal oxide is used as the semiconductor layer 208, there is a concern that when a metal that is easily oxidized is used as the conductive layer 212a and the conductive layer 212b, an insulating oxide is formed between the conductive layer 212a and the semiconductor layer 208 and between the conductive layer 212b and the semiconductor layer 208, hindering their conduction. Therefore, the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b preferably use a conductive material that is not easily oxidized, a conductive material that maintains a low resistance even when oxidized, or an oxide conductor.

[0217] The conductive layers 112a, 112b, 112a and 112b are preferably made of, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. Since these materials are conductive materials that are not easily oxidized or materials that maintain a low resistance even when oxidized, they are preferred.

[0218] The conductive layers 112a, 112b, 212a and 212b can use the above-mentioned oxide conductors. Specifically, oxide conductors such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, and zinc oxide doped with gallium can be used.

[0219] The conductive layers 112a, 112b, 212a and 212b can also all use nitride conductors. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0220] The conductive layers 112a, 112b, 104, 212a, 212b and 204 can also all have a stacked structure. In this case, at least the regions in contact with the semiconductor layers 108 and 208 are preferably made of a conductive material that is not easily oxidized, a conductive material that maintains a low resistance even when oxidized, or an oxide conductor. In addition, the regions not in contact with the semiconductor layer 108 and not in contact with the semiconductor layer 208 are preferably made of a material with a low resistivity. Thereby, the resistance of the conductive layer can be reduced. For example, In-Sn-Si oxide (ITSO) can be appropriately used for the regions in contact with the semiconductor layer 108 and the regions in contact with the semiconductor layer 208, and copper or tungsten can be appropriately used for the regions not in contact with the semiconductor layer 108 and not in contact with the semiconductor layer 208.

[0221] [Insulating layer 106] The insulating layer 106 can have a single-layer structure or a stacked structure of two or more layers. The insulating layer 106 preferably includes one or more inorganic insulating films. Examples of materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and oxynitrides. The insulating layer 106 can use the materials that can be used for the insulating layer 110.

[0222] The insulating layer 106 has regions in contact with the semiconductor layer 108 and the semiconductor layer 208. When metal oxides are used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable that at least the film of the insulating layer 106 in contact with the semiconductor layer 108 and the semiconductor layer 208 uses any one of the above-mentioned oxides and oxynitrides. In addition, the insulating layer 106 more preferably uses a film that releases oxygen upon heating.

[0223] Specifically, when the insulating layer 106 has a single-layer structure, the insulating layer 106 preferably uses an oxide or an oxynitride. Specifically, the insulating layer 106 is suitably made of silicon oxide or silicon oxynitride.

[0224] When the insulating layer 106 has a stacked structure, preferably, the insulating film on the side in contact with the semiconductor layer 108 and the semiconductor layer 208 contains an oxide or an oxynitride, and the insulating film on the side in contact with the conductive layer 104 and the conductive layer 204 contains a nitride or a oxynitride. As such an oxide or oxynitride, for example, silicon oxide or silicon oxynitride is suitably used. As such a nitride or oxynitride, silicon nitride or silicon oxynitride is suitable.

[0225] Silicon nitride and silicon oxynitride have the characteristics that the amount of impurities (e.g., water and hydrogen) released by themselves is small and it is not easy for oxygen and hydrogen to permeate through, so they are suitable for use as the insulating layer 106. Since the diffusion of impurities from the insulating layer 106 to the semiconductor layer 108 and the semiconductor layer 208 is suppressed, good electrical characteristics of the transistor can be achieved and the reliability can be improved.

[0226] Note that in a micro transistor, when the thickness of the gate insulating layer is small, the leakage current sometimes increases. By using a material with a relatively high relative dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to achieve low voltage operation of the transistor while maintaining the physical thickness. As high-k materials that can be used for the insulating layer 106, for example, gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium can be cited.

[0227] [Insulating layer 195] The insulating layer 195 used as a protective layer for the transistor 100 and the transistor 200 preferably uses a material in which impurities do not easily diffuse. By providing the insulating layer 195, it is possible to effectively suppress the diffusion of impurities from the outside into the transistor, thereby improving the reliability of the semiconductor device. Examples of impurities include water and hydrogen.

[0228] The insulating layer 195 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. The insulating layer 195 is, for example, suitable for using inorganic materials such as oxides, oxynitrides, nitrides, or nitrides. More specifically, one or more of silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. As the organic material, for example, one or more of acrylic resin and polyimide resin can be used. A photosensitive material can also be used as the organic material. In addition, two or more of the above insulating films can be laminated. The insulating layer 195 can also have a laminated structure including an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0229] [Substrate 102] Although there is no particular limitation on the material of the substrate 102, it is at least necessary to have heat resistance capable of withstanding subsequent heat treatment. For example, a single-crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate can be used as the substrate 102. In addition, semiconductor elements can also be provided on the substrate 102. Note that the shapes of the semiconductor substrate and the insulating substrate can be circular or angular.

[0230] As the substrate 102, a flexible substrate can also be used, and transistors 100 etc. can be directly formed on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the transistors 100 etc. By providing the release layer, after manufacturing a part or all of the semiconductor device on the release layer, it can be separated from the substrate 102 and transferred to another substrate. At this time, the transistors 100 etc. can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0231] As the substrate 102, an insulating layer can also be laminated on the above substrate.

[0232] Next, a structural example of a semiconductor device whose partial structure is different from the above structural example 1 will be described. Hereinafter, the description of the parts overlapping with the above structural example 1 may be omitted. In addition, in the following drawings, the parts having the same functions as those in the above structural example 1 are shaded with the same hatching, and sometimes no reference numerals are attached.

[0233] <Structural Example 2> Figure 15A A top view of a semiconductor device 10A showing one aspect of the present invention is shown. Figure 15B Shown along Figure 15A The cross-sectional view of the cross-section along the dotted line A1 - A2 shown is shown.

[0234] The semiconductor device 10A includes a transistor 100A, a transistor 200A, and an insulating layer 110. The main difference between the transistor 100A and the Figure 12A transistor 100 shown, for example, is that the transistor 100A includes an insulating layer 147 and an insulating layer 149. The main difference between the transistor 200A and the Figure 12A transistor 200 shown, for example, is that the transistor 200A includes an insulating layer 247 and an insulating layer 249.

[0235] In the transistor 200A, the insulating layer 247 and the insulating layer 249 are provided between the insulating layer 110 and the semiconductor layer 208, between the conductive layer 212a and the semiconductor layer 208, and between the conductive layer 212b and the semiconductor layer 208.

[0236] The insulating layer 247 contacts the side surface of the insulating layer 110, the side surfaces of the conductive layer 212a and the conductive layer 212b, the top surface of the substrate 102, the side surfaces and the bottom surface of the semiconductor layer 208, and the side surfaces and the bottom surface of the insulating layer 249. As Figure 15B shown, in a cross-section, a protrusion is formed in a portion of the insulating layer 247 that contacts the top surface of the substrate 102. At the end of the protrusion, the insulating layer 247 contacts the semiconductor layer 208. The protrusion of the insulating layer 247 is shaped to protrude toward the central portion of the opening 145 more than other portions.

[0237] The insulating layer 247 preferably has a hydrogen barrier property, and particularly preferably has a high ability to suppress hydrogen diffusion. The insulating layer 247 can be, for example, one or more of alumina, magnesia, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon oxynitride. As the insulating layer 247, for example, silicon nitride is suitably used. By providing the insulating layer 247, hydrogen diffusion from the outside of the transistor 200A through the insulating layer 247 to the semiconductor layer 208 can be suppressed.

[0238] In this specification and the like, the barrier property refers to one or both of the following functions: a function in which the target substance is not easily diffused, thereby suppressing the permeation of the substance (it can also be said that the permeability is low); a function of capturing or fixing (also referred to as gettering) the target substance.

[0239] The insulating layer 249 contacts the side surfaces of the insulating layer 247 and the top surface of the protrusion, and the side surfaces and the bottom surface of the semiconductor layer 208. As Figure 15B shown, in a cross-section, the side surface of the insulating layer 249 sometimes aligns with the side end of the protrusion of the insulating layer 247.

[0240] The insulating layer 249 preferably has a hydrogen barrier property, and more preferably has a high ability to capture or fix (also referred to as gettering) hydrogen. As the insulating layer 249, for example, one or more of an oxide containing magnesium and an oxide containing one or both of aluminum and silicon can be used. Further, these oxides more preferably have an amorphous structure. Oxides having an amorphous structure sometimes have the following property: oxygen atoms have dangling bonds and capture or fix hydrogen by these dangling bonds. Further, these metal oxides preferably have an amorphous structure, but a part thereof may form a crystalline region. As the insulating layer 249, for example, hafnium oxide is suitably used. By providing the insulating layer 249, for example, hydrogen, water, etc. contained in the semiconductor layer 208 or the insulating layer 106 can be captured or fixed by the insulating layer 249.

[0241] The semiconductor layer 208 is provided so as to be in contact with the top surface of the conductive layer 212a, the top surface of the conductive layer 212b, the top surface and side surfaces of the insulating layer 247, and the top surface and side surfaces of the insulating layer 249. Further, as Figure 15B shown, the bottom surface of the semiconductor layer 208 may also be in contact with the top surface of the substrate 102.

[0242] Since the insulating layer 247 and the insulating layer 249 are provided in the transistor 200A, when an oxide semiconductor is used for the semiconductor layer 208, hydrogen, water, etc. that may be mixed into the oxide semiconductor can be removed, and thus a highly reliable semiconductor device can be realized.

[0243] In the transistor 100A, the insulating layer 147 and the insulating layer 149 are provided between the insulating layer 110 and the semiconductor layer 108 and between the conductive layer 112b and the semiconductor layer 108.

[0244] The insulating layer 147 is in contact with the side surface of the insulating layer 110, the side surfaces of the conductive layer 112b and the conductive layer 112a, the side surfaces and the bottom surface of the semiconductor layer 108, and the side surfaces and the bottom surface of the insulating layer 149. As Figure 15B shown, in a cross section, a protrusion is formed in a portion of the insulating layer 147 that is in contact with the top surface of the conductive layer 112a. At the end of the protrusion, the insulating layer 147 is in contact with the semiconductor layer 108. The protrusion of the insulating layer 147 has a shape that protrudes toward the central portion of the opening 141 more than other portions.

[0245] As the insulating layer 147, a material that can be used for the insulating layer 247 can be used. The insulating layer 147 can be formed in the same process as the insulating layer 247. For example, a film that will become the insulating layer 247 and the insulating layer 147 can be formed and processed to form the insulating layer 247 and the insulating layer 147.

[0246] The insulating layer 149 is in contact with the side surfaces of the insulating layer 147 and the top surface of the protrusion, and the side surfaces and the bottom surface of the semiconductor layer 108. As Figure 15BAs shown, in a cross-sectional view, the side surface of the insulating layer 149 sometimes aligns with the side end portion of the protruding portion of the insulating layer 147.

[0247] The insulating layer 149 can use the material that can be used for the insulating layer 249. The insulating layer 149 can be formed in the same process as the insulating layer 249. For example, a film that will become the insulating layer 249 and the insulating layer 149 can be formed and processed to form the insulating layer 249 and the insulating layer 149.

[0248] The semiconductor layer 108 is disposed in contact with the top surface of the conductive layer 112a, the top surface of the conductive layer 112b, the top surface and the side surface of the insulating layer 147, and the top surface and the side surface of the insulating layer 149.

[0249] Note that the structures of the insulating layer 147, the insulating layer 149, the insulating layer 247, the insulating layer 249, the semiconductor layer 108, and the semiconductor layer 208 shown here can also be applied to other structural examples.

[0250] <Structural Example 3> Figure 16A A top view of a semiconductor device 10B showing one embodiment of the present invention. Figure 16B Shown along Figure 16A The cross-sectional view of the cross-section along the dash-dotted line A1 - A2 shown.

[0251] The semiconductor device 10B includes a transistor 100A, a transistor 200B, and an insulating layer 110. The main difference between the transistor 200B and Figure 15A the transistor 200A shown, etc., is that in the transistor 200B, the semiconductor layer 208 is also provided at the bottom of the opening 145. The transistor 200B adopts the structure of the above-mentioned transistor 20A.

[0252] Note that the structure of the semiconductor layer 208 shown here can also be applied to other structural examples.

[0253] <Structural Example 4> Figure 17A A top view of a transistor 200C showing one embodiment of the present invention. Figure 17B Shown along Figure 17A The cross-sectional view of the cross-section along the dash-dotted line A1 - A2 shown.

[0254] The transistor 200C and Figure 12A the transistor 200 shown, etc., the main difference is that in the transistor 200C, the shape of the opening 145 is a shape including an extension portion and a bent portion. Here, the top surface shape of the opening 145 formed by combining the extension portion and the bent portion can be called a meandering shape, a tortuous shape, a zigzag shape, or a bent shape.

[0255] AsFigure 17A As shown, the opening 145 includes an extension portion 146a, an extension portion 146b, an extension portion 146c, a bending portion 148a, and a bending portion 148b. The shape of the top surface of the opening 145 can be regarded as a shape in which the extension portion 146a and the extension portion 146b are connected by the bending portion 148a, and the extension portion 146b and the extension portion 146c are connected by the bending portion 148b. A semiconductor layer 208 is provided in contact with the side surface of the opening 145. Inside the opening 145, the semiconductor layer 208 is disposed opposite to the conductive layer 204 with an insulating layer 106 therebetween. Here, the semiconductor layer 208 is in contact with the conductive layer 212a in the extension portion 146a and in contact with the conductive layer 212b in the extension portion 146b.

[0256] The extension portion 146a, the extension portion 146b, and the extension portion 146c have a shape extending in one direction ( Figure 17A the direction perpendicular to the dotted line A1 - A2 in the plan view). In contrast, in the plan view, the bending portion 148a and the bending portion 148b are disposed such that one end thereof is bent with respect to the other end.

[0257] By connecting two extension portions with one bending portion, a folded structure can be formed in the opening 145. By forming one or more of the above - mentioned folded shapes, the length of the opening 145 can be made significantly larger than the distance between the conductive layer 212a and the conductive layer 212b. Therefore, the channel length of the transistor 200C can be significantly increased, and thus the saturation of the transistor 200C can be further improved.

[0258] Figure 17A The structure showing that the opening 145 includes the extension portion 146a, the extension portion 146b, the extension portion 146c, the bending portion 148a, and the bending portion 148b is shown, but the present invention is not limited thereto. It is sufficient that the opening 145 has a plurality of extension portions and at least one or more bending portions. Here, the number of bending portions is preferably one less than the number of extension portions. For example, the opening 145 may also have two extension portions and one bending portion. In addition, for example, the opening 145 may also have four or more extension portions and three or more bending portions.

[0259] In Figure 17A the plan view, the shape of the top surface of the opening 145 is a shape with rounded corners, but the present invention is not limited thereto, and it may also be a shape in which the corners of the extension portion and the bending portion are angular. At this time, the shape of the top surface of the opening 145 may also be referred to as a saw - tooth shape.

[0260] Note that although Figure 17A the structure in which the conductive layer 204 covers the entire opening 145 is shown, the present invention is not limited thereto. For example, as Figure 18A and Figure 18BSimilar to the transistor 200D shown, the conductive layer 204 may also overlap with a part of the opening 145.

[0261] Here, as Figure 18A shown, the semiconductor layer 208 connecting the conductive layer 212a and the conductive layer 212b has two paths represented by the dotted lines C1 - C2 and the dotted lines D1 - D2. In Figure 18A the transistor, the path represented by the dotted lines C1 - C2 is covered by the conductive layer 204, but the path represented by the dotted lines D1 - D2 is exposed from the conductive layer 204. In the region where the conductive layer 204 is not formed, the top surface of the insulating layer 195 contacts the top surface of the insulating layer 106. By adopting such a structure, the layout area of the conductive layer 204 can be reduced, and the transistors 200D can be arranged in a high density.

[0262] In the transistor 200D, only the semiconductor layer 208 of the path represented by the dotted lines C1 - C2 is used as the channel formation region. Therefore, compared with Figure 17A the transistor 200C shown, the substantial channel width can be considered to be approximately half. Therefore, in Figure 18A the transistor 200D shown, the channel width is smaller, so the saturation can be further improved.

[0263] Note that the structure of the opening 145 shown here can also be used in other structural examples.

[0264] <Structural Example 5> Figure 19A A cross-sectional view of the transistor 200E showing one embodiment of the present invention. In addition, Figure 19B a cross-sectional view of the transistor 100B showing one embodiment of the present invention is shown.

[0265] The main difference between the transistor 200E and the transistor 200 is that in the transistor 200E, conductive layers 216 are included between the substrate 102 and the conductive layer 212a and between the substrate 102 and the conductive layer 212b, and the insulating layer 110 has a six-layer structure.

[0266] The insulating layer 110 includes an insulating layer 110a on the substrate 102, an insulating layer 110b1 on the insulating layer 110a, an insulating layer 110d1 on the insulating layer 110b1, an insulating layer 110d2 on the insulating layer 110d1 and the conductive layer 216, an insulating layer 110b2 on the insulating layer 110d2, and an insulating layer 110c on the insulating layer 110b2.

[0267] The conductive layer 216 is used as the back gate electrode (also referred to as the second gate electrode) of the transistor 200E. The conductive layer 216 is preferably located on the insulating layer 110d1. The conductive layers 212a and 212b are electrically insulated from the conductive layer 216 by the insulating layers 110c, 110b2, and 110d2. The conductive layer 216 is preferably provided with an opening, and an opening 145 is preferably provided inside the opening.

[0268] The conductive layer 216 may also be electrically connected to the conductive layer 212a or the conductive layer 212b. For example, the conductive layer 212a and the conductive layer 216 may also be in contact through an opening provided in the insulating layers 110d2, 110b2, and 110c.

[0269] Note that although Figure 19A shows that the cross-sectional shape of the conductive layer 216 has a tapered structure, one embodiment of the present invention is not limited thereto. For example, the cross-sectional shape of the conductive layer 216 may also be a vertical shape. By making the conductive layer 216 have a vertical cross-sectional shape, the side surface of the conductive layer 216 is parallel to the surface of the semiconductor layer 208 in contact with the insulating layer 110. Thereby, the potential supplied to the conductive layer 216 can be efficiently supplied to the semiconductor layer 208, which is preferable.

[0270] The conductive layer 216 may have a single-layer structure or a stacked structure of two or more layers. The conductive layer 216 may use materials that can be used for the conductive layer 212a, the conductive layer 212b, and the conductive layer 204.

[0271] The insulating layer 110d2 covers the top surface and the side surface of the conductive layer 216. The insulating layer 110d2 is provided so as to cover a part of the opening of the conductive layer 216. The insulating layer 110d2 is preferably in contact with the insulating layer 110d1 through the opening.

[0272] The insulating layer 110d1 and the insulating layer 110d2 preferably have the same structure as the insulating layers 110a and 110c. Specifically, the insulating layer 110d1 and the insulating layer 110d2 preferably use a film through which oxygen does not easily diffuse. In addition, the insulating layer 110d1 and the insulating layer 110d2 preferably use a film through which hydrogen does not easily diffuse. By providing such insulating layers 110d1 and 110d2, oxidation of the conductive layer 216 can be suppressed. In addition, diffusion of hydrogen contained in the conductive layer 216 into the semiconductor layer 208 can be suppressed.

[0273] Note that although Figure 19AAn example is shown in which the thickness of the insulating layer 110d1 is uniform regardless of its position, but the present invention is not limited thereto. For example, the thickness of the insulating layer 110d1 is sometimes different between the region overlapping the conductive layer 216 and the region not overlapping the conductive layer 216. For example, when processing the film that will become the conductive layer 216, sometimes a part of the region of the insulating layer 110d1 that does not overlap the conductive layer 216 is removed, and its thickness is reduced.

[0274] The insulating layer 110b2 preferably covers the top surface and the side surface of the conductive layer 216 with the insulating layer 110d2 interposed therebetween. The insulating layer 110b2 is preferably provided so as to cover a part of the opening of the conductive layer 216 with the insulating layer 110d2 interposed therebetween.

[0275] Both the insulating layer 110b1 and the insulating layer 110b2 can have the same structure as that applicable to the insulating layer 110b. Specifically, both the insulating layer 110b1 and the insulating layer 110b2 preferably use an oxygen-containing layer and preferably have a region with a higher oxygen content than at least one of the insulating layer 110a, the insulating layer 110c, the insulating layer 110d1, and the insulating layer 110d2.

[0276] By adopting such a structure, the structure of the insulating layer 110 can be a vertically symmetric structure with respect to the conductive layer 216. In addition, since oxygen can be supplied to the semiconductor layer 208 from both the insulating layers 110b1 and 110b2, transistor characteristics can be improved.

[0277] Note that the present invention is not limited to the above structure. For example, a structure in which the insulating layer 110b1 is not provided may be adopted. In addition, a structure in which the insulating layers 110d1 and 110d2 are not provided may be adopted.

[0278] In the transistor 200E, the semiconductor layer 208 has a region overlapping the conductive layer 204 with the insulating layer 106 interposed therebetween and overlapping the conductive layer 216 with a part of the insulating layer 110 (in particular, the insulating layer 110b2 and the insulating layer 110d2) interposed therebetween. In other words, at least a part of the semiconductor layer 208 is sandwiched between the side surface of the conductive layer 204 and the side surface of the conductive layer 216, a part of the insulating layer 110 (in particular, the insulating layer 110b2 and the insulating layer 110d2) is provided between at least a part of the semiconductor layer 208 and the side surface of the conductive layer 204, and the insulating layer 106 is provided between at least a part of the semiconductor layer 208 and the side surface of the conductive layer 216. Here, a part of the insulating layer 110 is used as the back gate insulating layer (also referred to as the second gate insulating layer) of the transistor 200C.

[0279] Since the transistor 200E has a back gate electrode, the potential of the back gate side (also referred to as the back channel) of the semiconductor layer 208 can be fixed. Therefore, the saturation in the Id-Vd characteristics of the transistor 200E can be further improved.

[0280] Since the transistor 200E has a back gate electrode, the back channel potential of the semiconductor layer 208 can be fixed, and the negative drift of the threshold voltage can be suppressed. Thereby, a transistor with normally-off characteristics (that is, the threshold voltage is positive) can be realized.

[0281] The transistor 200E has a region in which a conductive layer 216, an insulating layer 110, a semiconductor layer 208, an insulating layer 106, and a conductive layer 204 are sequentially stacked in one direction, and no other layers are included therebetween. By expanding this region, the electric field of the back channel of the semiconductor layer 208 can be more surely controlled.

[0282] Note that in a cross-sectional view, sometimes the shortest distances between the conductive layer 216 and the semiconductor layer 208 on the left and right sides of the opening of the insulating layer 110 are different.

[0283] In addition, similar to the transistor 200E, a back gate can also be provided in the transistor 100. Figure 19B The main difference between the shown transistor 100B and the transistor 100 is that in the transistor 100B, a conductive layer 116 is included between the conductive layer 112a and the conductive layer 112b, and the insulating layer 110 has a six-layer structure. Note that although Figure 19B shows that the cross-sectional shape of the conductive layer 116 has a tapered shape structure, it is not limited thereto. For example, the cross-sectional shape of the conductive layer 116 can also be configured vertically. By adopting this configuration, the side surface of the conductive layer 116 is parallel to the surface of the semiconductor layer 208 in contact with the insulating layer 110. By adopting the above configuration, the potential supplied to the conductive layer 116 can be efficiently supplied to the semiconductor layer 208, so it is preferable.

[0284] Here, the conductive layer 116 corresponds to the above-mentioned conductive layer 216, and the description of the conductive layer 216 can be referred to. That is, the conductive layer 116 is used as the back gate electrode of the transistor 100B. In addition, the insulating layer 110 has the same structure as Figure 19A the shown insulating layer 110. In other words, a part of the insulating layer 110 is used as the back gate insulating layer of the transistor 100B.

[0285] Therefore, also in the transistor 100B, the semiconductor layer 108 has a region that overlaps with the conductive layer 104 across the insulating layer 106 and overlaps with the conductive layer 116 across a part of the insulating layer 110 (in particular, the insulating layer 110b2 and the insulating layer 110d2). In other words, at least a part of the semiconductor layer 108 is sandwiched between the side surface of the conductive layer 104 and the side surface of the conductive layer 116, a part of the insulating layer 110 (in particular, the insulating layer 110b2 and the insulating layer 110d2) is provided between at least a part of the semiconductor layer 108 and the side surface of the conductive layer 104, and the insulating layer 106 is provided between at least a part of the semiconductor layer 108 and the side surface of the conductive layer 116.

[0286] Since the transistor 100B has a back gate, the potential of the back gate side (also referred to as the back channel) of the semiconductor layer 108 can be fixed. Therefore, the saturation in the Id-Vd characteristics of the transistor 200B can be improved.

[0287] In addition, since the transistor 100B has a back gate electrode, the back channel potential of the semiconductor layer 108 can be fixed, and the negative drift of the threshold voltage can be suppressed. Thereby, a transistor with normally-off characteristics (that is, the threshold voltage is positive) can be realized.

[0288] Note that the structures of the conductive layer 216 and the insulating layer 110 shown here can also be applied to other structural examples.

[0289] This embodiment can be appropriately combined with other embodiments. In addition, in this specification, when multiple structural examples are shown in one embodiment, the structural examples can be appropriately combined.

[0290] (Embodiment 3) In this embodiment, with reference to Figure 20A FIG. 30 to FIG. 30, a manufacturing method of a display device according to one aspect of the present invention will be described. Note that, regarding the materials and formation methods of the respective components, parts that are the same as those described in the above Embodiment 2 may sometimes be omitted.

[0291] The thin films (such as insulating films, semiconductor films, and conductive films) constituting the semiconductor device can be formed by a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a vacuum evaporation method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, an ALD method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, etc. As the CVD method, there are a PECVD method and a thermal CVD method, etc. In addition, as one of the thermal CVD methods, there is a metal organic chemical vapor deposition (MOCVD: Metal Organic CVD) method.

[0292] The thin films (such as insulating films, semiconductor films, and conductive films) that make up a semiconductor device can be formed by wet deposition methods such as spin coating, dip coating, spray coating, inkjet printing, dispenser printing, screen printing, offset printing, doctor knife method, slot die coating, roll coating, curtain coating, or blade coating.

[0293] When processing the thin films that make up a semiconductor device, photolithography or the like can be used. Alternatively, nanoimprinting, sandblasting, lift-off, or the like can be used to process the thin films. In addition, island-shaped thin films can be directly formed by a deposition method using a masking mask such as a metal mask.

[0294] Typically, there are the following two methods of photolithography. One is a method of forming a resist mask on a thin film to be processed, processing the thin film by etching or the like, and removing the resist mask. The other is a method of depositing a photosensitive thin film and then performing exposure and development to process the thin film into a desired shape.

[0295] In photolithography, as the light used for exposure, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing these lights can be used. In addition, ultraviolet light, KrF laser, ArF laser, or the like can also be used. In addition, immersion exposure technology can also be used for exposure. In addition, as the light used for exposure, extreme ultraviolet (EUV) light or X-rays can also be used. In addition, instead of the light used for exposure, an electron beam can also be used. When using extreme ultraviolet light, X-rays, or an electron beam, extremely fine processing can be performed, so it is preferred. Note that when performing exposure by scanning with a light beam such as an electron beam, a photomask is not required.

[0296] As an etching method for thin films, one or more of dry etching, wet etching, and sandblasting can be used.

[0297] <Example of manufacturing method 1> Here, with reference to Figures 20A to 25B Explanation Figure 12A And Figure 12B An example of the manufacturing method of the semiconductor device 10 shown in Figures 20A to 23B Shows a cross-sectional view along Figure 12A The dotted line A1 - A2 shown in Figures 24A to 25B Shows a top view.

[0298] First, a film that will become the conductive layer 112a is formed on the substrate 102, and this film is processed to form the conductive layer 112a. This film is preferably formed by sputtering.

[0299] Next, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed on the substrate 102 and the conductive layer 112a( Figure 20A ).

[0300] When forming the insulating film 110af and the insulating film 110bf, the sputtering method or the PECVD method is preferably used. It is preferable to continuously form the insulating film 110bf in a vacuum without exposing the surface of the insulating film 110af to the atmosphere after forming the insulating film 110af. By continuously forming the insulating film 110af and the insulating film 110bf, attachment of impurities derived from the atmosphere to the surface of the insulating film 110af can be suppressed. Examples of such impurities include water and organic substances.

[0301] The substrate temperature when forming the insulating film 110af and the insulating film 110bf is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, more preferably 350°C or higher and 400°C or lower. By setting the substrate temperature when forming the insulating film 110af and the insulating film 110bf within the above range, release of impurities (e.g., water and hydrogen) from the insulating film 110af and the insulating film 110bf themselves can be reduced, and thus diffusion of impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor having good electrical characteristics and high reliability can be realized.

[0302] Note that since the insulating film 110af and the insulating film 110bf are formed first and then the semiconductor layer 108 and the semiconductor layer 208 are formed, there is no concern about oxygen detachment from the semiconductor layer 108 and the semiconductor layer 208 due to heat applied when forming the insulating film 110af and the insulating film 110bf.

[0303] After forming the insulating film 110bf, oxygen can also be supplied to the insulating film 110bf. As a method for supplying oxygen, for example, the ion implantation method, the ion doping method, the plasma immersion ion implantation method, or plasma treatment can be used. As plasma treatment, a device that plasmaizes oxygen gas with high-frequency power is preferably used. As a device that plasmaizes a gas with high-frequency power, for example, a PECVD device, a plasma etching device, and a plasma ashing device can be cited. The plasma treatment is preferably performed in an oxygen-containing atmosphere. For example, it is preferable to perform the plasma treatment in an atmosphere containing one or more of oxygen, nitrous oxide (N2O), nitrogen dioxide (NO2), carbon monoxide, and carbon dioxide.

[0304] Note that this plasma treatment can also be continuously performed in a vacuum in such a manner that the surface of the insulating film 110bf is not exposed to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform this plasma treatment using the PECVD apparatus. Thereby, the productivity can be improved. Specifically, after the insulating film 110bf is formed using the PECVD apparatus, N2O plasma treatment can be continuously performed in a vacuum.

[0305] Preferably, a metal oxide layer 137 is formed on the insulating film 110bf ( Figure 20B ). By forming the metal oxide layer 137, oxygen can be supplied to the insulating film 110bf.

[0306] There is no limitation on the conductivity of the metal oxide layer 137. The metal oxide layer 137 can use at least one of an insulating film, a semiconductor film, and a conductive film. For example, the metal oxide layer 137 can use alumina, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO).

[0307] As the metal oxide layer 137, it is preferable to use an oxide material containing one or more elements the same as those of the semiconductor layer 108 and the semiconductor layer 208. In particular, it is preferable to use a metal oxide material applicable to the semiconductor layer 108 and the semiconductor layer 208.

[0308] When forming the metal oxide layer 137, the higher the oxygen flow ratio of the deposition gas introduced into the processing chamber of the deposition apparatus or the oxygen partial pressure in the processing chamber, the more the amount of oxygen supplied to the insulating film 110bf can be increased. The oxygen flow ratio or the oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% or more and 100% or less, more preferably 80% or more and 100% or less, and further preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow ratio to 100% to make the oxygen partial pressure as close to 100% as possible.

[0309] Thus, by forming the metal oxide layer 137 by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf while preventing oxygen from escaping from the insulating film 110bf when forming the metal oxide layer 137. As a result, more oxygen can be enclosed in the insulating film 110bf. And, more oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, oxygen vacancies and V O H in the semiconductor layer 108 can be reduced, and a transistor having good electrical characteristics and high reliability can be realized.

[0310] The heat treatment is preferably performed after forming the metal oxide layer 137. By performing the heat treatment after forming the metal oxide layer 137, oxygen can be effectively supplied from the metal oxide layer 137 to the insulating film 110bf.

[0311] The temperature of the heat treatment is preferably 150 °C or higher, 200 °C or higher, 230 °C or higher, or 250 °C or higher and lower than the strain point of the substrate, 450 °C or lower, 400 °C or lower, 350 °C or lower, or 300 °C or lower. The heat treatment can be performed in an atmosphere containing one or more of noble gases, nitrogen, and oxygen. As the nitrogen-containing atmosphere or oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) can also be used. Note that the content of hydrogen, oxygen, etc. in this atmosphere is preferably as small as possible. As this atmosphere, a high-purity gas with a dew point of -60 °C or lower, preferably -100 °C or lower, is preferably used. By using an atmosphere with as little content of hydrogen, water, etc. as possible, absorption of hydrogen, water, etc. by the insulating film 110af, the insulating film 110bf, etc. can be prevented as much as possible. This heat treatment can use an oven, a rapid thermal annealing (RTA) apparatus, etc. By using an RTA apparatus, the heat treatment time can be shortened.

[0312] After forming the metal oxide layer 137 or after the above heat treatment, oxygen can also be supplied to the insulating film 110bf through the metal oxide layer 137. As a method for supplying oxygen, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used. Regarding the plasma treatment, reference can be made to the above description, so its detailed description is omitted.

[0313] Next, the metal oxide layer 137 is removed. Although there is no particular limitation on the method for removing the metal oxide layer 137, a wet etching method is preferably used. By using the wet etching method, etching of the insulating film 110bf when removing the metal oxide layer 137 can be suppressed. Therefore, a decrease in the thickness of the insulating film 110bf can be suppressed, and the thickness of the insulating layer 110b can be made uniform.

[0314] After removing the metal oxide layer 137, oxygen can also be supplied to the insulating film 110bf. Regarding the method for supplying oxygen, reference can be made to the above description. For example, as Figure 20C shown, a film 139 is formed on the insulating film 110bf, and oxygen can also be supplied to the insulating film 110bf through the film 139. As this treatment, a plasma treatment in an oxygen-containing atmosphere can be used. Figure 20C The case of supplying oxygen to the insulating film 110bf is schematically indicated by an arrow in

[0315] The film 139 is preferably a conductive film or a semiconductor film. The film 139 can be a metal oxide film, a metal film, or an alloy film. When a metal oxide is used as the film 139 and is formed by sputtering or the like in an oxygen-containing atmosphere, oxygen can also be supplied to the insulating film 110bf when the film 139 is formed, so it is preferred.

[0316] The thickness of the film 139 is preferably thin. Specifically, the thickness of the film 139 is preferably 1 nm or more, 2 nm or more, or 3 nm or more and 20 nm or less, 15 nm or less, or 10 nm or less. Typically, it can be about 5 nm.

[0317] The substrate temperature during the formation of the film 139 is preferably 350 °C or less, more preferably 340 °C or less, still more preferably 330 °C or less, and further preferably 300 °C or less. Thereby, the amount of oxygen supplied to the insulating film 110bf can be increased.

[0318] By providing the film 139, when a bias voltage is applied between a pair of electrodes in the presence of supplied oxygen, ionized oxygen is easily attracted. Therefore, the amount of oxygen supplied to the insulating film 110bf can be increased.

[0319] As a processing device for supplying oxygen, a dry etching device, an ashing device, a PECVD device, etc. are suitable. In particular, an ashing device is preferably used. When a bias voltage is applied between a pair of electrodes included in the processing device, for example, the bias voltage can be set to 10 V or more and 1 kV or less. Or, for example, the power density of the bias voltage can be set to 1 W / cm 2 and 5 W / cm 2 or less.

[0320] Next, the film 139 is removed. The removal of the film 139 is suitably carried out by a wet etching method.

[0321] The oxygen supply treatment for the insulating film 110bf is not limited to the above method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions are supplied to the insulating film 110bf by ion doping, ion implantation, or plasma treatment. In addition, after forming a film that inhibits oxygen desorption on the insulating film 110bf, oxygen can be supplied to the insulating film 110bf through this film. It is preferred to remove this film after supplying oxygen. As the above-mentioned film that inhibits oxygen desorption, a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten can be used.

[0322] Next, an insulating film 110cf ( Figure 20D ) that will become the insulating layer 110c is formed on the insulating film 110bf. Since the formation of the insulating film 110cf can be referred to the description regarding the formation of the insulating film 110af and the insulating film 110bf, the detailed description is omitted.

[0323] Next, a conductive film 112bf that will become the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b is formed on the insulating film 110cf( Figure 20E ). The conductive film 112bf is preferably formed by, for example, a sputtering method.

[0324] Next, the conductive film 112bf is processed to form the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b( Figure 21A ). The conductive layer 112b, the conductive layer 212a, and the conductive layer 212b are preferably formed by, for example, a wet etching method.

[0325] Next, a part of the insulating film 110af, the insulating film 110bf, and the insulating film 110cf is removed to form an insulating layer 110 including an opening 141 and an opening 145( Figure 21B ). The opening 141 is provided in a region overlapping the opening 143. By forming the opening 141, the conductive layer 112a is exposed, and by forming the opening 145, the substrate 102 is exposed. The insulating layer 110 is preferably formed by, for example, a dry etching method.

[0326] In addition, a part of the conductive layer 112a in a region overlapping the opening 141 may be removed when the opening 141 is formed or after the opening 141 is formed. By making the thickness of the region of the conductive layer 112a in contact with the bottom surface of the semiconductor layer 108 thinner than the thickness of the region not in contact with the semiconductor layer 108, the electric field applied to the gate electrode in the channel formation region near the conductive layer 112a can be enhanced, and thus the on-state current of the transistor can be increased.

[0327] Next, a metal oxide film 108f that will become the semiconductor layer 108 and the semiconductor layer 208 is formed so as to cover the opening 141, the opening 143, and the opening 145( Figure 21C ). The metal oxide film 108f is provided in contact with the top surface and the side surface of the conductive layer 112b, the top surface and the side surface of the insulating layer 110, the top surface of the conductive layer 112a, the top surface and the side surface of the conductive layer 212a, the top surface and the side surface of the conductive layer 212b, and the top surface of the substrate 102.

[0328] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target. Alternatively, the metal oxide film 108f is preferably formed by an ALD method. Because of the high coverage, the ALD method is also suitable for forming the metal oxide film 108f provided so as to cover the opening 141, the opening 143, and the opening 145. By using the ALD method, the metal oxide film can also be formed with high coverage on the side surface of the insulating layer 110. In addition, the ALD method can easily control the deposition rate, so that a thin film with high yield can be formed.

[0329] The metal oxide film 108f is preferably a dense film with as few defects as possible. In addition, the metal oxide film 108f is preferably a high-purity film in which impurities containing hydrogen elements are reduced as much as possible. In particular, a crystalline metal oxide film is preferably used as the metal oxide film 108f.

[0330] When forming the metal oxide film 108f, oxygen gas is preferably used. By using oxygen gas, it is suitable to supply oxygen to the insulating layer 110. For example, when the insulating layer 110b uses an oxide or an oxynitride, it is suitable to supply oxygen to the insulating layer 110b.

[0331] By supplying oxygen to the insulating layer 110b and supplying oxygen to the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208 in subsequent processes, oxygen vacancies and V O H in their channel formation regions can be reduced.

[0332] When forming the metal oxide film 108f, oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can also be mixed. Note that the higher the oxygen flow ratio or the oxygen partial pressure in the processing chamber during the formation of the metal oxide film, the higher the crystallinity of the metal oxide film can be, and a transistor with high reliability can be achieved. On the other hand, the lower the oxygen flow ratio or the oxygen partial pressure, a metal oxide film with lower crystallinity and higher conductivity can be achieved, so a transistor with a large on-state current can be achieved.

[0333] Here, when the oxygen flow ratio or the oxygen partial pressure is high, the metal oxide film sometimes has a polycrystalline structure. In a metal oxide film with a polycrystalline structure, grain boundaries become recombination centers and capture carriers, so the on-state current of the transistor sometimes becomes small. Therefore, it is preferable to adjust the oxygen flow ratio or the oxygen partial pressure so that the metal oxide film 108f does not have a polycrystalline structure. Since it is likely to have a polycrystalline structure depending on the composition of the metal oxide film, it is only necessary to adjust the oxygen flow ratio or the oxygen partial pressure according to the composition of the metal oxide film 108f.

[0334] When the substrate temperature during the formation of the metal oxide film is higher, a metal oxide film with higher crystallinity and higher density can be formed. On the other hand, as the substrate temperature becomes lower, a metal oxide film with lower crystallinity and higher conductivity can be formed.

[0335] The substrate temperature when forming the metal oxide film 108f is preferably above room temperature and below 250 °C, more preferably above room temperature and below 200 °C, and further preferably above room temperature and below 140 °C. For example, the substrate temperature is preferably above room temperature and below 140 °C, whereby the productivity can be improved. In addition, by forming the metal oxide film 108f at room temperature or in a state where the substrate is not heated, the crystallinity can be reduced.

[0336] When the substrate temperature is high, the metal oxide film sometimes has a polycrystalline structure. Therefore, it is preferable to adjust the substrate temperature so that the metal oxide film 108f does not have a polycrystalline structure. The substrate temperature can be adjusted according to the composition applied to the metal oxide film 108f.

[0337] When using the ALD method, it is preferable to use deposition methods such as thermal ALD or PEALD (Plasma Enhanced ALD). The thermal ALD method has extremely high coverage, so it is preferable. In addition, the PEALD method not only has high coverage but also can perform low-temperature deposition, so it is preferable.

[0338] The metal oxide film can be formed, for example, by using a precursor containing a constituent metal element and an oxidizing agent and using the ALD method.

[0339] For example, when forming an In-Ga-Zn oxide, three precursors including a precursor containing indium, a precursor containing gallium, and a precursor containing zinc can be used. Alternatively, two precursors including a precursor containing indium and a precursor containing gallium and zinc can also be used.

[0340] Examples of the precursor containing indium include triethylindium, indium tris(2,2,6,6-tetramethyl-3,5-heptanedionate), cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0341] Examples of the precursor containing gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, gallium tris(2,2,6,6-tetramethyl-3,5-heptanedionate), dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0342] Examples of the precursor containing zinc include dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0343] Examples of the oxidizing agent include ozone, oxygen, and water.

[0344] As a method for controlling the composition of the obtained film, adjustment of one or more of the type of source gas, the flow rate ratio of the source gas, the time for flowing the source gas, and the order of flowing the source gas can be cited. By adjusting them, the composition of the metal oxide film 108f can be controlled. In addition, by adjusting them, a film with a continuously changing composition can be formed. The composition of the metal oxide film 108f can also change continuously.

[0345] Before depositing the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, etc. adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen to the insulating layer 110. For example, a heat treatment can be performed at a temperature of 70°C or higher and 200°C or lower in a reduced-pressure atmosphere. Alternatively, a plasma treatment in an oxygen-containing atmosphere can also be performed. Or, by performing a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N2O), oxygen can also be supplied to the insulating layer 110. When performing a plasma treatment containing nitrous oxide gas, it is suitable for removing organic substances on the surface of the insulating layer 110 and can supply oxygen to the insulating layer 110. Preferably, after such a treatment, the metal oxide film 108f is continuously deposited in such a manner that the surface of the insulating layer 110 is not exposed to the atmosphere.

[0346] Note that in the case where the semiconductor layer 108 and the semiconductor layer 208 have a stacked structure, it is preferable that after depositing the lower metal oxide film, the upper metal oxide film is continuously deposited in such a manner that its surface is not exposed to the atmosphere.

[0347] In the case where the semiconductor layer 108 and the semiconductor layer 208 have a stacked structure, all the layers constituting the semiconductor layer 108 and the semiconductor layer 208 can be formed using the same deposition method (e.g., sputtering method or ALD method), or different deposition methods can be used for each layer. For example, the first metal oxide layer can be deposited using the sputtering method and the second metal oxide layer can be deposited using the ALD method.

[0348] Next, a resist mask 159 ( Figure 21D and Figure 24A ) is formed on the metal oxide film 108f. The resist mask 159 is disposed in the region where the semiconductor layer 108 is formed and is disposed so as to cover at least the openings 141 and 143. In Figure 24A , hatching is attached to the metal oxide film 108f and the resist mask 159. In addition, in order to easily understand the structure on the lower side of the metal oxide film 108f, the hatching of the metal oxide film 108f is shown in perspective.

[0349] Next, by processing the metal oxide film 108f into an island shape, the semiconductor layer 108 and the semiconductor layer 208A ( Figure 22A and Figure 24B ) that will become the semiconductor layer 208 are formed. The semiconductor layer 108 and the semiconductor layer 208A are suitably formed using a dry etching method. The semiconductor layer 108 and the semiconductor layer 208A are particularly suitably formed using an anisotropic dry etching method. The semiconductor layer 108 is formed in the region of the metal oxide film 108f covered by the resist mask 159, and the semiconductor layer 208A is formed in the region in contact with the side surface of the opening 145. Note that inFigure 24B In this case, the resist mask 159 and the semiconductor layer 208A are hatched.

[0350] Next, the resist mask 159 ( Figure 22B ) is removed.

[0351] Next, a resist mask 157 is formed on the semiconductor layer 108, the semiconductor layer 208A, the conductive layer 112b, the conductive layer 212a, the conductive layer 212b, the insulating layer 110, and the substrate 102 ( Figure 22C and Figure 25A ). The resist mask 157 is provided so as to cover at least the semiconductor layer 108 and the semiconductor layer 208A in the region that will become the semiconductor layer 208. At this time, the semiconductor layer 208A in the region where the semiconductor layer 208 is not provided is exposed. Note that in Figure 25A , the semiconductor layer 108, the semiconductor layer 208A, and the resist mask 157 are hatched. In addition, in order to easily understand the structure below the resist mask 157, the hatching of the resist mask 157 is shown in perspective.

[0352] Next, the semiconductor layer 208A in the region not covered by the resist mask 157 is removed to form the semiconductor layer 208. The semiconductor layer 208 can be formed by using one or both of a wet etching method and a dry etching method. In particular, a dry etching method is suitable.

[0353] Next, the resist mask 157 ( Figure 22D and Figure 25B ) is removed. Note that in Figure 25B , the semiconductor layer 108 and the semiconductor layer 208 are hatched.

[0354] Preferably, the heat treatment is performed after depositing the metal oxide film 108f or after processing the metal oxide film 108f into the semiconductor layer 108 and the semiconductor layer 208. By the heat treatment, hydrogen and water contained in the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 or adsorbed on the surfaces of the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 can be removed. In addition, by the heat treatment, sometimes the film quality of the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 is improved (for example, reduction of defects or improvement of crystallinity, etc.).

[0355] By the heat treatment, oxygen can be supplied from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108. Thereby, the oxygen vacancies (V O ) and V OH. At this time, it is more preferable to perform a heat treatment before processing the metal oxide film 108f into the semiconductor layers 108 and 208. Since the heat treatment can be referred to the above description, detailed explanation is omitted. Note that, not limited to this heat treatment, oxygen can also be supplied to the channel formation region in a heating step (for example, the step of forming the insulating layer 106) after forming the metal oxide film 108f.

[0356] Note that it is not necessarily required to perform this heat treatment. It is also possible not to perform the heat treatment in this step and use the heat treatment to be performed in a subsequent step as the heat treatment in this step. Sometimes, the heat treatment in a subsequent step (for example, the deposition step) can be used as the heat treatment in this step.

[0357] Next, an insulating layer 106 is formed so as to cover the semiconductor layer 108, the semiconductor layer 208, the insulating layer 110, and the substrate 102 ( Figure 23A ). When forming the insulating layer 106, for example, the PECVD method or the ALD method is suitable.

[0358] When using a metal oxide for the semiconductor layer 108 and the semiconductor layer 208, it is preferable to use the insulating layer 106 as a barrier film for suppressing oxygen diffusion. By the insulating layer 106 having the function of suppressing oxygen diffusion, it is possible to suppress the oxygen contained in the semiconductor layer 108 and the semiconductor layer 208 from diffusing to the upper side of the insulating layer 106, and thus it is possible to suppress the increase of oxygen vacancies (V O ) in the semiconductor layer 108 and the semiconductor layer 208. As a result, a transistor with good electrical characteristics and high reliability can be realized.

[0359] Note that in this specification and the like, a barrier film refers to a film having barrier properties. For example, an insulating layer having barrier properties can be called a barrier insulating layer.

[0360] By increasing the temperature during the formation of the insulating layer 106 used as the gate insulating layer, an insulating layer with fewer defects can be formed. However, when the temperature during the formation of the insulating layer 106 is high, oxygen detaches from the semiconductor layer 108 and the semiconductor layer 208, and sometimes oxygen vacancies (V O ) and V OH increases. The substrate temperature during the formation of the insulating layer 106 is preferably 180 °C or higher and 450 °C or lower, more preferably 200 °C or higher and 450 °C or lower, more preferably 250 °C or higher and 450 °C or lower, more preferably 300 °C or higher and 450 °C or lower, and even more preferably 300 °C or higher and 400 °C or lower. By setting the substrate temperature during the formation of the insulating layer 106 within the above range, it is possible to reduce defects in the insulating layer 106 while suppressing the detachment of oxygen from the semiconductor layer 108 and the semiconductor layer 208. Therefore, a transistor with good electrical characteristics and high reliability can be achieved.

[0361] Before forming the insulating layer 106, the surfaces of the semiconductor layer 108 and the semiconductor layer 208 may also be subjected to plasma treatment. By this plasma treatment, impurities such as water adsorbed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208 can be reduced. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 and at the interface between the semiconductor layer 208 and the insulating layer 106 can be reduced, and thus a highly reliable transistor can be achieved. In particular, when the surfaces of the semiconductor layer 108 and the semiconductor layer 208 are exposed to the atmosphere between the formation of the semiconductor layer 108 and the semiconductor layer 208 and the formation of the insulating layer 106, plasma treatment is preferred. The plasma treatment can be performed, for example, in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, etc. The plasma treatment and the deposition of the insulating layer 106 are preferably carried out continuously without exposure to the atmosphere.

[0362] Next, a film that will become the conductive layer 104 and the conductive layer 204 is formed on the insulating layer 106, and this film is processed to form the conductive layer 104 and the conductive layer 204 ( Figure 23B ). This film is suitably formed, for example, by a sputtering method, a thermal CVD method (including MOCVD method), or an ALD method.

[0363] Next, an insulating layer 195 is formed so as to cover the conductive layer 104, the conductive layer 204, and the insulating layer 106 ( Figure 12B ). The insulating layer 195 is suitably formed by a PECVD method.

[0364] A heat treatment may also be performed after the formation of the insulating layer 195. Note that this heat treatment may sometimes not be performed. In addition, the heat treatment to be performed in a later process may be used as this heat treatment without performing a heat treatment in this process. Sometimes, the heat treatment in a later process (for example, a deposition process) may be used as the heat treatment in this process.

[0365] Through the above steps, a semiconductor device according to one embodiment of the present invention can be manufactured.

[0366] <Example of manufacturing method 2> Here, referring to Figures 26A to 30BDescription Figure 15A and Figure 15B An example of a method for manufacturing the semiconductor device 10A shown in Figures 26A to 28D shows a cross-sectional view along the dash-dotted line A1 - A2 in Figure 15A . Figures 29A to 30B Shows a top view. Note that the description of the parts that overlap with the above Example 1 of the manufacturing method is omitted, and the different parts are described.

[0367] First, similarly to Example 1 of the manufacturing method, form up to the conductive film 112bf (refer to Figures 20A to 20E ).

[0368] Next, process the conductive film 112bf to form the conductive layer 112A ( Figure 26A ). The conductive layer 112A later becomes the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b. In addition, the conductive layer 112A includes the opening 143 and the opening 146. The opening 143 is formed in the region overlapping with the opening 141, and the opening 146 is formed in the region overlapping with the opening 145.

[0369] Next, remove a part of the insulating film 110af, the insulating film 110bf, and the insulating film 110cf to form the insulating layer 110 including the opening 141 and the opening 145 ( Figure 26B ).

[0370] Next, form an insulating film 147f that will become the insulating layer 147 and the insulating layer 247 so as to cover the opening 141, the opening 143, the opening 145, and the opening 146, and form an insulating film 149f that will become the insulating layer 149 and the insulating layer 249 on the insulating film 147f ( Figure 26C ).

[0371] The insulating film 147f is preferably formed in contact with the side wall of the opening 145. The insulating film 149f is preferably formed in contact with the concave portion of the insulating film 147f formed by reflecting the shape of the opening 145. Therefore, each of the insulating film 147f and the insulating film 149f preferably uses a deposition method with good coverage, and the CVD method or the ALD method can be used. It is preferable to continuously form the insulating film 149f in a vacuum without exposing the surface of the insulating film 147f to the atmosphere after forming the insulating film 147f. By continuously forming the insulating film 147f and the insulating film 149f, attachment of impurities from the atmosphere to the surface of the insulating film 147f can be suppressed. Examples of such impurities include water and organic substances.

[0372] Next, process the insulating film 149f and the insulating film 147f to form the insulating layer 149, the insulating layer 249, the insulating layer 147, and the insulating layer 247 ( Figure 26D)。At this time, the top surface of the conductive layer 112a is exposed in the opening 141, the top surface of the substrate 102 is exposed in the opening 145, and the top surface of the conductive layer 112A is exposed. The insulating layer 147 and the insulating layer 247 can be formed by an anisotropic dry etching method.

[0373] Next, the conductive layer 112A is processed to form the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b ( Figure 27A ).

[0374] Next, a metal oxide film 108f that will become the semiconductor layer 108 and the semiconductor layer 208 is formed ( Figure 27B ). The metal oxide film 108f is disposed in contact with the top and side surfaces of the conductive layer 112b, the top and side surfaces of the insulating layer 147, the top and side surfaces of the insulating layer 149, the top and side surfaces of the insulating layer 247, the top and side surfaces of the insulating layer 249, the top surface of the insulating layer 110, the top surface of the conductive layer 112a, the top and side surfaces of the conductive layer 212a, the top and side surfaces of the conductive layer 212b, and the top surface of the substrate 102.

[0375] Next, a resist mask 159, a resist mask 159a, and a resist mask 159b are formed on the metal oxide film 108f ( Figure 27C and Figure 29A ). The resist mask 159 is disposed in the region where the semiconductor layer 108 is to be formed so as to cover at least the opening 141 and the opening 143. The resist mask 159a is disposed at least in the region where the conductive layer 212a contacts the semiconductor layer 208. The resist mask 159b is disposed at least in the region where the conductive layer 212b contacts the semiconductor layer 208. Note that in Figure 29A , the metal oxide film 108f, the resist mask 159, the resist mask 159a, and the resist mask 159b are hatched. In addition, in order to easily understand the structure below the metal oxide film 108f, the hatching of the metal oxide film 108f is shown in perspective.

[0376] Next, by processing the metal oxide film 108f into an island shape, the semiconductor layer 108 and a semiconductor layer 208A that will become the semiconductor layer 208 are formed ( Figure 27D and Figure 29B ). The semiconductor layer 108 is formed in the region of the metal oxide film 108f covered by the resist mask 159, and the semiconductor layer 208A is formed in the regions covered by the resist mask 159a, the regions covered by the resist mask 159b, and the region in contact with the side surface of the opening 145. Note that in Figure 29B , the semiconductor layer 108 and the semiconductor layer 208A are hatched.

[0377] Next, the resist masks 159, 159a, and 159b are removed.

[0378] Next, a resist mask 157 is formed on the semiconductor layer 108, semiconductor layer 208A, conductive layer 112b, conductive layer 212a, conductive layer 212b, insulating layer 110, and substrate 102 ( Figure 28A and Figure 30A ). The resist mask 157 is disposed so as to cover at least the semiconductor layer 108 and the semiconductor layer 208A in the region that will become the semiconductor layer 208. At this time, the semiconductor layer 208A in the region where the semiconductor layer 208 is not provided is exposed. Note that in Figure 30A , the semiconductor layer 108, semiconductor layer 208A, and resist mask 157 are hatched. In addition, in order to easily understand the structure below the resist mask 157, the structure is shown by seeing through the hatching of the resist mask 157.

[0379] Next, the semiconductor layer 208A in the region not covered by the resist mask 157 is removed to form the semiconductor layer 208.

[0380] Next, the resist mask 157 ( Figure 28B and Figure 30B ) is removed. Note that in Figure 30B , the semiconductor layer 108 and semiconductor layer 208 are hatched.

[0381] Next, an insulating layer 106 is formed so as to cover the semiconductor layer 108, semiconductor layer 208, insulating layer 110, and substrate 102 ( Figure 28C ).

[0382] Next, a film that will become the conductive layer 104 and conductive layer 204 is formed on the insulating layer 106, and the film is processed to form the conductive layer 104 and conductive layer 204 ( Figure 28D ).

[0383] Next, an insulating layer 195 is formed so as to cover the conductive layer 104, conductive layer 204, and insulating layer 106 ( Figure 15B ).

[0384] A semiconductor device according to one embodiment of the present invention can be manufactured by the above-described process.

[0385] At least a part of the structural example shown in this embodiment and the drawings corresponding to the structural example can be appropriately combined with other structural examples or drawings.

[0386] (Embodiment 4) In this embodiment, a display device according to one embodiment of the present invention will be described with reference to FIGS. 31 to Figure 35 .

[0387] The display device of this embodiment can be a high-resolution display device or a large display device. Therefore, for example, the display device of this embodiment can be used as the display unit of the following devices: electronic devices with a large screen such as a television device, a desktop or notebook computer, a monitor for a computer, etc., a digital signage, a large game machine such as a pachinko machine; a digital camera; a digital video camera; a digital photo frame; a mobile phone; a portable game machine; a portable information terminal; a sound reproduction device.

[0388] The display device of this embodiment can be a high-definition display device. Therefore, for example, the display device of this embodiment can be used as the display unit of information terminal devices (wearable devices) such as watch-type and bracelet-type, and the display unit of wearable devices that can be worn on the head such as VR devices such as head-mounted displays (HMDs) and glasses-type AR devices.

[0389] A semiconductor device according to one aspect of the present invention can be used in a display device or a module including the display device. As a module including the display device, there can be mentioned a module in which the display device is mounted with a connector such as a flexible printed circuit board (hereinafter referred to as FPC) or a TCP (Tape Carrier Package), and a module in which an integrated circuit (IC) is mounted by a COG (Chip On Glass) method or a COF (Chip On Film) method, etc.

[0390] The display device of this embodiment can also have the function of a touch panel. For example, various detection elements (which can also be called sensor elements) capable of detecting the approach or contact of a detection object such as a finger can be used for the display device.

[0391] For example, as the sensor method, there can be mentioned a capacitive type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0392] As the capacitive type, for example, there are a surface capacitive type, a projected capacitive type, etc. In addition, as the projected capacitive type, for example, there are a self-capacitive type, a mutual-capacitive type, etc. It is preferable to use the mutual-capacitive type, whereby multi-point detection can be performed simultaneously.

[0393] As a touch panel, for example, there can be mentioned an Out-Cell type, an On-Cell type, and an In-Cell type. Note that the In-Cell type touch panel refers to a structure in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element (also called a display device) and a counter substrate.

[0394] <Structural Example 1> Figure 31A A perspective view showing the display device 50A is presented.

[0395] The display device 50A has a structure in which the bonding substrate 152 and the substrate 151 are bonded. Among them, the substrate 152 is indicated by a dashed line. Figure 31A In [the figure], the substrate 152 is indicated by a dashed line.

[0396] The display device 50A includes a display unit 162, a connection unit 140, a circuit unit 164, a conductive layer 165, and the like. Figure 31A An example in which the display device 50A is mounted with the IC 173 and the FPC 172 is shown. Therefore, the structure shown can also be referred to as a display module including the display device 50A, the IC, and the FPC. Figure 31A The structure shown can also be referred to as a display module including the display device 50A, the IC, and the FPC.

[0397] The connection unit 140 is provided outside the display unit 162. The connection unit 140 can be provided along one or more sides of the display unit 162. The connection unit 140 can also be one or more. Figure 31A An example in which the connection unit 140 is provided so as to surround the four sides of the display unit is shown. In the connection unit 140, the common electrode of the display element is electrically connected to the conductive layer, and a potential can be supplied to the common electrode.

[0398] The circuit unit 164 includes, for example, a scan line driving circuit (also referred to as a gate driver). In addition, the circuit unit 164 can also include both a scan line driving circuit and a signal line driving circuit (also referred to as a source driver).

[0399] The conductive layer 165 has a function of supplying signals and power to the display unit 162 and the circuit unit 164. The signals and power are input to the conductive layer 165 from the outside via the FPC 172 or input to the conductive layer 165 from the IC 173.

[0400] Figure 31A An example in which the IC 173 is provided on the substrate 151 by a COG method or a COF method, etc. is shown. As the IC 173, for example, an IC including one or both of a scan line driving circuit and a signal line driving circuit can be used. Note that the display device 50A and the display module do not necessarily have to be provided with an IC. In addition, the IC can also be mounted on the FPC by a COF method or the like.

[0401] One aspect of the semiconductor device of the present invention can be used, for example, in one or both of the display unit 162 and the circuit unit 164 of the display device 50A. The channel formation region of the transistor included in the display device is preferably formed of an oxide semiconductor (OS). By using an OS transistor, a display device with low power consumption can be achieved. In addition, one aspect of the semiconductor device of the present invention can be used in both the display unit 162 and the circuit unit 164, that is, all the transistors included in the display device are OS transistors. In this way, by using OS transistors as all the transistors included in the display device, the effect of reducing the manufacturing cost can be achieved.

[0402] For example, when one aspect of the semiconductor device of the present invention is used in the pixel circuit of the display device, the occupied area of the pixel circuit can be reduced, and a high-definition display device can be achieved. In addition, for example, when one aspect of the semiconductor device of the present invention is used in the drive circuit of the display device (for example, one or both of the gate line drive circuit and the source line drive circuit), the occupied area of the drive circuit can be reduced, and a narrow-bezel display device can be achieved. In addition, one aspect of the semiconductor device of the present invention has good electrical characteristics, and by using this semiconductor device in the display device, the reliability of the display device can be improved.

[0403] The display unit 162 is an image display area in the display device 50A, and includes a plurality of pixels 210 arranged periodically. Figure 31A An enlarged view of one pixel 210 is shown.

[0404] There is no particular limitation on the arrangement of the pixels in the display device of the present embodiment, and various methods can be adopted. As the arrangement of the pixels, for example, stripe arrangement, S stripe arrangement, matrix arrangement, Delta arrangement, Bayer arrangement, and Pentile arrangement can be cited.

[0405] Figure 31A The pixel 210 shown includes a sub-pixel 230R that emits red light, a sub-pixel 230G that emits green light, and a sub-pixel 230B that emits blue light. By using the pixel 230R, the pixel 230G, and the pixel 230B to form one pixel 210, full-color display can be achieved. The pixel 230R, the pixel 230G, and the pixel 230B are all used as sub-pixels. In addition, in Figure 31A The display device 50A shown shows an example in which the pixels 230 used as sub-pixels are arranged in a stripe pattern. The number of sub-pixels constituting one pixel 210 is not limited to three, and may be four or more. For example, it may also include four sub-pixels that emit light of R, G, B, and white (W). Alternatively, it may also include four sub-pixels that emit four kinds of light of R, G, B, and Y.

[0406] The pixel 230R, the pixel 230G, and the pixel 230B each include a display element and a circuit for controlling the driving of the display element.

[0407] As the display element, various elements can be used. For example, a liquid crystal element (also referred to as a liquid crystal device) and a light-emitting device can be cited. In addition to these, MEMS (Micro Electro Mechanical Systems) elements of a shutter type or an optical interference type, display elements using a microcapsule method, an electrophoresis method, an electro-wetting method, or an electrophoretic display (registered trademark) method, etc. can also be used. Further, a QLED (Quantum-dot LED) using a light source and a color conversion technology employing a quantum dot material can also be used.

[0408] As a display device using a liquid crystal element, for example, a transmissive liquid crystal display device, a reflective liquid crystal display device, and a transflective liquid crystal display device can be cited.

[0409] As modes applicable to a display device using a liquid crystal element, for example, a vertical alignment (VA) mode, a fringe field switching (FFS) mode, an in-plane switching (IPS) mode, a twisted nematic (TN) mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, an electrically controlled birefringence (ECB) mode, and a guest-host mode can be cited. As the VA mode, for example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, and an advanced super view (ASV) mode can be cited.

[0410] As a liquid crystal material that can be used for liquid crystal elements, for example, thermotropic liquid crystals, low-molecular liquid crystals, high-molecular liquid crystals, polymer-dispersed liquid crystals (PDLC: Polymer Dispersed Liquid Crystal), polymer-network liquid crystals (PNLC: Polymer Network Liquid Crystal), ferroelectric liquid crystals, and antiferroelectric liquid crystals can be cited. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, a blue phase, etc. depending on conditions. In addition, as the liquid crystal material, either a positive-type liquid crystal or a negative-type liquid crystal can be used, and it can be selected according to the mode or design used.

[0411] As a light-emitting device, for example, self-luminous light-emitting devices such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers can be cited. As an LED, for example, a small-sized LED, a micro-LED, etc. can be used.

[0412] As a light-emitting substance contained in the light-emitting device, for example, a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material), and an inorganic compound (quantum dot material, etc.) can be cited.

[0413] The light-emitting color of the light-emitting device can be infrared, red, green, blue, cyan, magenta, yellow, white, etc. In addition, when the light-emitting device has a microcavity structure, the color purity can be further improved.

[0414] In a pair of electrodes included in the light-emitting device, one electrode is used as an anode and the other electrode is used as a cathode.

[0415] The display device according to one embodiment of the present invention can also adopt any one of the following structures: a top emission type that emits light in a direction opposite to the substrate on which the light-emitting device is formed, a bottom emission type that emits light toward the side of the substrate on which the light-emitting device is formed, and a dual emission type that emits light on both sides.

[0416] In the present embodiment, the case where a light-emitting device is used as a display element is mainly described as an example.

[0417] Figure 31BIt is a block diagram showing a display device 50A. The display device 50A includes a display unit 162 and a circuit unit 164. The display unit 162 includes a plurality of pixels 230 arranged periodically (pixel 230[1,1] to pixel 230[m,n], where m and n are each independently an integer of 2 or more). The circuit unit 164 includes a first drive circuit unit 231 and a second drive circuit unit 232.

[0418] The circuits included in the first drive circuit unit 231 are used, for example, as a scan line drive circuit. The circuits included in the second drive circuit unit 232 are used, for example, as a signal line drive circuit. Note that a certain circuit may be provided at a position facing the first drive circuit unit 231 with the display unit 162 interposed therebetween. A certain circuit may be provided at a position facing the second drive circuit unit 232 with the display unit 162 interposed therebetween.

[0419] As the circuit unit 164, various circuits such as a shift register circuit, a level converter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexing circuit, and a logic circuit can be used. Transistors and capacitor elements can be used in the circuit unit 164. The transistors included in the circuit unit 164 can also be formed by the same process as the transistors included in the pixel 230.

[0420] The display device 50A includes wirings 236 and 238 arranged substantially in parallel. The potential of the wiring 236 is controlled by the circuits included in the first drive circuit unit 231, and the potential of the wiring 238 is controlled by the circuits included in the second drive circuit unit 232. In Figure 31B an example in which the wirings 236 and 238 are connected to the pixel 230 is shown. However, the wirings 236 and 238 are just an example, and the wirings connected to the pixel 230 are not limited to the wirings 236 and 238.

[0421] A semiconductor device according to one embodiment of the present invention can form a VFET having a channel length in the submicron range and a large on-state current and a VLFET having a long channel length and high saturation using some processes in common. An oxide semiconductor (OS) is suitably used in the channel formation regions of these transistors, and transistors with a small off-state current can be realized. A semiconductor device according to one embodiment of the present invention is suitable for use in one or both of the display unit 162 and the circuit unit 164. In addition, the semiconductor device according to one embodiment of the present invention can be used for both the display unit 162 and the circuit unit 164, that is, all the transistors included in the display device are OS transistors. Thus, by using OS transistors as all the transistors included in the display device, the effect of reducing the manufacturing cost can be achieved.

[0422] <Structural Example 2> As a circuit that can be used in the circuit unit 164, the structural example will be described by taking a latch circuit as an example.

[0423] Figure 32A This is a circuit diagram showing an example of the structure of the latch circuit LAT. Figure 32A The latch circuit LAT shown includes transistor Tr31, transistor Tr33, transistor Tr35, transistor Tr36, capacitor element C31, and inverter circuit INV. In Figure 32A it, the node that electrically connects one of the source and drain of transistor Tr33, the gate of transistor Tr35, and one electrode of capacitor element C31 is referred to as node N.

[0424] In Figure 32A the latch circuit LAT shown, when a high-potential signal is input to terminal SMP, transistor Tr33 becomes in an on state. Therefore, the potential of node N becomes a potential corresponding to the potential of terminal ROUT, and the data corresponding to the signal input to the latch circuit LAT from terminal ROUT is written into the latch circuit LAT. After writing data into the latch circuit LAT, by making the potential of terminal SMP become a low potential, transistor Tr33 becomes in an off state. Therefore, the potential of node N is held, and the data written into the latch circuit LAT is held. Specifically, for example, when the potential of node N is a low potential, the latch circuit LAT can hold the data of "0", and when the potential of node N is a high potential, the latch circuit LAT can hold the data of "1".

[0425] Transistor Tr33 preferably uses a transistor with a small off-state current. Transistor Tr33 is suitably an OS transistor. Therefore, the latch circuit LAT can hold data for a long period. Therefore, the frequency of writing data into the latch circuit LAT again can be reduced.

[0426] In this specification and the like, sometimes "writing the data that makes the signal input from terminal SP2 output to terminal LIN into the latch circuit LAT" is simply referred to as "writing data into the latch circuit LAT". That is to say, for example, sometimes "writing the data of '1' into the latch circuit LAT" is simply referred to as "writing data into the latch circuit LAT".

[0427] In the latch circuit LAT, a semiconductor device according to one aspect of the present invention is suitably used. For example, as one or more of transistor Tr31, transistor Tr33, transistor Tr35, and transistor Tr36, transistor 100 or transistor 200 shown in Figure 12B etc. can be used.

[0428] Figure 32B Shows an example of the structure of the inverter circuit INV. The inverter circuit INV includes transistor Tr41, transistor Tr43, transistor Tr45, transistor Tr47, and capacitor element C41.

[0429] When the latch circuit LAT has Figure 32A the structure shown and the inverter circuit INV has Figure 32B the structure shown, all the transistors in the latch circuit LAT are transistors of the same polarity, for example, n-channel transistors. Thus, for example, in addition to the transistor Tr33, the transistors Tr31, Tr35, Tr36, Tr41, Tr43, Tr45, and Tr47 can also be OS transistors. Therefore, all the transistors in the latch circuit LAT can be manufactured by the same process.

[0430] In the inverter circuit INV, a semiconductor device according to one aspect of the present invention is suitably used. For example, as one or more of the transistors Tr41, Tr43, Tr45, and Tr47, the Figure 12B transistor 100 or transistor 200 shown, etc., can be used.

[0431] As the transistors required to have high saturation, one or more of the transistors 20 to 20B, and transistors 200 to 200E are suitably used. In addition, as the transistors required to have a large on-state current, one or more of the transistors 100 to 100B are suitably used. Thus, a high-performance display device can be realized. Furthermore, the occupied area can be reduced, and thus a narrow-bezel display device can be realized.

[0432] <Structural Example 3> Figure 33A Shows a structural example of the pixel 230. The pixel 230 includes a pixel circuit 51 and a light-emitting device 61.

[0433] Figure 33A The pixel circuit 51 shown includes a transistor 52A, a transistor 52B, and a capacitor element 53. The pixel circuit 51 is a 2Tr1C type pixel circuit including two transistors and one capacitor element. Note that there is no particular limitation on the pixel circuit applicable to one aspect of the present invention.

[0434] The anode of the light-emitting device 61 is electrically connected to one of the source and drain of the transistor 52B and one electrode of the capacitor element 53. The other of the source and drain of the transistor 52B is electrically connected to the wiring ANO. The gate of the transistor 52B is electrically connected to one of the source and drain of the transistor 52A and the other electrode of the capacitor element 53. The other of the source and drain of the transistor 52A is electrically connected to the wiring GL. The gate of the transistor 52A is electrically connected to the wiring GL. The cathode of the light-emitting device 61 is electrically connected to the wiring VCOM.

[0435] The wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 238. The wiring VCOM is a wiring for supplying a potential for supplying current to the light-emitting device 61. The transistor 52A has a function of controlling the conduction state or non-conduction state between the wiring SL and the gate of the transistor 52B according to the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

[0436] The transistor 52B has a function of controlling the amount of current flowing through the light-emitting device 61. The capacitor element 53 has a function of holding the gate potential of the transistor 52B. The intensity of the light emitted by the light-emitting device 61 is controlled according to the image signal supplied to the gate of the transistor 52B.

[0437] A part or all of the transistors included in the pixel circuit 51 may also be provided with a back gate. Figure 33A The pixel circuit 51 shown shows a structure in which the transistor 52B includes a back gate and the back gate is electrically connected to one of the source and drain of the transistor 52B. In addition, the back gate of the transistor 52B may also be electrically connected to the gate of the transistor 52B.

[0438] The above semiconductor device can be applied to the pixel circuit 51. Preferably, the saturation of the transistor 52B, which is a driving transistor for controlling the current flowing through the light-emitting device 61, is higher than that of the transistor 52A, which is a selection transistor for controlling the selection state of the pixel 230. By using one of the transistors 20 to 20B and transistors 200 to 200E with a long channel length as the transistor 52B, a display device with high reliability can be provided. In addition, by using one of the transistors 100 to 100B as the transistor 52A, the occupied area of the pixel circuit 51A can be reduced, and thus a high-definition display device can be realized.

[0439] Note that the transistor 100 may also be used as the transistor 52B. By using a transistor with a short channel length as the transistor 52B, a display device with high brightness can be realized. In addition, the occupied area of the pixel circuit 51 can be reduced, and thus a high-definition display device can be realized.

[0440] Figure 33A Shows a structure example different from Figure 33B the pixel 230 shown. The pixel 230 includes a pixel circuit 51A and a light-emitting device 61.

[0441] Figure 33B The pixel circuit 51A shown is different from Figure 33AThe main difference of the pixel circuit 51 shown is that it includes a transistor 52C. The pixel circuit 51A includes a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor element 53. The pixel circuit 51A is a 3Tr1C type pixel circuit including three transistors and one capacitor element.

[0442] One of the source and drain of the transistor 52C is electrically connected to the other of the source and drain of the transistor 52B. The other of the source and drain of the transistor 52C is electrically connected to the wiring V0. For example, the wiring V0 is supplied with a reference potential. The gate of the transistor 52C is electrically connected to the wiring GL.

[0443] The transistor 52C has a function of controlling the conduction state or non-conduction state between one of the source and drain of the transistor 52B and the wiring V0 according to the potential of the wiring GL. According to the reference potential of the wiring V0 supplied through the transistor 52C, the unevenness of the gate-source potential of the transistor 52B can be suppressed.

[0444] In addition, a current value available for setting pixel parameters can be obtained using the wiring V0. Specifically, the wiring V0 can be used as a monitoring line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting device 61 to the outside. The current output to the wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Or, it can be converted into a digital signal by an AD converter or the like and output to the outside.

[0445] The above semiconductor device can be applied to the pixel circuit 51A. By using one of the transistors 20 to 20B, 200 to 200E with a long channel length as the transistor 52B, a display device with high reliability can be provided. In addition, by using one of the transistors 100 to 100B as the transistors 52A and 52C, the occupied area of the pixel circuit 51A can be reduced, and thus a high-definition display device can be realized. Note that one of the transistors 100 to 100B can also be used as the transistor 52B.

[0446] Figure 33C An example of the structure of the pixel circuit 51 is shown. Figure 33C It is a cross-sectional view of the pixel circuit 51. Figure 33C The abstract shows the pixel electrodes included in the transistor 52A, the transistor 52B, and the light-emitting device 61. Note that the electrical connection between the transistor 52A and the transistor 52B is omitted.

[0447] Transistor 52A includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. Transistor 52B includes an insulating layer 106, a semiconductor layer 208, a conductive layer 204, a conductive layer 212a, and a conductive layer 212b. Since transistors 52A and 52B can be referred to the above description, detailed descriptions thereof are omitted.

[0448] Transistors 52A and 52B are disposed on a substrate 102. Figure 33C A structure is shown in which an insulating layer 121 and an insulating layer 123 are provided between transistors 52A and 52B and the substrate 102. Note that the semiconductor layer 108 of transistor 52A is disposed on the conductive layer 112a, and the semiconductor layer 208 of transistor 52B is disposed on the insulating layer 123. Thus, by disposing the semiconductor layers of the two transistors in different layers, transistors having different structures can be easily manufactured on the same substrate.

[0449] The insulating layer 121 preferably has a hydrogen barrier property, and particularly preferably has a high ability to capture or fix (getter) hydrogen. The insulating layer 121 is, for example, suitably made of a material that can be used for the insulating layer 149 and the insulating layer 249. The insulating layer 121 is, for example, suitably made of hafnium oxide. The insulating layer 123 disposed on the insulating layer 121 is, for example, suitably made of a material that can be used for the insulating layer 110. The insulating layer 123 is, for example, suitably made of silicon oxide.

[0450] An insulating layer 195 is provided to cover transistors 52A, 52B, and a capacitor element 53. An insulating layer 233 is provided to cover the insulating layer 195. An insulating layer 235 is provided to cover the insulating layer 233. A light-emitting device 61 can be provided on the insulating layer 235. Figure 33C A pixel electrode 111 serving as one electrode of the light-emitting device 61 is shown. The insulating layer 195 and the insulating layer 233 have a first opening reaching the conductive layer 212a, and a conductive layer 234 is provided to cover the first opening. The conductive layer 234 is electrically connected to the conductive layer 212a through the first opening. The insulating layer 235 has a second opening reaching the conductive layer 234, and the pixel electrode 111 is provided to cover the second opening. The pixel electrode 111 is electrically connected to the conductive layer 234 through the second opening. The insulating layer 195 can be referred to the above description, and thus detailed descriptions thereof are omitted. The insulating layer 233 and the insulating layer 235 have a function of reducing the unevenness caused by transistors 52A, 52B, and 52C to make the formation surface of the light-emitting device 61 flatter. In addition, in this specification and the like, the insulating layer 233 and the insulating layer 235 are sometimes referred to as a planarization layer.

[0451] The insulating layer 233 and the insulating layer 235 preferably use an organic insulating film. As materials that can be used for the organic insulating film, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimide amide resin, silicone resin, benzocyclobutene resin, phenolic resin, and precursors of these resins can be used. The insulating layer 235 can also adopt a laminated structure of an organic insulating film and an inorganic insulating film. The insulating layer 235 preferably has a laminated structure of an organic insulating film and an inorganic insulating film on the organic insulating film. Thus, the inorganic insulating film can be used as an etching protection layer when forming the light-emitting device 61. Specifically, it is possible to suppress a part of the insulating layer 235 from being etched when forming the pixel electrode 111 and forming a recess in the insulating layer 235. Alternatively, a recess can be provided in the insulating layer 235 when forming the pixel electrode 111. Similarly, the insulating layer 233 can also adopt a laminated structure of an organic insulating film and an inorganic insulating film.

[0452] Although Figure 33C shows a structure in which the transistor 200 shown in Figure 12A etc. is used for the transistor 52B, one aspect of the present invention is not limited thereto. As Figure 34 shown, the transistor 200A shown in Figure 15A etc. can also be used for the transistor 52B.

[0453] <Structural Example 4> Figure 35 shows a structural example different from the above example. In the display device 50B, a pixel circuit, a driving circuit, etc. are provided on the substrate 310. The display device 50B includes an element layer 71, an element layer 73, an element layer 75, and a wiring layer 77. The wiring layer 77 is a layer provided with wirings.

[0454] The element layer 71 includes the substrate 310, and a transistor 300 is formed on the substrate 310. In addition, a wiring layer 77 is provided above the transistor 300, and the wiring layer 77 is provided with wirings for electrically connecting the transistor 300, the transistor MTCK, the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B. In addition, an element layer 73 and an element layer 75 are provided above the wiring layer 77, and the element layer 73 includes the transistor MTCK etc. The element layer 75 includes the light-emitting device 130 ( Figure 35 the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B in

[0455] The transistor 300 can be a transistor included in the element layer 71. In addition, the transistor MTCK can be a transistor included in the element layer 73. In addition, the light-emitting device 130 can be a light-emitting device included in the element layer 75.

[0456] As the transistor MTCK, it is suitable to use one of the above-described transistors 20 to 20B, or transistors 200 to 200E. Alternatively, as the transistor MTCK, one of transistors 100 to 100B may also be used.

[0457] As the substrate 310, for example, a semiconductor substrate (e.g., a single crystal substrate made of silicon or germanium) can be used. In addition, as the substrate 310, in addition to the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate including a stainless steel foil, a tungsten substrate, a substrate including a tungsten foil, a flexible substrate, a laminated film, a paper or a base film including fibrous materials can also be used. In the present embodiment, the case where the substrate 310 is a semiconductor substrate containing silicon as a material will be described. Therefore, the transistors included in the element layer 71 can be silicon-containing transistors (also referred to as Si transistors).

[0458] The transistor 300 includes an element isolation layer 312, a conductive layer 316, an insulating layer 315, an insulating layer 317, a semiconductor region 313 formed of a part of the substrate 310, a low-resistance region 314a serving as a source region or a drain region, and a low-resistance region 314b. Therefore, the transistor 300 uses an Si transistor. Note that Figure 35 A structure in which one of the source and the drain of the transistor 300 is electrically connected to the conductive layers 328, 330, 356, and 514 through the conductive layer 328 is shown, but the electrical connection structure of the semiconductor device according to one aspect of the present invention is not limited thereto. For example, a display device according to one aspect of the present invention may also adopt a structure in which the gate of the transistor 300 is electrically connected to the conductive layer 514 through the conductive layer 328.

[0459] The transistor 300 can achieve a Fin type structure, for example, by adopting a structure in which the top surface and the side surfaces in the channel width direction of the semiconductor region 313 are covered with the conductive layer 316 with the insulating layer 315 serving as a gate insulating layer interposed therebetween. By forming the Fin type transistor 300, the effective channel width can be increased, so that the on-state characteristics of the transistor 300 can be improved. In addition, since the influence of the electric field of the gate electrode can be increased, the off-state characteristics of the transistor 300 can be improved. For example, the transistor 300 may also have a planar structure without a Fin type structure.

[0460] The transistor 300 can be a p-channel transistor or an n-channel transistor. In addition, a plurality of transistors 300 may be provided, and both p-channel type transistors and n-channel type transistors may be used.

[0461] The channel formation region of the semiconductor region 313, the region near it, the low-resistance regions 314a and 314b used as the source region or the drain region preferably contain a silicon-based semiconductor, and specifically preferably contain single-crystalline silicon. Alternatively, each of the above regions may be formed of, for example, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride. Silicon that applies stress to the lattice and changes the lattice plane spacing to control the effective mass can be used. In addition, the transistor 300 may be, for example, a HEMT (High Electron Mobility Transistor) using gallium arsenide and aluminum gallium arsenide.

[0462] As the conductive layer 316 used as the gate electrode, a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic or phosphorus or an element that imparts p-type conductivity such as boron or aluminum can be used. Alternatively, as the conductive layer 316, for example, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

[0463] In addition, since the material of the conductor determines the work function, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, as the conductor, a material of one or both of titanium nitride and tantalum nitride is preferably used. In order to have both conductivity and embedding properties, a laminate of a metal material of one or both of tungsten and aluminum is preferably used as the conductor, and tungsten is particularly preferably used in terms of heat resistance.

[0464] In order to separate the multiple transistors formed on the substrate 310 from each other, an element isolation layer 312 is provided. The element isolation layer can be formed, for example, by the LOCOS (Local Oxidation of Silicon) method, the STI (Shallow Trench Isolation) method, or the mesa isolation method.

[0465] Figure 35 An insulating layer 320 and an insulating layer 322 are sequentially stacked on the transistor 300 shown from the substrate 310 side.

[0466] As the insulating layer 320 and the insulating layer 322, for example, one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride can be used.

[0467] The insulating layer 322 can also be used as a planarization film for planarizing the steps generated by the transistor 300 and the like covered by the insulating layer 320 and the insulating layer 322. For example, in order to improve the flatness of the top surface of the insulating layer 322, planarization can also be achieved by a planarization process using the chemical mechanical polishing (CMP) method.

[0468] A conductive layer 328 that is connected to transistors MTCK etc. disposed above the insulating layer 322 is embedded in the insulating layer 320 and the insulating layer 322. In addition, the conductive layer 328 has the function of a plug or a wiring. Therefore, the conductive layer 328 can use the material that can be used for the conductive layer MPG.

[0469] In the display device 50B, a wiring layer 77 is disposed on the transistor 300. For example, the wiring layer 77 includes an insulating layer 324, an insulating layer 326, a conductive layer 330, an insulating layer 350, an insulating layer 352, an insulating layer 354, and a conductive layer 356.

[0470] The insulating layer 324 and the insulating layer 326 are sequentially stacked on the insulating layer 322 and the conductive layer 328. In addition, openings are formed in the insulating layer 324 and the insulating layer 326 in a region overlapping with the conductive layer 328. In addition, the conductive layer 330 is embedded in the openings.

[0471] The insulating layer 350, the insulating layer 352, and the insulating layer 354 may be sequentially stacked on the insulating layer 326 and the conductive layer 330. In addition, openings are formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354 in a region overlapping with the conductive layer 330. In addition, the conductive layer 356 is embedded in the openings.

[0472] The conductive layer 330 and the conductive layer 356 have, for example, the function of a plug or a wiring connected to the transistor 300. In addition, the conductive layer 330 and the conductive layer 356 can be formed using the same material as the above-mentioned conductive layer 328 or the conductive layer 596.

[0473] For example, the insulating layer 324 and the insulating layer 350 are preferably made of an insulator that has a barrier property against one or more of hydrogen, oxygen, and water. In addition, similar to the insulating layer 594, the insulating layer 326, the insulating layer 352, and the insulating layer 354 are preferably made of an insulator with a relatively low relative permittivity to reduce the parasitic capacitance generated between wirings. In addition, the insulating layer 326, the insulating layer 352, and the insulating layer 354 are used as an interlayer insulating film and a planarization film. In addition, the conductive layer 330 and the conductive layer 356 preferably include a conductor that has a barrier property against one or more of hydrogen, oxygen, and water.

[0474] Note that, as a conductor having a hydrogen barrier property, tantalum nitride is preferably used, for example. In addition, by laminating tantalum nitride and tungsten with high conductivity, the diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity as a wiring. At this time, the tantalum nitride layer having a barrier property against hydrogen preferably contacts the insulating layer 350 having a barrier property against hydrogen.

[0475] An insulating layer 512 is provided above the insulating layer 354 and the conductive layer 356. An insulating layer IS1 is provided on the insulating layer 512, and an insulating layer IS2 is provided on the insulating layer IS1. In addition, a conductive layer 514 serving as a plug or a wiring is embedded in the insulating layer IS2, the insulating layer IS1, and the insulating layer 512. Thus, one of the source and drain of the transistor MTCK is electrically connected to one of the source and drain of the transistor 300. In addition, the conductive layer 514 can use, for example, a material that can be used for the conductive layer MPG.

[0476] A transistor MTCK is provided on the insulating layer IS1 and the conductive layer 514. In addition, an insulating layer 574 is formed on the transistor MTCK, and an insulating layer 581 is formed on the insulating layer 574. In addition, a conductive layer MPG serving as a plug or a wiring is embedded in the insulating layer IS3, the insulating layer 574, and the insulating layer 581. Regarding the insulating layer, the conductive layer, and the semiconductor layer around the transistor MTCK, refer to Embodiment 2.

[0477] An insulating layer IS3 is formed above the transistor MTCK. In addition, the insulating layer 574 and the insulating layer 581 are sequentially stacked on the insulating layer IS3.

[0478] The insulating layer 574 preferably has a function of suppressing the diffusion of impurities such as water and hydrogen (for example, one or both of hydrogen atoms and hydrogen molecules). In other words, the insulating layer 574 is preferably used as a barrier insulating film that suppresses the mixing of the impurities into the transistor MTCK. In addition, the insulating layer 574 preferably has a function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules). For example, the oxygen permeability of the insulating layer 574 is preferably lower than that of the insulating layer IS2 and the insulating layer IS3.

[0479] Therefore, the insulating layer 574 is preferably used as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen. Therefore, the insulating layer 574 preferably uses an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N2O, NO, and NO2), and copper atoms (not easily allowing the above impurities to pass through). Or, it is preferably used an insulating material having a function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules) (not easily allowing the above oxygen to pass through).

[0480] As an insulator having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, for example, a single layer or a laminate of an insulator containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used. Specifically, as an insulator having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, for example, metal oxides such as alumina, magnesia, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be cited. In addition, as an insulator having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, for example, an oxide containing aluminum and hafnium (hafnium aluminate) can be cited. In addition, as an insulator having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, for example, metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon oxynitride, and silicon nitride can be cited.

[0481] Particularly preferably, alumina or silicon nitride is used as the insulating layer 574. Thereby, diffusion of impurities such as water and hydrogen from above the insulating layer 574 to the transistor MTCK can be suppressed. Or, diffusion of oxygen contained in the insulating layer IS3 or the like to above the insulating layer 574 can be suppressed.

[0482] The insulating layer 581 is preferably used as an interlayer film and has a lower dielectric constant than the insulating layer 574. By using a material having a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, the relative dielectric constant of the insulating layer 581 is preferably less than 4, more preferably less than 3. For example, the relative dielectric constant of the insulating layer 581 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulating layer 574. By using a material having a low dielectric constant for the insulating layer 581 used as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0483] The concentration of impurities such as water and hydrogen in the insulating layer 581 is preferably reduced. At this time, as the insulating layer 581, for example, silicon oxide, silicon oxynitride, silicon oxynitride, or silicon nitride can be used. In addition, as the insulating layer 581, for example, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride have thermal stability, so they are preferred. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferred because they easily form regions containing oxygen that is released by heating. In addition, a resin can be used as the insulating layer 581. In addition, the above materials can be appropriately combined as the materials that can be used for the insulating layer 581.

[0484] An insulating layer 592 and an insulating layer 594 are sequentially stacked on the insulating layer 574 and the insulating layer 581.

[0485] The insulating layer 592 preferably uses a barrier insulating film (referred to as a barrier insulating film) that prevents impurities such as water and hydrogen from diffusing from the substrate 310 and the transistor MTCK to the area above the insulating layer 592 (for example, the area where the light-emitting devices 130R, 130G, and 130B are provided). Therefore, the insulating layer 592 preferably uses an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (not easily allowing the above impurities to pass through). In addition, depending on the situation, the insulating layer 592 preferably uses an insulating material having a function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N2O, NO, and NO2), and copper atoms (not easily allowing the above oxygen to pass through). Or, it preferably has a function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules).

[0486] As a film having hydrogen barrier properties, for example, silicon nitride formed by CVD can be used.

[0487] The amount of hydrogen desorption can be analyzed, for example, by thermal desorption spectrometry (TDS: Thermal Desorption Spectrometry). For example, in the range where the film surface temperature in TDS is from 50 °C to 500 °C, when the desorption amount of hydrogen atoms is converted to the amount per unit area of the insulating layer 324, the desorption amount of hydrogen in the insulating layer 324 is 10×10 15 atoms / cm 2 Hereinafter, it is preferably 5×10 15 atoms / cm 2 Hereinafter, it is sufficient.

[0488] Similar to the insulating layer 581, the insulating layer 594 is preferably an interlayer film with a low dielectric constant. Therefore, the insulating layer 594 can use the materials that can be used for the insulating layer 581.

[0489] In addition, the dielectric constant of the insulating layer 594 is preferably lower than that of the insulating layer 592. For example, the relative dielectric constant of the insulating layer 594 is preferably less than 4, more preferably less than 3. In addition, for example, the relative dielectric constant of the insulating layer 594 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulating layer 592. By using an interlayer film of a material with a low dielectric constant as the insulating layer 594, the parasitic capacitance generated between wirings can be reduced.

[0490] The conductive layers MPG used as plugs or wirings are embedded in the insulating layer GI1 and the insulating layer IS3, and the conductive layer 596 used as a plug or a wiring is embedded in the insulating layer 592 and the insulating layer 594. In particular, the conductive layer MPG and the conductive layer 596 are electrically connected to light-emitting devices and the like provided above the insulating layer 594. Note that sometimes the same reference numeral is used to denote a plurality of conductive layers used as plugs or wirings. In addition, in this specification and the like, a wiring and a plug connected to the wiring may also be one component. That is, a part of the conductive layer is sometimes used as a wiring, and a part of the conductive layer is sometimes used as a plug.

[0491] As materials for the respective plugs and wirings (the conductive layer MPG and the conductive layer 596), a single layer or a laminate of one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials can be used. High melting point materials such as tungsten or molybdenum having both heat resistance and conductivity are preferably used, and tungsten is preferably used. In addition, a low-resistance conductive material such as aluminum or copper is preferably used to form. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0492] The insulating layer 598 and the insulating layer 599 are sequentially formed on the insulating layer 594 and the conductive layer 596.

[0493] Similar to the insulating layer 592, the insulating layer 598 preferably uses an insulator having a barrier property against one or more of hydrogen, oxygen, and water. In addition, similar to the insulating layer 594, the insulating layer 599 preferably uses an insulator having a relatively low relative dielectric constant to reduce the parasitic capacitance generated between wirings. In addition, the insulating layer 599 is used as an interlayer insulating film and a planarization film.

[0494] The light-emitting device 130 and the connection portion 140 are formed on the insulating layer 599.

[0495] The connection portion 140 is sometimes referred to as a cathode contact portion and is electrically connected to the cathode electrodes of each of the light-emitting devices 130R, 130G, and 130B. In Figure 35 it, the connection portion 140 includes: one or more conductive layers selected from the conductive layers 182a to 182c; at least one conductive layer of the conductive layers 126a to 126c; one or more conductive layers selected from the conductive layers 129a to 129c; the common layer 114; and the common electrode 115.

[0496] The connection portion 140 can be provided so as to surround the four sides of the display portion when viewed from a plane, or can be provided within the display portion (for example, between adjacent light-emitting devices 130) (not shown).

[0497] The light-emitting device 130R includes a conductive layer 182a, a conductive layer 126a on the conductive layer 182a, and a conductive layer 129a on the conductive layer 126a. The conductive layer 182a, the conductive layer 126a, and the conductive layer 129a can all be referred to as pixel electrodes, or a part of the conductive layer 182a, the conductive layer 126a, and the conductive layer 129a can be referred to as pixel electrodes. In addition, the light-emitting device 130G includes a conductive layer 182b, a conductive layer 126b on the conductive layer 182b, and a conductive layer 129b on the conductive layer 126b. Similar to the light-emitting device 130R, the conductive layer 182b, the conductive layer 126b, and the conductive layer 129b can all be referred to as pixel electrodes, or a part of the conductive layer 182b, the conductive layer 126b, and the conductive layer 129b can be referred to as pixel electrodes. In addition, the light-emitting device 130B includes a conductive layer 182c, a conductive layer 126c on the conductive layer 182c, and a conductive layer 129c on the conductive layer 126c. Similar to the light-emitting device 130R and the light-emitting device 130G, the conductive layer 182c, the conductive layer 126c, and the conductive layer 129c can all be referred to as pixel electrodes, or a part of the conductive layer 182c, the conductive layer 126c, and the conductive layer 129c can be referred to as pixel electrodes.

[0498] As the conductive layers 182a to 182c and the conductive layers 126a to 126c, for example, a conductive layer used as a reflective electrode can be used. As the conductive layer used as a reflective electrode, for example, a conductive layer having a high reflectivity to visible light such as silver, aluminum, an alloy film composed of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu (APC) film), etc. can be used. In addition, the conductive layers 182a to 182c and the conductive layers 126a to 126c can, for example, use a stacked film of aluminum sandwiched by a pair of titaniums (a film in which Ti, Al, and Ti are stacked in sequence), a stacked film of silver sandwiched by a pair of indium tin oxides (a film in which ITO, Ag, and ITO are stacked in sequence).

[0499] For example, as the conductive layers 182a to 182c, a conductive layer used as a reflective electrode can also be used, and as the conductive layers 126a to 126c, a material with high translucency can be used. As the material with high translucency, for example, an alloy of silver and magnesium; and indium tin oxide can be cited.

[0500] As the conductive layers 129a to 129c, for example, a conductive layer used as a transparent electrode can be used. As the conductive layer used as a transparent electrode, for example, the above-mentioned conductive layer with high translucency can be used.

[0501] The light-emitting device 130, which will be described in detail later, may also adopt a microcavity structure (micro resonator structure). The microcavity structure refers to a structure in which the distance between the bottom surface of the light-emitting layer and the top surface of the lower electrode is the thickness corresponding to the wavelength of the color of the light emitted from the light-emitting layer. In this case, preferably, the conductive layers 129a to 129c as the upper electrode (common electrode) are made of a conductive material having light transmittance and light reflectivity, and the conductive layers 182a to 182c and the conductive layers 126a to 126c as the lower electrode (pixel electrode) are made of a conductive material having light reflectivity.

[0502] The microcavity structure refers to a structure in which the optical distance between the lower electrode and the light-emitting layer is adjusted to (2n - 1)λ / 4 (note that n is an integer of 1 or more, and λ is the wavelength of the light to be amplified). Therefore, the light reflected by the lower electrode (reflected light) and the light directly incident on the upper electrode from the light-emitting layer (incident light) interfere significantly. As a result, the phases of the reflected lights of wavelength λ and the incident light can be made consistent, and thus the light emitted from the light-emitting layer can be further amplified. On the other hand, when the reflected light and the incident light are other than wavelength λ, the phases are inconsistent, resulting in attenuation and no resonance.

[0503] The conductive layer 182a is connected to the conductive layer 596 embedded in the insulating layer 594 through an opening provided in the insulating layer 599. In addition, the end of the conductive layer 126a is located outside the end of the conductive layer 182a. The end of the conductive layer 126a is aligned or substantially aligned with the end of the conductive layer 129a.

[0504] The conductive layers 182b, 126b, 129b in the light-emitting device 130G and the conductive layers 182c, 126c, 129c in the light-emitting device 130B are the same as the conductive layers 182a, 126a, 129a in the light-emitting device 130R, so the detailed description is omitted.

[0505] Recesses are formed in the conductive layers 182a, 182b, and 182c to cover the openings provided in the insulating layer 599. In addition, the layer 128 is embedded in the recesses.

[0506] The layer 128 has a function of flattening the recesses of the conductive layers 182a to 182c. The conductive layers 126a to 126c electrically connected to the conductive layers 182a to 182c are provided on the conductive layers 182a to 182c and the layer 128. Therefore, the region overlapping with the recesses of the conductive layers 182a to 182c can also be used as a light-emitting region, thereby improving the aperture ratio of the pixel.

[0507] Layer 128 can be an insulating layer or a conductive layer. For example, various inorganic insulating materials, organic insulating materials, and conductive materials can be used as layer 128. In particular, layer 128 is preferably formed using an insulating material.

[0508] As layer 128, an insulating layer containing an organic material is suitably used. For example, as layer 128, an acrylic resin, a polyimide resin, an epoxy resin, a polyamide resin, a polyimide amide resin, a silicone resin, a benzocyclobutene resin, a phenolic resin, and precursors of the above resins can be used. In addition, as layer 128, a photosensitive resin can be used. As the photosensitive resin, a positive type material or a negative type material can be cited.

[0509] By using a photosensitive resin, layer 128 can be manufactured only through exposure and development processes, and the influence of dry etching or wet etching on the surfaces of conductive layer 182a, conductive layer 182b, and conductive layer 182c can be reduced. In addition, by forming layer 128 using a negative photosensitive resin, sometimes the same photomask (exposure mask) used to form the opening of insulating layer 599 can be used to form layer 128.

[0510] The light-emitting device 130R includes a first layer 113a, a common layer 114 on the first layer 113a, and a common electrode 115 on the common layer 114. In addition, the light-emitting device 130G includes a second layer 113b, a common layer 114 on the second layer 113b, and a common electrode 115 on the common layer 114. In addition, the light-emitting device 130B includes a third layer 113c, a common layer 114 on the third layer 113c, and a common electrode 115 on the common layer 114.

[0511] In addition, the first layer 113a is formed so as to cover the top surface and side surfaces of the conductive layer 126a and the top surface and side surfaces of the conductive layer 129a. Similarly, the second layer 113b is formed so as to cover the top surface and side surfaces of the conductive layer 126b and the top surface and side surfaces of the conductive layer 129b. In addition, similarly, the third layer 113c is formed so as to cover the top surface and side surfaces of the conductive layer 126c and the top surface and side surfaces of the conductive layer 129c. Therefore, the regions where the conductive layer 126a, the conductive layer 126b, and the conductive layer 126c are provided can be used as the light-emitting regions of the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B as a whole, so the aperture ratio of the pixel can be increased.

[0512] In the light-emitting device 130R, the first layer 113a and the common layer 114 can be collectively referred to as the EL layer. Similarly, in the light-emitting device 130G, the second layer 113b and the common layer 114 can be collectively referred to as the EL layer. Similarly, in the light-emitting device 130B, the third layer 113c and the common layer 114 can be collectively referred to as the EL layer.

[0513] There is no particular limitation on the structure of the light-emitting device of the present embodiment, and a single structure or a tandem structure may be adopted.

[0514] The first layer 113a, the second layer 113b, and the third layer 113c are processed into an island shape by photolithography. Therefore, the angles formed by the top surface and the side surface at each end of the first layer 113a, the second layer 113b, and the third layer 113c are nearly 90 degrees. On the other hand, for example, the thickness of the organic film formed using an FMM (Fine Metal Mask) tends to decrease closer to the end. For example, its top surface is formed in a sloped shape in the range of more than 1 μm and less than 10 μm, so it is difficult to distinguish the top surface from the side surface.

[0515] In the first layer 113a, the second layer 113b, and the third layer 113c, the distinction between the top surface and the side surface is clear. Therefore, in the adjacent first layer 113a and second layer 113b, one side surface of the first layer 113a and one side surface of the second layer 113b face each other. The same applies to any combination of the first layer 113a, the second layer 113b, and the third layer 113c.

[0516] The first layer 113a, the second layer 113b, and the third layer 113c at least include a light-emitting layer. For example, a structure in which the first layer 113a, the second layer 113b, and the third layer 113c respectively include a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light is preferably adopted. In addition, in addition to the above colors, the light-emitting layers can adopt cyan, magenta, yellow, or white.

[0517] The first layer 113a, the second layer 113b, and the third layer 113c preferably include a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Since the surfaces of the first layer 113a, the second layer 113b, and the third layer 113c may be exposed in the manufacturing process of the display device, by providing a carrier transport layer on the light-emitting layer, it is possible to prevent the light-emitting layer from being exposed on the outermost surface and reduce the damage to the light-emitting layer. Thereby, the reliability of the light-emitting device can be improved.

[0518] The common layer 114 includes, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may have a stack of an electron transport layer and an electron injection layer, or may have a stack of a hole transport layer and a hole injection layer. The light-emitting devices 130R, 130G, and 130B commonly include the common layer 114.

[0519] The light-emitting devices 130R, 130G, and 130B commonly include a common electrode 115. In addition, as Figure 35 shown, the common electrode 115 commonly included in the plurality of light-emitting devices is electrically connected to the conductive layer in the connection portion 140.

[0520] The insulating layer 125 is preferably used as a barrier insulating layer against one or both of water and oxygen. In addition, the insulating layer 125 preferably has a function of suppressing the diffusion of one or both of water and oxygen. In addition, the insulating layer 125 preferably has a function of capturing or fixing (also referred to as gettering) one or both of water and oxygen. When the insulating layer 125 is used as a barrier insulating layer or has a gettering function, it may have a structure that suppresses the entry of impurities (typically, one or both of water and oxygen) that may diffuse from the outside into each light-emitting device. By adopting this structure, a light-emitting device with high reliability can be provided, and a display device with high reliability can be provided.

[0521] The impurity concentration of the insulating layer 125 is preferably low. Thereby, the mixing of impurities from the insulating layer 125 into the EL layer and the deterioration of the EL layer can be suppressed. In addition, by reducing the impurity concentration in the insulating layer 125, the barrier property against one or both of water and oxygen can be improved. For example, it is preferable that one of the hydrogen concentration and the carbon concentration in the insulating layer 125 is sufficiently low, and preferably both the hydrogen concentration and the carbon concentration are sufficiently low.

[0522] As the insulating layer 127, an insulating layer containing an organic material is preferably used. As the organic material, a photosensitive organic resin is preferably used, for example, a photosensitive resin composition containing an acrylic resin is preferably used. In addition, the viscosity of the material of the insulating layer 127 may be 1 cP or more and 1500 cP or less, and preferably 1 cP or more and 12 cP or less. By setting the viscosity of the material of the insulating layer 127 within the above range, it is possible to more easily form the insulating layer 127 having a tapered shape. Note that in this specification and the like, the acrylic resin does not only refer to polymethyl methacrylate or methacrylic resin, and sometimes refers to the entire acrylic polymer in a broad sense.

[0523] In this specification and the like, the tapered shape means a shape in which at least a part of the side surface of the constituent element is inclined with respect to the substrate surface. For example, a region having an angle (also referred to as a taper angle) formed by the inclined side surface and the substrate surface less than 90° is preferable.

[0524] Note that the insulating layer 127 only needs to have a tapered shape on the side surface, and the organic materials that can be used for the insulating layer 127 are not limited to the above materials. For example, sometimes acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of the above resins can be used as the insulating layer 127. In addition, as the insulating layer 127, sometimes organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral (PVB), polyvinylpyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can be used. In addition, as the insulating layer 127, sometimes a photoresist can be used as a photosensitive resin. As the photosensitive resin, positive-type materials or negative-type materials can be cited.

[0525] A material that absorbs visible light can also be used as the insulating layer 127. By the insulating layer 127 absorbing the light emitted from the light-emitting device, light leakage from the light-emitting device through the insulating layer 127 to an adjacent light-emitting device (stray light) can be suppressed. Thereby, the display quality of the display panel can be improved. In addition, since the display quality can be improved even without using a polarizing plate in the display device, weight reduction and thinning of the display device can be achieved.

[0526] As the material that absorbs visible light, materials including pigments such as black, materials including dyes, light-absorbing resin materials (e.g., polyimide), and resin materials (color filter materials) that can be used for color filters can be cited. In particular, when using a resin material formed by mixing or laminating two colors or three or more colors of color filter materials, the effect of shielding visible light can be improved, so it is preferred. In particular, by mixing three or more colors of color filter materials, a black or nearly black resin layer can be achieved.

[0527] The insulating layer 127 can be formed, for example, by wet deposition methods such as spin coating, dipping, spraying, inkjet printing, dispenser method, screen printing, offset printing, doctor blade method, slot die coating method, roll coating method, curtain coating method, knife-over-edge coating method, etc. In particular, it is preferred to form the organic insulating film that will become the insulating layer 127 by spin coating.

[0528] In addition, the insulating layer 127 is formed at a temperature lower than the heat-resistant temperature of the EL layer. The substrate temperature when forming the insulating layer 127 is typically 200 °C or lower, preferably 180 °C or lower, more preferably 160 °C or lower, further preferably 150 °C or lower, and even more preferably 140 °C or lower.

[0529] Hereinafter, the structure of the insulating layer 127 and the like will be described by taking the structure of the insulating layer 127 between the light-emitting device 130R and the light-emitting device 130G as an example. The same applies to the insulating layer 127 between the light-emitting device 130G and the light-emitting device 130B, the insulating layer 127 between the light-emitting device 130B and the light-emitting device 130R, and the like. In addition, hereinafter, the end portion of the insulating layer 127 on the second layer 113b will sometimes be taken as an example for description, and the same applies to the end portion of the insulating layer 127 on the first layer 113a and the end portion of the insulating layer 127 on the third layer 113c.

[0530] Preferably, when the display device is viewed in cross-section, the insulating layer 127 has a tapered shape with a tapered angle θ1 on the side surface. The tapered angle θ1 is the angle formed by the side surface of the insulating layer 127 and the substrate surface. Note that the tapered angle θ1 is not limited to the substrate surface, and can also be the angle formed by the top surface of the flat portion of the insulating layer 125 or the top surface of the flat portion of the second layer 113b and the side surface of the insulating layer 127. In addition, by making the side surface of the insulating layer 127 have a tapered shape, the side surfaces of the insulating layer 125 and the mask layer 118a sometimes have a tapered shape.

[0531] The tapered angle θ1 of the insulating layer 127 is less than 90°, preferably 60° or less, and more preferably 45° or less. By making the side end portion of the insulating layer 127 have the above-mentioned positive tapered shape, deposition can be performed with high coverage in such a manner that disconnection or partial thinning does not occur in the common layer 114 and the common electrode 115 provided on the side end portion of the insulating layer 127. Thereby, the in-plane uniformity of the common layer 114 and the common electrode 115 can be improved, and the display quality of the display device can be improved.

[0532] When the display device is viewed in cross-section, the top surface of the insulating layer 127 preferably has a convex curved surface shape. The convex curved surface shape of the top surface of the insulating layer 127 is preferably a shape that gently protrudes toward the center. In addition, it is preferably a shape in which the convex curved surface portion at the center of the top surface of the insulating layer 127 is continuously connected to the tapered portion at the side end portion. By adopting the above shape as the insulating layer 127, the common layer 114 and the common electrode 115 can be deposited on the entire top surface of the insulating layer 127 with high coverage.

[0533] The insulating layer 127 is formed in a region between two EL layers (for example, a region between the first layer 113a and the second layer 113b). At this time, a part of the insulating layer 127 is sandwiched between the side end portions of one EL layer (for example, the first layer 113a) and the side end portions of the other EL layer (for example, the second layer 113b).

[0534] Preferably, one end of the insulating layer 127 overlaps with the conductive layer 126a serving as a pixel electrode, and the other end of the insulating layer 127 overlaps with the conductive layer 126b serving as a pixel electrode. By adopting the above structure, the end of the insulating layer 127 can be formed on a substantially flat area of the first layer 113a (second layer 113b). Therefore, it is easier to process the insulating layer 127 into a tapered shape as described above.

[0535] As described above, by providing the insulating layer 127 and the like, it is possible to prevent disconnection portions and portions where the thickness is locally thinned from occurring in the common layer 114 and the common electrode 115 from the substantially flat area of the first layer 113a to the substantially flat area of the second layer 113b. Therefore, it is possible to suppress connection failures caused by disconnection portions and resistance increases caused by portions with locally thin thickness in the common layer 114 and the common electrode 115 between the respective light-emitting devices.

[0536] In the display device of the present embodiment, the distance between the light-emitting devices can be reduced. Specifically, the distance between the light-emitting devices, the distance between the EL layers, or the distance between the pixel electrodes can be reduced to less than 10 μm, 8 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 500 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the display device of the present embodiment has a region where the interval between two adjacent island-shaped EL layers is 1 μm or less, preferably has a region where the interval is 0.5 μm (500 nm) or less, and more preferably has a region where the interval is 100 nm or less. By reducing the distance between the respective light-emitting devices as described above, a display device with high definition and a high aperture ratio can be provided.

[0537] A protective layer 131 is provided on the light-emitting device 130. The protective layer 131 serves as a passivation film for protecting the light-emitting device 130. By forming the protective layer 131 covering the light-emitting device, it is possible to suppress the entry of impurities such as water and oxygen into the light-emitting device, thereby improving the reliability of the light-emitting device 130. As the protective layer 131, for example, alumina, silicon nitride, or silicon oxynitride can be used.

[0538] The protective layer 131 and the substrate 119 are bonded by an adhesive layer 107. As the sealing of the light-emitting device, a solid sealing structure, a hollow sealing structure, or the like can be adopted. Figure 35In this case, the space between the substrate 310 and the substrate 119 is filled with the adhesive layer 107, that is, a solid sealing structure is adopted. Alternatively, a hollow sealing structure using an inert gas (such as nitrogen or argon) to fill the space can also be adopted. At this time, the adhesive layer 107 can also be arranged in a manner that does not overlap with the light-emitting device. In addition, the space can also be filled with a resin different from the adhesive layer 107 arranged in a frame shape.

[0539] As the adhesive layer 107, various curable adhesives such as photocurable adhesives like ultraviolet curable adhesives, reaction curable adhesives, thermosetting adhesives, or anaerobic adhesives can be used. As these adhesives, for example, epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene-vinyl acetate) resins can be cited. In particular, a material with low moisture permeability of epoxy resin is preferably used. In addition, a two-component mixed resin can also be used. In addition, an adhesive sheet can also be used.

[0540] The display device 50B has a top emission type structure. The light-emitting device emits light to the substrate 119 side. Therefore, it is preferable to use a material with high visible light transmittance for the substrate 119. For example, as the substrate 119, a substrate with high visible light transmittance among the substrates applicable to the substrate 310 can be selected. The pixel electrode contains a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0541] Note that the display device according to one aspect of the present invention can also adopt a bottom emission structure in which the light emitted by the light-emitting device is emitted to the substrate 310 side instead of the top emission structure. In this case, a substrate with high visible light transmittance can be selected as the substrate 310.

[0542] By applying one of the above structural examples to the display device, a display device with high resolution and high definition can sometimes be achieved. Specifically, for example, a display device with a resolution of HD (pixel number 1280×720), FHD (pixel number 1920×1080), WQHD (pixel number 2560×1440), WQXGA (pixel number 2560×1600), 4K (pixel number 3840×2160), or 8K (pixel number 7680×4320) can sometimes be achieved. In addition, specifically, for example, a display device with a definition of 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, 5000 ppi or more, or 6000 ppi or more can sometimes be achieved.

[0543] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined and used with the configurations, structures, methods, etc. shown in this embodiment. In addition, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined and used with the configurations, structures, methods, etc. shown in other embodiments, etc.

[0544] At least a part of the structural example shown in this embodiment and the drawings corresponding to the structural example can be appropriately combined with other structural examples or drawings, etc.

[0545] (Embodiment 5) In this embodiment, an electronic device, a display device, etc. according to one aspect of the present invention will be described. One aspect of the present invention is suitable for, for example, wearable electronic devices for VR or AR applications.

[0546] <Structural example of the electronic device> As an example of the wearable electronic device, Figure 36A a perspective view of the glasses-type electronic device 150 is shown. In Figure 36A the electronic device 150 shown, a pair of display devices 90 (display device 90_L and display device 90_R), an action detection unit 101, a gaze detection unit 84, an arithmetic unit 103, and a communication unit 85 are included in a housing 105.

[0547] Figure 36B is Figure 36A a block diagram of the electronic device 150. Similarly to Figure 36A the electronic device 150 includes a display device 90_L, a display device 90_R, an action detection unit 101, a gaze detection unit 84, an arithmetic unit 103, and a communication unit 85, and sends and receives various signals to and from each other via a bus BW. Each of the display device 90_L and the display device 90_R includes a plurality of pixels 230, a driving circuit 65, and a functional circuit 40. One pixel 230 includes one light-emitting device 61 and one pixel circuit 51. Therefore, each of the display device 90_L and the display device 90_R includes a plurality of light-emitting devices 61 and a plurality of pixel circuits 51.

[0548] The action detection unit 101 has a function of detecting the action of the housing 105, that is, the head action of the user wearing the electronic device 150. As the action detection unit 101, for example, a motion sensor using MEMS technology can be used. As the motion sensor, a three-axis motion sensor or a six-axis motion sensor, etc. can be used. Information about the action of the housing 105 detected by the action detection unit 101 is sometimes referred to as first information or action information, etc.

[0549] The line-of-sight detection unit 84 has a function of obtaining information about the user's line of sight. Specifically, it has a function of detecting the user's line of sight. For example, the user's line of sight can be detected by a line-of-sight measurement (eye tracking) method such as the Pupil Center Corneal Reflection method or the Bright / Dark Pupil Effect method. Alternatively, the user's line of sight can also be obtained by using a line-of-sight measurement method using laser or ultrasonic waves, etc.

[0550] The arithmetic unit 103 has a function of calculating the user's fixation point by using the line-of-sight detection result of the line-of-sight detection unit 84. That is to say, it can be known which object in the images displayed on the display devices 90_L and 90_R the user is fixating on. In addition, it can be known whether the user is fixating on a part outside the screen. Note that the information about the user's line of sight (line-of-sight detection result) obtained by the line-of-sight detection unit 84 is sometimes referred to as second information or line-of-sight information, etc.

[0551] The arithmetic unit 103 has a function of performing rendering processing (arithmetic processing of image data) according to the movement of the housing 105. The arithmetic unit 103 performs rendering processing according to the movement of the housing 105 by using the first information and the image data input from the outside through the communication unit 85. As this image data, for example, 360-degree omnidirectional image data can be used. The 360-degree omnidirectional image data can be, for example, image data captured by an all-sky camera (omnidirectional camera, 360° camera), or image data generated by computer graphics, etc. The arithmetic unit 103 has a function of converting the 360-degree omnidirectional image data into image data that can be displayed on the display devices 90_L and 90_R according to the first information.

[0552] The arithmetic unit 103 has a function of determining the size and shape of a plurality of regions set for the display units of the display devices 90_L and 90_R respectively by using the second information. Specifically, the arithmetic unit 103 calculates the fixation point on the display unit according to the second information, and sets the following first region S1 to third region S3, etc. on the display unit with this fixation point as the reference.

[0553] As the arithmetic unit 103, a microprocessor such as a central processing unit (CPU), a digital signal processor (DSP), or a graphics processing unit (GPU) can be used alone or in combination. In addition, these microprocessors can also be constituted by a programmable logic device (PLD) such as a field programmable gate array (FPGA) or a field programmable analog array (FPAA).

[0554] The arithmetic unit 103 performs various data processing and program controls by interpreting and executing instructions from various programs by the processor. Programs executable by the processor can be stored in a memory area in the processor or in a separately provided storage unit. As the storage unit, for example, a storage device using a non-volatile storage element such as a flash memory, a magnetoresistive random access memory (MRAM), a phase change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FeRAM), etc. or a storage device using a volatile storage element such as a dynamic RAM (DRAM) and a static RAM (SRAM) can also be used.

[0555] The communication unit 85 has a function of communicating with external devices wirelessly or wiredly in order to acquire various data such as image data. For example, in the communication unit 85, a high-frequency circuit (RF circuit) may be provided to perform transmission and reception of RF signals. The high-frequency circuit is a circuit that mutually converts electromagnetic signals in the frequency bands specified by the laws of various countries and electrical signals and uses the electromagnetic signals to communicate with other communication devices wirelessly. When performing wireless communication, the following can be used as communication protocols or communication technologies: communication standards such as LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Division Multiple Access 2000), WCDMA (Wideband Code Division Multiple Access: registered trademark); or specifications standardized by IEEE (Institute of Electrical and Electronics Engineers) for communication such as Wi-Fi (Wireless Fidelity: registered trademark), Bluetooth (registered trademark), ZigBee (registered trademark), etc. In addition, the third-generation mobile communication system (3G), fourth-generation mobile communication system (4G), or fifth-generation mobile communication system (5G), etc. determined by the International Telecommunication Union (ITU) can be used.

[0556] The communication unit 85 may also include external ports such as LAN (Local Area Network) connection terminals, digital broadcast reception terminals, terminals for connecting an AC adapter, etc.

[0557] Each of the display devices 90_L and 90_R includes a plurality of light-emitting devices 61, a plurality of pixel circuits 51, a drive circuit 65, and a functional circuit 40. The pixel circuit 51 has a function of controlling the light emission of the light-emitting device 61. The drive circuit 65 has a function of controlling the pixel circuit 51.

[0558] The information of a plurality of regions in the display unit of the display device determined by the arithmetic unit 103 is used to differentially set the driving of the resolution between the regions. The functional circuit 40 has the following functions: controlling the drive circuit 65 so as to perform high-resolution display in the region close to the fixation point; controlling the drive circuit 65 so as to perform low-resolution display in the region far from the fixation point.

[0559] For example, by rewriting image data every other pixel or every multiple pixels, a low-resolution display can be achieved. By reducing the number of pixels for which the image data is to be rewritten, the power consumption of the display device can be reduced.

[0560] In addition, a sensor 97 can also be provided in the electronic device 150. The sensor 97 only needs to have the function of obtaining any one or more of the information of the user's vision, hearing, touch, taste, and smell. More specifically, the sensor 97 only needs to have the function of detecting or measuring any one or more of force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, magnetism, temperature, sound, time, electric field, current, voltage, power, radiation, humidity, inclination, vibration, odor, and infrared rays. The electronic device 150 can also include one or more sensors 97.

[0561] In addition, the sensor 97 can also be used to measure the surrounding temperature, humidity, illuminance, odor, etc. In addition, the sensor 97 can be used, for example, to obtain information for personal identification using fingerprints, palm prints, irises, retinas, vein shapes (including vein shapes and artery shapes), or faces. In addition, the sensor 97 can be used to measure the user's blink count, eyelid movement, pupil size, body temperature, pulse, or oxygen saturation in the blood, etc., to detect the user's fatigue level and health status, etc. The electronic device 150 can also detect the user's fatigue level and health status, etc., and display warnings, etc., on the display device 90.

[0562] In addition, the user's line of sight and eyelid movement can also be detected to control the operation of the electronic device 150. Since the user does not need to touch the electronic device 150 to perform operations, input operations, etc., in a hands-free state (a state where both hands are unrestrained) can be achieved.

[0563] In addition, Figure 37A is a perspective view showing the electronic device 150. In Figure 37A the housing 105 of the electronic device 150 includes, for example, a mounting portion 86, a buffer member 87, a pair of lenses 88, etc., in addition to a pair of display devices 90_L, display device 90_R, and an arithmetic unit 103. The pair of display devices 90_L and display device 90_R are each provided at a position inside the housing 105 where they can be seen through the lenses 88.

[0564] In addition, Figure 37A The housing 105 shown is provided with an input terminal 109 and an output terminal 89. A cable for supplying an image signal (image data) from a video output device or the like or power for charging a battery (not shown) provided inside the housing 105 can be connected to the input terminal 109. The output terminal 89 is used as a sound output terminal, for example, and can be connected to a headphone or a headset, etc.

[0565] In addition, the housing 105 preferably has a mechanism in which the left and right positions of the lens 88 and the display devices 90_L and 90_R can be adjusted so that the lens 88 and the display devices 90_L and 90_R are located at the most suitable positions according to the position of the user's eyes. In addition, it is preferable to have a mechanism in which the focus is adjusted by changing the distance between the lens 88 and the display devices 90_L and 90_R.

[0566] The buffer member 87 is a part that contacts the user's face (such as the forehead or cheek). By making the buffer member 87 in close contact with the user's face, external light can be prevented from entering (light leakage), and thus the sense of immersion can be further enhanced. The buffer member 87 is preferably made of a soft material so as to be in close contact with the user's face when the user wears the electronic device 150. When using such a material, it not only makes the user feel skin-friendly, but also does not make the user feel cold when worn in colder seasons, etc., so it is preferable. When the buffer member 87 or members such as the mounting portion 86 that contact the user's skin have a detachable structure, it is easy to clean and replace, so it is preferable.

[0567] The electronic device according to one aspect of the present invention may also include earphones 99A. The earphones 99A include a communication unit (not shown) and have a wireless communication function. The earphones 99A can output sound data by using the wireless communication function. The earphones 99A may also include a vibration mechanism to be used as bone conduction earphones.

[0568] In addition, as Figure 37B shown in the earphones 99B, the earphones 99A can be directly connected to the mounting portion 86 or connected by wire. In addition, the earphones 99B and the mounting portion 86 may also include magnets. Thereby, the earphones 99B can be fixed to the mounting portion 86 by magnetic force, and the storage becomes easy, so it is preferable.

[0569] <Structural examples of display devices> Refer to Figure 38A 、 Figure 38B and Figure 39 to describe the structure of the display device 90A applicable to the display devices 90_L and 90_R shown in Figure 36A and Figure 36B shown.

[0570] Figure 38A is a perspective view of the display device 90A applicable to the display devices 90_L and 90_R shown in Figure 36A and Figure 36B shown.

[0571] The display device 90A includes a substrate 91 and a substrate 92. The display device 90A includes a display unit 93 disposed between the substrate 91 and the substrate 92. The display unit 93 includes a plurality of pixels 230. The pixel 230 includes a pixel circuit 51 and a light-emitting device 61. The display unit 93 is an area in the display device 90A where a display image is formed.

[0572] When the pixels 230 are arranged in a matrix of 1920×1080 pixels, a display unit 93 capable of displaying at a resolution of so-called full high definition (also referred to as "2K resolution", "2K1K", or "2K", etc.) can be realized. In addition, for example, when the pixels 230 are arranged in a matrix of 3840×2160 pixels, a display unit 93 capable of displaying at a resolution of so-called ultra high definition (also referred to as "4K resolution", "4K2K", or "4K", etc.) can be realized. In addition, for example, when the pixels 230 are arranged in a matrix of 7680×4320 pixels, a display unit 93 capable of displaying at a resolution of so-called ultra high definition (also referred to as "8K resolution", "8K4K", or "8K", etc.) can be realized. By increasing the pixels 230, a display unit 93 capable of displaying at a resolution of 16K or even 32K can also be realized.

[0573] In addition, the pixel density (clarity) of the display unit 93 is preferably 1000 ppi or more and 10000 ppi or less. For example, it can be 2000 ppi or more and 6000 ppi or less, or it can be 3000 ppi or more and 5000 ppi or less.

[0574] Note that there is no particular limitation on the screen ratio (aspect ratio) of the display unit 93. The display unit 93 can correspond to various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, etc., for example.

[0575] In addition, in this specification and the like, "element" may sometimes be referred to as "device". For example, a display element, a light-emitting device, and a liquid crystal element may be referred to as a display device, a light-emitting device, and a liquid crystal device, respectively.

[0576] The display device 90A can be input with various signals and power supply potentials from the outside through the terminal portion 94 and use the display elements provided in the display unit 93 to perform image display. Various elements can be used as the display element. Typically, a light-emitting device having a function of emitting light such as an organic EL element and an LED element, a liquid crystal element, or a MEMS (MicroElectro Mechanical Systems) element can be used.

[0577] A plurality of layers are provided between substrate 91 and substrate 92, and transistors for circuit operation or display elements for emitting light are provided in each layer. A pixel circuit having a function of controlling the operation of the display element, a driving circuit having a function of controlling the pixel circuit, a functional circuit having a function of controlling the driving circuit, etc. are provided in the plurality of layers.

[0578] Figure 38B It is a perspective view schematically showing the structure of each layer provided between substrate 91 and substrate 92.

[0579] A layer 62 is provided on substrate 91. The layer 62 includes a driving circuit 65, a functional circuit 40, and an input / output circuit 80. The layer 62 includes a transistor 63 containing silicon in a channel formation region 64. As the substrate 91, for example, a silicon substrate can be used. Since the thermal conductivity of the silicon substrate is higher than that of the glass substrate, it is preferable. By providing the driving circuit 65, the functional circuit 40, and the input / output circuit 80 in the same layer, the wiring for electrically connecting the driving circuit 65, the functional circuit 40, and the input / output circuit 80 can be shortened. As a result, the charge / discharge time of the control signal for the functional circuit 40 to control the driving circuit 65 becomes shorter, and power consumption can be reduced. In addition, the charge / discharge time required for the input / output circuit 80 to supply signals to the functional circuit 40 and the driving circuit 65 becomes shorter, and power consumption can be reduced.

[0580] The transistor 63 can be, for example, a transistor containing single-crystalline silicon in a channel formation region (also referred to as a "c-Si transistor"). In particular, when a transistor containing single-crystalline silicon in the channel formation region is used as the transistor provided in the layer 62, the on-state current of the transistor can be increased. As a result, the circuits included in the layer 62 can be driven at high speed, so it is preferable. In addition, since the Si transistor can be formed by microfabrication with a channel length of 3 nm or more and 10 nm or less, a display device 90A in which a display unit, accele...

Claims

1. A semiconductor device, comprising: A first insulating layer; A second insulating layer; And A transistor, Wherein the transistor is disposed on the first insulating layer, The transistor includes a semiconductor layer, a gate insulating layer, a first gate electrode, a source electrode, and a drain electrode, The second insulating layer includes an opening reaching the first insulating layer, The source electrode and the drain electrode are disposed on the second insulating layer, The semiconductor layer is disposed in contact with the side surface of the second insulating layer in the opening and the side surfaces of the source electrode and the drain electrode, The gate insulating layer is located on the semiconductor layer, the source electrode, and the drain electrode, and the first gate electrode overlaps with the opening and is located on the gate insulating layer.

2. A semiconductor device, comprising: A first insulating layer; A second insulating layer; And A transistor, Wherein the transistor is disposed on the first insulating layer, The transistor includes a semiconductor layer, a gate insulating layer, a first gate electrode, a source electrode, and a drain electrode, The second insulating layer includes an opening reaching the first insulating layer, The source electrode and the drain electrode are disposed on the second insulating layer, The semiconductor layer has a first region in contact with the side surface of the second insulating layer in the opening, a second region in contact with the side surface of the source electrode, and a third region in contact with the side surface of the drain electrode in the opening, In the semiconductor layer, the first region is located between the second region and the third region, The gate insulating layer is located on the semiconductor layer, the source electrode, and the drain electrode, and the first gate electrode overlaps with the opening and is located on the gate insulating layer.

3. A semiconductor device, comprising: A first insulating layer; A second insulating layer; And A transistor, Wherein the transistor is disposed on the first insulating layer, The transistor includes a semiconductor layer, a gate insulating layer, a first gate electrode, a source electrode, and a drain electrode, The second insulating layer includes an opening reaching the first insulating layer, The source electrode and the drain electrode are disposed on the second insulating layer, The semiconductor layer is disposed in contact with the side surface of the second insulating layer in the opening, the top surface of the first insulating layer in the opening, and the side surfaces of the source electrode and the drain electrode, The gate insulating layer is located on the semiconductor layer, the source electrode, and the drain electrode, and the first gate electrode overlaps with the opening and is located on the gate insulating layer.

4. The semiconductor device according to any one of claims 1 to 3, Wherein the semiconductor layer is in contact with one or both of the top surfaces of the source electrode and the drain electrode.

5. The semiconductor device according to any one of claims 1 to 3, Wherein the first insulating layer and the gate insulating layer have a portion in contact at the bottom of the opening.

6. The semiconductor device according to any one of claims 1 to 3, Wherein the semiconductor layer has a portion in contact with the top surface of the second insulating layer.

7. The semiconductor device according to any one of claims 1 to 3, Further comprising a second gate electrode, Wherein the second gate electrode is covered by the second insulating layer, And a part of the second insulating layer is located between the side surface of the second gate electrode and the semiconductor layer.

8. The semiconductor device according to claim 7, wherein a third insulating layer is included between the first insulating layer and the second gate electrode.

9. The semiconductor device according to any one of claims 1 to 3, wherein the contour shape of the opening is any shape of a circle, an ellipse, a quadrangle with rounded corners, a regular polygon, a polygon other than a regular polygon, a concave polygon, an ellipse, a polygon with rounded corners, or a closed curve combining a straight line and a curve.

10. The semiconductor device according to any one of claims 1 to 3, wherein the opening includes a plurality of extending portions and one or more bending portions, the extending portions have a shape extending in one direction in a top view, and one of the plurality of extending portions is connected to another through the bending portion.

11. A semiconductor device, comprising: a first insulating layer; a second insulating layer; a first transistor; and a second transistor, wherein the first transistor is provided on the first insulating layer, the first transistor includes a first semiconductor layer, a gate insulating layer, a first gate electrode, a first source electrode, and a first drain electrode, the second insulating layer includes a first opening reaching the first insulating layer, the first source electrode and the first drain electrode are provided on the second insulating layer, the first semiconductor layer is provided in contact with the side surface of the second insulating layer in the first opening, the top surface of the first insulating layer in the first opening, and the side surfaces of the first source electrode and the first drain electrode, the gate insulating layer is located on the first semiconductor layer, the first source electrode, and the first drain electrode, the first gate electrode overlaps with the first opening and is located on the gate insulating layer, the second transistor includes a second semiconductor layer, the gate insulating layer, a second gate electrode, a second source electrode, and a second drain electrode, the second source electrode and the second drain electrode are at different heights, the second insulating layer includes a second opening reaching one of the second source electrode and the second drain electrode, the other of the second source electrode and the second drain electrode is provided on the second insulating layer, the second semiconductor layer is provided in contact with the side surface of the second insulating layer in the second opening, the top surface of one of the second source electrode and the second drain electrode, and the side surface of the other of the second source electrode and the second drain electrode, the gate insulating layer is located on the second semiconductor layer, the second source electrode, and the second drain electrode, and the second gate electrode overlaps with the second opening and is located on the gate insulating layer.

12. The semiconductor device according to claim 11, wherein the first semiconductor layer is in contact with one or both of the top surfaces of the first source electrode and the first drain electrode.

13. The semiconductor device according to claim 11, wherein the first insulating layer and the gate insulating layer have a portion in contact with the bottom of the first opening.

14. The semiconductor device according to claim 11, Wherein the first semiconductor layer has a portion in contact with the top surface of the second insulating layer.

15. The semiconductor device according to claim 11, wherein the contour shape of the first opening is any shape such as a circle, an ellipse, a quadrangle with rounded corners, a regular polygon, a polygon other than a regular polygon, a concave polygon, an ellipse, a polygon with rounded corners, or a closed curve combining a straight line and a curve.

16. The semiconductor device according to claim 11, wherein the first opening includes a plurality of extending portions and one or more bending portions, the extending portions have a shape extending in one direction in a plan view, and one of the plurality of extending portions is connected to another through the bending portion.

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