Phase-locked loop test method and device and electronic equipment
The phase noise curve and phase noise data are generated by the phase noise meter, and the test results of the phase locked loop are directly acquired, solving the problem of cumbersome and time-consuming phase locked loop testing in the prior art, and achieving an efficient test method.
Patent Information
- Application Number
- CN202410186138.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-19
- Publication Date
- 2025-07-25
AI Technical Summary
The existing phase-locked loop automation test solutions are cumbersome and time-consuming, and have low testing efficiency, especially when testing phase noise, jitter and frequency spurious.
By determining the test configuration information of the phase lock loop to be tested, a phase noise curve and phase noise data are generated using a phase noise meter, and combined with the test case information, the phase noise, jitter and spurious test results of the phase lock loop are directly obtained.
It realizes that the phase-locking loop test can be completed using only the phase noise meter, reducing the use of the instrument, saving test time and improving testing efficiency.
Smart Images
Figure CN120370128A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of chip automated testing, and in particular, to a testing method, device, and electronic device for a phase-locked loop. Background Art
[0002] As the operating speed of current chip systems is getting faster and faster, higher performance requirements are imposed on all aspects of the phase-locked loop. Therefore, it is necessary to conduct a comprehensive test and analysis of its performance, among which the most important tests include parameters such as jitter, phase noise, spurious signals, and settling time.
[0003] In the phase-locked loop automated testing scheme in the related art, a phase noise meter is basically used to test the phase noise of the phase-locked loop, and then a spectrum analyzer is used to test its frequency spurious signals. The testing method is relatively cumbersome and time-consuming, and the testing efficiency is relatively low. Summary of the Invention
[0004] To overcome the problems existing in the related art, the present disclosure provides a testing method, device, and electronic device for a phase-locked loop.
[0005] According to the first aspect of the embodiments of the present disclosure, a testing method for a phase-locked loop is provided, including:
[0006] Determine the test configuration information of the phase-locked loop to be tested; wherein, the test configuration information includes the first test frequency point information and the first test case information of a plurality of first test frequency points to be measured; the first test case information is used to test the first type of indicators of the phase-locked loop to be tested;
[0007] According to the first test frequency point information, determine the first test frequency point to be measured, and control the phase-locked loop to be tested to lock the first test frequency point;
[0008] Configure a phase noise meter according to the first test frequency point and the first test case information, so that the phase noise meter generates a corresponding phase noise curve, as well as the phase noise data and jitter data of the first test frequency point; wherein, the phase noise meter is connected to the phase-locked loop to be tested;
[0009] Obtain the phase noise curve, the phase noise data, and the jitter data from the phase noise meter, and determine the test result of the first type of indicators of the phase-locked loop to be tested at the first test frequency point according to the phase noise curve, the phase noise data, and the jitter data.
[0010] According to the second aspect of the embodiments of the present disclosure, a testing device for a phase-locked loop is provided, including:
[0011] A first determination module, configured to determine test configuration information of a phase-locked loop to be tested; wherein, the test configuration information includes first test frequency point information and first test case information of a plurality of first frequency points to be tested; the first test case information is used to test first type of indicators of the phase-locked loop to be tested;
[0012] A second determination module, configured to determine a first frequency point to be tested according to the first test frequency point information, and control the phase-locked loop to be tested to lock to the first frequency point to be tested;
[0013] A first configuration module, configured to configure a phase noise meter according to the first frequency point to be tested and the first test case information, so that the phase noise meter generates a corresponding phase noise curve, and phase noise data and jitter data of the first frequency point to be tested; wherein, the phase noise meter is connected to the phase-locked loop to be tested;
[0014] A third determination module, configured to obtain the phase noise curve, the phase noise data and the jitter data from the phase noise meter, and determine a test result of the first type of indicators of the phase-locked loop to be tested at the first frequency point to be tested according to the phase noise curve, the phase noise data and the jitter data.
[0015] According to a third aspect of an embodiment of the present disclosure, there is provided an electronic device, including: a memory, a processor, and a computer program stored on the memory and executable on the processor, when the processor executes the computer program, implementing the method described in the first aspect above.
[0016] According to a fourth aspect of an embodiment of the present disclosure, there is provided a computer-readable storage medium, on which a computer program is stored, when the computer program is executed by a processor, implementing the method described in the first aspect above.
[0017] The technical solution provided by the embodiment of the present disclosure may include the following beneficial effects: By determining a first frequency point to be tested according to the first test frequency point information, controlling the phase-locked loop to be tested to lock to the first frequency point to be tested, configuring the phase noise meter according to the first frequency point to be tested and the first test case information, so that the phase noise meter generates a corresponding phase noise curve, and phase noise data and jitter data of the first frequency point to be tested, and obtaining the phase noise curve, phase noise data and jitter data from the phase noise meter to determine a test result of the first type of indicators of the phase-locked loop to be tested at the first frequency point to be tested. That is to say, this solution can implement the test of the phase-locked loop only through a phase noise meter, which can reduce the use of instruments, greatly save the test time, and improve the test efficiency.
[0018] It should be understood that the above general description and subsequent detailed description are only exemplary and explanatory, and cannot limit the present disclosure. Description of the Drawings
[0019] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention.
[0020] Figure 1 It is a schematic diagram of device connection for a phase-locked loop test scheme in the related art;
[0021] Figure 2 It is a flowchart of a method for testing a phase-locked loop shown according to an exemplary embodiment;
[0022] Figure 3 It is a schematic diagram of device connection for a phase-locked loop test shown according to an exemplary embodiment;
[0023] Figure 4 It is a flowchart of another method for testing a phase-locked loop shown according to an exemplary embodiment;
[0024] Figure 5 It is a flowchart of yet another method for testing a phase-locked loop shown according to an exemplary embodiment;
[0025] Figure 6 It is a flowchart of yet another method for testing a phase-locked loop shown according to an exemplary embodiment;
[0026] Figure 7 It is a flowchart of yet another method for testing a phase-locked loop shown according to an exemplary embodiment;
[0027] Figure 8 It is a block diagram of the structure of a phase-locked loop test device shown according to an exemplary embodiment;
[0028] Figure 9 It is a block diagram of the structure of an electronic device for implementing a method for testing a phase-locked loop shown according to an exemplary embodiment. Detailed Embodiments
[0029] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.
[0030] It should be noted that the frequency source can be said to be the heart of a communication system, and its quality largely determines the health of a system. The phase-locked loop (PLL) is a major component of the frequency source. Therefore, a PLL circuit with excellent performance is very important for a communication system. The phase noise of the PLL has a great impact on the performance of communication systems and devices. In the frequency domain, it is distributed on both sides of the carrier signal according to a power-law spectrum. Whether it is used as the transmit excitation signal, the local oscillator signal of the receiver, or various frequency references, these phase noises will appear at the demodulation terminal during the demodulation process just like the signal, causing a decrease in the baseband signal-to-noise ratio and an increase in the bit error rate. As the operating speed of current chip systems is getting faster and faster, the performance requirements for all aspects of the PLL are getting higher and higher. Therefore, it is necessary to comprehensively test and analyze its performance, and the most important tests include parameters such as jitter, phase noise, spurs, and settling time.
[0031] In the PLL automatic test scheme in the related art, a phase noise meter is basically used to test the phase noise of the PLL, and then a spectrum analyzer is used to test its frequency spurs. As Figure 1 shown, the test method is relatively cumbersome and time-consuming, and the test efficiency is low.
[0032] To solve the above problems, the present disclosure provides a test method, device, and electronic device for a phase-locked loop.
[0033] Figure 2 FIG. is a flowchart of a test method for a phase-locked loop shown according to an exemplary embodiment. It should be noted that the test method for the phase-locked loop implemented in the present disclosure can be applied to the test device for the phase-locked loop implemented in the present disclosure, and the device can be configured in an electronic device. The phase-locked loop in the embodiments of the present disclosure can be a phase-locked loop for communication chips in scenarios such as LTE (Long Term Evolution) and 5G NG (5G New Radio). As Figure 2 shown, the method may include the following steps:
[0034] Step 201, determine the test configuration information of the phase-locked loop to be tested; wherein, the test configuration information includes first test frequency point information and first test case information of a plurality of first frequency points to be tested; the first test case information is used to test the first type of indicators of the phase-locked loop to be tested.
[0035] Among them, the test configuration information of the phase-locked loop to be tested can be determined based on a test script. For example, relevant staff edit the test script before the test. When starting the test, the computer can read the test script file based on the test script set in the program to obtain the test configuration information. In addition, the test configuration information of the phase-locked loop to be tested can also be determined based on the configuration operations in the visual interface of the PLL test.
[0036] In some embodiments of the present disclosure, the first test frequency point information of multiple first frequency points to be measured may include a test frequency point scenario and relevant information of multiple first frequency points to be measured. Among them, the test frequency point scenario may be a full frequency point scanning test or a custom frequency point test. In the full frequency point scanning test, the first test frequency point information may include a frequency step and the range of test frequency points. In the custom frequency point test scenario, the first test frequency point information may include multiple custom first frequency points to be measured.
[0037] Among them, the first test case information is used to test the first type of indicators of the PLL to be measured. The first type of indicators may include indicators such as phase noise, jitter, and spurious. The first test case information includes the configuration information of the phase noise meter and the control information of the chip when testing the above indicators.
[0038] It should be noted that before the test, it is also necessary to detect whether the instruments required for the test are controlled, that is, to determine the connection of each interface, and based on the first test case information, initialize the configuration of the chip through SPI. Figure 3 This is a schematic diagram of the device connection for a PLL test in the embodiments of the present disclosure. That is to say, the PLL test process involves a host computer, a chip, a power supply, and a phase noise meter. Among them, the host computer is connected to the chip and the phase noise meter, the phase noise meter is connected to the chip, and the power supply is connected to the chip. For example, the phase noise meter is connected to the host computer through a LAN (local area network, network port) port via a switch. The host computer configures the chip using USB_SPI, and the host computer controls the phase noise meter through SCPI (Standard Commands for Programmable Instruments) instructions.
[0039] Step 202: Determine the first frequency point to be measured according to the first test frequency point information, and control the PLL to be measured to lock the first frequency point to be measured.
[0040] That is to say, the PLL test includes testing multiple first frequency points to be measured. After the test of the previous first frequency point to be measured is completed, the test of the next first frequency point to be measured is automatically carried out. The first frequency point to be measured here is the first frequency point to be measured that needs to be tested currently.
[0041] In some embodiments of the present disclosure, the test configuration information also includes the path configuration information of the PLL, and the host computer configures the path of the PLL based on the path configuration information. Among them, the path configuration information may include information such as test uplink and test downlink.
[0042] Step 203: Configure the phase noise meter according to the first frequency point to be measured and the first test case information, so that the phase noise meter generates a corresponding phase noise curve, as well as the phase noise data and jitter data of the first frequency point to be measured; wherein, the phase noise meter is connected to the PLL to be measured.
[0043] That is to say, configure the first frequency point to be measured, as well as the test frequency range information of the first frequency point to be measured, the sampling point information of the phase noise data, the sampling point information of the jitter data, etc. into the phase noise meter, so that the phase noise meter generates a corresponding phase noise curve, as well as the phase noise data and jitter data of the first frequency point to be measured. As an example, the phase noise meter can be configured by means of SCPI commands according to the first frequency point to be measured and the first test case information.
[0044] Step 204: Obtain the phase noise curve, phase noise data and jitter data from the phase noise meter, and determine the test results of the first type of indicators of the PLL to be measured at the first frequency point to be measured according to the phase noise curve, phase noise data and jitter data.
[0045] In some embodiments of the present disclosure, the test results of the first type of indicators include the phase noise test results, jitter test results and spurious test results of the first frequency point to be measured. The implementation method of determining the test results of the first type of indicators of the PLL to be measured at the first frequency point to be measured according to the phase noise curve, phase noise data and jitter data includes: determining the phase noise data as the phase noise test results of the first frequency point to be measured; determining the jitter data as the jitter test results of the first frequency point to be measured; and determining the spurious test results of the first frequency point to be measured according to the phase noise curve.
[0046] That is to say, this solution can realize the test of the PLL on the premise of only connecting the phase noise meter, which can not only save costs but also improve the test efficiency.
[0047] As a possible implementation method, the implementation of determining the spurious test results of the first frequency point to be measured according to the phase noise curve may include: performing smoothing processing on the phase noise curve to obtain a smooth curve; calculating the height difference between each sampling point in the phase noise curve and the obtained smooth curve; if the height difference exceeds a preset height threshold, determining the corresponding sampling point as a spurious point, and determining the frequency and power of the spurious point based on the phase noise curve, and determining the frequency and power of the spurious point as the spurious test results.
[0048] As another possible implementation method, it is possible to determine the phase noise change rate of each sampling point in the phase noise curve, and based on the phase noise change rate of each sampling point, determine whether there is a spurious point. If there is a spurious point, determine the frequency and power of the spurious point as the spurious test results of the first frequency point to be measured.
[0049] Since the first test frequency point information includes multiple first frequency points to be measured, during the test of the phase-locked loop, after the test of the current first frequency point to be measured is completed, the test of the next frequency point to be measured can be automatically performed.
[0050] In some other embodiments of the present disclosure, the test configuration information may further include temperature configuration information, and the method may further include: controlling the ambient temperature of the phase-locked loop to be measured based on the temperature configuration information. For example, when testing the phase-locked loop to be measured, the ambient temperature can be controlled by an incubator. Here, the temperature of the incubator can be controlled based on the temperature configuration information to achieve the control of the ambient temperature.
[0051] It should be noted that the test method of the phase-locked loop in the embodiments of the present disclosure can be implemented based on a Python script or by a program in other languages, and the present disclosure does not make any limitations in this regard.
[0052] According to the test method of the phase-locked loop in the embodiments of the present disclosure, by determining the first frequency point to be measured according to the first test frequency point information, controlling the phase-locked loop to be measured to lock the first frequency point to be measured, configuring the phase noise meter according to the first frequency point to be measured and the first test case information, so that the phase noise meter generates a corresponding phase noise curve, as well as the phase noise data and jitter data of the first frequency point to be measured, and obtaining the phase noise curve, phase noise data and jitter data from the phase noise meter to determine the test result of the first type of index of the phase-locked loop to be measured at the first frequency point to be measured. That is to say, this solution can realize the test of the phase-locked loop only through the phase noise meter, which can reduce the use of instruments, greatly save the test time, and improve the test efficiency.
[0053] Next, a detailed introduction will be made to determining the spurious test result of the first frequency point to be measured according to the phase noise curve.
[0054] Figure 4 is a flowchart of another test method of a phase-locked loop shown according to an exemplary embodiment. As Figure 4 shown, based on the above embodiments, the implementation process of determining the spurious test result of the first frequency point to be measured according to the phase noise curve may include:
[0055] Step 401, determine the phase noise change rate of each sampling point in the phase noise curve.
[0056] In some embodiments of the present disclosure, the phase noise curve is composed of phase noise data of multiple sampling points. The phase noise change rate of each sampling point can represent the phase noise change amplitude of each sampling point in the phase noise curve. As an example, the phase noise change rate of each sampling point can be determined according to the phase noise and frequency of every two adjacent sampling points.
[0057] Step 402, determine whether there are spurious points in the sampling points according to the phase noise change rate.
[0058] It can be understood that the stray points in the phase noise curve refer to the points with large variation amplitudes. Therefore, whether there are stray points among the sampling points can be determined according to the phase noise change rate of each sampling point.
[0059] As an example, the phase noise change rate of each sampling point can be compared with a preset change rate threshold respectively; if the phase noise change rate of the first sampling point among the sampling points is greater than the change rate threshold, the first sampling point is determined as a stray point. Among them, the number of the first sampling points can be one or more.
[0060] Step 403, if there are stray points among the sampling points, determine the frequency and power of the stray points from the phase noise curve, and determine the frequency and power of the stray points as the stray test result.
[0061] If there are no stray points among the sampling points, it is determined that the stray test result is no stray.
[0062] According to the test method of the phase-locked loop according to the embodiments of the present disclosure, by determining the phase noise change rate of each sampling point in the phase noise curve, whether there are stray points among the sampling points is determined according to the phase noise change rate. If there are stray points among the sampling points, the frequency and power of the stray points are determined from the phase noise curve, and the frequency and power of the stray points are determined as the stray test result. This solution can, on the premise of only using a phase noise meter, not only realize the test of phase noise and jitter, but also realize the stray test, which can not only save instrument resources, save test costs, but also reduce the test time and improve the test efficiency.
[0063] Next, the test of the settling time of the phase-locked loop to be tested will be introduced.
[0064] Figure 5 It is a flowchart of another test method of a phase-locked loop shown according to an exemplary embodiment. It should be noted that in some embodiments of the present disclosure, the test configuration information further includes second test frequency point information and second test case information of a plurality of second frequency points to be tested, where the second test case information is used to test the settling time of the phase-locked loop to be tested. As Figure 5 shown, based on the above embodiments, the method may further include:
[0065] Step 501, according to the second test frequency point information, determine the second frequency point to be tested, and control the phase-locked loop to be tested to lock the second frequency point to be tested.
[0066] Among them, the second test frequency point information is the test frequency point information for testing the settling time of the phase-locked loop. The second frequency point to be tested can be the current second frequency point to be tested determined based on the second test frequency point information.
[0067] Step 502: Configure the phase noise meter according to the second frequency point to be measured and the second test case information, so that the phase noise meter generates a frequency change curve; where the frequency change curve is the curve of the frequency changing with time during the process of the phase-locked loop to be measured locking the second frequency point to be measured.
[0068] In some embodiments of the present disclosure, the corresponding configuration information can be determined according to the second frequency point to be measured and the second test case information, and the phase noise meter can be controlled based on the configuration information through SCPI control instructions. Among them, the second test case information may include the configuration information corresponding to different frequency points. According to the second frequency point to be measured, the configuration information corresponding to the second frequency point to be measured can be determined. Among them, the configuration information can be pre-determined based on a large number of experiments and may include: trigger source, frequency, threshold, start time, etc., for enabling the phase noise meter to capture the frequency change during the process of the phase-locked loop to be measured locking the second frequency point to be measured and generate a frequency change curve.
[0069] Step 503: Obtain the frequency change curve from the phase noise meter, and determine the stabilization time of the phase-locked loop to be measured at the second frequency point to be measured according to the frequency change curve.
[0070] As a possible implementation, the first time when the phase-locked loop to be measured starts to lock the second frequency point to be measured and the second time when the frequency stabilizes can be determined from the frequency change curve, and the time difference between the first time and the second time is used as the stabilization time of the phase-locked loop to be measured at the second frequency point to be measured. Among them, both the first time and the second time can be determined based on the frequency change rate of each sampling point in the frequency change curve.
[0071] According to the test method of the phase-locked loop in the embodiment of the present disclosure, the second frequency point to be measured is determined according to the second test frequency point information, and the phase-locked loop to be measured is controlled to lock the second frequency point to be measured; the phase noise meter is configured according to the second frequency point to be measured and the second test case information, so that the phase noise meter generates a frequency change curve; the frequency change curve is obtained from the phase noise meter, and the stabilization time of the phase-locked loop to be measured at the second frequency point to be measured is determined according to the frequency change curve. This solution can use only one phase noise meter, and can simultaneously test the phase noise, jitter, spurious and stabilization time of the phase-locked loop, which not only improves the test efficiency but also reduces the test cost.
[0072] In order to improve the test convenience, the test configuration information in the test method of the phase-locked loop in the embodiment of the present disclosure can be determined based on the configuration of the test visualization interface. For this reason, the present disclosure provides another embodiment.
[0073] Figure 6 is a flowchart of another test method of a phase-locked loop shown according to an exemplary embodiment. As Figure 6 shown, based on the above example, Figure 2The implementation process of step 201 in [the relevant context] may include the following steps:
[0074] Step 601, display a test visualization interface; wherein, the test visualization interface is used to configure test parameter information of the phase-locked loop to be tested.
[0075] That is to say, the display interface of the upper computer can display the test visualization interface, and relevant staff can operate the test visualization interface to configure the test parameter information of the phase-locked loop to be tested. For example, the test visualization interface may include a test case selection area, a test scenario selection area, a test adjustment selection area (temperature, frequency, bandwidth, etc.), and may also include a test progress display area to display the ongoing test progress, and may also include a test result display area, and may also include an area for operating the test interface.
[0076] The test visualization interface of the embodiments of the present disclosure can implement functions such as test interface control, test instrument detection, multi-test case selection, multi-test condition configuration, multi-temperature cycle test, test data saving, and test status management. These functions can all be conveniently and quickly set and operated on the UI interface. Thereby, problems such as the need to modify the settings in the script multiple times when the test conditions change, a large amount of script preparation, a low coverage of test cases, and low test efficiency can be avoided.
[0077] Step 602, obtain the configured test parameter information in the test visualization interface, and determine test configuration information based on the test parameter information.
[0078] That is to say, relevant staff configure the test parameter information of the phase-locked loop to be tested on the test visualization interface based on the test requirements. After the configuration is completed, the upper computer obtains the configured test parameter information in the test visualization interface and determines the test configuration information based on the test parameter information.
[0079] In some other embodiments of the present disclosure, in order to improve the convenience of testing, the method may further include:
[0080] Step 603, generate a test template based on the test parameter information.
[0081] Step 604, store the test template so that the stored test template is used as the option content of the test template selection control in the test visualization interface.
[0082] That is to say, a test template can be generated based on the test parameter information in this test, and the generated test template is stored. When relevant staff perform test configuration through the test visualization interface again, they can directly select the stored test template to implement the configuration of test parameters, thereby reducing the workload of test configuration.
[0083] According to the test method of the phase-locked loop according to an embodiment of the present disclosure, a test visualization interface can be displayed, and the configured test parameter information in the test visualization interface can be obtained. Based on the test parameter information, the test configuration information can be determined. That is to say, the parameter information of the phase-locked loop test can be configured based on the visualization interface, which is not only convenient and fast, but also can further improve the test efficiency, avoid the problem of repeatedly modifying the script when the test conditions change, and avoid the problem of low test case coverage rate.
[0084] Figure 7 It is a flowchart of another test method of the phase-locked loop shown according to an exemplary embodiment. As Figure 7 shown, based on the above example, Figure 2 the implementation process of step 201 in
[0085] Step 701, display the test visualization interface; wherein, the test visualization interface includes a test template selection control.
[0086] In some embodiments of the present disclosure, the test template selection control in the test visualization interface is used to select a test template. The options in the test template selection control are the stored test templates. The stored test templates this time can be the test templates stored by relevant staff based on the test visualization interface, can also be the test templates pre-stored by the system, or can also be automatically stored based on historical test configuration information.
[0087] Step 702, obtain the selected test template in the test template selection control, and determine the test configuration information based on the selected test template.
[0088] That is to say, the test parameter configuration information corresponding to the selected test template can be directly called based on the selected test template in the test visualization interface, and the test configuration information can be determined based on the test parameter configuration information corresponding to the selected test template.
[0089] According to the test method of the phase-locked loop according to an embodiment of the present disclosure, a test visualization interface can be displayed, and the selected test template in the test template selection control can be obtained, and the test configuration information can be determined based on the selected test template. That is to say, the parameter information of the phase-locked loop test can be used to select the test template based on the visualization interface, so as to further improve the test efficiency.
[0090] In order to implement the above embodiments, the present disclosure provides a test device for a phase-locked loop.
[0091] Figure 8 It is a structural block diagram of a test device for a phase-locked loop shown according to an exemplary embodiment. As Figure 8As shown, the device includes a first determination module 801, a second determination module 802, a first configuration module 803, and a third determination module 804.
[0092] Among them,
[0093] The first determination module 801 is used to determine the test configuration information of the PLL to be tested; among them, the test configuration information includes the first test frequency point information and the first test case information of multiple first test frequency points to be tested; the first test case information is used to test the first type of indicators of the PLL to be tested;
[0094] The second determination module 802 is used to determine the first test frequency point to be tested according to the first test frequency point information, and control the PLL to be tested to lock the first test frequency point;
[0095] The first configuration module 803 is used to configure the phase noise meter according to the first test frequency point and the first test case information, so that the phase noise meter generates a corresponding phase noise curve, as well as the phase noise data and jitter data of the first test frequency point; among them, the phase noise meter is connected to the PLL to be tested;
[0096] The third determination module 804 is used to obtain the phase noise curve, phase noise data and jitter data from the phase noise meter, and determine the test result of the first type of indicators of the PLL to be tested at the first test frequency point according to the phase noise curve, phase noise data and jitter data.
[0097] In some embodiments of the present disclosure, the test result of the first type of indicators includes the phase noise test result, jitter test result and spurious test result of the first test frequency point; specifically, the third determination module 804 is used for:
[0098] Determine the phase noise data as the phase noise test result;
[0099] Determine the jitter data as the jitter test result;
[0100] Determine the spurious test result according to the phase noise curve.
[0101] As a possible implementation manner, the third determination module 804 is further used for:
[0102] Determine the phase noise change rate of each sampling point in the phase noise curve;
[0103] Determine whether there are spurious points in the sampling points according to the phase noise change rate;
[0104] If there are spurious points in the sampling points, determine the frequency and power of the spurious points from the phase noise curve, and determine the frequency and power of the spurious points as the spurious test result.
[0105] As an example, the third determination module 804 is further used for:
[0106] Compare the phase noise change rate of each sampling point with a preset change rate threshold respectively;
[0107] If the phase noise change rate of the first sampling point among the sampling points is greater than the change rate threshold, determine the first sampling point as a spurious point.
[0108] In some embodiments of the present disclosure, the test configuration information further includes second test frequency point information and second test case information of a plurality of second frequency points to be measured; wherein, the second test case information is used to test the settling time of the PLL to be measured; the apparatus further includes:
[0109] A fourth determination module 805, configured to determine a second frequency point to be measured according to the second test frequency point information, and control the PLL to be measured to lock to the second frequency point to be measured;
[0110] A second configuration module 806, configured to configure the phase noise meter according to the second frequency point to be measured and the second test case information, so that the phase noise meter generates a frequency change curve; wherein, the frequency change curve is a curve of the frequency changing with time during the process of the PLL to be measured locking to the second frequency point to be measured;
[0111] A fifth determination module 807, configured to obtain the frequency change curve from the phase noise meter, and determine the settling time of the PLL to be measured at the second frequency point to be measured according to the frequency change curve.
[0112] As a possible implementation manner, the test configuration information further includes temperature configuration information; the apparatus further includes:
[0113] A first control module 808, configured to control the ambient temperature of the PLL to be measured based on the temperature configuration information.
[0114] In some embodiments of the present disclosure, the first determination module 801 is specifically configured to:
[0115] Display a test visualization interface; wherein, the test visualization interface is used to configure test parameter information of the PLL to be measured;
[0116] Obtain the configured test parameter information in the test visualization interface, and determine test configuration information based on the test parameter information.
[0117] As a possible implementation manner, the apparatus further includes a test template module 809, and the test template module 809 is used for:
[0118] Generate a test template based on the test parameter information;
[0119] Store the test template, so as to use the stored test template as the option content of the test template selection control in the test visualization interface.
[0120] As another possible implementation, the first determination module 801 is further configured to:
[0121] display a test visualization interface; wherein, the test visualization interface includes a test template selection control;
[0122] obtain the selected test template in the test template selection control, and determine test configuration information based on the selected test template.
[0123] Regarding the device in the above embodiments, the specific manners in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated herein.
[0124] According to the test device of the phase-locked loop according to the embodiments of the present disclosure, by determining a first frequency point to be measured according to first test frequency point information, controlling the phase-locked loop to be measured to lock to the first frequency point to be measured, and configuring a phase noise meter according to the first frequency point to be measured and first test case information, so that the phase noise meter generates a corresponding phase noise curve, as well as phase noise data and jitter data of the first frequency point to be measured, and obtaining the phase noise curve, phase noise data and jitter data from the phase noise meter to determine the test result of the first type of index of the phase-locked loop to be measured at the first frequency point to be measured. That is to say, this solution can realize the test of the phase-locked loop only through a phase noise meter, which can reduce the use of instruments, greatly save the test time, and improve the test efficiency.
[0125] To implement the above embodiments, the present disclosure also provides an electronic device.
[0126] Figure 9 It is a block diagram of an electronic device 900 for implementing the test method of the phase-locked loop shown according to an exemplary embodiment. For example, the electronic device 900 may be a device such as a computer, a digital broadcast terminal, a server, etc. As Figure 9 shown, the electronic device 900 includes:
[0127] a memory 910, a processor 920, and a bus 930 connecting different components (including the memory 910 and the processor 920), and the memory 910 stores executable instructions of the processor 920; wherein, the processor 920 is configured to execute the instructions to implement the test method of the phase-locked loop according to the embodiments of the present disclosure.
[0128] The bus 930 represents one or more of several types of bus structures, including a memory bus or a memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any bus structure in a variety of bus structures. For example, these architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.
[0129] The electronic device 900 typically includes a variety of electronic device-readable media. These media can be any available media that can be accessed by the electronic device 900, including volatile and non-volatile media, removable and non-removable media. The memory 910 may also include computer system-readable media in the form of volatile memory, such as random access memory (RAM) 940 and / or cache memory 950. The electronic device 900 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 960 can be used for reading and writing on non-removable, non-volatile magnetic media ( Figure 9 not shown, typically referred to as a "hard disk drive"). Although Figure 9 not shown in, a disk drive for reading and writing on a removable non-volatile disk (such as a "floppy disk") and an optical disk drive for reading and writing on a removable non-volatile optical disk (such as a CD-ROM, DVD-ROM or other optical media) can be provided. In these cases, each drive can be connected to the bus 930 through one or more data media interfaces. The memory 910 may include at least one program product having a set (such as at least one) of program modules that are configured to perform the functions of the embodiments of the present disclosure.
[0130] A program / utility 980 having a set (at least one) of program modules 970 can be stored in, for example, the memory 910. Such program modules 970 include—but are not limited to—an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. The program modules 970 generally perform the functions and / or methods in the embodiments described in the present disclosure.
[0131] The electronic device 900 can also communicate with one or more external devices 990 (such as a keyboard, a pointing device, a display 991, etc.), and can also communicate with one or more devices that enable a user to interact with the electronic device 900, and / or communicate with any device that enables the electronic device 900 to communicate with one or more other computing devices (such as a network card, a modem, etc.). Such communication can be carried out through the input / output (I / O) interface 992. Moreover, the electronic device 900 can also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through the network adapter 993. As shown in the figure, the network adapter 993 communicates with other modules of the electronic device 900 through the bus 930. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in combination with the electronic device 900, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.
[0132] The processor 920 executes various functional applications and data processing by running the programs stored in the memory 910.
[0133] It should be noted that for the implementation process and technical principle of the server in this embodiment, refer to the foregoing explanation of the test method of the phase-locked loop in the embodiments of the present disclosure, which will not be elaborated here.
[0134] To implement the above embodiments, the present disclosure also proposes a storage medium.
[0135] Wherein, when the instructions in the storage medium are executed by the processor of the server, the server can execute the test method of the phase-locked loop as described above.
[0136] To implement the above embodiments, the present disclosure also provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by the processor of the server, it implements the test method of the phase-locked loop as described above.
[0137] Those skilled in the art will readily think of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present invention, which follow the general principles of the present invention and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present invention are pointed out by the following claims.
[0138] It should be understood that the present invention is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.
Claims
1. A test method for a phase-locked loop, characterized in that, Including: Determine the test configuration information of the PLL under test; wherein, the test configuration information includes the first test frequency point information and the first test case information of multiple first test frequency points to be measured; the first test case information is used to test the first type of indicators of the PLL under test; According to the first test frequency point information, determine the first test frequency point to be measured, and control the PLL under test to lock to the first test frequency point; Configure the phase noise meter according to the first test frequency point and the first test case information, so that the phase noise meter generates a corresponding phase noise curve, as well as the phase noise data and jitter data of the first test frequency point; wherein, the phase noise meter is connected to the PLL under test; Obtain the phase noise curve, the phase noise data and the jitter data from the phase noise meter, and determine the test result of the first type of indicators of the PLL under test at the first test frequency point according to the phase noise curve, the phase noise data and the jitter data.
2. The method according to claim 1, wherein The test result of the first type of indicators includes the phase noise test result, the jitter test result and the spurious test result of the first test frequency point; The determining the test result of the first type of indicators of the PLL under test at the first test frequency point according to the phase noise curve, the phase noise data and the jitter data includes: Determine the phase noise data as the phase noise test result; Determine the jitter data as the jitter test result; Determine the spurious test result according to the phase noise curve.
3. The method according to claim 2, wherein The determining the spurious test result according to the phase noise curve includes: Determine the phase noise change rate of each sampling point in the phase noise curve; Determine whether there are spurious points among the sampling points according to the phase noise change rate; If there are spurious points among the sampling points, determine the frequency and power of the spurious points from the phase noise curve, and determine the frequency and power of the spurious points as the spurious test result.
4. The method according to claim 3, wherein The determining whether there are spurious points among the sampling points according to the phase noise change rate includes: Compare the phase noise change rate of each sampling point with a preset change rate threshold respectively; If the phase noise change rate of the first sampling point among the sampling points is greater than the change rate threshold, determine the first sampling point as the spurious point.
5. The method according to claim 1, characterized in that The test configuration information further includes the second test frequency point information and the second test case information of multiple second test frequency points to be measured; wherein, the second test case information is used to test the settling time of the PLL under test; the method further includes: According to the second test frequency point information, determine the second test frequency point to be measured, and control the PLL under test to lock to the second test frequency point; Configure the phase noise meter according to the second test frequency point and the second test case information, so that the phase noise meter generates a frequency change curve; wherein, the frequency change curve is the curve of the frequency changing with time during the process of the PLL under test locking to the second test frequency point; Obtain the frequency change curve from the phase noise meter, and determine the settling time of the PLL under test at the second test frequency point according to the frequency change curve.
6. The method according to claim 1, wherein The test configuration information further includes temperature configuration information; the method further includes: Based on the temperature configuration information, controlling the ambient temperature of the PLL under test.
7. The method according to claim 1, characterized in that, Determining the test configuration information of the PLL under test includes: Displaying a test visualization interface; wherein, the test visualization interface is used to configure the test parameter information of the PLL under test; Obtaining the configured test parameter information in the test visualization interface, and determining the test configuration information based on the test parameter information.
8. The method according to claim 7, wherein The method further includes: Generating a test template based on the test parameter information; Storing the test template so that the stored test template is used as the option content of the test template selection control in the test visualization interface.
9. The method according to claim 1, characterized in that, Determining the test configuration information of the PLL under test includes: Displaying a test visualization interface; wherein, the test visualization interface includes a test template selection control; Obtaining the selected test template in the test template selection control, and determining the test configuration information based on the selected test template.
10. A test device for a phase-locked loop, characterized in that, Includes: A first determination module, configured to determine the test configuration information of the PLL under test; wherein, the test configuration information includes first test frequency point information and first test case information of a plurality of first test frequency points to be measured; the first test case information is used to test the first type of indicators of the PLL under test; A second determination module, configured to determine the first test frequency point to be measured according to the first test frequency point information, and control the PLL under test to lock the first test frequency point; A first configuration module, configured to configure a phase noise meter according to the first test frequency point and the first test case information, so that the phase noise meter generates a corresponding phase noise curve, as well as phase noise data and jitter data of the first test frequency point; wherein, the phase noise meter is connected to the PLL under test; A third determination module, configured to obtain the phase noise curve, the phase noise data and the jitter data from the phase noise meter, and determine the test result of the first type of indicators of the PLL under test at the first test frequency point according to the phase noise curve, the phase noise data and the jitter data.
11. The device according to claim 10, characterized in that, The test result of the first type of indicators includes the phase noise test result, the jitter test result and the spurious test result of the first test frequency point; specifically, the third determination module is configured to: Determine the phase noise data as the phase noise test result; Determine the jitter data as the jitter test result; Determine the spurious test result according to the phase noise curve.
12. The device according to claim 11, wherein The third determination module is further configured to: Determine the phase noise change rate of each sampling point in the phase noise curve; Determine whether there are spurious points in the sampling points according to the phase noise change rate; If there are spurious points in the sampling points, determine the frequency and power of the spurious points from the phase noise curve, and determine the frequency and power of the spurious points as the spurious test result.
13. The device according to claim 12, wherein The third determination module is further configured to: Compare the phase noise change rate of each sampling point with a preset change rate threshold respectively; If the phase noise change rate of the first sampling point among the sampling points is greater than the change rate threshold, determine the first sampling point as the spurious point.
14. The device according to claim 10, wherein The test configuration information further includes second test frequency point information and second test case information for a plurality of second frequency points to be measured; wherein, the second test case information is used to test the settling time of the PLL to be measured; the apparatus further includes: A fourth determination module, configured to determine a second frequency point to be measured according to the second test frequency point information, and control the PLL to be measured to lock to the second frequency point to be measured; A second configuration module, configured to configure the phase noise meter according to the second frequency point to be measured and the second test case information, so that the phase noise meter generates a frequency change curve; wherein, the frequency change curve is a curve of the frequency change of the PLL to be measured with time during the process of locking to the second frequency point to be measured; A fifth determination module, configured to obtain the frequency change curve from the phase noise meter, and determine the settling time of the PLL to be measured at the second frequency point to be measured according to the frequency change curve.
15. The device according to claim 10, characterized in that, The test configuration information further includes temperature configuration information; the apparatus further includes: A first control module, configured to control the ambient temperature of the PLL to be measured based on the temperature configuration information.
16. The device according to claim 10, characterized in that The first determination module is specifically configured to: Display a test visualization interface; wherein, the test visualization interface is used to configure test parameter information of the PLL to be measured; Obtain the configured test parameter information in the test visualization interface, and determine the test configuration information based on the test parameter information.
17. The device according to claim 16, characterized in that, The apparatus further includes a test template module, and the test template module is used for: Generating a test template based on the test parameter information; Storing the test template, so as to use the stored test template as the option content of the test template selection control in the test visualization interface.
18. The device according to claim 10, characterized in that, The first determination module is further used for: Displaying a test visualization interface; wherein, the test visualization interface includes a test template selection control; Obtaining the selected test template in the test template selection control, and determining the test configuration information based on the selected test template.
19. An electronic device, characterized in that, Including: A memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the computer program, the method according to any one of claims 1 to 9 is implemented.
20. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the method according to any one of claims 1 to 9 is implemented.