LDO (Low Dropout Regulator) circuit with fast transient response
By combining the design error amplifier, drive stage and differential transient enhancement module, the loop stability and transient response problems of off-chip capacitor LDO circuits are solved, and rapid response and stability improvement are achieved. It is suitable for mobile devices, high-performance computing and RF communications and other fields.
Patent Information
- Application Number
- CN202510619159.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-14
- Publication Date
- 2025-07-25
AI Technical Summary
Off-chip capacitor LDO circuits have difficulties in loop stability and fast transient response, especially in the fields of mobile devices, high-performance computing and RF communications. Traditional off-chip capacitor designs occupy a large area of layout and are unstable ESR.
The combined design of error amplifier module, drive stage module, feedforward amplifier loop module, resistance feedback network and differential transient enhancement module is adopted. The cross-coupled level shifter generates dynamic current, enhances the loop response speed and gain, and improves the transient response and stability of the circuit through the dual negative feedback loop drive stage and the differential transient enhancement module.
It achieves rapid transient response and loop stability improvement, reduces the layout area requirement, and at the same time improves the dynamic current and gain of the circuit, enhancing the stability and power supply rejection ratio of the system.
Smart Images
Figure CN120371072A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to an LDO circuit with fast transient response. Background Art
[0002] With the daily upgrading of electronic products, the demand for power management strategies is becoming increasingly important. The demand for power supply stability and response speed of various electronic devices is growing, especially in the fields of mobile devices, high-performance computing, and radio frequency communication. As an important power management device, the low dropout regulator (LDO) is widely used in these fields due to its simple circuit structure and low noise characteristics.
[0003] For the traditional LDO with an external capacitor, the output pole is pulled to a low frequency due to the external large capacitor and fixed as the dominant pole. And due to the existence of the equivalent series resistance (ESR) of the external capacitor, a left half-plane zero will be generated, thereby compensating the phase margin and improving the stability of the circuit. At the same time, due to the effect of the external large capacitor storing electrical energy, the LDO will also have good transient characteristics. However, the large external capacitor brings the following problems: First, the large external capacitor will naturally occupy a large layout area, which does not conform to the trend of chip integration development; second, the equivalent series resistance brought by the ESR is greatly affected by temperature and cannot maintain a stable value, which will pose a hidden danger to the working state of the circuit.
[0004] Although the absence of an external capacitor can greatly reduce the layout area, the lack of the assistance of the external capacitor will naturally bring problems such as fast transient response and loop stability. Therefore, the design difficulty of the LDO without an external capacitor lies in loop stability compensation and achieving high transient response at a low static current. Summary of the Invention
[0005] Object of the Invention: The object of the present invention is to provide an LDO circuit with fast transient response, so as to improve the loop response speed and gain and increase the stability of the system.
[0006] Technical Solution: An LDO circuit with fast transient response includes an error amplifier module, a driver stage module, a power transistor, a feedforward amplification loop module, a resistor feedback network, and a differentiator transient enhancement module; the error amplifier module compares the feedback voltage transmitted by the resistor feedback network with the externally connected reference voltage and outputs a control voltage; the power transistor module is responsible for providing the current required by the load; the driver stage module quickly charges and discharges the gate of the power transistor to accelerate the node slew rate and split the low-frequency poles at the same time, improving the loop stability; the resistor feedback network feeds back the output voltage to the error amplifier module according to the feedback ratio; the differentiator transient enhancement module realizes the rapid change of the voltage of the large-capacitance node in the loop.
[0007] The non-inverting input terminal of the error amplifier module is connected to the external reference voltage VREF, and the inverting input terminal is connected to the feedback voltage of the resistor feedback network; the output terminal of the error amplifier is connected to the input terminal of the buffer in the driving stage module; the output terminal of the driving stage module is connected to the gate of the power transistor; the differentiator transient enhancement module is arranged between the output terminal Vout of the LDO circuit and the error amplifier module; the driving stage module and the power transistor are respectively connected to the error amplifier module through the feedforward amplification loop module, and a frequency compensation module is also arranged between the error amplifier module and the output terminal Vout of the LDO circuit.
[0008] Further, the error amplifier module includes PMOS transistor M1, PMOS transistor M2, PMOS transistor M5, PMOS transistor M6, PMOS transistor M15, NMOS transistor M3, NMOS transistor M4, NMOS transistors (M7 to M14), NMOS transistor M16, first resistor R1, and first capacitor C1. The sources of PMOS transistor M1, PMOS transistor M2, PMOS transistor M5, PMOS transistor M6, NMOS transistor M11, NMOS transistor M12, and PMOS transistor M15 are connected to the power supply voltage VDD. The source-gate of PMOS transistor M1 / PMOS transistor M2 and the drain of PMOS transistor M1 are both connected to the drain of NMOS transistor M3. The drain of PMOS transistor M2, the gate of PMOS transistor M15, and the drain of NMOS transistor M4 are connected. The reference voltage VREF is connected to the gates of NMOS transistor M3 / NMOS transistor M7. The gates of NMOS transistor M4 / NMOS transistor M8 are connected to the feedback voltage output terminal FB of the resistor feedback network. The gates of PMOS transistor M5 / PMOS transistor M6 are connected to the externally supplied bias voltage VP1. The drains of PMOS transistor M5 / NMOS transistor M7 are connected to the gate of NMOS transistor M11. The drains of PMOS transistor M6 / NMOS transistor M8 are connected to the gate of NMOS transistor M12. The sources of NMOS transistor M4 / NMOS transistor M7 are connected to the drain of NMOS transistor M9. The sources of NMOS transistor M3 / NMOS transistor M8 are connected to the drain of NMOS transistor M10. The source of NMOS transistor M11, the drain of NMOS transistor M13, and the gate of NMOS transistor M9 are connected. The source of NMOS transistor M12, the drain of NMOS transistor M14, and the gates of NMOS transistor M10 / NMOS transistor M16 are connected. The gates of NMOS transistor M13 / NMOS transistor M14 are connected to the externally supplied bias voltage VN1. The sources of NMOS transistor M9, NMOS transistor M10, NMOS transistor M13, NMOS transistor M14, and NMOS transistor M16 are grounded. The drains of PMOS transistor M15 / NMOS transistor M16 are connected to the error amplifier output terminal. The first capacitor C1 is connected in series with the first resistor R1 and is placed between the gate and the drain of PMOS transistor M15. The drain of PMOS transistor M1 is connected to the feedback current Ifb1 from the differentiator transient enhancement module, and the drain of PMOS transistor M2 is connected to the feedback current Ifb2 from the differentiator transient enhancement module.
[0009] Further, in the static state, NMOS transistors M3, M4, M7, and M8 have the same static current. When an input differential signal is applied, due to the voltage level shifting effect of NMOS transistors M7 and M8, the source voltages of NMOS transistors M3 and M4 change synchronously and reversely, increasing the dynamic change of the gate-source voltage VGS of NMOS transistors M3 and M4, exponentially increasing the dynamic current of NMOS transistors M3 and M4, and achieving the performance of a large dynamic current.
[0010] Among them, NMOS transistors M11, M12, M13, and M14 form a pair of source followers to constitute a FVF structure, providing an adaptive bias for NMOS transistors M9 and M10.
[0011] Furthermore, the driver stage module includes PMOS transistors M17, M21, M22, NMOS transistors M18 to M20, a second capacitor C2, and a second resistor R2. The source of PMOS transistor M21 / PMOS transistor M22 is connected to the power supply voltage VDD, and the gate of PMOS transistor M21 is connected to the externally supplied bias voltage VP1. The drain of PMOS transistor M21, the gate of PMOS transistor M22, and the drain of NMOS transistor M20 are connected. The gate of PMOS transistor M17 is connected to the output terminal of the error amplifier module as the input terminal of the driver stage module. The source of PMOS transistor M17, the drain of NMOS transistor M19, and the drain of PMOS transistor M22 are connected as the output terminal of the driver stage module. The gate of NMOS transistor M20 is connected to the gate of NMOS transistor M12 to transmit the received feedforward amplified signal. The drain of PMOS transistor M17, the gate of NMOS transistor M19, and the source of NMOS transistor M20 are connected. The source of NMOS transistor M18 / NMOS transistor M19 is grounded. The gate of NMOS transistor M18 is connected to the gate of NMOS transistor M9 to transmit the feedforward amplified signal. The second capacitor C2 and the second resistor R2 are connected in series between the gate of PMOS transistor M22 and the power supply voltage VDD.
[0012] Furthermore, PMOS transistor M17, NMOS transistor M18, and NMOS transistor M19 form an SSF feedback loop. When the input voltage instantaneously drops and the output terminal of the driver stage module needs to quickly discharge, the gate-source voltage VGS of PMOS transistor M17 instantaneously increases. When the input voltage instantaneously rises, the gate voltage of NMOS transistor M19 instantaneously drops, and the current of NMOS transistor M19 decreases or even turns off.
[0013] PMOS transistor M17, NMOS transistor M20, PMOS transistor M21, and PMOS transistor M22 form a FVF structure. When the input voltage instantaneously rises and the output terminal of the driver stage module needs to quickly charge, the gate-source voltage VGS of PMOS transistor M17 instantaneously decreases. When the input voltage instantaneously drops, the conduction current of PMOS transistor M22 instantaneously decreases or even turns off.
[0014] Further, the differentiator transient enhancement module includes seven NMOS transistors M26 to M29, M34 to M36; seven PMOS transistors M23 to M25, M30 to M33; and a sixth capacitor C6. One end of the sixth capacitor C6 is connected to the feedback voltage output terminal FB of the resistor feedback network, and the other end is connected to the gate of the NMOS transistor M24. The sources of the NMOS transistors M23, M30 to M33, M35, and M38 are grounded. The gate of the NMOS transistor M23 is connected to the external bias voltage VN1. The sources of the NMOS transistors M23, M30 to M33 are grounded. The gate of the NMOS transistor M23 is connected to the external bias voltage VN1. The drain of the NMOS transistor M23 is connected to the sources of the NMOS transistors M24 / M25. The gate of the NMOS transistor M24 is connected to the drain of the PMOS transistor M26. The drain of the NMOS transistor M24, the gate of the PMOS transistor M28, the drain and gate of the PMOS transistor M26 are connected. The drain of the NMOS transistor M25, the gate of the NMOS transistor M29, the drain and gate of the NMOS transistor M27 are connected. The gate of the NMOS transistor M25 is connected to the reference voltage VREF. The sources of the PMOS transistors M26 to M29, M34, M37, M39, and M40 are connected to the power supply voltage VDD. The drain of the PMOS transistor M29, the gate of the NMOS transistor M31, the gate and drain of the NMOS transistor M30, and the drain of the NMOS transistor M32 are connected. The drain of the PMOS transistor M28, the gate of the NMOS transistor M32, the gate and drain of the NMOS transistor M33, and the drain of the NMOS transistor M31 are connected to the gate of the NMOS transistor M35. The gates of the PMOS transistors M34, M36, and M37 are connected to the external bias voltage VP1. The drain of the NMOS transistor M35, the drain of the PMOS transistor M34, the source of the PMOS transistor M36, and the gate of the NMOS transistor M38 are connected. The drain of the NMOS transistor M38, the drain of the PMOS transistor M37, the gate of the PMOS transistor M39, and the gate of the PMOS transistor M40 are connected. The drain of the PMOS transistor M39 is connected to the feedback output terminal Ifb1, and the drain of the PMOS transistor M40 is connected to the feedback output terminal Ifb2.
[0015] Compared with the prior art, the present invention has the following remarkable effects:
[0016] 1. The error amplifier of the present invention uses a pair of cross-coupled level shifters to generate a dynamic current that is not controlled by the static bias current, so as to improve the slew rate of the internal nodes of the circuit; at the same time, the static bias current source inside the loop is converted into a feedforward amplified bias, thereby improving the loop response speed and gain;
[0017] 2. Compared with the traditional driver stage, the double negative feedback loop type driver stage of the present invention has stronger driving ability and can track the change of the input voltage faster, thereby improving the transient response of the circuit; the differentiator slew rate enhancement module can help the node voltage in the loop change rapidly, thereby improving the transient response of the LDO circuit, and the differentiator can avoid mis-triggering caused by low-frequency noise to a certain extent and increase the stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 It is a circuit structure block diagram of the LDO in the present invention;
[0019] Figure 2 It is the main circuit diagram of the LDO in the present invention;
[0020] Figure 3 It is the differentiator slew rate enhancement circuit diagram in the present invention;
[0021] Figure 4 It is a schematic diagram of the dynamic current of the error amplifier in the present invention;
[0022] Figure 5 It is a schematic diagram of the loop gain and loop phase of the LDO in the present invention;
[0023] Figure 6 It is a transient response curve diagram of the LDO in the present invention. DETAILED DESCRIPTION OF THE INVENTION
[0024] The present invention will be further described in detail below with reference to the accompanying drawings of the specification and specific embodiments.
[0025] As Figure 1 shown, the fast transient LDO circuit of the present invention includes an error amplifier (Error Amplifie) module, a driver stage module, a power transistor, a feedforward amplification loop module, a resistor feedback network, and a differentiator transient enhancement module. Among them, the resistor feedback network is responsible for feeding back the output voltage to the error amplifier module according to the feedback ratio; the error amplifier module is responsible for comparing the feedback voltage transmitted by the resistor feedback network with the externally connected reference voltage and outputting a control voltage. The driver stage module is responsible for quickly charging and discharging the gate of the power transistor, accelerating the node slew rate, splitting the low-frequency poles at the same time, and improving the loop stability; the differentiator transient enhancement module helps the large-capacitance node voltage in the loop change rapidly, thereby improving the transient characteristics of the LDO circuit. The power transistor module is responsible for providing the current required by the load. The resistor feedback network is responsible for adjusting the feedback coefficient to stabilize the output voltage.
[0026] As Figure 1As shown, the external reference voltage VREF is connected to the positive input terminal of the error amplifier module; the feedback voltage of the resistor feedback network is connected to the negative input terminal of the error amplifier module; the output terminal 3 of the error amplifier is connected to the input of the buffer (BUFFER) in the driver stage module; the output terminal 7 of the driver stage module is connected to the gate of the power transistor; the differentiator transient enhancement module is connected between the output Vout of the LDO circuit and the error amplifier module; a feedforward amplification loop module and a frequency compensation module are also connected between the error amplifier module, the driver stage module and the power transistor.
[0027] As Figure 2As shown, the error amplifier module includes PMOS transistors M1, M2, M5, M6, M15; NMOS transistors M3, M4, (M7 to M14), M16; a first resistor R1; and a first capacitor C1. Among them, the sources of PMOS transistors M1, M2, M5, M6, NMOS transistors M11, M12, and PMOS transistor M15 are connected to the power supply voltage VDD; the source-gates of PMOS transistors M1 / PMOS transistor M2, the drain of PMOS transistor M1, and the drain of NMOS transistor M3 are connected; the drain of PMOS transistor M2, the gate of PMOS transistor M15, and the drain of NMOS transistor M4 are connected; the reference voltage VREF is connected to the gates of NMOS transistors M3 / NMOS transistor M7; the gates of NMOS transistors M4 / NMOS transistor M8 are connected to the feedback voltage output terminal FB of the resistor feedback network; the gates of PMOS transistors M5 / PMOS transistor M6 are connected to the externally supplied bias voltage VP1; the drains of PMOS transistor M5 / NMOS transistor M7 and the gate of NMOS transistor M11 are connected; the drains of PMOS transistor M6 / NMOS transistor M8 and the gate of NMOS transistor M12 are connected; the sources of NMOS transistors M4 / NMOS transistor M7 and the drain of NMOS transistor M9 are connected; the sources of NMOS transistors M3 / NMOS transistor M8 and the drain of NMOS transistor M10 are connected; the source of NMOS transistor M11, the drain of NMOS transistor M13, and the gate of NMOS transistor M9 are connected; the source of NMOS transistor M12, the drain of NMOS transistor M14, and the gates of NMOS transistors M10 / NMOS transistor M16 are connected; the gates of NMOS transistors M13 / NMOS transistor M14 are connected to the externally supplied bias voltage VN1; the sources of NMOS transistors M9, M10, M13, M14, M16 are grounded; the drains of PMOS transistor M15 / NMOS transistor M16 are connected to the error amplifier output terminal 3; the first capacitor C1 is connected in series with the first resistor R1 and placed between the gate and the drain of PMOS transistor M15; the drain of PMOS transistor M1 is connected to the feedback current Ifb1 from the differentiator transient enhancement module, and the drain of PMOS transistor M2 is connected to the feedback current Ifb2 from the differentiator transient enhancement module.
[0028] The drive stage module includes three PMOS transistors (M17, M21, M22); three NMOS transistors M18 to M20; a second capacitor C2; and a second resistor R2. Among them, the sources of PMOS transistor M21 / PMOS transistor M22 are connected to the power supply voltage VDD; the gate of PMOS transistor M21 is connected to the externally supplied bias voltage VP1; the drain of PMOS transistor M21, the gate of PMOS transistor M22, and the drain of NMOS transistor M20 are connected; the gate of PMOS transistor M17 is connected to the output terminal 3 of the error amplifier module, serving as the input terminal 5 of the drive stage module; the source of PMOS transistor M17, the drain of NMOS transistor M19, and the drain of PMOS transistor M22 are connected, serving as the output terminal 7 of the drive stage module; the gate of NMOS transistor M20 is connected to the gate of NMOS transistor M12 in the error amplifier to transmit the received feedforward amplified signal; the drain of PMOS transistor M17, the gate of NMOS transistor M19, and the source of NMOS transistor M20 are connected; the sources of NMOS transistor M18 / NMOS transistor M19 are grounded; the gate of NMOS transistor M18 is connected to the gate of NMOS transistor M9 in the error amplifier to transmit the feedforward amplified signal. The second capacitor C2 and the second resistor R2 are connected in series and placed between the gate of PMOS transistor M22 and the power supply voltage VDD.
[0029] Such as Figure 3As shown, the differentiator transient enhancement module includes seven NMOS transistors M26 - M29, M34 - M36; seven PMOS transistors M23 - M25, M30 - M33; and a sixth capacitor C6. One end of the sixth capacitor C6 is connected to the feedback voltage output terminal FB of the resistor feedback network, and the other end is connected to the gate of the NMOS transistor M24; the sources of the NMOS transistors M23, M30 - M33, M35, M38 are grounded; the gate of the NMOS transistor M23 is connected to the external bias voltage VN1; the sources of the NMOS transistors M23, M30 - M33 are grounded; the gate of the NMOS transistor M23 is connected to the external bias voltage VN1; the drains of the NMOS transistor M23, the source of the NMOS transistor M24, and the source of the NMOS transistor M25 are connected; the gate of the NMOS transistor M24 is connected to the drain of the PMOS transistor M26; the drain of the NMOS transistor M24, the gate of the PMOS transistor M28, the drain and gate of the PMOS transistor M26 are connected; the drain of the NMOS transistor M25, the gate of the NMOS transistor M29, the drain and gate of the NMOS transistor M27 are connected; the gate of the NPMOS transistor M25 is connected to the reference voltage VREF; the sources of the PMOS transistors M26 - M29, M34, M37, M39, M40 are connected to the power supply voltage VDD; the drain of the PMOS transistor M29, the gate of the NMOS transistor M31, the gate and drain of the NMOS transistor M30, and the drain of the NMOS transistor M32 are connected; the drain of the PMOS transistor M28, the gate of the NMOS transistor M32, the gate and drain of the NMOS transistor M33, the drain of the NMOS transistor M31 are connected to the gate of the NMOS transistor M35; the gates of the PMOS transistors M34, M36, M37 are connected to the external bias voltage VP1; the drain of the NMOS transistor M35, the drain of the PMOS transistor M34, the source of the PMOS transistor M36 are connected to the gate of the NMOS transistor M38; the drain of the NMOS transistor M38, the drain of the PMOS transistor M37, the gate of the PMOS transistor M39, and the gate of the PMOS transistor M40 are connected; the drain of the PMOS transistor M39 is connected to the feedback output terminal Ifb1, and the drain of the PMOS transistor M40 is connected to the feedback output terminal Ifb2.
[0030] For the error amplifier, a pair of cross-coupled level shifters are used to achieve low quiescent current and high dynamic current. At quiescence, NMOS transistors M3, M4, M7, and M8 have the same quiescent current. When an input differential signal is applied, due to the level shifting effect of NMOS transistors M7 and M8, the source voltages of NMOS transistors M3 and M4 change synchronously and in opposite directions, thereby increasing the dynamic change in the gate-source voltage VGS of the input pair of NMOS transistors M3 and M4, exponentially increasing the dynamic current of NMOS transistors M3 and M4, and thus achieving the performance of large dynamic current. For small signals, due to the dynamic increase in VGS, the transconductance of the current can also be increased, achieving an increase in gain.
[0031] Among them, NMOS transistors M11, M12, M13, and M14 form a pair of source followers, constituting an FVF (Flipped Voltage Follower) structure, providing adaptive biasing for NMOS transistors M9 and M10. Compared with the traditional direct feedback connection method, using source followers can greatly increase the input range of the amplifier. At the same time, it can provide a feedforward signal for the subsequent stage circuit, achieving an improvement in the transient characteristics of the overall circuit.
[0032] For the driver stage module, the present invention adopts a method combining the SSF (Super Source Follower) structure and the FVF structure, and at the same time introduces a feedforward amplified signal to further enhance the transient characteristics.
[0033] Among them, PMOS transistor M17, NMOS transistors M18, and M19 form an SSF feedback loop. When the input voltage drops instantaneously and the output terminal 7 of the driver stage module needs to discharge quickly, at this time, the gate-source voltage VGS of PMOS transistor M17 (as the input transistor) increases instantaneously. Since PMOS transistor M17 and NMOS transistor M18 form a common-gate amplifier, the gate voltage of NMOS transistor M19 increases instantaneously, and the conduction current of NMOS transistor M19 increases instantaneously, helping the output terminal 7 of the driver stage module to discharge quickly, achieving a large pull-down current. On the contrary, when the input voltage rises instantaneously, the gate voltage of NMOS transistor M19 drops instantaneously, and the current of NMOS transistor M19 decreases or even turns off, helping the output terminal 7 of the driver stage module to charge to a certain extent.
[0034] The PMOS transistor M17, NMOS transistor M20, PMOS transistor M21, and PMOS transistor M22 form an FVF structure. When the input voltage rises instantaneously and the output terminal 7 of the driving stage module needs to be quickly charged, at this time, the gate-source voltage VGS of the NMOS transistor M17 decreases instantaneously. Since the PMOS transistor M17 and NMOS transistor M18 form a common-gate amplifier, the source voltage of the NMOS transistor M20 decreases instantaneously. This signal is amplified through the common-source amplifier of the NMOS transistor M20 and PMOS transistor M21 and transmitted to the gate of the PMOS transistor M22, causing the gate voltage of the PMOS transistor M22 to decrease instantaneously, and the current passing through the PMOS transistor M22 to increase instantaneously, realizing the rapid charging of the output terminal 7 of the driving stage module. On the contrary, when the input voltage drops instantaneously, the on-current of the PMOS transistor M22 decreases instantaneously or even turns off, helping the output terminal 7 of the driving stage module to discharge to a certain extent.
[0035] Since the common-gate amplifier formed by the NMOS transistor M20 and PMOS transistor M21 in the FVF loop will introduce a low-frequency pole, the second resistor R2 and second capacitor C2 are added to introduce a zero point to compensate for the frequency.
[0036] For the frequency compensation of the overall circuit, a first capacitor C1 and first resistor R1 are set inside the error amplifier for Miller compensation; a third capacitor C3 and third resistor R3 are connected between the LDO output terminal Vout and the output terminal of the error amplifier for Miller compensation; a fourth capacitor C4 and fourth resistor R4 are connected between the LDO output terminal and the output terminal 7 of the driving stage module for Miller compensation; a feedforward capacitor C5 is connected in parallel across the feedback resistor R5 to generate a zero point to compensate the phase margin. By adjusting the values of the resistors and capacitors, the positions of the various zero and pole points inside the loop are adjusted to ensure the stability of the loop.
[0037] For the feedforward amplification loop module, in a general circuit without feedforward, the gates of the NMOS transistor M16 in the error amplifier, the NMOS transistor M20 in the driving stage module, and the NMOS transistor M18 are respectively connected to the externally provided bias voltages. In this way, the dynamic current of the circuit will be limited, and the gain is also low. In the present invention, the gate of the NMOS transistor M16 is connected to the gate of the NMOS transistor M10 in the FVF structure; the gate of the NMOS transistor M20 is connected to the gate of the NMOS transistor M12 in the FVF structure in the error amplifier; the gate of the NMOS transistor M18 is connected to the gate of the NMOS transistor M9 in the FVF structure of the error amplifier, thereby realizing signal feedforward.
[0038] The NMOS transistor M16 and NMOS transistor M10 form a pair of current mirrors. When there is a differential signal input, the NMOS transistor M10 is self-adaptively biased, and the large dynamic current from the NMOS transistor M3 is copied by the NMOS transistor M16, realizing the rapid pull-down or rise of the output terminal voltage.
[0039] Similarly, NMOS transistors M18 and M20 respectively receive small signals from NMOS transistors M9 and M12, bypass PMOS transistor M15, NMOS transistor M16, and PMOS transistor M17 for signal feedforward, achieving fast signal transmission and improving the transient response speed of the circuit.
[0040] At the same time, the feedforward amplification loop module and the main path form a push-pull relationship, greatly enhancing the gain of the loop. The level shift structure and self-adaptive bias structure in the FVF structure also well solve the input range problem in the push-pull structure, greatly increasing the operating voltage range.
[0041] It is worth mentioning that since the feedforward amplification loop module improves the low-frequency gain, the LDO of the present invention also has good performance in terms of PSRR (Power Supply Rejection Ratio).
[0042] For the differentiator transient enhancement module, seven PMOS transistors M26 - M29, M34 - M36; and seven NMOS transistors M23 - M25, M30 - M33 form a hysteresis comparator. Among them, NMOS transistors M23 - M25 and PMOS transistors M26 - M27 are pre-amplification circuits, which can improve the sensitivity of the comparator and isolate noise to prevent crosstalk; PMOS transistors M28 - M29 and NMOS transistors M30 - M33 form a positive feedback circuit, whose function is to lock in a larger input signal and further amplify its change. The aspect ratio of NMOS transistors M31 and M32 determines the threshold voltage; it is worth mentioning that it is necessary to ensure that the aspect ratio of NMOS transistors M31 and M32 is greater than that of NMOS transistors M30 and M32 to achieve hysteresis amplification; PMOS transistor M34 and NMOS transistor M35 are amplification buffer stages, which can increase the amplification factor and expand the output voltage range; NMOS transistor M38, PMOS transistor M39, and PMOS transistor M40 are current feedback structures, whose function is to generate compensation currents Ifb1 and Ifb2 after receiving the working signal.
[0043] The theoretical dynamic current of the input transistor of the error amplifier of the present invention:
[0044]
[0045] Among them, V GS is the gate-source voltage of the input transistor at static, V TH is the threshold voltage; β = μ n C OX (W / L) is the conduction coefficient, μ n is the carrier mobility, C OXis the capacitance per unit area of the gate oxide layer, W / L is the width-to-length ratio of the input transistor, and I b1 is the given bias current of the input transistor.
[0046] The simulation results are as Figure 4 shown. The currents of the NMOS transistors M3 and M4, which are the input pair of the error amplifier, increase with the increase of the differential input voltage, which is consistent with the theoretical derivation.
[0047] The loop gain and loop phase curves of the LDO circuit are as Figure 5 shown. The obtained loop bandwidth is 17.75 MHz and the loop margin is 61.3°, which can keep the system stable.
[0048] The transient response curve is as Figure 6 shown. The blue curve is the transient response curve without the differentiator transient enhancement module, and the red curve is the transient response curve with the differentiator transient enhancement module added. It can be seen from this that the differentiator transient response enhancement module can effectively reduce the overshoot voltage.
Claims
1. An LDO circuit with fast transient response, characterized in that, It includes an error amplifier module, a driver stage module, a power transistor, a feedforward amplification loop module, a resistor feedback network, and a differentiator transient enhancement module; the error amplifier module compares the feedback voltage transmitted by the resistor feedback network with the externally connected reference voltage and outputs a control voltage; the power transistor module is responsible for providing the current required by the load; the driver stage module quickly charges and discharges the gate of the power transistor to accelerate the node slew rate, and at the same time splits the low-frequency poles to improve the loop stability; the resistor feedback network feeds back the output voltage to the error amplifier module according to the feedback ratio; the differentiator transient enhancement module enables the voltage of the large-capacitance node in the loop to change rapidly; the non-inverting input terminal of the error amplifier module is connected to the external reference voltage VREF, and the inverting input terminal is connected to the feedback voltage of the resistor feedback network; the output terminal (3) of the error amplifier is connected to the input terminal of the buffer in the driver stage module; the output terminal (7) of the driver stage module is connected to the gate of the power transistor; the differentiator transient enhancement module is arranged between the output terminal Vout of the LDO circuit and the error amplifier module; the driver stage module and the power transistor are respectively connected to the error amplifier module through the feedforward amplification loop module, and a frequency compensation module is also arranged between the error amplifier module and the output terminal Vout of the LDO circuit.
2. The LDO circuit with fast transient response according to claim 1, wherein The error amplifier module includes PMOS transistor M1, PMOS transistor M2, PMOS transistor M5, PMOS transistor M6, PMOS transistor M15, NMOS transistor M3, NMOS transistor M4, NMOS transistors (M7 to M14), NMOS transistor M16, first resistor R1, and first capacitor C1. Among them, the sources of PMOS transistor M1, PMOS transistor M2, PMOS transistor M5, PMOS transistor M6, NMOS transistor M11, NMOS transistor M12, and PMOS transistor M15 are connected to the power supply voltage VDD. The source-gate of PMOS transistor M1 / PMOS transistor M2 and the drain of PMOS transistor M1 are both connected to the drain of NMOS transistor M3. The drain of PMOS transistor M2, the gate of PMOS transistor M15, and the drain of NMOS transistor M4 are connected. The reference voltage VREF is connected to the gates of NMOS transistor M3 / NMOS transistor M7. The gates of NMOS transistor M4 / NMOS transistor M8 are connected to the feedback voltage output terminal FB of the resistor feedback network. The gates of PMOS transistor M5 / PMOS transistor M6 are connected to the externally supplied bias voltage VP1. The drains of PMOS transistor M5 / NMOS transistor M7 are connected to the gate of NMOS transistor M11. The drains of PMOS transistor M6 / NMOS transistor M8 are connected to the gate of NMOS transistor M12. The sources of NMOS transistor M4 / NMOS transistor M7 are connected to the drain of NMOS transistor M9. The sources of NMOS transistor M3 / NMOS transistor M8 are connected to the drain of NMOS transistor M10. The source of NMOS transistor M11, the drain of NMOS transistor M13, and the gate of NMOS transistor M9 are connected. The source of NMOS transistor M12, the drain of NMOS transistor M14, and the gates of NMOS transistor M10 / NMOS transistor M16 are connected. The gates of NMOS transistor M13 / NMOS transistor M14 are connected to the externally supplied bias voltage VN1. The sources of NMOS transistor M9, NMOS transistor M10, NMOS transistor M13, NMOS transistor M14, and NMOS transistor M16 are grounded. The drains of PMOS transistor M15 / NMOS transistor M16 are connected to the error amplifier output terminal (3). The first capacitor C1 is connected in series with the first resistor R1 and placed between the gate and drain of PMOS transistor M15. The drain of PMOS transistor M1 is connected to the feedback current Ifb1 from the differentiator transient enhancement module, and the drain of PMOS transistor M2 is connected to the feedback current Ifb2 from the differentiator transient enhancement module.
3. The LDO circuit with fast transient response according to claim 2, wherein In the static state, NMOS transistors M3, M4, M7, and M8 have the same static current. When an input differential signal is applied, due to the voltage level shifting effect of NMOS transistors M7 and M8, the source voltages of NMOS transistors M3 and M4 change synchronously and in opposite directions, increasing the dynamic change in the gate-source voltage VGS of NMOS transistors M3 and M4, exponentially increasing the dynamic current of NMOS transistors M3 and M4, and achieving the performance of a large dynamic current. Among them, NMOS transistors M11, M12, M13, and M14 form a pair of source followers, constituting an FVF structure to provide adaptive biasing for NMOS transistors M9 and M10.
4. The LDO circuit with fast transient response according to claim 1, characterized in that, The driver stage module includes PMOS transistors M17, M21, M22, NMOS transistors M18 to M20, a second capacitor C2, and a second resistor R2. The source of PMOS transistor M21 / PMOS transistor M22 is connected to the power supply voltage VDD, and the gate of PMOS transistor M21 is connected to the externally supplied bias voltage VP1. The drain of PMOS transistor M21, the gate of PMOS transistor M22, and the drain of NMOS transistor M20 are connected. The gate of PMOS transistor M17 is connected to the output terminal (3) of the error amplifier module, serving as the input terminal (5) of the driver stage module. The source of PMOS transistor M17, the drain of NMOS transistor M19, and the drain of PMOS transistor M22 are connected, serving as the output terminal (7) of the driver stage module. The gate of NMOS transistor M20 is connected to the gate of NMOS transistor M12 to transmit the received feedforward amplified signal. The drain of PMOS transistor M17, the gate of NMOS transistor M19, and the source of NMOS transistor M20 are connected. The source of NMOS transistor M18 / NMOS transistor M19 is grounded. The gate of NMOS transistor M18 is connected to the gate of NMOS transistor M9 to transmit the feedforward amplified signal. The second capacitor C2 and the second resistor R2 are connected in series and placed between the gate of PMOS transistor M22 and the power supply voltage VDD.
5. The LDO circuit with fast transient response according to claim 4, characterized in that, PMOS transistor M17, NMOS transistors M18, and M19 form an SSF feedback loop. When the input voltage instantaneously drops and the output terminal (7) of the driver stage module needs to discharge quickly, the gate-source voltage VGS of PMOS transistor M17 instantaneously increases. When the input voltage instantaneously rises, the gate voltage of NMOS transistor M19 instantaneously drops, and the current of NMOS transistor M19 decreases or even turns off. PMOS transistor M17, NMOS transistor M20, PMOS transistors M21, and M22 form an FVF structure. When the input voltage instantaneously rises and the output terminal (7) of the driver stage module needs to charge quickly, the gate-source voltage VGS of PMOS transistor M17 instantaneously decreases. When the input voltage instantaneously drops, the conduction current of PMOS transistor M22 instantaneously decreases or even turns off.
6. The LDO circuit with fast transient response according to claim 1, wherein The differentiator transient enhancement module includes seven NMOS transistors M26 to M29, M34 to M36; seven PMOS transistors M23 to M25, M30 to M33; and a sixth capacitor C6. One end of the sixth capacitor C6 is connected to the feedback voltage output terminal FB of the resistor feedback network, and the other end is connected to the gate of the NMOS transistor M24; the sources of the NMOS transistors M23, M30 to M33, M35, and M38 are grounded; the gate of the NMOS transistor M23 is connected to the external bias voltage VN1; the sources of the NMOS transistors M23, M30 to M33 are grounded; the gate of the NMOS transistor M23 is connected to the external bias voltage VN1; the drain of the NMOS transistor M23 is connected to the sources of the NMOS transistors M24 / M25; the gate of the NMOS transistor M24 is connected to the drain of the PMOS transistor M26; the drain of the NMOS transistor M24 is connected to the gate of the PMOS transistor M28, the drain and gate of the PMOS transistor M26; the drain of the NMOS transistor M25 is connected to the gate of the NMOS transistor M29, the drain and gate of the NMOS transistor M27; the gate of the NMOS transistor M25 is connected to the reference voltage VREF; the sources of the PMOS transistors M26 to M29, M34, M37, M39, and M40 are connected to the power supply voltage VDD; the drain of the PMOS transistor M29 is connected to the gate of the NMOS transistor M31, the gate and drain of the NMOS transistor M30, and the drain of the NMOS transistor M32; the drain of the PMOS transistor M28 is connected to the gate of the NMOS transistor M32, the gate and drain of the NMOS transistor M33, and the drain of the NMOS transistor M31 is connected to the gate of the NMOS transistor M35; the gates of the PMOS transistors M34, M36, and M37 are connected to the external bias voltage VP1; the drain of the NMOS transistor M35 is connected to the drain of the PMOS transistor M34, the source of the PMOS transistor M36, and the gate of the NMOS transistor M38; the drain of the NMOS transistor M38 is connected to the drain of the PMOS transistor M37, the gate of the PMOS transistor M39, and the gate of the PMOS transistor M40; the drain of the PMOS transistor M39 is connected to the feedback output terminal Ifb1, and the drain of the PMOS transistor M40 is connected to the feedback output terminal Ifb2.