Voltage drop processing method and device, electronic equipment, chip and storage medium

Abstract

The invention provides a voltage sag processing method and device, electronic equipment, a chip and a storage medium, the method is executed by a voltage sag processing system, the voltage sag processing system comprises a power management unit (PMU), a system power management interface (SPMI) and a system-on-chip (SOC), and the method comprises the following steps: the PMU generates voltage sag information; the power management unit PMU transmits the voltage drop information to a system on chip SOC through a system power management interface SPMI; and the system-on-chip SOC executes voltage sag protection based on the voltage sag information. The complexity of the method can be reduced, the response speed of the system can be improved, and the continuity of key operation and the safety of data can be ensured when voltage drop occurs.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technologies, and particularly to a method and apparatus for voltage sag processing, an electronic device, a chip, and a storage medium. Background Art

[0002] Voltage sags in a low-temperature environment and under high-load conditions can affect the stability of mobile devices, resulting in problems such as reduced performance or even sudden shutdown of the devices, which affects the user experience. The existing methods for processing voltage sags are complex and have a slow response. Summary of the Invention

[0003] The present disclosure provides a method and apparatus for voltage sag processing, an electronic device, a chip, and a storage medium to solve the problems in the related art.

[0004] In a first aspect embodiment of the present disclosure, a method for voltage sag processing is proposed. The method is executed by a voltage sag processing system, which includes a power management unit (PMU), a system power management interface (SPMI), and a system-on-chip (SOC). The method includes: the PMU generates voltage sag information; the PMU transmits the voltage sag information to the SOC through the SPMI; and the SOC performs voltage sag protection based on the voltage sag information.

[0005] In some embodiments of the present disclosure, the PMU generating voltage sag information includes that the PMU monitors the device voltage; when the device voltage is lower than the sag voltage threshold, the PMU determines that a voltage sag event has occurred and generates voltage sag information.

[0006] In some embodiments of the present disclosure, performing voltage sag protection includes that the SOC determines key sub-modules, where the key sub-modules are modules in the device to which the voltage sag processing system belongs and whose loads meet preset conditions; and the SOC reduces the operating frequency of the key sub-modules.

[0007] In some embodiments of the present disclosure, the method further includes that the SOC receives the device voltage information reported by the PMU through the SPMI; or the SOC queries the device voltage information through the SPMI, and the device voltage information is obtained by the PMU monitoring the device voltage; when the device voltage information meets the first condition, the SOC sends an indication message to the PMU through the SPMI, and the indication message instructs the PMU to delete the voltage sag information.

[0008] In some embodiments of the present disclosure, the method further includes that when the power management unit (PMU) meets the second condition, it deletes the voltage drop information; the PMU sends notification information to the system on a chip (SOC) through the system power management interface (SPMI), and the notification information is used to notify the SOC that the voltage drop information has been deleted.

[0009] In some embodiments of the present disclosure, the method further includes that the SOC increases the operating frequency of the key sub-module based on the notification information.

[0010] An embodiment of the second aspect of the present disclosure provides a voltage drop processing system, which includes: a power management unit (PMU), a system power management interface (SPMI), and a system on a chip (SOC). The PMU is used to generate voltage drop information and transmit the voltage drop information to the SOC through the SPMI; the SOC is used to perform voltage drop protection based on the voltage drop information.

[0011] In some embodiments of the present disclosure, the voltage drop processing system further includes a key sub-module.

[0012] An embodiment of the third aspect of the present disclosure provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method described in the first aspect embodiment of the present disclosure.

[0013] An embodiment of the fourth aspect of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the method described in the first aspect embodiment of the present disclosure.

[0014] An embodiment of the fifth aspect of the present disclosure provides a chip, which includes at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method described in the first aspect embodiment of the present disclosure through logic circuits or by executing code instructions.

[0015] In summary, the voltage drop processing method proposed by the present disclosure monitors the device voltage through the power management unit, generates voltage drop information when the voltage is lower than the voltage drop threshold, and sends the voltage drop information to the SOC through the SPMI. The SOC can perform protection based on the voltage drop information, which can ensure the continuity of key operations and the security of data during voltage drops. By adopting the mature SPMI communication protocol, the complexity can be reduced and the system's response speed to voltage drops can be improved.

[0016] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit the present disclosure. Brief Description of the Drawings

[0017] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure and do not constitute an undue limitation to the present disclosure.

[0018] Figure 1 Schematic flowchart of a voltage dip processing method provided for an embodiment of the present disclosure;

[0019] Figure 2 Schematic flowchart of a voltage dip processing method provided for an embodiment of the present disclosure;

[0020] Figure 3 Schematic flowchart of a voltage dip processing method provided for an embodiment of the present disclosure;

[0021] Figure 4 Schematic flowchart of a voltage dip processing method provided for an embodiment of the present disclosure;

[0022] Figure 5 Schematic diagram of an application scenario of a defense method for power supply voltage dip of a portable battery device provided for an embodiment of the present disclosure;

[0023] Figure 6 Schematic flowchart of a defense method for power supply voltage dip of a portable battery device provided for an embodiment of the present disclosure;

[0024] Figure 7 Schematic timing diagram of a defense method for power supply voltage dip of a portable battery device provided for an embodiment of the present disclosure;

[0025] Figure 8 Schematic structural diagram of a voltage dip processing system provided for an embodiment of the present disclosure;

[0026] Figure 9 Schematic structural diagram of an electronic device provided for an embodiment of the present disclosure;

[0027] Figure 10 Schematic structural diagram of a chip provided for an embodiment of the present disclosure. Detailed Embodiments

[0028] Embodiments of the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where like or similar reference numerals denote like or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure and should not be construed as limiting the present disclosure.

[0029] Voltage dips under low-temperature environments and high-load conditions are important factors affecting the stability of mobile devices such as smartphones. Under low-temperature conditions, the internal chemical reaction rate of the battery slows down, significantly reducing the battery's discharge efficiency and causing the voltage to drop rapidly, which may lead to the device shutting down unexpectedly before the battery is completely depleted. This phenomenon is particularly common in cold climates and is especially troublesome for users who use their devices outdoors or in low-temperature environments.

[0030] On the other hand, when the device is operating under high load, such as performing high-performance computing or using high-power functions, the battery needs to provide a higher current. This high current demand causes an increase in the internal resistance of the battery, which in turn leads to a voltage drop. If the voltage drops below the device's minimum operating voltage, the device may suddenly shut down or its performance may degrade.

[0031] Therefore, it is crucial to develop effective voltage dip prevention technologies. The development of these technologies is essential for improving the reliability of devices in low-temperature environments and the user experience.

[0032] Some technical solutions have been proposed in the prior art to address the voltage dip phenomenon, and the specific content of the solutions is as follows.

[0033] 1. A voltage fluctuation compensation method and corresponding circuit are proposed, including: a voltage fluctuation detection circuit: detecting the amplitude of the power supply voltage fluctuation of the load circuit and feeding it back to the processor. The processor: calculating the voltage correction amount according to the fluctuation amplitude and sending it to the Power Management Unit (PMU). The Power Management Unit (PMU): adjusting the output voltage according to the correction amount.

[0034] This solution relies on the processor to calculate the voltage correction amount, which may result in a response speed insufficient to cope with rapid or severe voltage fluctuations. If the PMU of the power management unit does not respond quickly or accurately enough to the correction instruction, it may not be able to effectively prevent the problems caused by voltage dips.

[0035] 2. Using a transfer capacitor connected to the power supply as a backup power source. When the voltage detector detects that the power supply voltage is lower than a predetermined threshold, the transfer capacitor supplies power to the controller to keep it running. This method not only ensures the power supply of key components during instantaneous voltage dips but also can effectively reduce the volume and cost of the device compared to traditional dedicated backup power sources.

[0036] Although this solution reduces the volume and cost of the device, the energy storage of the transfer capacitor may not be sufficient to support long-term voltage stability requirements. There are high requirements for the performance of the capacitor, and specific types or high-quality capacitors may need to be used.

[0037] 3. A protection module is proposed which allows current to flow from the power storage device to the load and prevents current from flowing back to the power storage device. The protection module includes a voltage drop, ensuring that the voltage drop is bypassed through a bypass module when power is absent from the power source. Additionally, the protection module has a diode function in some embodiments, ensuring that current can only flow from the power storage device to the load and not in the reverse direction. This design provides an effective voltage drop protection solution for volume-constrained electronic devices or circuits.

[0038] This solution can prevent current from flowing back to the power storage device, but in complex circuits, more protection modules may be required to cover all critical paths.

[0039] 4. In the case of low battery conditions, mobile devices such as smartphones face an increased risk of sudden voltage drops under heavy loads, which may cause the device to reset or shut down autonomously to prevent damage, thus affecting the user experience. To address this issue, a sudden voltage drop protection technology is proposed, which integrates programmable low battery state awareness logic in the Power Management Integrated Circuit (PMIC) and the Application Processor (AP) to achieve sudden voltage drop detection and performance adjustment. System stability is mainly maintained by controlling the clock frequency, thereby minimizing unstable states and enhancing user satisfaction. Experimental results show that this technology can significantly reduce the failure rate caused by sudden voltage drops in low battery states.

[0040] The integration and implementation of this solution may be relatively complex and require additional logic to be integrated in the PMIC and the AP; it is not clearly stated how the warning information of the PMIC is transmitted to the SOC.

[0041] Therefore, to solve the above problems, the present disclosure proposes a voltage drop processing method, which can actively transmit voltage drop information to the System On Chip (SOC) through the System Power Management Interface (SPMI) communication bus after the power management unit (PMU) monitors a battery voltage drop. After receiving the warning signal, the SOC immediately reduces the frequency to relieve the load; after the voltage recovers, the frequency is increased again to restore the normal load; avoiding system crashes and enhancing the power load capacity.

[0042] The specific content of this method is as follows.

[0043] Figure 1 It is a schematic flow diagram of a voltage drop processing method provided for an embodiment of the present disclosure. As Figure 1As shown, this method can be executed by an electronic device. Optionally, this method can be executed by a voltage sag handling system, which includes a Power Management Unit (PMU), a System Power Management Interface (SPMI), and a System on Chip (SOC). This method can include the following steps.

[0044] Step 101, the Power Management Unit (PMU) generates voltage sag information.

[0045] In some embodiments, the Power Management Unit (PMU) is a power management integrated circuit that can manage power. For example, the PMU can monitor the device voltage. Here, the device can be an electronic device, optionally, an Internet of Things device that relies on integrated power management. For example, the device can be a mobile device, such as a smartphone, a tablet, a wearable device, etc. The device includes a voltage sag handling system.

[0046] In some embodiments, when the device voltage is lower than the sag voltage threshold, the PMU can determine that a voltage sag event has occurred and generate voltage sag information. Among them, the voltage sag can be a phenomenon of reduced power discharge efficiency and decreased voltage value caused by a low-temperature environment or large load conditions, etc.

[0047] In some embodiments, the above sag voltage threshold can be a threshold set according to actual application scenarios, and the present disclosure does not limit this.

[0048] In some embodiments, after determining that a voltage sag event has occurred, the PMU can generate voltage sag information and store it locally in the PMU.

[0049] Step 102, the PMU transmits the voltage sag information to the SOC through the SPMI.

[0050] In some embodiments, for example, the voltage sag information transmitted by the PMU can be an error warning code predefined by the protocol. When the SOC receives this warning code, it knows that a voltage sag event has occurred.

[0051] In some embodiments, the System on Chip (SOC) can send its own clock information to the PMU when starting to work, for example, when the device starts up. The PMU can adjust its own clock based on the clock information to achieve clock synchronization with the SOC, facilitating synchronous data transmission under the same clock.

[0052] In some embodiments, the Power Management Unit (PMU) can supply power to the System on Chip (SOC).

[0053] In some embodiments, the Power Management Unit (PMU) can transmit data to the System on Chip (SOC) through the System Power Management Interface (SPMI). The SPMI is an interface standard designed specifically for power management. Through this interface, communication between the System on Chip (SOC) and multiple Power Management Units (PMUs) can be achieved.

[0054] In some embodiments, when the Power Management Unit (PMU) communicates with the System on Chip (SOC) through the System Power Management Interface (SPMI), the SOC side can act as the master node of the SPMI, while the PMU can act as the slave node of the SPMI. At this time, the slave node of the SPMI, that is, the Power Management Unit (PMU), has the ability to initiate a write request actively (master write command sequence), that is, the Power Management Unit (PMU) can actively send information to the System on Chip (SOC), enabling the Power Management Unit (PMU) to quickly transmit key events back to the System on Chip (SOC).

[0055] In some embodiments, the Power Management Unit (PMU) can utilize the above-mentioned ability to initiate a write request actively (master write command sequence) of the SPMI to transmit voltage sag information to the System on Chip (SOC).

[0056] In some embodiments, the Power Management Unit actively uploads voltage sag information through the System Power Management Interface (SPMI), which can improve the response speed of the System on Chip (SOC). The System on Chip (SOC) does not need to query the internal information of the PMU again, reducing permanent damage to the chip's physics.

[0057] Step 103: The System on Chip (SOC) performs voltage sag protection based on the voltage sag information.

[0058] In some embodiments, the System on Chip can perform voltage sag protection based on the voltage sag information to avoid problems such as poor device stability caused by voltage sag.

[0059] In some embodiments, the System on Chip (SOC) can determine key sub-modules, where the key sub-modules are modules in the devices belonging to the voltage sag processing system whose loads meet preset conditions. For example, the preset condition can be that the load is greater than or equal to the load threshold, and the load threshold can be set based on the actual application scenario. The present disclosure does not limit this.

[0060] In the above embodiments, after receiving the voltage sag information, the system-on-chip (SOC) can first determine the modules with larger loads as key sub-modules and process these key sub-modules. Since their loads are relatively large, they may be the cause of the voltage sag. In addition, during a voltage sag, the large loads of the key sub-modules may cause a decrease in device performance or sudden power-off. Therefore, it is necessary to process them.

[0061] In some embodiments, after determining the voltage sag, the system-on-chip (SOC) can dynamically determine the key sub-modules. The system-on-chip can determine the modules whose loads meet the conditions in the current state as key sub-modules. The key sub-modules can include a central processing unit (CPU), a neural-network processing unit (NPU), a graphics processing unit (GPU), etc. For example, when playing games, the demand for the CPU is relatively high and the CPU load is relatively high. At this time, the CPU can be determined as a key sub-module.

[0062] In some embodiments, the system-on-chip (SOC) can reduce the operating frequency of the key sub-modules. By way of example, the system-on-chip can control the key sub-modules to reduce the frequency through hardware. For example, the system-on-chip can reduce the main clock of the key sub-modules through a clock control module, that is, reduce the operating frequency of the key sub-modules, so as to reduce the load of the key sub-modules and avoid affecting the device during a voltage sag.

[0063] In some embodiments, the system-on-chip (SOC) can transmit the voltage sag information to the underlying software and control the key sub-modules to reduce the frequency through the underlying software.

[0064] In summary, in the above embodiments of the present disclosure, when a voltage sag occurs, the power management unit (PMU) can transmit the voltage sag information to the system-on-chip (SOC) through the system power management interface (SPMI). After receiving the voltage sag information, the system-on-chip (SOC) can perform voltage sag protection, protect the device during a voltage sag, ensure the continuity of critical operations and the security of data. By adopting the mature SPMI protocol, the development time can be reduced, no additional hardware investment is required, the complexity of method implementation can be reduced, and the response speed can be improved.

[0065] Figure 2 It is a schematic flowchart of a voltage sag processing method provided by an embodiment of the present disclosure. As Figure 2 shown, based on Figure 1 the embodiments shown, the method may further include the following steps.

[0066] Step 201, the system-on-chip (SOC) receives device voltage information reported by the power management unit (PMU) through the system power management interface (SPMI); alternatively, the SOC queries the device voltage information through the SPMI.

[0067] In some embodiments, the device voltage information can be obtained by the PMU monitoring the device voltage. The device voltage information may include the device voltage value and the device voltage status (e.g., whether the device voltage is stable), etc.

[0068] Exemplarily, the SOC can receive the device voltage information reported by the PMU through the SPMI. That is, the SOC can obtain the device voltage information through a pure hardware automatic processing flow. For example, after a voltage drop event occurs, the PMU can continuously monitor the device voltage. When the device voltage is greater than the voltage recovery threshold and / or the device voltage remains stable, it can use the ability to actively initiate a write request through the SPMI to transmit the device voltage information to the SOC, for notifying the SOC that the device voltage has recovered.

[0069] Exemplarily, the SOC can query the device voltage information through the SPMI. That is, the SOC can obtain the device voltage through a software processing flow. For example, after a voltage drop event occurs, the SOC can continuously query the device voltage information monitored by the PMU through the SPMI, so as to obtain the device voltage information.

[0070] Step 202, when the device voltage information meets the first condition, the SOC sends an indication message to the PMU through the SPMI.

[0071] In some embodiments, the first condition may be that the device voltage is greater than the voltage recovery threshold and / or the device voltage remains stable. The voltage recovery threshold is different from the voltage drop threshold value. Preferably, the voltage recovery threshold can be higher than the voltage drop threshold. The specific values of the voltage drop threshold and the voltage recovery threshold can be specified according to the actual situation, and the present disclosure does not limit this.

[0072] In some embodiments, the first condition may be that the device voltage information is obtained by the SOC using the above software processing flow. That is, when the SOC obtains the device voltage information using the above software processing flow, the SOC can send an indication message to the PMU through the SPMI, and use the indication message to instruct the PMU to delete the voltage drop information.

[0073] In some embodiments, when the system on chip SOC adopts the above-mentioned pure hardware automatic processing flow to obtain device voltage information, the power management unit PMU can actively delete the voltage drop information when the device voltage is greater than the recovery voltage threshold and / or the device voltage remains stable. At this time, the system on chip SOC does not need to send indication information to the power management unit PMU.

[0074] In the above embodiment, when the power management unit detects that the device voltage is greater than the recovery voltage threshold, if the device voltage is directly determined to be recovered and the voltage drop protection state is released, the system frequency may be unstable due to voltage instability, resulting in system jitter. Therefore, the first condition may be that the device voltage remains stable, for example, the voltage value of the device voltage within a period of time is greater than the recovery voltage threshold and floats within a certain range, at which time it can be determined that the device voltage remains stable.

[0075] In some embodiments, after the device voltage information satisfies the first condition, the system on chip SOC can send indication information to the power management unit PMU through the system power management interface SPMI, wherein the indication information instructs the power management unit PMU to delete the voltage drop information. That is, when the device voltage information satisfies the first condition, the power management unit PMU can be instructed to delete the voltage drop information and release the voltage drop protection state.

[0076] In summary, in the above-mentioned embodiments of the present application, after determining that the device voltage information meets the first condition, the system on chip SOC can send indication information to the power management unit PMU through the system power management interface SPMI, instructing the power management unit to delete the voltage drop information. The mature SPMI communication protocol can be adopted to improve the response speed without the need for additional hardware investment, thereby achieving faster adjustment of the device status.

[0077] Figure 3 The following is a flow chart of a voltage drop processing method provided by an embodiment of the present disclosure. Figure 3 As shown, based on Figure 2 In the illustrated embodiment, the method may further include the following steps.

[0078] Step 301: The power management unit PMU deletes voltage drop information when a second condition is met.

[0079] In some embodiments, the second condition may be that the power management unit (PMU) receives the indication information sent by the system on a chip (SOC) through the system power management interface (SPMI). Alternatively, the second condition may be that the PMU determines that the device voltage has become greater than the voltage recovery threshold and / or the device voltage remains stable by monitoring the device voltage. That is, the PMU may delete the voltage sag information by receiving the indication from the SOC, or the PMU may also actively delete the voltage sag information after monitoring the recovery of the device voltage.

[0080] In some embodiments, when the SOC obtains the device voltage information using the above software processing flow, the PMU may clear the locally recorded voltage sag information based on the indication information sent by the SOC.

[0081] In some embodiments, when the SOC obtains the device voltage information using the above pure hardware automatic processing flow, the PMU may actively delete the voltage sag information when the device voltage is greater than the voltage recovery threshold and / or the device voltage remains stable. In this case, the SOC does not need to send indication information to the PMU.

[0082] Step 302, the PMU sends notification information to the SOC through the SPMI.

[0083] In some embodiments, the notification information may be used to notify the SOC that the voltage sag information has been deleted, and this information indicating the completion of the deletion may be used to notify the SOC to stop performing voltage sag protection.

[0084] In some embodiments, the PMU may transmit the notification information to the SOC through the SPMI based on its ability to initiate a write request actively (master write command sequence). In summary, in the above embodiments of the present application, the PMU clears the local voltage sag information based on the instruction information of the SOC, and after the completion of the clearing, notifies the SOC through the SPMI, which can reduce the complexity and improve the response speed using the SPMI communication protocol, and can quickly respond for processing after the voltage recovers.

[0085] Figure 4 It is a schematic flow chart of a voltage sag processing method provided by an embodiment of the present disclosure. As Figure 4 shown, based on Figure 3 the embodiments shown, the method may further include the following steps.

[0086] Step 401, the system-on-chip (SOC) increases the operating frequency of the critical sub-module based on the notification information.

[0087] In some embodiments, the system-on-chip (SOC) can increase the operating frequency of the critical sub-module back to the normal level based on the notification information sent by the power management unit (PMU). Exemplarily, the system-on-chip can increase the main clock of the critical sub-module through the clock control module.

[0088] In some embodiments, the system-on-chip (SOC) can increase the main clock of the critical sub-module through hardware control, or the system-on-chip (SOC) can transmit the notification information to the underlying software, and then control the main clock of the critical sub-module to increase the frequency through the underlying software.

[0089] In summary, in the above embodiments of the present application, after the voltage returns to the normal level, the system-on-chip (SOC) can adjust the frequency of the critical sub-module, restore the normal load, can achieve the adaptive adjustment of the system, meet the user's needs, receive the notification information through the SPMI communication protocol, and the system-on-chip (SOC) can quickly respond and make adjustments.

[0090] The technical solution of the present disclosure will be further described in detail below in conjunction with specific application embodiments.

[0091] The following is a method for defending against the power voltage drop of a portable battery device provided by an embodiment of the present disclosure. As Figure 5 shown, after the power management unit (PMU) monitors the battery voltage drop, it actively transmits the voltage drop information to the system-on-chip (SOC) through the SPMI communication bus. After the SOC receives the warning signal, it immediately reduces the frequency to relieve the load; after the voltage recovers, it increases the frequency again to restore the normal load; avoiding system crashes and improving the power load capacity.

[0092] The flowchart of this method is as Figure 6 shown, and the timing diagram is as Figure 7 shown. The specific content of this method is as follows.

[0093] 1. The system power management interface (SPMI) is an interface standard specifically designed for power management, aiming to achieve data communication between the SOC and multiple power management units (PMUs). In this architecture, the SOC side acts as the master node of the SPMI, while the PMU side acts as the slave node of the SPMI. It should be noted that the SPMI slave node has the ability to actively initiate a write request (master write command sequence), enabling the PMU side to quickly transmit critical events back to the SOC.

[0094] 2. By leveraging the function of the SPMI to actively initiate write requests, the PMU can proactively report key PMU events to the SOC, including battery voltage drop events. When the PMU detects that the battery voltage is below the set threshold, it records the relevant information of the voltage drop event. Subsequently, the PMU transfers the information of this voltage drop event to the SOC through the SPMI master write command sequence.

[0095] 3. After receiving the information about the voltage drop, the SOC will specifically reduce the main clock frequencies of systems such as the CPU, GPU, and NPU through the clock control module. At the same time, the SOC will notify the software about the occurrence of this event.

[0096] 4. After the voltage drop occurs, either of the following two processing flows can be adopted to continuously monitor the voltage:

[0097] Pure hardware automatic processing flow: The PMU continuously monitors whether the battery voltage recovers, that is, whether it is higher than the recovery threshold; after the voltage recovers, the PMU actively clears the voltage drop indication signal and transfers this voltage recovery information back to the SOC through the SPMI's master write command sequence function.

[0098] Software processing flow: The software continuously queries through the SPMI whether the battery voltage in the PMU has recovered. Once it detects that the battery voltage has recovered, the SOC actively clears the battery voltage drop signal through the SPMI, and then the PMU notifies the SOC through the SPMI that the battery voltage has recovered.

[0099] 5. Finally, after detecting the above information, the SOC adjusts the main clock frequencies of systems such as the CPU, GPU, and NPU back to the normal level through the clock control module.

[0100] In summary, the above examples of the present disclosure enable the system to respond promptly to voltage anomalies and avoid system reset or crash. This proactive management method significantly enhances the robustness of the system under unstable power supply conditions, ensuring the continuity of critical operations and the security of data.

[0101] The mature SPMI protocol adopted in the solution reduces the additional costs and time required for developing a new protocol and also avoids adding additional hardware ports such as GPIO ports. This solution utilizes the existing communication protocol, thereby reducing the overall system complexity and implementation difficulty and accelerating the development process.

[0102] This solution mainly relies on the coordination between software logic and existing hardware (PMU and SOC). The advantage of this method is that it does not require additional hardware investment, but achieves it by optimizing existing resources and logic. The implementation of this strategy is relatively simple, can quickly respond to voltage changes, and is easily integrated into the existing power management framework.

[0103] Figure 8 FIG. 4 is a schematic structural diagram of a voltage sag processing system 800 provided by an embodiment of the present disclosure. As Figure 8 shown, the system includes:

[0104] A power management unit PMU810, a system power management interface SPMI820, and a system on chip SOC830. The power management unit PMU810 is used to generate voltage sag information and transmit the voltage sag information to the system on chip SOC830 through the system power management interface SPMI820; the system on chip SOC830 is used to perform voltage sag protection based on the voltage sag information.

[0105] In some embodiments, the voltage sag processing system 800 further includes a critical sub module.

[0106] In some embodiments, the power management unit PMU810 can also be used to monitor the device voltage; when the device voltage is lower than the sag voltage threshold, the power management unit PMU determines that a voltage sag event has occurred and generates voltage sag information.

[0107] In some embodiments, the system on chip SOC830 can also be used to determine a critical sub module, where the critical sub module is a module in the device to which the voltage sag processing system belongs and whose load meets a preset condition; and to reduce the operating frequency of the critical sub module.

[0108] In some embodiments, the system on chip SOC830 can also be used to receive the device voltage information reported by the power management unit PMU through the system power management interface SPMI; or, it can be used to query the device voltage information through the system power management interface SPMI, and the device voltage information is obtained by the power management unit PMU monitoring the device voltage.

[0109] In some embodiments, the system on chip SOC830 further includes a clock control module for performing frequency up or down operations on the critical sub module.

[0110] In some embodiments, the system on chip SOC830 can also be used to, when the device voltage meets a first condition, the system on chip SOC sends an indication message to the power management unit PMU through the system power management interface SPMI, and the indication message instructs the power management unit PMU to delete the voltage sag information.

[0111] In some embodiments, the power management unit PMU810 can also be used to delete the voltage sag information when the second condition is met; and send a notification message to the system on a chip (SOC) through the system power management interface (SPMI), where the notification message is used to notify the SOC that the voltage sag information has been deleted.

[0112] In some embodiments, the system on a chip (SOC)830 can also be used to increase the operating frequency of the critical sub-module based on the notification message.

[0113] In summary, when it is determined that a voltage sag occurs, the voltage sag processing system 800 transmits the voltage sag information to the system on a chip (SOC) through the system power management interface (SPMI). The SOC performs voltage sag protection based on the voltage sag information, which can maintain the stability of the device, ensure the continuity of critical operations and the security of data when a voltage sag occurs. By using the mature communication protocol SPMI for data transmission, the complexity of the method can be reduced and the response speed of the system can be improved.

[0114] In the above embodiments provided by the present application, the methods and devices provided by the embodiments of the present application are introduced. To implement the various functions in the methods provided by the embodiments of the present application, the electronic device may include a hardware structure, software modules, and implement the above various functions in the form of a hardware structure, software module, or a combination of a hardware structure and a software module. A certain function among the above various functions can be executed in the form of a hardware structure, software module, or a combination of a hardware structure and a software module.

[0115] Figure 9 FIG. is a block diagram of an electronic device 900 for implementing the above method according to an exemplary embodiment. For example, the electronic device 900 can be a mobile phone, a computer, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0116] Referring to Figure 9 , the electronic device 900 may include one or more of the following components: a processing component 902, a memory 904, a power component 906, a multimedia component 908, an audio component 910, an input / output (I / O) interface 912, a sensor component 914, and a communication component 916.

[0117] The processing component 902 generally controls the overall operation of the electronic device 900, such as operations associated with display, telephone calls, data communication, camera operations, and recording operations. The processing component 902 may include one or more processors 920 to execute instructions to complete all or part of the steps of the above methods. In addition, the processing component 902 may include one or more modules to facilitate the interaction between the processing component 902 and other components. For example, the processing component 902 may include a multimedia module to facilitate the interaction between the multimedia component 908 and the processing component 902.

[0118] The memory 904 is configured to store various types of data to support the operation of the electronic device 900. Examples of such data include instructions for any application or method operating on the electronic device 900, contact data, phone book data, messages, pictures, videos, etc. The memory 904 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0119] The power component 906 provides power to various components of the electronic device 900. The power component 906 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 900.

[0120] The multimedia component 908 includes a screen that provides an output interface between the electronic device 900 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can not only sense the boundaries of touch or swipe actions, but also detect the duration and pressure associated with the touch or swipe operation. In some embodiments, the multimedia component 908 includes a front camera and / or a rear camera. When the electronic device 900 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0121] The audio component 910 is configured to output and / or input audio signals. For example, the audio component 910 includes a microphone (MIC), which is configured to receive external audio signals when the electronic device 900 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals can be further stored in the memory 904 or transmitted via the communication component 916. In some embodiments, the audio component 910 further includes a speaker for outputting audio signals.

[0122] The I / O interface 912 provides an interface between the processing component 902 and a peripheral interface module, and the peripheral interface module can be a keyboard, a click wheel, buttons, etc. These buttons can include, but are not limited to: a home button, a volume button, a power button, and a lock button.

[0123] The sensor component 914 includes one or more sensors for providing an assessment of the state of various aspects of the electronic device 900. For example, the sensor component 914 can detect the on / off state of the electronic device 900, the relative positioning of components, such as the display and keypad of the electronic device 900. The sensor component 914 can also detect a change in the position of the electronic device 900 or a component of the electronic device 900, the presence or absence of user contact with the electronic device 900, the orientation or acceleration / deceleration of the electronic device 900, and a change in the temperature of the electronic device 900. The sensor component 914 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor component 914 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor component 914 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0124] The communication component 916 is configured to facilitate communication between the electronic device 900 and other devices in a wired or wireless manner. The electronic device 900 can access a wireless network based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (New Radio), or a combination thereof. In an exemplary embodiment, the communication component 916 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 916 further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0125] In an exemplary embodiment, the electronic device 900 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above method.

[0126] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions, such as a memory 904 including instructions, is also provided. The above instructions may be executed by a processor 920 of the electronic device 900 to complete the above method. For example, the non-transitory computer-readable storage medium may be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0127] An embodiment of the present disclosure also proposes a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the method described in the above embodiments of the present disclosure.

[0128] An embodiment of the present disclosure also proposes a communication system. The communication system includes a terminal and a network device. The terminal is used to implement the method described in the embodiment of the first aspect of the present disclosure, and the network device may be used to implement the method described in the embodiment of the second aspect of the present disclosure.

[0129] In some embodiments, the above communication system further includes a console, and the console may send a modification instruction to the terminal to control the filtering information adopted by the terminal, etc.

[0130] Figure 10 FIG. is a schematic structural diagram of a chip 900 for implementing the above method shown according to an exemplary embodiment. Referring to Figure 10 , the chip 1000 includes a communication interface 1001 and at least one processor 1002. The communication interface 1001 is used to receive a signal input to the chip 1000 or a signal output from the above chip 1000, and the processor 1002 communicates with the communication interface 801 and implements the method described in the above embodiments of the present disclosure through a logic circuit or by executing code instructions.

[0131] It should be noted that the terms "first", "second", etc. in the description of the present disclosure, the claims and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0132] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples" or "some examples", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in at least one embodiment or example.

[0133] Any process or method description shown in the flowchart or described in other ways herein can be understood as representing a module, segment or part of code including one or more executable instructions for implementing a specific logical function or process, and the scope of the preferred embodiments of the present invention includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in a reverse order according to the functions involved, rather than in the order shown or discussed, which should be understood by those skilled in the technical field to which the embodiments of the present invention belong.

[0134] The logic and / or steps represented in the flowchart or otherwise described herein can be considered, for example, as a definable sequence list of executable instructions for implementing logical functions, which can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in conjunction with these instruction execution systems, apparatuses, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion with at least one wiring (control method), a portable computer disk cartridge (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, a computer-readable medium can even be paper or other suitable media on which a program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other suitable processing as necessary, and then stored in a computer memory.

[0135] It should be understood that various parts of the embodiments of the present invention can be implemented using hardware, software, firmware, or combinations thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits having suitable combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0136] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0137] In addition, each functional unit in various embodiments of the present invention may be integrated into one processing module, may exist physically alone for each unit, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium. The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disc, etc.

[0138] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for voltage sag handling, characterized in that, The method is executed by a voltage sag handling system, which includes a power management unit (PMU), a system power management interface (SPMI), and a system on chip (SOC). The method includes: The power management unit (PMU) generates voltage sag information; The power management unit (PMU) transmits the voltage sag information to the system on chip (SOC) through the system power management interface (SPMI); Based on the voltage sag information, the system on chip (SOC) performs voltage sag protection.

2. The method according to claim 1, wherein The power management unit (PMU) generating the voltage sag information includes The power management unit (PMU) monitors the device voltage; When the device voltage is lower than the sag voltage threshold, the power management unit (PMU) determines that a voltage sag event has occurred and generates the voltage sag information.

3. The method according to claim 1, wherein The performing of the voltage sag protection includes The system on chip (SOC) determines key sub-modules, where the key sub-modules are modules in the device to which the voltage sag handling system belongs and whose loads meet preset conditions; The system on chip (SOC) reduces the operating frequency of the key sub-modules.

4. The method according to claim 3, characterized in that, The method further includes The system on chip (SOC) receives device voltage information reported by the power management unit (PMU) through the system power management interface (SPMI); Or The system on chip (SOC) queries the device voltage information through the system power management interface (SPMI), and the device voltage information is obtained by the power management unit (PMU) monitoring the device voltage; When the device voltage information meets the first condition, the system on chip (SOC) sends an indication message to the power management unit (PMU) through the system power management interface (SPMI), and the indication message instructs the power management unit (PMU) to delete the voltage sag information.

5. The method according to claim 1, wherein The method further includes The power management unit (PMU) deletes the voltage sag information when the second condition is met; The power management unit (PMU) sends a notification message to the system on chip (SOC) through the system power management interface (SPMI), and the notification message is used to notify the system on chip that the voltage sag information has been deleted.

6. The method according to claim 5, wherein The method further includes Based on the notification message, the system on chip (SOC) increases the operating frequency of the key sub-modules.

7. A voltage sag handling system, which includes a power management unit (PMU), a system power management interface (SPMI), and a system on chip (SOC). The power management unit (PMU) is used to generate voltage sag information and transmit the voltage sag information to the system on chip (SOC) through the system power management interface (SPMI); The system on chip (SOC) is used to perform voltage sag protection based on the voltage sag information.

8. The system according to claim 7, wherein the voltage sag handling system further includes key sub-modules.

9. An electronic device, characterized in that, Including: At least one processor; And A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method according to any one of claims 1-6.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the method according to any one of claims 1-6.

11. A chip, characterized in that, Comprising at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method according to any one of claims 1 to 6 through logic circuits or by executing code instructions.

Images