Multi-event synchronous snapshot method and circuit for HPM under RISC-V architecture

Abstract

The present invention discloses a multi-event synchronous snapshot method and circuit for HPM under the RISC-V architecture, the method comprising: synchronous snapshot mechanism triggering; event correlation classification and correlation event screening; non-blocking snapshot reading. The processing circuit comprises a snapshot controller and a snapshot register group, the snapshot controller and the snapshot register group being integrated into the PMU; the snapshot controller is used for triggering detection of the synchronous snapshot mechanism, selecting relevant events when the synchronous snapshot mechanism is triggered, generating a freeze signal and writing it into the snapshot register group; the snapshot register group is used for saving all selected correlation event counter data when the freeze signal is valid. The present invention does not read information at different times by reading correlated event information during performance analysis, saves the scene of the same type of event by snapshot, ensures that the correlated event data is captured at the same time, eliminates timing errors, and improves the accuracy of performance analysis.

Description

Technical Field

[0001] The present invention relates to the technical field of high-performance chip design, and in particular to a multi-event synchronous snapshot method and circuit for HPM under the RISC-V architecture. Background Art

[0002] Hardware Performance Counter (HPC) is a built-in counter commonly found in modern microprocessors. It is used to store hardware-related event information. These events typically include the number of clock cycles, the number of executed instructions, the number of branch prediction failures, the number of cache misses / hits at each level, and the number of TLB (Translation Look-aside Buffer) misses / hits.

[0003] According to the RISC-V privileged instruction specification, the processor provides two types of counters: fixed counters and programmable counters. Two fixed counters are used to count clock cycles and executed instructions, respectively. The remaining 29 programmable counters can be used to capture selected events and complete the counting. Event selection is controlled by the Machine Performance-Monitoring Event Selector (Mhpmevent) register specified in the RISC-V privileged document, which can select one or more events.

[0004] In traditional methods, when using performance analysis tools for performance analysis, CSR instructions are used to read the corresponding event counters to obtain the corresponding data information. Usually, performance analysis reads a set of related event counter information for analysis. For example, to calculate the accuracy of branch prediction, it is necessary to obtain the number of instruction executions and the number of branch prediction failures at the same time. This requires executing two CSR instructions to read the counters of the corresponding events. The first CSR instruction reads the number of branch prediction failures, and the second CSR instruction reads the number of instruction retirements. The performance analysis tool obtains two sets of data and can obtain information on branch prediction accuracy through calculation. If more performance information is needed, multiple CSR instructions need to be executed to read the corresponding performance counters.

[0005] Using this information can more efficiently monitor the system status, efficiently utilize hardware resources, reasonably manage power consumption, and optimize the computer system structure. Therefore, almost all modern processors are equipped with this counter.

[0006] In existing technologies, performance analysis requires sequentially reading multiple counters through multiple CSR (Control and Status Register) instructions. However, because counters are continuously updated, differences in the read timestamps of associated events can lead to data bias. For example, calculating branch prediction accuracy requires reading both the "number of branch failures" and the "number of instruction retirements." However, the counters may have been updated between these two reads, resulting in inaccurate analysis results. Existing technologies lack a mechanism for synchronously capturing multiple events, limiting the accuracy of performance analysis. Summary of the Invention

[0007] The purpose of the present invention is to address the deficiencies in the existing technology and provide a technical solution for a multi-event synchronous snapshot method and circuit for HPM under the RISC-V architecture. When reading related event information during performance analysis, information at different times will not be read. The scene of the same type of event is saved in the form of snapshots, ensuring that the related event data is captured at the same time, eliminating timing errors, and improving the accuracy of performance analysis. The method can be applied to scenarios requiring precise related event analysis, such as processor performance tuning and real-time system monitoring.

[0008] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0009] A multi-event synchronous snapshot method for HPM under RISC-V architecture is characterized by comprising the following steps:

[0010] Step 1. Synchronous snapshot mechanism is triggered;

[0011] Step 2: Event correlation classification and correlation event screening;

[0012] Step 3: Non-blocking snapshot reading.

[0013] A multi-event synchronous snapshot processing circuit for HPM under RISC-V architecture, characterized by comprising a snapshot controller and a snapshot register group, wherein the snapshot controller and the snapshot register group are integrated into a PMU;

[0014] The snapshot controller is used for trigger detection of the synchronous snapshot mechanism, selects relevant events when the synchronous snapshot mechanism is triggered, and generates a freeze signal to write into the snapshot register group;

[0015] A snapshot register group is used to save all selected correlation event counter data when the freeze signal is valid.

[0016] The present invention has the following beneficial effects due to the adoption of the above technical solution:

[0017] The present invention reads relevant event information during performance analysis without reading information at different times. It saves the scene of the same type of event in the form of snapshots, ensures that the related event data is captured at the same time, eliminates timing errors, and improves the accuracy of performance analysis. It can be applied to scenarios that require precise related event analysis, such as processor performance tuning and real-time system monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention will be further described below in conjunction with the accompanying drawings:

[0019] Figure 1 Flowchart of the multi-event synchronous snapshot method of HPM under RISC-V architecture and the multi-event synchronous snapshot method in the circuit of the present invention;

[0020] Figure 2 This is an execution flow chart of the synchronous snapshot mechanism in the present invention;

[0021] Figure 3 This is a circuit block diagram of the synchronous snapshot mechanism in the present invention. DETAILED DESCRIPTION

[0022] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0023] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0024] It should be noted that the terms "first," "second," and so on in the description and claims of the present invention and the accompanying drawings are used to distinguish similar items and are not necessarily used to describe a specific order or precedence. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0025] Definitions of professional terms used in this invention:

[0026] .

[0027] like Figure 1 and Figure 2 As shown in the figure, the multi-event synchronous snapshot method of HPM under the RISC-V architecture of the present invention includes the following steps:

[0028] Step 1. Synchronous snapshot mechanism is triggered;

[0029] The synchronous snapshot mechanism triggering specifically includes: automatically detecting the CSR instruction to read the event counter, generating a freeze signal when the synchronous snapshot mechanism needs to be triggered, ensuring that the associated counters are synchronously paused and updated, and storing the current values ​​in the snapshot register group.

[0030] When the event counter is read by the automatic detection CSR instruction:

[0031] If there is no snapshot currently, or the event group stored in the snapshot does not include the current event, the synchronous snapshot mechanism is triggered to store all current related counters into the snapshot register group to complete the event information reading;

[0032] If the current snapshot exists and the current event is stored by the snapshot, directly read the corresponding information of the snapshot register group to complete the event reading.

[0033] Step 2: Event correlation classification and correlation event screening;

[0034] Event correlation classification and correlation event screening specifically include: assigning related events to a group based on the function or physical characteristics of the event, assigning a group number to each event group, automatically identifying related event groups based on the group number of the event coding rule, and storing all event data with the same group number into the snapshot register group.

[0035] Step 3: Non-blocking snapshot reading.

[0036] Non-blocking snapshot reading specifically includes: if the CSR instruction read event belongs to the event group stored in the current snapshot group, directly return the snapshot data to avoid repeated freezing of the counter; if it is not a related event, trigger the generation of a new snapshot.

[0037] like Figure 3 As shown, the multi-event synchronous snapshot processing circuit of the HPM under the RISC-V architecture of the present invention includes a snapshot controller and a snapshot register group, and the snapshot controller and the snapshot register group are integrated into the PMU;

[0038] The snapshot controller is used for trigger detection of the synchronous snapshot mechanism, selects relevant events when the synchronous snapshot mechanism is triggered, and generates a freeze signal to write into the snapshot register group;

[0039] When the synchronous snapshot mechanism is triggered, relevant events are selected and identified and classified according to the event classification rules. Specifically, the related events are assigned to a group based on the functional or physical characteristics of the event (such as cache events, branch prediction events, etc.), and a group number (Group ID) is assigned to each event group. The group number based on the event coding rule automatically identifies the associated event group, and all event data with the same group number are stored in the snapshot register group.

[0040] The snapshot controller includes a snapshot event control register, a freeze signal generator and a snapshot event selector;

[0041] The snapshot event control register is implemented by a 1-bit control register and a 4-bit data register, which is used to update the data register according to the control bit of the control register;

[0042] Updating the data register according to the control bit of the control register specifically includes: when the control register is 0, no snapshot information is saved; when the control register is 1, the snapshot information is saved, and the data register saves the group number of the snapshot event.

[0043] A freeze signal generator is used to detect whether the snapshot event control register is valid when the CSR instruction is at the execution level and the performance counter is read, and to determine whether the stored event group is the event group currently read. If the snapshot event is not saved, a freeze signal is generated to filter the snapshot event and update the snapshot register group;

[0044] Snapshot event selector, used to select all correlation events when the freeze signal is valid.

[0045] When all correlation events are selected, the group number (Group ID) saved in the Mhpmevent register read by the current CSR instruction is read, and the counters corresponding to all Mhpmevents with the group number are selected.

[0046] For example, the L1 cache event group can be defined as Group 0, the branch prediction event can be defined as Group 1, etc. The group number is configured through the Mhpmevent reserved bit, and the relevant events are automatically identified and classified through the snapshot related event selector.

[0047] The synchronous snapshot mechanism triggering process includes the following steps:

[0048] When the hardware detects that the CSR instruction reads the performance counter MhpmcounterX, it will read the control register of the snapshot event control register.

[0049] If the control bit is 0, it means that no snapshot information is currently saved, and a freeze signal is generated to freeze the counter information read by the CSR instruction and the related performance counter information into the snapshot register group, and the control bit of the control register is set to 1 and the group number is updated to the data register.

[0050] If the control bit is 1 and the group number of the current event stored in Mhpmevent is equal to the group number stored in the current control register, it means that the currently accessed event belongs to the saved snapshot event, and the corresponding event counter stored in the snapshot register group is read. Otherwise, a new snapshot is triggered.

[0051] If the control bit is 1 and the group number of the current event stored in Mhpmevent is not equal to the group number stored in the current control register, a freeze signal is generated, the counter information read by the CSR instruction and the related performance counter information are frozen and stored in the snapshot register group, and the control bit of the control register is set to 1 and the group number is updated to the data register.

[0052] A snapshot register group is used to save all selected correlation event counter data when the freeze signal is valid.

[0053] Each snapshot register in the snapshot register group consists of a control bit and a data bit. The control bit is used to determine whether the data currently saved in the snapshot register is valid, and the data bit is used to save the event number of the event and the data of the corresponding performance counter.

[0054] When the snapshot register group performs data selection, the event counter read by the current CSR instruction is saved in the snapshot register group, the event number of the current event is read and compared with the data saved in each snapshot register. If the control bit of the selected snapshot register is 1, the data to be read is selected; if the control bit of the selected snapshot register is 0, a value of 0 is read.

[0055] The above are only specific embodiments of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent replacements, or modifications based on the present invention to achieve substantially the same technical effects are all within the scope of protection of the present invention.

Claims

1. A multi-event synchronous snapshot method for HPM under RISC-V architecture, characterized by The steps include: Step 1: Synchronous snapshot mechanism is triggered; The synchronous snapshot mechanism triggering specifically includes: automatically detecting the CSR instruction to read the event counter, generating a freeze signal when the synchronous snapshot mechanism needs to be triggered, ensuring that the associated counters are synchronously paused and updated, and storing the current value in the snapshot register group; Step 2: Event correlation classification and correlation event screening. Event correlation classification and correlation event screening specifically include: assigning related events to a group based on the function or physical characteristics of the event, assigning a group number to each event group, automatically identifying related event groups based on the group number of the event coding rule, and storing all event data with the same group number in the snapshot register group; Step 3, non-blocking snapshot reading; non-blocking snapshot reading specifically includes: if the CSR instruction read event belongs to the event group stored in the current snapshot group, directly return the snapshot data to avoid repeated freezing of the counter; if it is not a related event, trigger a new snapshot generation.

2. The multi-event synchronous snapshot method for HPM under the RISC-V architecture according to claim 1, characterized in that: When the event counter is read by the automatic detection CSR instruction: If there is no snapshot currently, or the event group stored in the snapshot does not include the current event, the synchronous snapshot mechanism is triggered to store all current related counters into the snapshot register group to complete the event information reading; If the current snapshot exists and the current event is stored by the snapshot, directly read the corresponding information of the snapshot register group to complete the event reading.

3. The multi-event synchronous snapshot processing circuit of the HPM under the RISC-V architecture is characterized by: It includes a snapshot controller and a snapshot register group, wherein the snapshot controller and the snapshot register group are integrated into the PMU; The snapshot controller is used for trigger detection of the synchronous snapshot mechanism, selects relevant events when the synchronous snapshot mechanism is triggered, generates a freeze signal and writes it into the snapshot register group; the snapshot controller includes a snapshot event control register, a freeze signal generator and a snapshot event selector; the snapshot event control register is implemented by a 1-bit control register and a 4-bit data register, and is used to update the data register according to the control bit of the control register; the freeze signal generator is used to detect whether the snapshot event control register is valid when the CSR instruction is in the execution level and the performance counter is read, and to determine whether the stored event group is the currently read event group. If the snapshot event is not saved, a freeze signal is generated to perform the snapshot event. The snapshot event selector is configured to select all correlation events when the freeze signal is valid; when all correlation events are selected, the group number stored in the Mhpmevent register read by the current CSR instruction is read, and the counters corresponding to all Mhpmevents with the group number are selected; when the synchronous snapshot mechanism is triggered, the relevant events are selected and classified according to the event classification rules, specifically including: assigning the related events to a group according to the function or physical characteristics of the event, assigning a group number to each event group, automatically identifying the associated event group based on the group number of the event coding rule, and storing all event data with the same group number in the snapshot register group; The snapshot register group is used to save all selected correlation event counter data when the freeze signal is valid.

4. The multi-event synchronous snapshot processing circuit for HPM under the RISC-V architecture according to claim 3, characterized in that: Updating the data register according to the control bit of the control register specifically includes: when the control register is 0, no snapshot information is saved; when the control register is 1, the snapshot information is saved, and the data register saves the group number of the snapshot event.

5. The multi-event synchronous snapshot processing circuit for HPM under the RISC-V architecture according to claim 3, characterized in that: Each snapshot register in the snapshot register group consists of a control bit and a data bit. The control bit is used to determine whether the data currently stored in the snapshot register is valid, and the data bit is used to store the event number of the event and the data of the corresponding performance counter.

6. The multi-event synchronous snapshot processing circuit for HPM under the RISC-V architecture according to claim 5, characterized in that: When the snapshot register group performs data selection, the event counter read by the current CSR instruction is saved in the snapshot register group, the event number of the current event is read and compared with the data saved in each snapshot register. If the control bit of the selected snapshot register is 1, the data to be read is selected; if the control bit of the selected snapshot register is 0, a value of 0 is read.

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