Multi-thread memory processing method and device, electronic equipment and storage medium
By embedding locking and lock release logic in the current operation function, the race conditions and deadlock problems caused by memory operations in multi-threaded systems are solved, and thread safety of memory access and modular code management are realized.
Patent Information
- Application Number
- CN202410101616.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-24
- Publication Date
- 2025-07-25
AI Technical Summary
In high concurrency multi-threading systems, multiple threads are prone to cause race conditions when operating memory at the same time, resulting in data inconsistency or deadlock. The existing technology relies on programmers to correctly manage locking and release of locks, but is prone to errors.
Embed locking logic, memory operation logic and lock release logic in the current operation function to ensure that only one thread can access the target memory at a time, and automatically release the lock through function calls to avoid deadlocks.
Ensure thread safety of memory access in a multi-threaded environment, avoid race conditions and data inconsistencies, and improve the modularity and maintainability of the code.
Smart Images
Figure CN120371554A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure relate to the field of computer technologies, and in particular, to a multi-threaded memory processing method, apparatus, electronic device, and storage medium. Background Art
[0002] In a high-concurrency multi-threaded system, there is a lot of memory that can only be used by one thread at a time. When multiple threads perform memory operations on the memory simultaneously, these concurrent operations may cause race conditions in a multi-threaded environment, resulting in data inconsistency or other errors.
[0003] In related solutions, it mainly relies on programmers to correctly manage the locking and unlocking of locks. However, in complex business logics, the operations of locking and unlocking are prone to errors. Especially in the case of forgetting to release the lock after locking, it may lead to the occurrence of deadlocks, that is, two or more threads fall into an infinite loop while waiting for each other to release the lock, resulting in the program being unable to execute normally. Summary of the Invention
[0004] The present disclosure provides a multi-threaded memory processing method, apparatus, electronic device, and storage medium to ensure secure reading and writing of memory in a multi-threaded environment and reduce the occurrence of deadlocks and forgotten locking.
[0005] In a first aspect, an embodiment of the present disclosure provides a multi-threaded memory processing method, the method including:
[0006] Determining a current operation function called by a current thread when performing a memory operation on a target memory, where a locking logic, a memory operation logic, and a lock release logic are embedded in the current operation function;
[0007] Performing a memory operation on the target memory through the memory operation logic in the current operation function, where the locking logic and the lock release logic in the current operation function are used to lock and release the target memory;
[0008] Returning a memory operation result of the target memory through the current operation function.
[0009] In a second aspect, an embodiment of the present disclosure further provides a multi-threaded memory processing apparatus, the apparatus including:
[0010] A determination module, configured to determine a current operation function called by a current thread when performing a memory operation on a target memory, where a locking logic, a memory operation logic, and a lock release logic are embedded in the current operation function;
[0011] An operation module, used to perform memory operation on the target memory through the memory operation logic in the current operation function, wherein the locking logic and the lock release logic in the current operation function are used to lock and release the target memory;
[0012] A return module is used to return the memory operation result of the target memory through the current operation function.
[0013] In a third aspect, an electronic device is also provided in an embodiment of the present disclosure, the electronic device comprising:
[0014] at least one processor; and
[0015] a memory communicatively connected to the at least one processor; wherein,
[0016] The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the multi-threaded memory processing method described in any one of the above embodiments.
[0017] In a fourth aspect, a computer-readable medium is also provided in an embodiment of the present disclosure, wherein the computer-readable medium stores computer instructions, and the computer instructions are used to enable a processor to implement the multi-threaded memory processing method described in any one of the above embodiments when executed.
[0018] The disclosed embodiment determines the current operation function called when the current thread performs a memory operation on the target memory, wherein the current operation function is embedded with locking logic, memory operation logic and lock release logic; performs memory operation on the target memory through the memory operation logic in the current operation function, and the locking logic and lock release logic in the current operation function are used to lock and release the target memory; returns the memory operation result on the target memory through the current operation function. In this scheme, by embedding the locking logic and lock release logic in the current operation function, only the thread that obtains the lock can perform the memory operation, thereby avoiding the problems of race conditions and data inconsistency. Only the current operation function can be used to operate the memory each time, and the locking logic, memory operation logic and lock release logic are encapsulated in the current operation function, making the code more modular and centrally managed. In this way, if the call of the current operation function is terminated, the lock release logic in the current operation function needs to be executed, and the problem of deadlock caused by forgetting to release the lock after locking due to complex business logic is avoided as much as possible, and it can be ensured that the access to the target memory in a multi-threaded environment is thread-safe, thereby avoiding memory data conflicts and errors caused by concurrent access of multiple threads.
[0019] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood from the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In conjunction with the accompanying drawings and with reference to the following detailed description, the above and other features, advantages, and aspects of the embodiments of the present disclosure will become more apparent. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic and that the elements and components are not necessarily drawn to scale.
[0021] Figure 1 is a schematic flowchart of a multi-threaded memory processing method provided by an embodiment of the present disclosure;
[0022] Figure 2 is a schematic structural diagram of the encapsulation of the current operation function in multi-threaded memory processing provided by an embodiment of the present disclosure;
[0023] Figure 3 is a schematic structural diagram of a multi-threaded memory processing device provided by an embodiment of the present disclosure;
[0024] Figure 4 is a schematic structural diagram of an electronic device for implementing a multi-threaded memory processing method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0025] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not used to limit the scope of protection of the present disclosure.
[0026] It should be understood that the various steps recited in the method embodiments of the present disclosure may be executed in a different order and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this regard.
[0027] As used herein, the term "including" and its variations are open-ended, i.e., "including but not limited to". The term "based on" is "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.
[0028] It should be noted that the concepts such as "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependent relationships.
[0029] It should be noted that the modifications of "one" and "multiple" mentioned in this disclosure are illustrative rather than restrictive. Those skilled in the art should understand that unless clearly specified otherwise in the context, it should be understood as "one or more".
[0030] The names of the messages or information exchanged between multiple devices in the embodiments of this disclosure are only for illustrative purposes and are not used to limit the scope of these messages or information.
[0031] Figure 1 The flowchart shows a multi-threaded memory processing method provided by an embodiment of this disclosure. The embodiments of this disclosure are applicable to the situation of reading and writing memory in a multi-threaded scenario. This method can be executed by a multi-threaded memory processing device, which can be implemented in the form of software and / or hardware and is generally integrated in any electronic device with network communication functions. The electronic device can be a mobile terminal, a PC or a server, etc.
[0032] As Figure 1 shown, the multi-threaded memory processing method of the embodiments of this disclosure may include the following processes:
[0033] S110. Determine the current operation function called when the current thread performs a memory operation on the target memory. The current operation function embeds a locking logic, a memory operation logic, and a lock release logic.
[0034] S120. Perform a memory operation on the target memory through the memory operation logic in the current operation function. The locking logic and the lock release logic in the current operation function are used to lock and release the target memory.
[0035] Most multi-threaded problems can be classified as thread safety problems, specifically including memory safety and business logic errors caused by multi-threading. Under the premise of multi-threading, the execution of a thread may stop at any line of code due to the switching of CPU time slices. Under this premise, it may occur that first a value is found in thread A, then thread B deletes this value, but thread A doesn't know, and then thread A operates on the memory or business logic with the previously obtained value, which will produce various unexpected results.
[0036] To ensure the coordination between multiple threads and data consistency, it is necessary to lock the memory. By locking the memory, it can be ensured that other threads cannot access the protected memory while a thread holds the lock, thus guaranteeing data consistency and thread safety. When a thread finishes operating on the memory, it will release the lock so that other waiting threads can acquire the lock and perform their own operations.
[0037] However, due to the complex business logic, in practical applications, there will be a problem of deadlock caused by forgetting to release the lock after locking the memory. This problem is particularly prominent in OC (Objective-C) and CPP (C++). To solve this problem, the defer function is introduced, which can ensure that the code in the defer function is executed when the stack is destroyed, thus binding the lock release logic to the defer to ensure that the lock is definitely released. However, even when using the defer function, there is still a risk of forgetting to write the defer statement and thus forgetting to release the lock, leading to deadlock, because whether to use the defer and where to use the defer need to be decided and managed by the developer himself. Things that need to be guaranteed by people are usually unreliable because human factors are prone to introduce errors or omissions. Even with tools and language features to assist in managing the release of locks, the possibility of human error cannot be completely eliminated.
[0038] Based on the above situation, an operation function for memory operations on the memory is pre-configured. When performing memory operations on the memory, it is not possible to directly operate on the memory. Instead, the operation function needs to be used to complete the memory operation. And by embedding the locking logic and lock release logic into the operation function for memory operations, it is ensured that only one thread can access the target memory at a time. That is to say, when the current thread uses the current operation function to operate on the target memory, other threads cannot operate on the target memory, thus avoiding the problem of race conditions and data inconsistency and ensuring that the access to the target memory in a multi-threaded environment is thread-safe.
[0039] For the current operation function, the locking logic, memory operation logic, and lock release logic are embedded in the current operation function. The locking logic is configured at the function entry of the current operation function, which can lock the target memory through the locking logic at the beginning of calling the current operation function to ensure that only one thread can access the target memory at a time. The lock release logic is configured at the function exit of the current operation function, which can ensure that after the memory operation logic in the current operation function is used to complete the memory operation on the target memory, the target memory is unlocked using the lock release logic before the call to the current operation function ends.
[0040] Optionally, during the process of invoking the current operation function to operate on the target memory, the locking logic in the current operation function is used to lock the target memory before operating on the target memory using the memory operation logic in the current operation function, and the lock release logic in the current operation function is used to release the lock on the target memory after operating on the target memory using the memory operation logic in the current operation function.
[0041] By embedding the locking logic and the lock release logic in the current operation function, it can be ensured that the access to the target memory in a multi-threaded environment is thread-safe. Only the thread that obtains the lock can operate on the target memory, avoiding the problems of race conditions and data inconsistency. Moreover, introducing the locking and lock release logic into the operation function can ensure that only one thread operates on the target memory at the same time, and at the same time, it can ensure that the lock on the memory can be released when the call to the operation function ends, thus avoiding the memory data conflicts and errors caused by multi-threaded concurrent access, as well as the deadlock problem caused by forgetting to release the lock after locking due to complex business logic.
[0042] Optionally, the memory operation includes a read operation on the memory, a write operation on the memory, and a concurrent operation combined based on the read operation and the write operation on the memory.
[0043] In multi-threaded programming, when multiple threads perform memory operations simultaneously, it is necessary to ensure thread safety to avoid race conditions and data inconsistency problems. Among them, the memory operation includes a read operation on the memory and a write operation on the memory, combining concurrent operations such as read-read, read-write, write-read, and write-write. Among these four combinations, only read-read can ensure thread safety without any processing, and the remaining three cases have thread safety problems.
[0044] In the above memory operations, the read-read operation is usually safe because multiple threads reading the same memory location simultaneously will not cause conflicts or data inconsistency. Multiple threads can read the value of the same variable at the same time without interfering with each other. However, read-write, write-read, and write-write operations may introduce thread safety problems. When one thread is writing to memory while another thread is reading from or writing to the same memory location, race conditions may occur, resulting in data inconsistency or other errors.
[0045] To ensure thread safety, in cases involving read-write, write-read, or write-write operations, it is usually necessary to use synchronization mechanisms such as mutexes, condition variables, etc. to protect shared resources. These synchronization mechanisms can ensure that at any given moment, only one thread can access the protected memory area, thus avoiding race conditions and data inconsistency issues. The goal of memory safety is to ensure that in a multi-threaded environment, when threads concurrently execute read-write, write-read, or write-write operations, the integrity and consistency of data are maintained, and race conditions and other thread-safety-related problems are avoided.
[0046] As an optional but non-limiting implementation, memory operations are performed on the target memory through the memory operation logic in the current operation function, including the following steps A1 - A3:
[0047] Step A1: Lock the target memory through the locking logic in the current operation function.
[0048] Step A2: After locking the target memory, perform memory operations on the target memory through the memory operation logic in the current operation function.
[0049] Step A3: After performing memory operations on the target memory, release the lock on the locked target memory through the lock release logic in the current operation function.
[0050] See Figure 2 , when the current thread calls the current operation function to perform memory operations on the target memory, the locking logic in the current operation function will first execute to obtain the lock of the target memory to lock the target memory, ensuring that only one thread can operate on the target memory at the same time. After successfully locking the target memory, the memory operation logic in the current operation function will then be used to perform memory operations on the target memory. If the target memory cannot be locked successfully, the subsequent memory operation logic in the current operation function cannot be continued, and thus the current thread cannot operate on the target memory. When multiple threads perform memory operations simultaneously, it is necessary to ensure thread safety to avoid race conditions and data inconsistency problems.
[0051] See Figure 2 , after performing memory operations on the target memory, the lock release logic in the current operation function will then be started in the current operation function to release the lock on the locked target memory, ensuring that when ending the call to the operation function to perform operations on the target memory, the lock release logic embedded in the current operation function can always be used to release the lock on the memory, thus avoiding the problem of deadlocks caused by forgetting to release the lock after locking due to complex business logic.
[0052] As an optional but non-limiting implementation, locking the target memory through the locking logic in the current operation function may include the following process:
[0053] Obtain the target lock pre-bound to the target memory through the locking logic in the current operation function, and lock the target memory with the target lock through the locking logic in the current operation function.
[0054] Memory and locks are two independent variables with weak correlation between them. This may lead to developers easily forgetting to lock thread-unsafe memory during multi-threaded operations. Since memory and locks are managed separately, developers need to identify which memory is thread-unsafe and manually add locks when necessary to ensure thread safety. However, this reliance on developers' memory and attention is prone to omissions or errors. The factor of manual guarantee is usually unreliable because people are prone to making mistakes or overlooking details, which may lead to thread safety issues such as race conditions and data inconsistency.
[0055] See Figure 2 , referring to the Ownership design, bind the target memory to be locked and the lock together. To obtain the memory, it must be through the target operation function used to operate on the target memory, and the target operation function locks and unlocks the target memory on the stack. Since the target operation function locks and unlocks on the stack, when the function returns, the lock is automatically released, avoiding issues such as deadlocks caused by forgetting to release the lock. Locking the memory through the target operation function can ensure that the lock has been obtained before reading the memory, thus avoiding data race issues caused by forgetting to lock. Moreover, encapsulating memory operations with data races in a function and locking and unlocking through the target operation function can confine the business code with data races together, preventing the business code from being concurrently accessed in different places and thus preventing business errors.
[0056] Optionally, the target lock pre-bound to the target memory is created and bound based on a thread mutex during initialization, and different memories are bound to their respective allocated locks during pre-creation.
[0057] Optionally, the target lock pre-bound to the target memory is configured to support enabling the priority inversion inheritance function during initialization creation.
[0058] Priority inversion refers to the situation where a low-priority thread acquires a lock, and then other high-priority threads come and wait for the lock and are suspended. However, since the low-priority thread cannot be allocated CPU time slices, the task cannot be completed for a long time, and finally gets stuck in such a state, which may ultimately cause all threads in the application to freeze and result in an ANR problem. Therefore, priority inheritance can be enabled by default based on the thread mutex pthread_mutex_t.
[0059] Among them, priority inheritance: In this solution, if a low-priority task holds a lock and a high-priority task attempts to acquire this lock, the low-priority task will temporarily raise its priority to the same level as the high-priority task. Once the low-priority task completes its critical section and releases the lock, its priority resumes to the original level.
[0060] Among them, priority ceiling, this method assigns a priority ceiling to each lock. When a task acquires a lock, the priority of the task will be raised (or maintained) to the same level as the priority ceiling of the lock. This can ensure that a low-priority task cannot prevent a high-priority task from accessing different fair locks while holding the lock. A fair lock is a synchronization primitive used to achieve ordered access to shared resources by multiple competing threads.
[0061] Among them, in a fair lock, when a thread acquires the lock, the resource will be allocated to the thread that has been waiting the longest. In other words, it follows the principle of first come, first served. In contrast, an unfair lock only guarantees that a certain thread will ultimately acquire the lock, but does not consider the order of waiting time. The way a fair lock alleviates the priority inversion problem is that it tries to follow the principle of "first come, first served" to ensure that the lock is allocated in the order of arrival. This mechanism helps to alleviate priority inversion to a certain extent because it reduces the possibility that a low-priority thread occupies the lock for a long time and blocks a high-priority thread.
[0062] S130. Return the memory operation result of the target memory through the current operation function.
[0063] When the current thread finishes calling the current operation function, return the operation result of the memory operation on the target memory by the memory operation logic in the current operation function through the current operation function.
[0064] As an optional but non-limiting implementation manner, see Figure 2 , there is also memory exception capture logic embedded in the current operation function. The memory processing method for multi-threads in this embodiment further includes the following:
[0065] The target memory that has a preset abnormal state is captured through the memory exception capture logic in the current operation function, and the captured target memory that has a preset abnormal state is locked and released.
[0066] See also Figure 2 When using the pthread_mutex_t series of thread mutex locks, if a memory crash occurs when performing business logic after locking, the corresponding lock may not be released correctly, resulting in the inability to read the lock at the subsequent location where the lock is used. To this end, the memory exception capture logic in the current operation function can be used to capture the target memory with a preset exception state. Once a memory crash occurs, the memory exception capture logic in the current operation function will capture the memory crash, and then release the lock added to the target memory before crashing, ensuring that the lock on the target memory can be released as expected when the memory crashes, thereby avoiding the problem of the lock not being released correctly during a crash.
[0067] The disclosed embodiment embeds the locking logic and the lock release logic in the current operation function, so that only the thread that obtains the lock can perform memory operations, thereby avoiding the problems of race conditions and data inconsistency. Each time, the memory can be operated only by using the current operation function, and the locking logic, the memory operation logic and the lock release logic are encapsulated in the current operation function, so that the code is more modular and centrally managed. In this way, if the call of the current operation function is terminated, the lock release logic in the current operation function needs to be executed, and the problem of deadlock caused by forgetting to release the lock after locking due to complex business logic is avoided as much as possible. It can ensure that the access to the target memory in a multi-threaded environment is thread-safe, thereby avoiding memory data conflicts and errors caused by concurrent access of multiple threads. In addition, the locking logic, the memory operation logic and the lock release logic are encapsulated in the current operation function, so that the code is more modular and centrally managed. When the logic related to the memory operation needs to be modified or maintained, only the current operation function needs to be focused on, thereby improving the maintainability of the code.
[0068] Figure 3 A flow chart of a multi-threaded memory processing method provided in an embodiment of the present disclosure is applicable to the case where memory is read and written in a multi-threaded situation. The multi-threaded memory processing device can be implemented in the form of software and / or hardware, and is generally integrated on any electronic device with network communication function, which can be a mobile terminal, PC or server, etc.
[0069] like Figure 3 As shown, the multi-threaded memory processing device of the embodiment of the present disclosure may include the following process:
[0070] A determination module 310, configured to determine a current operation function called by a current thread when performing a memory operation on a target memory, where a locking logic, a memory operation logic, and a lock release logic are embedded in the current operation function;
[0071] An operation module 320, configured to perform a memory operation on the target memory through the memory operation logic in the current operation function, where the locking logic and the lock release logic in the current operation function are used to lock and release the target memory;
[0072] A return module 330, configured to return a memory operation result of the target memory through the current operation function.
[0073] Based on the technical solution of the above embodiment, optionally, the memory operation includes a read operation on the memory, a write operation on the memory, and a concurrent operation combined based on the read operation on the memory and the write operation on the memory.
[0074] Based on the technical solution of the above embodiment, optionally, performing a memory operation on the target memory through the memory operation logic in the current operation function includes:
[0075] Locking the target memory through the locking logic in the current operation function;
[0076] After locking the target memory, performing a memory operation on the target memory through the memory operation logic in the current operation function;
[0077] After performing the memory operation on the target memory, releasing the lock on the locked target memory through the lock release logic in the current operation function.
[0078] Based on the technical solution of the above embodiment, optionally, locking the target memory through the locking logic in the current operation function includes:
[0079] Obtaining a target lock pre-bound to the target memory through the locking logic in the current operation function;
[0080] Locking the target memory with the target lock through the locking logic in the current operation function.
[0081] Based on the technical solution of the above embodiment, optionally, the target lock pre-bound to the target memory is configured to support enabling a priority inversion inheritance function during initialization creation.
[0082] Based on the technical solution of the above embodiment, optionally, the target lock pre-bound to the target memory is created and bound based on a thread mutex during initialization, and different memories are bound with their respective allocated locks during pre-creation.
[0083] Based on the technical solution of the above embodiment, optionally, a memory exception capture logic is further embedded in the current operation function; the method further includes:
[0084] Capturing a target memory in a preset abnormal state through the memory exception capture logic in the current operation function;
[0085] Releasing the lock on the captured target memory in a preset abnormal state.
[0086] In the technical solution of the embodiment of the present disclosure, the current operation function called when the current thread performs a memory operation on the target memory is determined. A locking logic, a memory operation logic, and a lock release logic are embedded in the current operation function; the target memory is operated on through the memory operation logic in the current operation function, and the locking logic and the lock release logic in the current operation function are used to lock and release the lock on the target memory; the memory operation result on the target memory is returned through the current operation function. In this solution, by embedding the locking logic and the lock release logic in the current operation function, only the thread that obtains the lock can perform a memory operation, avoiding the problems of race conditions and data inconsistency. Each time, only the current operation function can be used to operate on the memory, and the locking logic, the memory operation logic, and the lock release logic are encapsulated in the current operation function, making the code more modular and centrally managed. In this way, if the call of the current operation function ends, the lock release logic in the current operation function needs to be executed, as much as possible avoiding the problem of deadlock caused by forgetting to release the lock after locking due to complex business logic, and ensuring that the access to the target memory in a multi-threaded environment is thread-safe, thereby avoiding memory data conflicts and errors caused by multi-threaded concurrent access.
[0087] The multi-threaded memory processing device provided by the embodiment of the present disclosure can execute the multi-threaded memory processing method provided by any embodiment of the present disclosure, and has corresponding functional modules and beneficial effects for executing the multi-threaded memory processing method.
[0088] It should be noted that the various units and modules included in the above device are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be realized; in addition, the specific names of the functional units are only for the convenience of mutual distinction and do not limit the protection scope of the embodiment of the present disclosure.
[0089] Figure 4 It is a schematic structural diagram of an electronic device for implementing a multi-threaded memory processing method provided by an embodiment of the present disclosure. Referring below Figure 4 , which shows an electronic device suitable for implementing an embodiment of the present disclosure (such as Figure 4Schematic structural diagram of the terminal device or server) 400 in it. The terminal device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), PMPs (Portable Multimedia Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 4 The electronic device shown is merely an example and should not impose any limitations on the functions and usage scope of the embodiments of the present disclosure.
[0090] As Figure 4 shown, the electronic device 400 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 401, which may perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 402 or the program loaded from the storage device 408 into the random access memory (RAM) 403. In the RAM 403, various programs and data required for the operation of the electronic device 400 are also stored. The processing device 401, the ROM 402, and the RAM 403 are connected to each other through a bus 404. The editing / output (I / O) interface 405 is also connected to the bus 404.
[0091] Generally, the following devices may be connected to the I / O interface 405: an input device 406 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 407 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 408 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 409. The communication device 409 may allow the electronic device 400 to communicate with other devices wirelessly or wiredly to exchange data. Although Figure 4 the electronic device 400 with various devices is shown, it should be understood that it is not required to implement or have all the shown devices. More or fewer devices may be alternatively implemented or had.
[0092] Particularly, according to the embodiments of the present disclosure, the process described above with reference to the flowchart may be implemented as a computer software program. For example, the embodiments of the present disclosure include a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program contains program codes for executing the multi-threaded memory processing method shown in the flowchart. In such an embodiment, the computer program may be downloaded and installed from the network through the communication device 409, or installed from the storage device 408, or installed from the ROM 402. When the computer program is executed by the processing device 401, the above-mentioned functions defined in the multi-threaded memory processing method of the embodiments of the present disclosure are executed.
[0093] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are for illustrative purposes only and are not used to limit the scope of these messages or information.
[0094] The electronic device provided in the embodiments of the present disclosure and the multi-threaded memory processing method provided in the above embodiments belong to the same inventive concept. Technical details not described in detail in this embodiment can be referred to in the above embodiments, and this embodiment has the same beneficial effects as the above embodiments.
[0095] The embodiments of the present disclosure provide a computer storage medium, on which a computer program is stored, and when the program is executed by a processor, it implements the multi-threaded memory processing method provided in the above embodiments.
[0096] It should be noted that the computer-readable medium in the present disclosure may be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program can be used by or in combination with an instruction execution system, apparatus, or device. In the present disclosure, the computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium may also be any computer-readable medium other than the computer-readable storage medium, and the computer-readable signal medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.
[0097] In some embodiments, the client and the server can communicate using any currently known or future-developed network protocol such as HTTP (HyperText Transfer Protocol), and can be interconnected with digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include local area networks ("LANs"), wide area networks ("WANs"), the Internet (e.g., the Internet), and end-to-end networks (e.g., ad hoc end-to-end networks), as well as any currently known or future-developed networks.
[0098] The above computer-readable medium can be included in the above electronic device; it can also exist separately without being assembled into the electronic device.
[0099] The above computer-readable medium carries one or more programs. When the above one or more programs are executed by the electronic device, the electronic device is caused to: determine the current operation function called when the current thread performs a memory operation on the target memory, where the current operation function embeds locking logic, memory operation logic, and lock release logic; perform a memory operation on the target memory through the memory operation logic in the current operation function, and the locking logic and lock release logic in the current operation function are used to lock and release the target memory; return the memory operation result of the target memory through the current operation function.
[0100] Computer program code for performing the operations of the present disclosure can be written in one or more programming languages or combinations thereof. The above programming languages include, but are not limited to, object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., by using an Internet service provider to connect through the Internet).
[0101] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a portion of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks may occur in a different order than noted in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or by a combination of dedicated hardware and computer instructions.
[0102] The units involved in the embodiments described in the present disclosure can be implemented in software or in hardware. Among them, the name of the unit does not constitute a limitation to the unit itself in some cases. For example, the first acquisition unit can also be described as "the unit for acquiring at least two Internet protocol addresses".
[0103] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that can be used include: Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), Systems on Chip (SOCs), Complex Programmable Logic Devices (CPLDs), and so on.
[0104] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a Read-Only Memory (ROM), an Erasable Programmable Read-Only Memory (EPROM or Flash memory), an optical fiber, a portable Compact Disc Read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
[0105] The above description is only a preferred embodiment of the present disclosure and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the disclosure involved in the present disclosure is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosure concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present disclosure.
[0106] In addition, although the operations are depicted in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown or in sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features described in the context of separate embodiments may also be implemented combinatorially in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments.
[0107] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. On the contrary, the specific features and acts described above are merely example forms of implementing the claims.
Claims
1. A multi-threaded memory processing method, characterized in that, The method includes: Determining a current operation function called when the current thread performs a memory operation on a target memory, where a locking logic, a memory operation logic, and a lock release logic are embedded in the current operation function; Performing a memory operation on the target memory through the memory operation logic in the current operation function, where the locking logic and the lock release logic in the current operation function are used to lock and release the target memory; Returning, through the current operation function, a memory operation result for the target memory.
2. The method according to claim 1, characterized in that The memory operation includes a read operation on the memory, a write operation on the memory, and a concurrent operation combined based on the read operation on the memory and the write operation on the memory.
3. The method according to claim 1, characterized in that, Performing a memory operation on the target memory through the memory operation logic in the current operation function includes: Locking the target memory through the locking logic in the current operation function; Performing a memory operation on the target memory through the memory operation logic in the current operation function after locking the target memory; Releasing the lock on the locked target memory through the lock release logic in the current operation function after performing the memory operation on the target memory.
4. The method according to claim 3, wherein Locking the target memory through the locking logic in the current operation function includes: Obtaining a target lock pre-bound to the target memory through the locking logic in the current operation function; Locking the target memory with the target lock through the locking logic in the current operation function.
5. The method according to claim 4, wherein The target lock pre-bound to the target memory is configured to support enabling the priority inversion inheritance function when it is initialized and created.
6. The method according to claim 4, wherein The target lock pre-bound to the target memory is created and bound based on a thread mutex during initialization, and different memories are bound with their respective allocated locks when they are pre-created.
7. The method according to claim 3, wherein A memory exception capture logic is also embedded in the current operation function; the method further includes: Capturing a target memory in a preset abnormal state through the memory exception capture logic in the current operation function; Releasing the lock on the captured target memory in the preset abnormal state.
8. A multi-threaded memory processing device, characterized in that, The device includes: A determination module, configured to determine a current operation function called when the current thread performs a memory operation on a target memory, where a locking logic, a memory operation logic, and a lock release logic are embedded in the current operation function; An operation module, configured to perform a memory operation on the target memory through the memory operation logic in the current operation function, where the locking logic and the lock release logic in the current operation function are used to lock and release the target memory; A return module, configured to return, through the current operation function, a memory operation result for the target memory.
9. An electronic device, characterized in that, The electronic device includes: One or more processors; A storage device, configured to store one or more programs, When the one or more programs are executed by the one or more processors, enabling the one or more processors to implement the multi-threaded memory processing method according to any one of claims 1-7.
10. A storage medium containing computer-executable instructions, characterized in that, The computer-executable instructions, when executed by a computer processor, are used to execute the multi-threaded memory processing method according to any one of claims 1-7.