Electronic equipment, link recovery method, medium and product

Abstract

The invention discloses electronic equipment, a link recovery method, a medium and a product. The electronic equipment comprises a controller, a phase-locked loop component, a media access control layer component and an interface component, the controller is respectively connected with the phase-locked loop component and the media access control layer component, and the media access control layer component is connected with the interface component. And the controller is used for acquiring the stability state of the phase-locked loop component, determining a target link recovery mode from the first link recovery mode and the second link recovery mode according to the stability state, and executing the target link recovery mode so as to perform recovery processing on a link between the electronic equipment and the opposite-end equipment. Wherein the first link recovery mode is that the queue depth of a buffer area in the interface component is adjusted through the media access control layer component; the second link recovery mode is to control the media access control layer component to perform link negotiation with the opposite-end equipment. In this way, the link stability is improved.

Description

Technical Field

[0001] This application relates to the technical field of electronic devices, and in particular, to an electronic device, a link recovery method, a medium, and a product. Background Art

[0002] An electronic device can be connected to a peer device (another electronic device) through a Peripheral Component Interconnect Express (PCIe) link. In an electronic device, a phase-locked loop component can provide a clock signal for the electronic device, and the electronic device can perform data transmission and reception based on the clock signal.

[0003] However, when the phase-locked loop component is affected by external interference, the output clock signal may become unstable. When the clock signal is unstable, there are problems with abnormal data transmission and reception, resulting in poor stability of the PCIe link between the electronic device and the peer device. Summary of the Invention

[0004] This application provides an electronic device, a link recovery method, a medium, and a product to at least solve the problem of low link stability in the related art.

[0005] This application provides an electronic device, including a controller, a phase-locked loop component, a media access control layer component, and an interface component; the controller is respectively connected to the phase-locked loop component and the media access control layer component, and the media access control layer component is connected to the interface component;

[0006] The controller is configured to obtain the stability state of the phase-locked loop component;

[0007] The controller is further configured to determine a target link recovery method from a first link recovery method and a second link recovery method according to the stability state; the first link recovery method is to adjust the queue depth of the buffer in the interface component through the media access control layer component; the second link recovery method is to control the media access control layer component to perform link negotiation with the peer device;

[0008] The controller is further configured to execute the target link recovery method to perform link recovery processing on the link between the electronic device and the peer device.

[0009] This application also provides a link recovery method, including:

[0010] Obtaining the stability state of the phase-locked loop component through the controller;

[0011] The controller determines a target link recovery method from a first link recovery method and a second link recovery method according to the stability state. The first link recovery method is to adjust the queue depth of the buffer in the interface component through the media access control layer component. The second link recovery method is to control the media access control layer component to perform link negotiation with the peer device.

[0012] The controller executes the target link recovery method to recover the link between the electronic device and the peer device.

[0013] This application also provides a computer-readable storage medium. A computer program is stored in the computer-readable storage medium. When the computer program is executed by a processor, the steps of the link recovery method as described above are implemented.

[0014] This application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the link recovery method as described above are implemented.

[0015] Through this application, the controller in the electronic device can determine the target link recovery method from the first link recovery method (adjusting the queue depth of the buffer in the interface component through the media access control layer component) and the second link recovery method (controlling the media access control layer component to perform link negotiation with the peer device) according to the stability state of the phase-locked loop component, and then execute the target link recovery method, so as to recover the link between the electronic device and the peer device, improving the link stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more clearly illustrate the embodiments of this application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 Structural schematic diagram of an electronic device provided by an embodiment of this application Figure 1 ;

[0018] Figure 2 Structural schematic diagram of an electronic device provided by an embodiment of this application Figure 2 ;

[0019] Figure 3 Scenario schematic diagram of a link recovery method provided by an embodiment of this application;

[0020] Figure 4 Structural schematic diagram of an electronic device provided by an embodiment of this application Figure 3 ;

[0021] Figure 5 This is a schematic flowchart of a link recovery method provided by an embodiment of the present application. Specific implementation manners

[0022] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0023] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0024] An electronic device can be connected to a peer device (another electronic device) through a Peripheral Component Interconnect Express (PCIe) link. In the electronic device, a phase-locked loop component can provide a clock signal for the electronic device, and the electronic device can perform data transmission and reception based on the clock signal.

[0025] However, when the phase-locked loop component is affected by external interference, the output clock signal is unstable. In the case of an unstable clock signal, there are problems with abnormal data transmission and reception, resulting in a poor stability problem in the PCIe link between the electronic device and the peer device.

[0026] Therefore, in view of the above technical problems in the related art, it is found in the research process that if the controller in the electronic device can determine the target link recovery method from the first link recovery method and the second link recovery method according to the stability state of the phase-locked loop component, and then execute the target link recovery method, the link between the electronic device and the peer device can be recovered. Therefore, this application proposes an electronic device, a link recovery method, a medium and a product. Specifically, the electronic device may include a controller, a phase-locked loop component, a media access control layer component, and an interface component; the controller is respectively connected to the phase-locked loop component and the media access control layer component, and the media access control layer component is connected to the interface component. Among them, the controller is configured to obtain the stability state of the phase-locked loop component, and determine the target link recovery method from the first link recovery method and the second link recovery method according to the stability state, and execute the target link recovery method to recover the link between the electronic device and the peer device. Among them, the first link recovery method is to adjust the queue depth of the buffer in the interface component through the media access control layer component; the second link recovery method is to control the media access control layer component to negotiate a link with the peer device.

[0027] In order to enable those skilled in the art of this technology to better understand the solution of this application, the following further elaborates on this application in conjunction with the drawings and specific implementation manners.

[0028] Figure 1 Structural schematic of an electronic device provided by an embodiment of this application Figure 1 。

[0029] As Figure 1 shown, the electronic device 10 includes a controller 101, a phase-locked loop component 102, a media access control layer component 103, and an interface component 104. In addition, the electronic device 10 may further include a physical layer component 105.

[0030] The controller 101 is respectively connected to the phase-locked loop component 102 and the media access control layer component 103.

[0031] The media access control layer component 103 is connected to the interface component 104.

[0032] In addition, when the electronic device 10 includes a physical layer component 105, the physical layer component 105 is connected to the interface component 104.

[0033] It should be noted that the electronic device 10 may be a solid-state drive or other PCIe devices, and the embodiments of this application do not limit this.

[0034] The controller 101 is configured to obtain the stability state of the phase-locked loop component 102.

[0035] Among them, the stability state is a normal state or an abnormal state.

[0036] It should be noted that the abnormal state is any one of the following: overspeed margin state (which can also be called PLL_FAST_INFO state), underspeed margin state (which can also be called PLL_SLOW_INFO state), overspeed error state (which can also be called PLL_FAST_ERR state), and underspeed error state (which can also be called PLL_SLOW_ERR state).

[0037] Next, the process by which the controller 101 obtains the stability state of the phase-locked loop component 102 will be described.

[0038] In one implementation:

[0039] The controller 101 is used to obtain the clock signal frequency of the phase-locked loop component 102. For example, the clock signal frequency can be 100 MHz.

[0040] The controller 101 is used to determine the stability state of the phase-locked loop component 102 according to the clock signal frequency.

[0041] In one implementation, the controller 101 is used to determine the stability state of the phase-locked loop component 102 according to the clock signal frequency and the frequency ranges corresponding to the respective stability states.

[0042] It should be noted that the frequency range corresponding to the normal state is the first frequency range, the frequency range corresponding to the overspeed margin state is the second frequency range, the frequency range corresponding to the underspeed margin state is the third frequency range, the frequency range corresponding to the overspeed error state is the fourth frequency range, and the frequency range corresponding to the underspeed error state is the fifth frequency range.

[0043] It should also be noted that the fifth frequency range is less than the third frequency range, the third frequency range is less than the first frequency range, the first frequency range is less than the second frequency range, and the second frequency range is less than the fourth frequency range.

[0044] The controller 101 is further used to determine the target link recovery method from the first link recovery method and the second link recovery method according to the stability state.

[0045] It should be noted that the first link recovery method is to adjust the queue depth of the buffer in the interface component 104 through the media access control layer component 103.

[0046] It should also be noted that the buffer includes a receive buffer (which can also be called a receive-end data buffer) and a transmit buffer (which can also be called a transmit-end data buffer). Figure 2 Schematic structure of an electronic device provided by an embodiment of the present applicationFigure 2 As shown in Figure 2 , the interface component 104 includes a receive buffer 1041 and a transmit buffer 1042. Additionally, the interface component 104 may further include a first register 1043, a decoder 1044, a second register 1045, and an encoder 1046.

[0047] The second link recovery method is to control the media access control layer component 103 to negotiate a link with the peer device.

[0048] Next, the process by which the controller 101 determines the target link recovery method from the first link recovery method and the second link recovery method according to the stability state will be described.

[0049] In one implementation:

[0050] The controller 101 is configured to determine an exception level according to the stability state. In one implementation, the controller 101 may determine whether the stability state is an abnormal state. The controller 101 may determine the exception level according to the stability state when the stability state is an abnormal state. Additionally, it should be noted that the controller 101 may continue to monitor the stability state of the phase-locked loop component 102 when the stability state is not an abnormal state.

[0051] Among them, the exception level is the first exception level (which may also be referred to as the low exception level or the low error exception level) or the second exception level (which may also be referred to as the high exception level or the high error exception level).

[0052] It should be noted that when the stability state is the overspeed margin state or the underspeed margin state, the exception level is the first exception level; when the stability state is the overspeed error state or the underspeed error state, the exception level is the second exception level.

[0053] The controller 101 may determine that the target link recovery method is the first link recovery method based on the exception level being the first exception level.

[0054] In one implementation, the controller 101 may determine that the link recovery method is the first sub-link recovery method in the first link recovery method based on the exception level being the first exception level and the stability state being the overspeed margin state. Among them, the first sub-link recovery method is to perform a reduction process on the queue depth of the buffer.

[0055] In one implementation, the controller 101 may determine that the link recovery method is the second sub-link recovery method in the first link recovery method based on the exception level being the first exception level and the stability state being the underspeed margin state. Among them, the second sub-link recovery method is to perform an increase process on the queue depth of the buffer.

[0056] When the exception level is the second exception level, the controller 101 may determine that the target link recovery method is the second link recovery method.

[0057] The controller 101 is further configured to execute the target link recovery method to perform a recovery process on the link between the electronic device 10 and the peer device.

[0058] Beneficial effects of this embodiment: In this embodiment, the electronic device may include a controller, a phase-locked loop component, a media access control layer component, and an interface component; the controller is respectively connected to the phase-locked loop component and the media access control layer component, and the media access control layer component is connected to the interface component. Among them, the controller is configured to obtain the stability state of the phase-locked loop component, and according to the stability state, determine the target link recovery method from a first link recovery method (adjusting the queue depth of the buffer in the interface component through the media access control layer component) and a second link recovery method (controlling the media access control layer component to perform link negotiation with the peer device), and execute the target link recovery method to perform a recovery process on the link between the electronic device and the peer device. Through the above method, the link can be recovered in a timely manner to improve the link stability, and the problem of poor stability of the PCIe link between the electronic device and the peer device in the related art is solved.

[0059] Next, the process of the controller 101 executing the target link recovery method to perform a recovery process on the link between the electronic device 10 and the peer device when the target link recovery method is the first link recovery method will be described.

[0060] In one implementation:

[0061] When the target link recovery method is the first link recovery method, the controller 101 is configured to send a queue depth adjustment instruction to the interface component 104 through the media access control layer component 103.

[0062] In one implementation, the first link recovery method includes a first sub-link recovery method and a second sub-link recovery method.

[0063] Among them, the first sub-link recovery method is to perform a reduction process on the queue depth of the buffer. The second sub-link recovery method is to perform an increase process on the queue depth of the buffer.

[0064] In one implementation, when the target link recovery method is the first sub-link recovery method, the controller 101 sends a first queue depth adjustment instruction to the interface component 104 through the media access control layer component 103. Among them, the first queue adjustment instruction is an instruction to perform a reduction process on the queue depth of the buffer.

[0065] In one implementation, when the target link recovery mode is the second sub-link recovery mode, the controller 101 sends a second queue depth adjustment instruction to the interface component 104 through the media access control layer component 103. The second queue adjustment instruction is an instruction for increasing the queue depth of the buffer.

[0066] The interface component 104 is configured to adjust the value of the queue depth register corresponding to the buffer based on the queue depth adjustment instruction, so as to adjust the queue depth of the buffer.

[0067] In one implementation, the interface component 104 can adjust the value of the queue depth register corresponding to the buffer based on the first queue depth adjustment instruction. For example, the interface component 104 can adjust the value of the queue depth register from indicating a queue depth of 100 to a queue depth of 50 based on the first queue depth adjustment instruction.

[0068] In one implementation, the interface component 104 can adjust the value of the queue depth register corresponding to the buffer based on the second queue depth adjustment instruction. For example, the interface component 104 can adjust the value of the queue depth register from indicating a queue depth of 100 to a queue depth of 150 based on the second queue depth adjustment instruction.

[0069] Advantageous effects of this embodiment: In this embodiment, when the target link recovery mode is the first link recovery mode, the controller can send a queue depth adjustment instruction to the interface component through the media access control layer component, so that the interface component adjusts the value of the queue depth register corresponding to the buffer based on the queue depth adjustment instruction to adjust the queue depth of the buffer. By the above method of increasing the queue depth of the buffer when the stability state is the under-speed margin state, the capacity of the buffer can be expanded to accommodate the clock delay deviation, and link interruption or invalid retransmission caused by the buffer being emptied can be avoided. That is to say, the situation where the buffer in the interface component has an underflow fault due to the instability of the phase-locked loop component can be avoided. By the above method of reducing the queue depth of the buffer when the stability state is the over-speed margin state, the overflow fault of the buffer can be avoided. That is to say, by the above method of adjusting the queue depth of the buffer, the anti-under-speed disturbance ability of the receive buffer in the buffer is improved, the anti-over-speed congestion ability of the transmit buffer in the buffer is improved, the failure rate of the buffer is reduced, and the link stability is improved.

[0070] Next, the process in which the controller 101 executes the target link recovery method to recover the link between the electronic device 10 and the peer device in the case where the target link recovery method is the second link recovery method will be described.

[0071] In one implementation:

[0072] Figure 3 This is a schematic diagram of the scenario of a link recovery method provided by an embodiment of this application. As Figure 3 shown, this scenario includes the electronic device 10 and the peer device 20. It should be noted that the peer device 20 can be a central processing unit, a baseboard management controller, or other PCIe devices, and the embodiments of this application do not limit this.

[0073] The electronic device 10 includes a controller 101, a phase-locked loop component 102, a media access control layer component 103, an interface component 104, and a physical layer component 105.

[0074] Among them, the controller 101 is respectively connected to the phase-locked loop component 102 and the media access control layer component 103. The media access control layer component 103 is connected to the interface component 104. The physical layer component 105 is connected to the interface component 104.

[0075] The peer device 20 includes a peer media access control layer component 201, a peer interface component 202, and a peer physical layer component 203. In addition, the peer device 20 may further include a peer controller 204 and a peer phase-locked loop component 205.

[0076] Among them, the peer media access control layer component 201 is connected to the peer interface component 202. The peer physical layer component 203 is connected to the peer interface component 202. In addition, the peer controller 204 may also be respectively connected to the peer phase-locked loop component 205 and the peer media access control layer component 201.

[0077] In addition, it should be noted that the physical layer component 105 can be communicatively connected to the peer physical layer component 203.

[0078] The controller 101 is configured to control the media access control layer component 103 to enter the recovery state (recovery state) from the working state and control the media access control layer component 103 to generate a control instruction in the case where the target link recovery method is the second link recovery method.

[0079] In one implementation, Figure 4 This is a schematic structural diagram of an electronic device provided by an embodiment of this application Figure 3 . As Figure 4As shown in the figure, the Media Access Control (MAC) layer component 103 includes a status management component (which can also be referred to as a Link Training and Status State Machine (LTSSM) management component) 1031, a packet enhancement component (which can also be referred to as an enhanced synchronization transmission component) 1032, and a control instruction generation component (which can also be referred to as an Electric Idle Exit Ordered Set (EIEOS) component) 1033. Among them, the status management component 1031 is used to switch the status of the MAC layer component 103 from the working state to the recovery state in response to the control of the controller 101; the control instruction generation component 1033 is used to generate control instructions in response to the control of the controller 101.

[0080] The physical layer component 105 is used to obtain the control instructions sent by the MAC layer component 103 through the interface component 104.

[0081] The physical layer component 105 is also used to generate a target level signal (EIEOS level signal) according to the recovery state control instruction.

[0082] The physical layer component 105 is also used to send the target level signal to the peer physical layer component 203 of the peer device 20, so that the peer physical layer component 203 can obtain the recovery state control instruction based on the target level signal, and send the recovery state control instruction to the peer MAC layer component 201 of the peer device 20 through the peer interface component 202; the recovery state control instruction is used for the peer MAC layer component 201 to enter the recovery state from the working state.

[0083] The MAC layer component 103 is also used to generate multiple target packets based on the packet quantity information when the MAC layer component 103 is in the recovery state, and send the multiple target packets to the peer MAC layer component 201 of the peer device 20 through the interface component 104 and the physical layer component 105. It can be understood that the MAC layer component 103 sends the multiple target packets to the peer MAC layer component 201 through the interface component 104, the physical layer component 105, the peer physical layer component 203, and the peer interface component 202.

[0084] It should be noted that, as Figure 4 shown in the figure, it is the packet enhancement component 1032 that is used to generate multiple target packets based on the packet quantity information.

[0085] Among them, the target message is used for the peer Media Access Control (MAC) layer component 201 in the recovery state and the MAC layer component 103 in the recovery state to perform link negotiation, so as to perform link recovery processing between the electronic device 10 and the peer device 20.

[0086] It should be noted that the message quantity information includes the initial message quantity and the message quantity increasing method.

[0087] It should be noted that in one implementation, the message increasing method is to increase the initial message quantity according to a preset multiple.

[0088] In one implementation, the message increasing method is to increase the initial message quantity according to a preset increasing quantity.

[0089] Next, the process in which the MAC layer component 103 sends multiple target messages to the peer MAC layer component 201 of the peer device 20 through the interface component 104 and the physical layer component 105 based on the message quantity information will be described.

[0090] In one implementation:

[0091] The target message may include a first target message and a second target message.

[0092] The MAC layer component 103 sends multiple first target messages to the peer MAC layer component 201 of the peer device 20 through the interface component 104, the physical layer component 105, the peer physical layer component 203, and the peer interface component 202 based on the message quantity information. Among them, the quantity of the first target message is determined by the MAC layer component 103 based on the message quantity information. It should be noted that the first target message includes a first supported rate and a first indication information. Among them, the first supported rate is the maximum rate supported by the electronic device 10, and the second indication information is used to indicate that the electronic device 10 needs to switch the rate.

[0093] In response to receiving the first target message, the peer MAC layer component 201 sends multiple first peer messages to the MAC layer component 103 through the peer interface component 202, the peer physical layer component 203, the physical layer component 105, and the interface component 104. Among them, the quantity of the first peer message is determined by the peer MAC layer component 201 based on the initial message quantity. In addition, the first peer message includes a second supported rate and a first indication information. Among them, the second supported rate is the maximum rate supported by the peer device 20, and the second indication information is used to indicate that the peer device 20 needs to switch the rate.

[0094] The media access control layer component 103, in response to receiving the first peer message, determines a first target negotiation rate based on the second supported rate in the first peer message and the first supported rate (the maximum rate supported by the electronic device 10), and generates a second target message according to the first target negotiation rate. It should be noted that the second target message includes the first target negotiation rate and a third indication message. The third indication message is used to instruct the electronic device 10 to stop switching the rate.

[0095] Based on the message quantity information, the media access control layer component 103 sends multiple second target messages to the peer media access control layer component 201 through the interface component 104, the physical layer component 105, the peer physical layer component 203, and the peer interface component 202. The quantity of the second target messages is determined by the media access control layer component 103 based on the message quantity information.

[0096] The peer media access control layer component 201, in response to receiving the second target message, sends a second peer message to the media access control layer component 103 through the peer interface component 202, the peer physical layer component 203, the physical layer component 105, and the interface component 104. The quantity of the second peer message is determined by the peer media access control layer component 201 based on the initial message quantity. Additionally, the second peer message includes the second target negotiation rate and a fourth indication message. The second target negotiation rate is determined by the peer media access control layer component 201 based on the second supported rate and the first supported rate. The fourth indication message is used to instruct the peer device 20 to stop switching the rate.

[0097] In addition, when the peer media access control layer component 201 identifies that the second target negotiation rate is consistent with the first target negotiation rate in the second target message, it controls the peer media access control layer component 201 to switch from the recovery state to the normal state.

[0098] When the media access control layer component 103 identifies that the first target negotiation rate is consistent with the second target negotiation rate in the second peer message, it controls the media access control layer component 103 to switch from the recovery state to the normal state.

[0099] Advantages of this embodiment: In this embodiment, when the target link recovery method is the second link recovery method, the controller can control the media access control layer component to enter the recovery state from the working state, and control the media access control layer component to generate a control instruction. The physical layer component can obtain the control instruction sent by the media access control layer component through the interface component, and generate a target level signal according to the control instruction. The physical layer component can also send the target level signal to the peer physical layer component of the peer device, so that the peer physical layer component can obtain a recovery state control instruction based on the target level signal, and send the recovery state control instruction to the peer media access control layer component of the peer device through the peer interface component; the recovery state control instruction is used for the peer media access control layer component to enter the recovery state from the working state. The media access control layer component can, when the media access control layer component is in the recovery state, based on the message quantity information, send multiple target messages to the peer media access control layer component of the peer device through the interface component and the physical layer component; the target messages are used for the peer media access control layer component to perform link negotiation to recover the link between the electronic device and the peer device; wherein, the message quantity information includes an initial message quantity and a message quantity increase method. Through the above method, when it is determined to adopt the second link recovery method for link recovery based on the stability state of the phase-locked loop component, on the one hand, by increasing the quantity of target messages (the first target message and the second target message) based on the message increase method, the probability that the peer device receives the target messages is increased, thereby improving the effect and success rate of link negotiation between the electronic device and the peer device; on the other hand, by re-performing link negotiation, the link stability can be improved.

[0100] Figure 5 It is a schematic flowchart of a link recovery method provided by an embodiment of this application. Refer to Figure 5 , and the method specifically includes the following steps:

[0101] S501: Obtain the stability state of the phase-locked loop component through the controller.

[0102] In this embodiment, the electronic device includes a controller, a phase-locked loop component, a media access control layer component, an interface component, and a physical layer component. The controller is respectively connected to the phase-locked loop component and the media access control layer component, the media access control layer component is connected to the interface component, and the interface component is connected to the physical layer component.

[0103] The electronic device can obtain the stability state of the phase-locked loop component through the controller.

[0104] In one implementation:

[0105] The electronic device can obtain the clock signal frequency of the phase-locked loop component through the controller.

[0106] The electronic device can determine the stability state of the phase-locked loop component according to the clock signal frequency through the controller.

[0107] S502: Through the controller, determine the target link recovery method from the first link recovery method and the second link recovery method according to the stability state.

[0108] In this embodiment, the electronic device can determine the target link recovery method from the first link recovery method and the second link recovery method according to the stability state through the controller.

[0109] Among them, the first link recovery method is to adjust the queue depth of the buffer in the interface component through the media access control layer component.

[0110] The second link recovery method is to control the media access control layer component to negotiate a link with the peer device.

[0111] In one implementation:

[0112] The electronic device can determine the exception level according to the stability state through the controller.

[0113] Among them, when the stability state is the overspeed margin state or the underspeed margin state, the exception level is the first exception level; when the stability state is the overspeed error state or the underspeed error state, the exception level is the second exception level.

[0114] The electronic device can determine that the target link recovery method is the first link recovery method based on the exception level being the first exception level through the controller.

[0115] In one implementation, the electronic device can determine that the link recovery method is the first sub-link recovery method in the first link recovery method based on the exception level being the first exception level and the stability state being the overspeed margin state through the controller. In addition, the electronic device can determine that the link recovery method is the second sub-link recovery method in the first link recovery method based on the exception level being the first exception level and the stability state being the underspeed margin state through the controller.

[0116] It should be noted that the first sub-link recovery method is to perform a reduction process on the queue depth of the buffer. The second sub-link recovery method is to perform an increase process on the queue depth of the buffer.

[0117] In addition, the electronic device can determine that the target link recovery method is the second link recovery method based on the exception level being the second exception level through the controller.

[0118] S503: Execute the target link recovery method through the controller to perform a recovery process on the link between the electronic device and the peer device.

[0119] In this embodiment, the electronic device can execute a target link recovery method through the controller to perform link recovery processing on the link between the electronic device and the peer device.

[0120] In one implementation:

[0121] When the target link recovery method is the first link recovery method, the electronic device can send a queue depth adjustment instruction to the interface component through the media access control layer component through the controller, so that the interface component adjusts the value of the queue depth register corresponding to the buffer based on the queue depth adjustment instruction to adjust the queue depth of the buffer. The buffer includes a receive buffer and a transmit buffer.

[0122] In one implementation:

[0123] When the target link recovery method is the second link recovery method, the electronic device can control the media access control layer component to enter the recovery state from the working state through the controller and control the media access control layer component to generate a control instruction.

[0124] In addition, the electronic device can obtain the control instruction sent by the media access control layer component through the interface component through the physical layer component and generate a target level signal according to the control instruction.

[0125] The electronic device can send the target level signal to the peer physical layer component of the peer device through the physical layer component, so that the peer physical layer component obtains a recovery state control instruction based on the target level signal and sends the recovery state control instruction to the peer media access control layer component through the peer interface component; the recovery state control instruction is used for the peer media access control layer component to enter the recovery state from the working state.

[0126] When the media access control layer component is in the recovery state, the electronic device can generate a plurality of target packets based on the packet number information through the media access control layer component and send the plurality of target packets to the peer media access control layer component of the peer device through the interface component and the physical layer component; the target packets are used for the peer media access control layer component in the recovery state to negotiate a link with the media access control layer component in the recovery state to perform link recovery processing on the link between the electronic device and the peer device; the packet number information includes an initial packet number and a packet number increase method.

[0127] Advantages of this embodiment: In this embodiment, the electronic device can obtain the stability state of the phase-locked loop component through the controller, and determine the target link recovery method from the first link recovery method (adjusting the queue depth of the buffer in the interface component through the media access control layer component) and the second link recovery method (controlling the media access control layer component to perform link negotiation with the peer device) according to the stability state, and execute the target link recovery method to perform link recovery processing on the link between the electronic device and the peer device. Through the above method, the link can be recovered in a timely manner, solving the problem of poor stability of the link between the electronic device and the peer device in the related art.

[0128] An embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored, and the computer program is configured to execute the steps in any one of the above-mentioned link recovery method embodiments when running.

[0129] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drive, read-only memory (ROM for short), random access memory (RAM for short), mobile hard disk, magnetic disk or optical disk, etc., various media that can store computer programs.

[0130] An embodiment of the present application also provides a computer program product, the above computer program product includes a computer program, and the steps in any one of the above-mentioned link recovery method embodiments are implemented when the computer program is executed by a processor.

[0131] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium stores a computer program, and the steps in any one of the above-mentioned link recovery method embodiments are implemented when the computer program is executed by a processor.

[0132] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0133] The above is an electronic device, a link recovery method, a medium and a product provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. An electronic device, characterized in that, It includes a controller, a phase-locked loop component, a media access control layer component, and an interface component; the controller is respectively connected to the phase-locked loop component and the media access control layer component, and the media access control layer component is connected to the interface component; The controller is configured to obtain the stability state of the phase-locked loop component; The controller is further configured to determine a target link recovery mode from a first link recovery mode and a second link recovery mode according to the stability state; the first link recovery mode is to adjust the queue depth of the buffer in the interface component through the media access control layer component; the second link recovery mode is to control the media access control layer component to perform link negotiation with the peer device; The controller is further configured to execute the target link recovery mode to perform link recovery processing on the link between the electronic device and the peer device.

2. The electronic device according to claim 1, wherein When the controller determines the target link recovery mode from the first link recovery mode and the second link recovery mode according to the stability state, it is specifically configured to: Determine an exception level according to the stability state; wherein, when the stability state is an overspeed margin state or an underspeed margin state, the exception level is the first exception level; when the stability state is an overspeed error state or an underspeed error state, the exception level is the second exception level; Based on the exception level being the first exception level, determine that the target link recovery mode is the first link recovery mode; or, Based on the exception level being the second exception level, determine that the target link recovery mode is the second link recovery mode.

3. The electronic device according to claim 2, wherein When the controller determines that the link recovery mode is the first link recovery mode based on the exception level being the first exception level, it is specifically configured to: Based on the exception level being the first exception level and the stability state being the overspeed margin state, determine that the link recovery mode is the first sub-link recovery mode in the first link recovery mode; wherein, the first sub-link recovery mode is to perform a reduction process on the queue depth of the buffer; or, Based on the exception level being the first exception level and the stability state being the underspeed margin state, determine that the link recovery mode is the second sub-link recovery mode in the first link recovery mode; wherein, the second sub-link recovery mode is to perform an increase process on the queue depth of the buffer.

4. The electronic device according to any one of claims 1-3, characterized in that, When the controller executes the target link recovery mode to perform link recovery processing on the link between the electronic device and the peer device, it is specifically configured to: When the target link recovery mode is the first link recovery mode, send a queue depth adjustment instruction to the interface component through the media access control layer component; The interface component is configured to adjust the value of the queue depth register corresponding to the buffer based on the queue depth adjustment instruction to adjust the queue depth of the buffer.

5. The electronic device according to claim 4, characterized in that, The buffer includes a receive buffer and a transmit buffer.

6. The electronic device according to claim 2, wherein The electronic device further includes a physical layer component, and the physical layer component is connected to the interface component; when the controller executes the target link recovery method to perform link recovery processing between the electronic device and the peer device, it is specifically configured to: In the case where the target link recovery method is the second link recovery method, control the media access control layer component to enter the recovery state from the working state, and control the media access control layer component to generate a control instruction; The physical layer component is configured to obtain the control instruction sent by the media access control layer component through the interface component, and generate a target level signal according to the control instruction; The physical layer component is further configured to send the target level signal to the peer physical layer component of the peer device, so that the peer physical layer component obtains a recovery state control instruction based on the target level signal, and sends the recovery state control instruction to the peer media access control layer component through the peer interface component; the recovery state control instruction is used for the peer media access control layer component to enter the recovery state from the working state; The media access control layer component is further configured to, when the media access control layer component is in the recovery state, generate a plurality of target packets based on the packet number information, and send the plurality of target packets to the peer media access control layer component of the peer device through the interface component and the physical layer component; the target packets are used for the peer media access control layer component in the recovery state to perform link negotiation with the media access control layer component in the recovery state; wherein, the packet number information includes an initial packet number and a packet number increase method.

7. The electronic device according to claim 1, wherein When the controller obtains the stability state of the phase-locked loop component, it is specifically configured to: Obtain the clock signal frequency of the phase-locked loop component; Determine the stability state of the phase-locked loop component according to the clock signal frequency.

8. A link recovery method, characterized in that, Including: Obtain the stability state of the phase-locked loop component through the controller; Determine the target link recovery method from the first link recovery method and the second link recovery method according to the stability state through the controller; the first link recovery method is to adjust the queue depth of the buffer in the interface component through the media access control layer component; the second link recovery method is to control the media access control layer component to perform link negotiation with the peer device; Execute the target link recovery method through the controller to perform link recovery processing between the electronic device and the peer device.

9. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program, when executed by a processor, implements the steps of the link recovery method as claimed in claim 8.

10. A computer program product, comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the link recovery method as claimed in claim 8.

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