Novel read-interference-resistant flash memory data coding mode

Abstract

The invention discloses a novel read-interference-resistant flash memory data coding mode, which belongs to the technical field of flash memory data coding, and comprises an SSD (Solid State Disk) controller, a TLC (Thin Layer Check) word line, a flash memory controller, a flash memory block, flash memory particles and a second type of word lines influenced by read interference, therefore, the read interference resistance of the word lines is improved, the SSD controller can adopt a higher read frequency threshold value, the data write-back frequency generated by read interference is reduced, and the service life of the SSD controller is prolonged. According to the method, the anti-interference capability of the word line susceptible to read interference can be remarkably improved, so that an SSD controller can adopt a higher read frequency threshold value, data write-back operation caused by read interference is effectively reduced, the purpose of prolonging the service life of the SSD is achieved, the effective information bearing capacity of each page can be adjusted according to the interference degree, and the service life of the SSD is prolonged. And the purpose of balancing the anti-reading interference capability is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of flash memory data encoding, and specifically to a novel flash memory data encoding method for resisting read interference. Background Art

[0002] The read disturbance phenomenon refers to that as the number of read operations of a flash memory increases, the content of some memory cells in the same block will be changed. As a result, the number of error bits of some word lines increases, and in severe cases, uncorrectable errors (UECC) may occur. In existing SSD controllers, write-back processing is a commonly used method for dealing with read interference. During the operation of the SSD, the firmware will detect the number of read operations of the block where the currently read data is located. When the number of read operations of the block exceeds a pre-set read count threshold, data garbage collection will be performed on this block, then this block will be erased and released to the block recycle area for standby.

[0003] In flash memory cells, the word lines affected by read interference are of the following two types: The first type: near the word line being read; The second type: at certain specific positions, such as at the top of the block or in the middle of the block. Such word lines are more easily affected by the read disturbance phenomenon, and thus more likely to cause UECC errors. Among the pages of such word lines, the LSB page is the most easily affected and thus causes UECC errors. Compared with the first type of word lines affected by read interference, the second type of word lines is significantly affected more times. Therefore, when considering setting the read count threshold, it is often targeted at the second type of word lines because any read operation on this block will affect such word lines. While the first type of word lines will only be affected when the adjacent word lines are read. Suppose there are a total of w word lines in the block, and the reading of the word lines in this block is random and equally probable. If r read operations are performed on this block, the first type of word lines is affected r / w times, while the second type of word lines is affected r times. If the anti-interference ability of the second type of word lines against read interference is enhanced, the number of data garbage collection operations can be reduced, thereby reducing the number of erase and write operations of the flash memory and effectively increasing the usable life cycle of the flash memory. Summary of the Invention

[0004] The object of the present invention is to provide a novel flash memory data encoding method for resisting read interference, so as to solve the following two types of word lines affected by read interference in the flash memory cell as mentioned in the above background technology: The first type: near the word line to be read; The second type: at certain specific positions, such as at the top of the block or in the middle of the block. Such word lines are more susceptible to the read interference phenomenon, and thus more likely to cause UECC errors. Among the pages of such word lines, the LSB page is the most easily affected, thus causing UECC errors. Compared with the first type of word lines affected by read interference, the second type of word lines is significantly affected more times.

[0005] To achieve the above object, the present invention provides the following technical solutions: an SSD controller, TLC word lines, a flash memory controller, flash memory blocks, flash memory chips, and the second type of word lines affected by read interference;

[0006] Among them, for the second type of word lines affected by read interference, a special page data encoding method is adopted, so as to improve the read interference resistance ability of such word lines, so that the SSD controller can adopt a higher read count threshold, reduce the number of data rewrites caused by read interference, and thus improve the service life of the SSD;

[0007] Among them, by adopting a special page data encoding method, the read interference resistance ability of such word lines is improved, so that the SSD controller can adopt a higher read count threshold, reduce the number of data rewrites caused by read interference, and thus improve the service life of the SSD;

[0008] As a further preference of this technical solution: The TLC word line contains three pages, namely the LSB page, the CSB page, and the MSB page. The current common practice is that after 4KB of user data is added with parity data by an error correction code (ECC) encoder to construct a codeword, a page usually contains four codewords, and three pages will be programmed and written into one word line, as Figure 3 shown;

[0009] As a further preference of this technical solution: Through the read interference analysis items of flash memory characteristics analysis, the position information and page information of the second type of word lines in the flash memory chip (such as Figure 2 the word lines located in layer0, layer1, layer70, and layer71) can be obtained, and these information are programmed and written into the firmware of the flash memory controller to control the encoding method of page data;

[0010] Among them, the following encoding method can be adopted for the second type of word lines to enhance the read interference resistance ability:

[0011] 1) Write randomly generated data to the LSB page vulnerable to read interference, without writing any valid user data;

[0012] 2) Write the error correction code words generated according to user data to other pages not vulnerable to interference;

[0013] 3) Write the random data of the LSB and the code words of other pages into the corresponding word lines simultaneously;

[0014] Among them, for example, for the word lines in layer0 shown in Figure 2 adopt the data encoding method shown in Figure 4 This method avoids writing valid user data into the page vulnerable to read operation interference, so that a larger read count threshold can be used, reducing the number of data recovery times caused by read interference, and then improving the available life cycle of the flash memory. In the Figure 4 TLC example, if each block has 4 second-class word lines, to implement this method, the additional overhead is 4 / (140*3) = 0.9%, if it is QLC, the additional overhead of this method can be reduced to 4 / (140*4) = 0.7%;

[0015] As a further preference of this technical solution: there is no valid data in the LSB page vulnerable to read interference. This method has the strongest anti-read interference ability. To reduce the additional overhead, valid data can still be written into the LSB page, but the number of valid data is reduced and the number of error correction code check bits is increased, so as to enhance the anti-interference ability of the LSB page;

[0016] Here, TLC is still used as an example:

[0017] SI: A 16KB + 2KB flash memory page can write 4 4KB valid data, each 4KB has 512B of error correction code check bits, and the code rate of the corresponding error correction code (ldpc or BCH or others) is 0.88, as shown in Figure 3 ;

[0018] S2: If only 3 4KB of valid data are written, each 4KB can have 2048 error correction code check bits, and the code rate of the corresponding error correction code is reduced to 0.67, thus greatly enhancing the anti-interference ability of the LSB to read interference. For the TLC example in Figure 3 , the additional overhead is: 4 / (140*3*4) = 0.24%, as shown in Figure 5 ;

[0019] S3: If only 2 4KB of data are written, each 4KB can have 5120B of error correction code check bits, and the code rate of the corresponding error correction code is further reduced to 0.44, and the anti-interference ability can be further improved. For the Figure 3In the TLC example, the overhead is: 4 * 2 / (140 * 3 * 4) = 0.47%, as Figure 6 shown;

[0020] S4: If only 1 4KB data is written, each 4KB can have 14336B of error correction code check bits, and the corresponding error correction code rate is further reduced to 0.22. For the Figure 3 TLC example in, the overhead is: 4 * 3 / (140 * 3 * 4) = 0.71%, as Figure 7 shown;

[0021] As a further preference of this technical solution: The carrying capacity of the valid data of the LSB page provides a trade - off between overhead and read interference resistance;

[0022] As a further preference of this technical solution: By adjusting the carrying capacity of the valid data of the LSB page, the second - type word line and the first - type word line can tolerate a similar degree of read interference, so as to achieve the optimal balance between overhead and system performance. After adjusting the carrying capacity of the valid data of the LSB page, it is written into the current word line together with other pages of the current word line;

[0023] As a further preference of this technical solution: Adopting the anti - read - interference coding scheme proposed in this article, the second - type interfered word lines in the flash memory block need to be identified in advance, which can be completed through the read interference sharing item of flash memory characteristic analysis. After obtaining relevant information (such as word line number, the layer where the word line is located), this information will be written into the firmware or hardware memory in the flash memory controller. During the process of programming and writing information to a certain word line, the current word line is compared with the recorded word line information. If the current word line belongs to the second - type interfered word line, the anti - read - interference coding scheme proposed in this article is adopted, otherwise the traditional coding scheme (such as Figure 3 shown) The entire workflow is as Figure 1 shown.

[0024] Compared with the prior art, the beneficial effects of the present invention are:

[0025] 1. In the present invention, the anti - interference ability of the word lines vulnerable to read interference can be significantly improved, so that the SSD controller can adopt a higher read count threshold, thereby effectively reducing the data rewrite operation caused by read interference and achieving the purpose of extending the service life of the SSD;

[0026] 2. In the examples used in the present invention, it is assumed that the LSB is the page in the word line that is easily interfered with. If it is found through flash memory characteristic analysis that other pages, such as the CSB or MSB, are the pages that are easily interfered with, the same method of reducing the effective information carrying capacity can be adopted for the CSB or MSB to enhance the anti-read interference ability of such pages. If there are multiple pages in the same second type of word line that are all easily read-interfered pages, the information carrying capacities of the easily read-interfered pages can be the same or different. Therefore, the effective information carrying capacity of each page can be adjusted according to the degree of interference to achieve the purpose of balancing the anti-read interference ability. The effective user data and its corresponding error correction code check data do not have to completely fill the entire page. For the part of a page that is not filled with the effective data and its corresponding error correction code check bit data, randomly generated data or pre-prepared data can be filled in. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is the word line programming process of a new flash memory data encoding method for anti-read interference according to the present invention;

[0028] Figure 2 is an example of an interfered word line of a new flash memory data encoding method for anti-read interference according to the present invention;

[0029] Figure 3 is the word line programming write of a new flash memory data encoding method for anti-read interference according to the present invention;

[0030] Figure 4 is Example 1 of the word line encoding method for enhancing the anti-read interference ability of a new flash memory data encoding method for anti-read interference according to the present invention;

[0031] Figure 5 is Example 2 of the word line encoding method for enhancing the anti-read interference ability of a new flash memory data encoding method for anti-read interference according to the present invention;

[0032] Figure 6 is Example 3 of the word line encoding method for enhancing the anti-read interference ability of a new flash memory data encoding method for anti-read interference according to the present invention;

[0033] Figure 7 is Example 4 of the word line encoding method for enhancing the anti-read interference ability of a new flash memory data encoding method for anti-read interference according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0034] Next, in combination with the accompanying drawings in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0035] Embodiment

[0036] Please refer to Figures 1-7 As shown, the present invention provides a technical solution: a new flash memory data encoding method for resisting read interference, which is characterized in that it includes an SSD controller, a TLC word line, a flash memory controller, a flash memory block, a flash memory chip, and a second type of word line affected by read interference;

[0037] Among them, for the second type of word line affected by read interference, a special page data encoding method is adopted to improve the read interference resistance of this type of word line, so that the SSD controller can adopt a higher read count threshold, reduce the number of data rewrites caused by read interference, and thus improve the service life of the SSD;

[0038] Among them, by adopting a special page data encoding method, the read interference resistance of this type of word line is improved, so that the SSD controller can adopt a higher read count threshold, reduce the number of data rewrites caused by read interference, and thus improve the service life of the SSD.

[0039] In this embodiment, specifically: the TLC word line includes three pages: namely the LSB page, the CSB page, and the MSB page. The current common practice is that after 4KB of user data passes through an error correction code (ECC) encoder and adds parity data, a codeword is constructed. A page usually contains four codewords, and three pages will be programmed and written into a word line, as Figure 3 shown.

[0040] In this embodiment, specifically: through the read interference analysis items of flash memory characteristics analysis, the position information and page information of the second type of word line in the flash memory chip (for example Figure 2 the word lines located in layer0, layer1, layer70, and layer71) can be obtained, and this information is programmed and written into the firmware of the flash memory controller to control the encoding method of page data;

[0041] Among them, the following encoding method can be adopted for the second type of word line to enhance the read interference resistance:

[0042] 1) Write randomly generated data to the LSB pages vulnerable to read interference, without writing any valid user data;

[0043] 2) Write the error correction code words generated according to user data to other pages not vulnerable to interference;

[0044] 3) Write the random data of the LSB and the code words of other pages into the corresponding word lines simultaneously;

[0045] Among them, for example, for the word lines in layer0 shown in Figure 2 adopt the data encoding method shown in Figure 4 This method avoids writing valid user data into the pages vulnerable to read operation interference, so that a larger read count threshold can be used, reducing the number of data recoveries due to read interference, and thus improving the usable life cycle of the flash memory. In Figure 4 the TLC example, if each block has 140 layers and there are 4 second-type word lines among them, in order to implement this method, the additional overhead is 4 / (140*3)=0.9%, and if it is QLC, the additional overhead of this method can be reduced to 4 / (140*4)=0.7%.

[0046] In this embodiment, specifically: there is no valid data in the LSB pages vulnerable to read interference. This method has the strongest anti-read interference ability. In order to reduce the additional overhead, valid data can still be written into the LSB pages, but the amount of valid data is reduced and the number of error correction code check bits is increased, thereby enhancing the anti-interference ability of the LSB pages;

[0047] Here, TLC is still used as an example:

[0048] SI: A 16KB + 2KB flash memory page can write 4 pieces of 4KB valid data, and each 4KB has 512B of error correction code check bits. The code rate of the corresponding error correction code (ldpc or BCH or others) is 0.88, as Figure 3 shown;

[0049] S2: If only 3 pieces of 4KB valid data are written, each 4KB can have 2048 error correction code check bits, and the code rate of the corresponding error correction code is reduced to 0.67, thereby greatly enhancing the anti-interference ability of the LSB to read interference phenomena. For the TLC example in Figure 3 , the additional overhead is: 4 / (140*3*4)=0.24%, as Figure 5 shown;

[0050] S3: If only 2 pieces of 4KB data are written, each 4KB can have 5120B of error correction code check bits, and the code rate of the corresponding error correction code is further reduced to 0.44, and the anti-interference ability can be further improved. ForFigure 3 For the TLC example in Figure 6 , the overhead is 4 * 2 / (140 * 3 * 4) = 0.47%, as

[0051] shown. Figure 3 S4: If only 1 4KB data is written, each 4KB can have 14336B of error correction code check bits, and the corresponding error correction code rate is further reduced to 0.22. For the TLC example in Figure 7 , the overhead is 4 * 3 / (140 * 3 * 4) = 0.71%, as

[0052] shown.

[0053] In this embodiment, specifically: the carrying capacity of the valid data in the LSB page provides a trade - off between overhead and read interference resistance.

[0054] In this embodiment, specifically: by adjusting the carrying capacity of the valid data in the LSB page, the second - type word line and the first - type word line can tolerate a similar degree of read interference, so as to achieve the optimal balance between overhead and system performance. After adjusting the carrying capacity of the valid data in the LSB page, it is written into the current word line together with other pages of the current word line. Figure 3 In this embodiment, specifically: adopting the anti - read - interference coding scheme proposed in this article, the second - type interfered word lines in the flash memory block need to be identified in advance, which can be completed through the read interference sharing item of flash memory characteristic analysis. After obtaining relevant information (such as word line number, the layer where the word line is located), this information will be written into the firmware or hardware memory in the flash memory controller. During the process of programming and writing information to a certain word line, the current word line is compared with the recorded word line information. If the current word line belongs to the second - type interfered word line, the anti - read - interference coding scheme proposed in this article is adopted, otherwise the traditional coding scheme (such as Figure 1 shown) is adopted. The entire workflow is as

[0055] Working principle or structural principle: First, through the analysis of flash memory characteristics, the second type of word lines that are easily affected by read interference and their page information that is easily affected by read interference are obtained. Then, it is determined whether the current programming word line is the second type of word line. Next, for the pages of the second type of word lines that are easily affected by read interference, the method of reducing the effective data carrying capacity proposed in this paper is adopted, and all the page data of the second type of word lines are merged and programmed into the current word line, thereby significantly improving the anti-interference ability of the word lines vulnerable to read interference, enabling the SSD controller to adopt a higher read count threshold, effectively reducing the data rewrite operation caused by read interference, and achieving the purpose of extending the service life of the SSD. Finally, the LSB is the page in the word line vulnerable to interference. If it is found through the analysis of flash memory characteristics that other pages such as CSB or MSB are pages vulnerable to interference, the same method of reducing the effective information carrying capacity can be adopted for CSB or MSB to enhance the anti-read interference ability of such pages.

[0056] Although the embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A novel flash memory data encoding method for anti-reading interference, characterized in that: Including an SSD controller, TLC word lines, a flash memory controller, flash memory blocks, flash memory chips, and a second type of word lines affected by read interference; Among them, when the second type of word lines affected by read interference adopt a dedicated page data encoding method, thereby improving the read interference resistance of this type of word lines, so that the SSD controller can adopt a higher read count threshold, reduce the number of data rewrites caused by read interference, and thus improve the service life of the SSD controller; Among them, the dedicated page data encoding method is used to improve the read interference resistance of this type of word lines, so that the SSD controller can adopt a higher read count threshold, reduce the number of data rewrites caused by read interference, and thus improve the service life of the SSD.

2. A novel flash memory data encoding method for anti-reading interference as claimed in claim 1, characterized in that: The TLC word line contains three pages: namely, the LSB page, the CSB page, and the MSB page. The current common practice is that after 4KB of user data passes through an error correction code (ECC) encoder and parity data is added, a codeword is constructed. A page usually contains four codewords, and three pages are programmed and written into a word line, as shown in Figure 3.

3. A novel flash memory data encoding method for anti-reading interference according to claim 1, characterized in that: Through the read interference analysis items of flash memory characteristics analysis, the position information and page information of the second type of word lines in the flash memory chip can be obtained (such as the word lines located in layer0, layer1, layer70, and layer71 in Figure 2), and this information is programmed and written into the firmware of the flash memory controller to control the encoding method of page data; Among them, the following encoding method can be adopted for the second type of word lines to enhance the read interference resistance: 1) Write randomly generated data to the LSB page vulnerable to read interference, without writing any valid user data; 2) Write the error correction codeword generated according to the user data to other pages not vulnerable to interference; 3) Write the random data of the LSB and the codewords of other pages into the corresponding word lines at the same time; Among them, for example, the word line located in layer0 shown in Figure 2 adopts the data encoding method shown in Figure 4. This method avoids writing valid user data into the page vulnerable to read operations, so that a larger read count threshold can be used, reduces the number of data recoveries caused by read interference, and thus improves the available life cycle of the flash memory. In the TLC example in Figure 4, if each block has 4 second type of word lines, to implement this method, the additional overhead is 4 / (140*3)=0.9%, and if it is QLC, the additional overhead of this method can be reduced to 4 / (140*4)=0.7%.

4. A novel flash memory data encoding method for anti-reading interference according to claim 1, characterized in that: There is no valid data in the LSB page vulnerable to read interference. This method has the strongest read interference resistance. To reduce the additional overhead, valid data can still be written into the LSB page, but the amount of valid data is reduced and the number of error correction code parity bits is increased to enhance the anti-interference ability of the LSB page; Here, TLC is still used as an example: SI: A 16KB + 2KB flash page can write 4 pieces of 4KB valid data. Each 4KB has 512B of error correction code check bits. The code rate of the corresponding error correction code (ldpc or BCH or others) is 0.88, as shown in Figure 3; S2: If only 3 pieces of 4KB valid data are written, each 4KB can have 2048 error correction code check bits, and the code rate of the corresponding error correction code is reduced to 0.67, thus greatly enhancing the anti-interference ability of the LSB to read interference. For the TLC example in Figure 3, the additional overhead is: 4 / (140 * 3 * 4) = 0.24%, as shown in Figure 5; S3: If only 2 pieces of 4KB data are written, each 4KB can have 5120B of error correction code check bits, and the code rate of the corresponding error correction code is further reduced to 0.44, and the anti-interference ability can be further improved. For the TLC example in Figure 3, the additional overhead is: 4 * 2 / (140 * 3 * 4) = 0.47%, as shown in Figure 6; S4: If only 1 piece of 4KB data is written, each 4KB can have 14336B of error correction code check bits, and the code rate of the corresponding error correction code is further reduced to 0.

22. For the TLC example in Figure 3, the additional overhead is: 4 * 3 / (140 * 3 * 4) = 0.71%, as shown in Figure 1.

5. A novel flash memory data encoding method for anti-reading interference according to claim 4, characterized in that, The carrying capacity of the valid data of the LSB page provides a trade-off between additional overhead and anti-read interference ability.

6. A novel flash memory data encoding method for anti-reading interference according to claim 1, characterized in that: By adjusting the carrying capacity of the valid data of the LSB page, the second type of word line and the first type of word line can tolerate a similar degree of read interference, so as to achieve the optimal balance between additional overhead and system performance. After adjusting the carrying capacity of the valid data of the LSB page, it is written into the current word line together with other pages of the current word line.

7. A novel flash memory data encoding method for anti-reading interference according to claim 1, characterized in that: Adopting the anti-read interference coding scheme proposed in this article, the second type of interfered word lines in the flash memory block need to be identified in advance, which can be completed through the read interference sharing item of flash memory characteristic analysis. After obtaining relevant information (such as word line number, layer where the word line is located), this information will be written into the firmware or hardware memory in the flash memory controller. During the process of programming and writing information to a certain word line, the current word line is compared with the recorded word line information. If the current word line belongs to the second type of interfered word lines, the anti-read interference coding scheme proposed in this article is adopted, otherwise the traditional coding scheme is adopted (as shown in Figure 3). The entire workflow is shown in Figure 1.

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