Test board supporting multiple external interfaces and optical module test method

Abstract

The invention relates to the technical field of embedding, and provides a test board supporting multiple external interfaces and an optical module test method. The test board comprises an ARM main control chip and an FPGA control chip. The ARM main control chip and the FPGA control chip are connected through an internal communication bus; iP cores of various communication interfaces are realized in the FPGA control chip in advance, and a plurality of pins are arranged; the ARM main control chip is used for receiving an interface configuration file from an upper computer and writing a corresponding communication identifier into each preset register address of the FPGA control chip according to the interface configuration file; and when the FPGA control chip reads that the first communication identifier is stored in the first preset register address, the IP core of the first communication interface is connected with the first pin, so that the first pin is set as the first communication interface. According to the test board, the pins can be configured to support optical modules with different communication interfaces, so that the test board has multiple purposes, namely, one test board can meet the test requirements of the optical modules with multiple communication interfaces.

Description

Technical Field

[0001] The present invention relates to the field of embedded technology, and particularly to a test board supporting multiple external interfaces and an optical module test method. Background Art

[0002] In an embedded system, various test boards are often used to produce, test, and verify the functions of optical devices, optical modules, and optical components. Due to the large number of customer types and product categories, there are also a large number of test board types required to support test execution. Common communication interface types include, for example:

[0003] If the optical module is an Inter Integrated Circuit (I2C) interface, the test board needs to support the I2C interface or an I2C-to-serial port conversion; if the optical module is a serial port, the test board needs to support the serial port; if the optical module is an SPI interface, the test board needs to support the Serial Peripheral Interface (SPI); if the optical module is a Management Data Input / Output (MDIO) interface, the test board needs to support the MDIO interface; if the optical module is an Ethernet network interface, the test board needs to support the Ethernet port. Secondly, there are also many differences in IO ports, and the IO port requirements of different products are also different, resulting in differences in the design of the test board and many types emerging.

[0004] For optical devices, optical modules, or optical components, during the sample stage, due to the small quantity, the demand for production and testing is not very urgent. However, when these products reach the mass production stage, especially when the demand for optical modules is very large, if factors such as a large number of product types and customer types (each customer has its own customized requirements) are added, it will pose a very big problem in test board management and high requirements for the test board. Because if the test board design is unreasonable, it will lead to production capacity bottlenecks, or if the test verification is not comprehensive, it will result in the outflow of faults, and the impact and losses will be magnified exponentially. At this time, it will pose great challenges to the efficiency, performance, automation of production testing, and test board firmware management.

[0005] The traditional test board design idea is to design a test board for each customer's product. The advantage of this solution is simplicity in solving specific individual problems, but the disadvantages are also very obvious. That is, as the number of customers and products increases over time, the number of test boards also increases, resulting in the same management cost for test board management as for products. If the test board management is not good, various production capacity bottlenecks and test verification quality problems will occur.

[0006] In view of this, overcoming the defects existing in the prior art is an urgent problem to be solved in the technical field of the present invention. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a test board supporting multiple external interfaces to solve the problem that it is difficult for a test board in the prior art to meet the optical module tests of multiple communication interfaces.

[0008] The present invention adopts the following technical solutions:

[0009] In a first aspect, the present invention provides a test board supporting multiple external interfaces, including an ARM main control chip and an FPGA control chip;

[0010] The ARM main control chip and the FPGA control chip are connected through a communication bus;

[0011] IP cores of multiple communication interfaces are pre-implemented in the FPGA control chip, and multiple pins are provided;

[0012] The ARM main control chip is used to receive an interface configuration file from a host computer, and write corresponding communication identifiers to respective preset register addresses of the FPGA control chip according to the interface configuration file;

[0013] When the FPGA control chip reads that a first communication identifier is stored in a first preset register address, it connects the IP core of the first communication interface to the first pin to set the first pin as the first communication interface, so as to realize the configurable communication interface of the pin and be able to connect and test optical modules of different communication interfaces; wherein, each configurable pin corresponds to a preset register address, and the first pin corresponds to the first preset register address.

[0014] Preferably, two pins are used to implement the I2C communication interface, specifically including:

[0015] When the FPGA reads that I2C communication identifiers are stored in both the first preset register address and the second preset register address, it connects the clock line of the I2C core to the first pin and connects the data line of the I2C core to the second pin; wherein, the I2C core is the IP core of the I2C communication interface.

[0016] Preferably, two pins are used to implement the UART communication interface, specifically including:

[0017] When the FPGA reads that UART communication identifiers are stored in both the first preset register address and the second preset register address, it connects the sending end of the UART core to the first pin and connects the receiving end of the UART core to the second pin; wherein, the UART core is the IP core of the UART communication interface.

[0018] Preferably, four pins are used to implement the SPI communication interface, specifically including:

[0019] When the FPGA reads that the SPI communication identifiers are stored in the first preset register address, the second preset register address, the third preset register address, and the fourth preset register address, connect the SCK signal line of the SPI core to the first pin, connect the MOSI signal line of the SPI core to the second pin, connect the MISO signal line of the SPI core to the third pin, and connect the CS signal line of the SPI core to the fourth pin; wherein, the SPI core is the IP core of the SPI communication interface.

[0020] Preferably, two pins are used to implement the GPIO communication interface, specifically including:

[0021] When the FPGA reads that the GPIO communication identifiers are stored in the first preset register address and the second preset register address, connect the general input terminal of the GPIO core to the first pin, and connect the general output terminal of the I2C core to the second pin; wherein, the GPIO core is the IP core of the GPIO communication interface.

[0022] Preferably, 16 configurable pins are set, and the preset register addresses corresponding to the 16 configurable pins are 0x100 to 0x10f respectively.

[0023] Preferably, the communication identifier is represented as a 3-bit bit code. Among them, the GPIO communication identifier includes a GPIO input communication identifier and a GPIO output communication identifier, and the SPI communication identifier includes an SPI_STD communication identifier and an SPI_CUSTOMIZE communication identifier;

[0024] The GPIO input communication identifier is 0b000, the GPIO output communication identifier is 0b001, the UART communication identifier is 0b010, the I2C communication identifier is 0b011, the SPI_STD communication identifier is 0b100, and the SPI_CUSTOMIZE communication identifier is 0b101; where SPI_STD represents the standard SPI 4-wire timing protocol, and SPI_CUSTOMIZE is a customized SPI timing protocol. The customized SPI timing protocol includes MISO signal, CS signal, MOSI signal, SCK signal, communication completion done signal, and busy signal representing communication in progress.

[0025] In a second aspect, the present invention provides an optical module testing method, which uses the test board with multiple external interfaces described in the first aspect to test multiple optical modules. When multiple optical modules all match the I2C communication interface, the method includes:

[0026] Configure multiple pairs of pins of the test board as I2C communication interfaces;

[0027] According to the slave addresses of the optical modules, divide each optical module so that the optical modules with the same slave address are divided into different first sets;

[0028] Connect the optical modules belonging to one first set to the same I2C communication interface of the test board, and connect the optical modules belonging to different first sets to different I2C communication interfaces.

[0029] Preferably, the step of dividing each optical module according to the slave address of the optical module specifically includes:

[0030] Cluster each optical module to divide the optical modules with the same slave address into the same second set;

[0031] Establish N third sets, and sequentially allocate each optical module in the second set to the corresponding third set in the order of the number of elements contained from more to less, and use each third set after the allocation as the first set; wherein, preferentially allocate the optical module to the third set with the least number of elements, and multiple optical modules in one second set are allocated to different third sets; N is the number of elements in the second set with the most elements.

[0032] Preferably, when multiple optical modules respectively match different communication interfaces, the method further includes:

[0033] Configure the corresponding pins of the test board according to the communication interface requirements of the optical modules, and connect the optical modules to the corresponding communication interfaces to test multiple optical modules.

[0034] In a third aspect, the present invention further provides an optical module testing device for implementing the optical module testing method described in the second aspect. The device includes:

[0035] At least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the processor to execute the optical module testing method described in the first aspect.

[0036] In a fourth aspect, the present invention further provides a non-volatile computer storage medium, and the computer storage medium stores computer-executable instructions, and the computer-executable instructions are executed by one or more processors to complete the method described in the second aspect.

[0037] In a fifth aspect, a chip is provided, including: a processor and an interface, for calling and running a computer program stored in a memory from the memory and executing the method as described in the second aspect.

[0038] In a sixth aspect, there is provided a computer program product comprising instructions which, when run on a computer or a processor, cause the computer or the processor to execute the method according to the second aspect.

[0039] In the present invention, IP cores of multiple communication interfaces are provided, and according to the pin configuration requirements, the IP cores of the corresponding communication interfaces are connected to the corresponding pins, so as to realize the configurability of the pins, support optical modules of different communication interfaces, and thus achieve multi-purpose use of one board, that is, a test board can meet the test requirements of optical modules of multiple communication interfaces. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings according to these drawings without creative efforts.

[0041] Figure 1 is a schematic structural diagram of a test board supporting multiple external interfaces provided by an embodiment of the present invention;

[0042] Figure 2 is a schematic structural diagram of a test board supporting multiple external interfaces provided by an embodiment of the present invention;

[0043] Figure 3 is a schematic structural diagram of a test board supporting multiple external interfaces provided by an embodiment of the present invention;

[0044] Figure 4 is a schematic diagram of port configuration of a test board supporting multiple external interfaces provided by an embodiment of the present invention;

[0045] Figure 5 is a schematic flowchart of a method for testing an optical module provided by an embodiment of the present invention;

[0046] Figure 6 is a schematic diagram of the connection between a test board supporting multiple external interfaces and an optical module provided by an embodiment of the present invention;

[0047] Figure 7 is a schematic flowchart of a method for testing an optical module provided by an embodiment of the present invention;

[0048] Figure 8 is a schematic structural diagram of a test board supporting multiple external interfaces provided by an embodiment of the present invention;

[0049] Figure 9 is a schematic diagram of the connection between a test board supporting multiple external interfaces and an optical module provided by an embodiment of the present invention;

[0050] Figure 10 It is a schematic diagram of port configuration of a test board supporting multiple external interfaces provided by an embodiment of the present invention;

[0051] Figure 11 It is a schematic diagram of the architecture of an optical module test device provided by an embodiment of the present invention. Specific embodiments

[0052] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0053] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples", etc., are intended to indicate that specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily directed to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any suitable manner, that is, although they may be carried in the above-mentioned embodiments or examples due to reasons such as the order of appearance and position, etc., but it is not limited that they can be carried by one embodiment or example in a combined manner.

[0054] In the description of the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality" is two or more. In addition, for example, in the description, for the same type of nouns, the method of adding "A" and "B" at the end is used to describe them as two independent individuals. In this case, the features defined with "A" and "B" are only used for the purpose of distinguishing similar individuals and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0055] In the description of some embodiments, the expressions such as "coupled", "coupling" and "connected" and their derivatives may be used. For example, in the description of some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact with each other. Another example is that in the description of some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical or electrical contact. However, the term "connected" or "coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other, such as "optical path coupling", "wireless connection", etc. The embodiments disclosed herein are not necessarily limited to the content of the present invention.

[0056] In the description of the present invention, the expression "A and / or B" (where A and B are used to formally represent specific feature contents) is involved, and the corresponding expression includes the following three combinations: only A, only B, and the combination of A and B.

[0057] As used in the present invention, "about", "substantially" or "approximately" includes the stated value and the average value within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurement being discussed and the error associated with the measurement of the specific quantity (i.e., the limitations of the measurement system).

[0058] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0059] Embodiment 1:

[0060] Embodiment 1 of the present invention provides a test board supporting multiple external interfaces, as Figure 1 shown, including an ARM main control chip and a Field-Programmable Gate Array (FPGA) board; the ARM main control chip and the FPGA control chip are connected through a communication bus; in the FPGA control chip, intellectual property (IP) cores of multiple communication interfaces are pre-implemented, and a plurality of pins are provided; as Figure 1As shown, the multiple communication interfaces include one or more of a General-purpose input / output (GPIO) communication interface, an I2C communication interface, a Universal Asynchronous Receiver / Transmitter (UART) communication interface, and an SPI communication interface. It is also referred to as one or more of a UARTx communication interface, an I2Cx communication interface, an SPIx communication interface, and a GPIO communication interface. Among them, I2Cx, UARTx, SPIx, etc. indicate that multiple groups of interfaces can be supported, such as I2C0, I2C1, ……, I2CN, and the same applies to UARTx and SPIx, which provides an additional layer of flexibility for interface design.

[0061] The ARM main control chip is used to receive an interface configuration file from the host computer. According to the interface configuration file, corresponding communication identifiers are written into the preset register addresses of the FPGA control chip. The interface configuration file can be understood as a file storing information on which port is configured as which type of communication interface, and this file supports user modification, thereby realizing the configurability of the communication interfaces of the test board. Each communication identifier can be a specific value. In actual use, a communication interface may also have multiple different types of ports. One communication identifier can be used to represent all types of ports of a communication interface, or different communication identifiers can be used to represent different types of ports of a communication interface. For example, 0 is used to represent the general input terminal of the GPIO communication interface, 1 is used to represent the general output terminal of the GPIO communication interface, 2 is used to represent all ports of the UART communication interface, 3 is used to represent all ports of the I2C communication interface, 4 is used to represent the CS signal line of the SPI communication interface, and 5 is used to represent the SCK signal line, MOSI signal line, and MISO signal line of the SPI communication interface.

[0062] When the FPGA control chip reads that the first communication identifier is stored in the first preset register address, it connects the IP core of the first communication interface to the first pin, so as to set the first pin as the first communication interface, thereby realizing the configurability of the communication interface of the pin and enabling connection testing with optical modules of different communication interfaces. Among them, each configurable pin corresponds to a preset register address, and the first pin corresponds to the first preset register address. The preset register addresses corresponding to each pin are obtained by those skilled in the art through empirical analysis.

[0063] It should be noted here that the connection between the IP core of the first communication interface and the first pin can be understood as a connection in the software sense, that is, opening the data transmission channel between the two. In actual use, the IP core of each communication interface and each pin are pre-connected through a logic multi-throw switch. When it is necessary to configure the first pin as the first communication interface, the logic multi-throw switch is switched to communicate with the first pin.

[0064] In this embodiment, by setting the IP cores of multiple communication interfaces and connecting the IP cores of the corresponding communication interfaces to the corresponding pins according to the pin configuration requirements, the configurability of the pins is realized to support optical modules with different communication interfaces. For the outside, it can be understood as Figure 2 shown in the figure, that is, a test board is compatible with multiple communication interfaces. Thus, one board can be used for multiple purposes, that is, a test board can meet the test requirements of optical modules with multiple communication interfaces, as Figure 3 shown in the figure, the test board can be connected and tested with the optical module through multiple communication interfaces.

[0065] In a specific implementation manner, a communication interface may also have multiple different types of ports. For example, the I2C communication interface includes a data line and a clock line. Therefore, two pins are required to implement the I2C communication interface, specifically including: when the FPGA reads that both the first preset register address and the second preset register address store the I2C communication identifier, connect the clock line of the I2C core to the first pin and connect the data line of the I2C core to the second pin; where the I2C core is the IP core of the I2C communication interface.

[0066] The UART communication interface includes a transmitter and a receiver. Two pins are required to implement the UART communication interface, specifically including: when the FPGA reads that both the first preset register address and the second preset register address store the UART communication identifier, connect the transmitter of the UART core to the first pin and connect the receiver of the UART core to the second pin; where the UART core is the IP core of the UART communication interface.

[0067] The SPI communication interface includes an SCK signal line, a MOSI signal line, a MISO signal line, and a CS signal line. Therefore, four pins are required to implement the SPI communication interface, specifically including: when the FPGA reads that the first preset register address, the second preset register address, the third preset register address, and the fourth preset register address all store the SPI communication identifier, connect the SCK signal line of the SPI core to the first pin, connect the MOSI signal line of the SPI core to the second pin, connect the MISO signal line of the SPI core to the third pin, and connect the CS signal line of the SPI core to the fourth pin; where the SPI core is the IP core of the SPI communication interface.

[0068] The GPIO communication interface includes a general input terminal and a general output terminal. Therefore, two pins are required to implement the GPIO communication interface, specifically including: when the FPGA reads that both the first preset register address and the second preset register address store the GPIO communication identifier, connect the general input terminal of the GPIO core to the first pin, and connect the general output terminal of the I2C core to the second pin; where the GPIO core is the IP core of the GPIO communication interface.

[0069] It should be noted here that the first preset register address is the preset register address corresponding to the first pin, the second preset register address is the preset register address corresponding to the second pin, the third preset register address is the preset register address corresponding to the third pin, and the fourth preset register address is the preset register address corresponding to the fourth pin.

[0070] The first pin, the second pin, the third pin, and the fourth pin in this embodiment do not have the meaning of a designated order. Instead, they are limitations added for the convenience of describing two or more different objects of the same type, and should not be interpreted as having a further limiting meaning.

[0071] In an alternative embodiment, as Figure 4 shown, 16 configurable pins are set, and the preset register addresses corresponding to the 16 configurable pins are 0x100 to 0x10f respectively. That is, the first pin corresponds to 0x100, the second pin corresponds to 0x101, and so on. In an alternative embodiment, as Figure 10 shown, the 16 configurable pins can be pins 2 to 6, pins 9 to 14, and pins 17 to 22, that is, the 16 configurable pins corresponding to GPIO_1 to GPIO_16. Figure 10 shows the communication interfaces that can be configured for each pin of a test board, Figure 10It includes 50 pins, among which 16 pins are configurable, namely the above-mentioned 16 configurable pins. The communication identifier is represented as a 3-bit binary code. Among them, the GPIO communication identifier includes the GPIO input communication identifier and the GPIO output communication identifier, and the SPI communication identifier includes the SPI_STD communication identifier and the SPI_CUSTOMIZE communication identifier; the GPIO input communication identifier is 0b000, the GPIO output communication identifier is 0b001, the UART communication identifier is 0b010, the I2C communication identifier is 0b011, the SPI_STD communication identifier is 0b100, and the SPI_CUSTOMIZE communication identifier is 0b101; where SPI_STD represents the standard SPI 4-wire timing protocol, and SPI_CUSTOMIZE is a customized SPI timing protocol. The customized SPI timing protocol includes the MISO signal, the CS signal, the MOSI signal, the SCK signal, the communication completion done signal (i.e., the done signal used to represent the communication completion) and the busy signal used to represent the ongoing communication. It should be noted here that both SPI_STD and SPI_CUSTOMIZE include the four signals under the standard SPI 4-wire timing protocol, namely the MISO signal, the CS signal, the MOSI signal and the SCK signal. On this basis, SPI_CUSTOMIZE also includes the above-mentioned done signal and busy signal. The values in the range of 0x100 to 0x10f represent the communication interfaces required to be configured for each pin, and thus the switching of the logic multi-throw multi-pole switch is performed accordingly.

[0072] In the prior art, usually a test board is designed for each type of optical module. In terms of hardware, a set of interfaces matching the corresponding optical module needs to be designed separately for each test board. And in terms of software, firmware also needs to be designed for it correspondingly. This leads to more and more difficult management of test boards as the types of optical modules increase. However, in this embodiment, the test board is implemented by using an ARM main control chip and an FPGA control chip, and its ports are configurable. Thus, it can be compatible with optical modules with multiple interfaces in terms of hardware. On the other hand, since the ARM main control chip has a network function, the test board can be remotely controlled through the network, which is convenient for writing scripts and commands, achieving the purpose of being compatible with multiple optical modules in terms of software. Finally, it is realized that only one test board can be used for testing all types of optical modules, thus greatly reducing the management difficulty and test cost.

[0073] Embodiment 2:

[0074] Based on Embodiment 1, this embodiment also provides an optical module testing method. The test board with multiple external interfaces described in Embodiment 1 is used to test multiple optical modules. When multiple optical modules all match the I2C communication interface, such asFigure 5 As shown, the method includes:

[0075] In step 201, configure multiple pairs of pins of the test board as I2C communication interfaces.

[0076] In step 202, divide each optical module according to the slave address of the optical module, so that the optical modules with the same slave address are divided into different first sets; the slave address is the address used by the optical module for I2C communication.

[0077] In step 203, connect the optical modules belonging to one first set to the same I2C communication interface of the test board, and connect the optical modules belonging to different first sets to different I2C communication interfaces.

[0078] As Figure 6 shown, assume that there are 4 optical modules supporting I2C communication interfaces, namely interface module 1, interface module 2, interface module 3, and interface module 4. Among them, the slave addresses of interface module 1 and interface module 2 are different, and the slave addresses of interface module 1, interface module 3, and interface module 4 are the same. Then, interface module 1 and interface module 2 can be connected to an I2C communication interface, as Figure 6 shown, both are connected to I2C1. Interface module 1, interface module 3, and interface module 4 need to be connected to different I2C communication interfaces. For example, interface module 3 is connected to I2C2, and interface module 4 is connected to I2C3.

[0079] Figure 6 This is only for schematic presentation. In actual use, for batch testing, the number of optical modules that need to be connected to a test board may be large, and it is impossible to directly determine which optical module is connected to which interface. To solve this problem, this embodiment provides a preferred implementation method, that is, divide each optical module according to the slave address of the optical module, as Figure 7 shown, specifically including:

[0080] In step 301, cluster each optical module to divide the optical modules with the same slave address into the same second set.

[0081] In step 302, establish N third sets, and sequentially allocate each optical module in the second set to the corresponding third set in the order of the number of elements contained from more to less, and use each third set after the allocation as the first set; among them, preferentially allocate the optical module to the third set with the least number of elements, and multiple optical modules in one second set are allocated to different third sets; N is the number of elements in the second set with the most elements.

[0082] The above steps 301 - 302 can be understood as follows: First, multiple optical modules with the same slave address are divided into a second set, and then the optical modules in a second set are divided into different first sets, so that each optical module in a first set has a different slave address. Moreover, by using the second set with the largest number of elements, the number of first sets is determined. At this time, the number of required ports is the least, which can meet the test requirements of as many optical modules as possible. And by preferentially allocating optical modules to the first set with the least number of elements, the number of elements in each first set can be relatively balanced after the allocation, that is, the number of optical modules finally connected to each port is generally the same, so as to ensure the consistency of the overall transmission speed of the test board. In actual use, the number of slaves that an I2C communication interface can support for communication is limited. For example, it can support up to 255 slave communications at most. In this actual application scenario, the method further includes: when the number of elements in all first sets reaches the preset number, a new first set is established, and then the optical modules are allocated until all optical modules are allocated.

[0083] In another alternative implementation, as Figure 8 and Figure 9 shown, when multiple optical modules respectively match different communication interfaces, the method further includes: configuring the corresponding pins of the test board according to the communication interface requirements of the optical modules, and connecting the optical modules to the corresponding communication interfaces to test multiple optical modules.

[0084] Embodiment 3:

[0085] Based on the method described in Embodiment 1, the present invention combines specific application scenarios and uses technical expressions in related scenarios to elaborate on the implementation process in the characteristic scenarios of the present invention.

[0086] First, this embodiment uses the following method for designing a programmable interface general test board to solve the problems of non-uniform design of the N test board in the prior art, resulting in repeated software and hardware development and test board software and hardware control. The specific steps are as follows:

[0087] Step 1: The main control chip of the test board selects a design scheme with an FPGA. For example, it can select ARM + FPGA, or Altea, Xilinx SOC scheme. The main focus is that ARM needs to support network ports and serial ports and support other interface extensions (I2C, SPI, usb, etc.). The FPGA supports programmability, the logic resources are greater than 30K, and the number of IO ports is greater than 100, which specifically depends on the specific application. In terms of design, if it is for future demand scalability, a high - configuration main control (high - performance ARM main control, multiple cores, large FPGA logic resources, and a large number of IO ports) can be considered. In this way, it can ensure that one version of the design supports the needs for many years in the future. AsFigure 2 As shown, it is the design block diagram of the ARM+FPGA discrete solution; Figure 3 It is the design block diagram of the SOC integration solution.

[0088] Among them, I2Cx, UARTx, SPIx, etc. indicate that multiple groups of interfaces can be supported, such as I2C0, I2C1..., etc. The same applies to UARTx and SPIx, which provides an additional layer of flexibility for interface design.

[0089] Step 2: Reserve sufficient GPIO interfaces (i.e., ports) on the test board hardware. Usually, taking 50 pins as an example, this can ensure the unity of the interface hardware design of the test board. These GPIOs implement the physical channels of the hardware communication interfaces. The pin definitions are as Figure 10 shown, and the specific meaning of GPIO is dynamically switched through the FPGA registers.

[0090] Step 3: The key for the test board to support dynamic changes in the test interface lies in the design of the FPGA. By designing the FPGA program to pre-support common test interfaces (I2C, UART, and SPI, etc.), and then the ARM issues configuration registers to the FPGA to enable the required interfaces to take effect, thus achieving dynamic changes in the interfaces.

[0091] Step 3.1: As Figure 10 shown, the hardware can support 2 groups of SPI (up to 4 groups can be supported), 6 groups of I2C, and 6 groups of UART, and the FPGA program can take effect dynamically according to the configuration. When designing the FPGA program, IP cores for 2 groups of SPI, 6 groups of I2C, and 6 groups of UART are pre-instantiated, and the communication interfaces that are consistent with the maximum hardware requirements are supported at the code function level.

[0092] Step 3.2: Inside the FPGA program, through program design, conditional judgment, or switch statements, the pre-implemented communication interfaces are connected to the hardware GPIO through switches. That is, the 2 groups of SPI, 6 groups of I2C, and 6 groups of UART communication interfaces in the program are connected to the hardware GPIO ports through logical multi-throw switches.

[0093] Step 3.3: When different communication interface modules need to use the test board for testing, the ARM program will read the configuration file (obtain the module interface type), and then write to the FPGA registers to complete the switching of the multi-throw switch, thereby enabling the FPGA to dynamically support the module communication interface and support module testing.

[0094] The definitions of the register values of the FPGA are as follows:

[0095] 0: GPIO_I

[0096] 1: GPIO_O

[0097] 2: UART

[0098] 3: IIC

[0099] 4: SPI_STD

[0100] 5: SPI_CUSTOMIZE

[0101] The GPIO function configuration register can be configured according to Figure 4 , corresponding to the FPGA register table.

[0102] Step 3.4: For example, if the serial port module needs to be tested currently, and pins pin9 and pin10 of the 50Pin pins of the test board with the configuration shown in Figure 10 are used, then the configuration file (i.e., the interface configuration file) is 9:2, 10:2.

[0103] After the ARM reads the configuration, through the register definition, it knows that 2 represents the meaning of serial port communication.

[0104] The ARM then writes the register values of FPGA registers 108 and 109 as 2 according to Figure 4 the register definition.

[0105] At this time, when the FPGA judges that the values of registers 108 and 109 are 2, it will connect UART0 among the 6 groups of UARTs pre-implemented internally to pin9 and pin10, thus realizing the function of serial port 0.

[0106] Step 4: For the communication interface requirements of UART1, or UARTx, I2Cx, SPIx, etc., the specific implementation process is the same as above, except that the content written into the register is different, but the method is the same.

[0107] Based on the above method, this patent proposes a test board that supports multiple external interfaces. Through the programmable design idea, the test board is normalized in hardware design and software design, thus greatly simplifying the management complexity of the test board and improving the automation degree of testing, reducing the costs of human error and time consumption from the mechanism.

[0108] As Figure 8 shown, the general test board design is divided into two parts. One part is the test interface facing the host computer, including R & D self-verification test and production line sample production test. In this part, the test board can provide the most common and stable communication interfaces, such as serial ports and network ports. For small data volume command interaction and debugging interfaces, the serial port is selected; for large data transmission, test report export, log export, etc., it can be completed very quickly and conveniently through the network port, and its export format is in file format, which is very convenient for reading.

[0109] Another part is the interface facing the device to be tested. The test board can dynamically configure the communication interface according to the characteristics of the test device. If the module is for serial communication, the test board supports the serial port; if the module is for I2C communication, the test board supports the I2C interface, and so on. The greatest advantage here is that the test board can dynamically support different interfaces without modifying the hardware and upgrading the software. Only by loading the configuration file of the test board can the dynamic change of the interface be achieved.

[0110] Compared with the design of traditional test boards, the present invention has three obvious advantages. First, the hardware design of the test board can be normalized, without the need to constantly change the design according to the types of customers and modules, which simplifies the material management and reduces the workload of repeated hardware design. Second, the test board firmware can dynamically support different test interfaces, and the firmware of the test board is also normalized. Only by issuing different interface configurations can different interfaces be realized, reducing the workload of repeated firmware development. Third, when the hardware and software of the test board are unified, the requirements for the test process and test personnel will be lowered. Therefore, the design of the test tool and the upper computer will also be normalized, and the content that the test personnel need to learn and the test habits can be solidified, thus reducing the technical threshold of the entire test and improving the test efficiency. Since it supports the network port test interface, it provides great convenience for automation and remote testing, which is a function that traditional test boards have never achieved before.

[0111] Based on considering the defects of existing solutions, the present invention proposes a design method for a programmable interface general test board, which can effectively solve problems such as difficult management and low efficiency of existing test boards, improve the test and production efficiency, and enhance the test quality of products.

[0112] In actual use, for the interfaces of optical modules, this test board can test multiple optical modules at one time, and perform parallel testing to improve efficiency. On the test board, multiple optical modules are uniformly powered, and then multiple groups of communication interfaces are instantiated through the test board, and the number and types of communication ports can be dynamically adjusted.

[0113] For different packaged optical modules such as SFP / SFP+, QSFP28, and QSFP-DD, since their external interfaces are all I2C, the advantages of the test board are more prominent, and it can support the testing of this category of modules simultaneously.

[0114] The test board can instantiate one or more groups of I2C interfaces as well as GPIO such as reset and chip select. If the slave addresses of the optical modules are inconsistent, a group of I2C buses can be shared; if the slave addresses of the optical modules are the same, different I2C buses can be used. For example Figure 6As shown in the figure, when four optical modules need to be tested simultaneously, the test board can instantiate three or four I2C interfaces through configuration for testing the optical modules. When the slave addresses of optical module 1 and optical module 2 are different, the same group of I2C buses can be used for testing, while optical modules 3 and 4 use independent I2C buses for testing. For testing other numbers of optical modules, it can be analogized, and dynamic and flexible configuration can be performed to complete the testing.

[0115] When modules with different customer requirements need to be tested, such as serial port modules, SPI interface modules, I2C interface modules, etc., the general test board can also support parallel testing, as Figure 9 shown.

[0116] Embodiment 4:

[0117] As Figure 11 shown, it is a schematic structural diagram of the optical module testing device according to an embodiment of the present invention. The optical module testing device in this embodiment includes one or more processors 21 and a memory 22. Among them, Figure 11 one processor 21 is taken as an example.

[0118] The processor 21 and the memory 22 can be connected through a bus or other means. Figure 11 Taking the connection through a bus as an example.

[0119] The memory 22, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs and non-volatile computer-executable programs, such as the optical module testing method in Embodiment 1. The processor 21 executes the optical module testing method by running the non-volatile software programs and instructions stored in the memory 22.

[0120] The memory 22 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 22 may optionally include a memory remotely set relative to the processor 21, and these remote memories can be connected to the processor 21 through a network. Examples of the above network include but are not limited to the Internet, enterprise intranet, local area network, mobile communication network, and their combinations.

[0121] The program instructions / modules are stored in the memory 22 and, when executed by the one or more processors 21, execute the optical module testing method in the above Embodiment 1.

[0122] The method executed by the device in this embodiment can be understood as first dividing the optical modules, and then writing the corresponding interface configuration file to the test board. Among them, the optical module division result is displayed to the user so that the user can connect the optical modules to the corresponding ports of the test board according to the division result.

[0123] It should be noted that, regarding the information interaction, execution process, etc. among the modules and units in the above-mentioned device and system, since they are based on the same concept as the method embodiment of the present invention, for specific content, reference can be made to the description in the method embodiment of the present invention, and details will not be elaborated here.

[0124] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the embodiments can be completed by instructing relevant hardware through a program, and this program can be stored in a computer-readable storage medium. The storage medium can include: read-only memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disc, etc.

[0125] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A test board supporting multiple external interfaces, characterized in that, It includes an ARM main control chip and an FPGA control chip; The ARM main control chip and the FPGA control chip are connected through a communication bus; In the FPGA control chip, IP cores of multiple communication interfaces are pre-implemented and there are multiple pins; The ARM main control chip is used to receive an interface configuration file from a host computer, and according to the interface configuration file, write corresponding communication identifiers into each preset register address of the FPGA control chip; When the FPGA control chip reads that the first communication identifier is stored in the first preset register address, it connects the IP core of the first communication interface to the first pin, so as to set the first pin as the first communication interface, thereby realizing that the communication interface of the pin is configurable, so as to be able to connect and test optical modules with different communication interfaces; wherein, each configurable pin corresponds to a preset register address, and the first pin corresponds to the first preset register address.

2. The test board supporting multiple external interfaces according to claim 1, characterized in that, Using two pins to implement the I2C communication interface, specifically including: When the FPGA reads that the I2C communication identifiers are stored in both the first preset register address and the second preset register address, connect the clock line of the I2C core to the first pin and connect the data line of the I2C core to the second pin; wherein, the I2C core is the IP core of the I2C communication interface.

3. The test board supporting multiple external interfaces according to claim 1, characterized in that Using two pins to implement the UART communication interface, specifically including: When the FPGA reads that the UART communication identifiers are stored in both the first preset register address and the second preset register address, connect the sending end of the UART core to the first pin and connect the receiving end of the UART core to the second pin; wherein, the UART core is the IP core of the UART communication interface.

4. The test board supporting multiple external interfaces according to claim 1, characterized in that, Using four pins to implement the SPI communication interface, specifically including: When the FPGA reads that the SPI communication identifiers are stored in the first preset register address, the second preset register address, the third preset register address and the fourth preset register address, connect the SCK signal line of the SPI core to the first pin, connect the MOSI signal line of the SPI core to the second pin, connect the MISO signal line of the SPI core to the third pin, and connect the CS signal line of the SPI core to the fourth pin; wherein, the SPI core is the IP core of the SPI communication interface.

5. The test board supporting multiple external interfaces according to claim 1, characterized in that, Using two pins to implement the GPIO communication interface, specifically including: When the FPGA reads that the GPIO communication identifiers are stored in both the first preset register address and the second preset register address, connect the general input end of the GPIO core to the first pin and connect the general output end of the I2C core to the second pin; wherein, the GPIO core is the IP core of the GPIO communication interface.

6. The test board supporting multiple external interfaces according to any one of claims 1 to 5, characterized in that Set 16 configurable pins, and the preset register addresses corresponding to the 16 configurable pins are 0x100 to 0x10f respectively.

7. The test board supporting multiple external interfaces according to any one of claims 1 to 5, characterized in that The communication identifier is represented as a 3-bit bit code. Among them, the GPIO communication identifier includes a GPIO input communication identifier and a GPIO output communication identifier, and the SPI communication identifier includes an SPI_STD communication identifier and an SPI_CUSTOMIZE communication identifier; The GPIO input communication identifier is 0b000, the GPIO output communication identifier is 0b001, the UART communication identifier is 0b010, the I2C communication identifier is 0b011, the SPI_STD communication identifier is 0b100, and the SPI_CUSTOMIZE communication identifier is 0b101; where SPI_STD represents the standard SPI 4-wire timing protocol, and SPI_CUSTOMIZE is a customized SPI timing protocol. The customized SPI timing protocol includes MISO signal, CS signal, MOSI signal, SCK signal, communication completion done signal, and busy signal representing ongoing communication.

8. A method for testing an optical module, characterized in that, When using the test board with multiple external interfaces according to any one of claims 1-7 to test multiple optical modules, when multiple optical modules all match the I2C communication interface, the method includes: Configuring multiple pairs of pins of the test board as I2C communication interfaces; Dividing each optical module according to the slave address of the optical module, so that the optical modules with the same slave address are divided into different first sets; Connecting the optical modules belonging to one first set to the same I2C communication interface of the test board, and connecting the optical modules belonging to different first sets to different I2C communication interfaces.

9. The optical module testing method according to claim 8, wherein, The dividing each optical module according to the slave address of the optical module specifically includes: Clustering each optical module to divide the optical modules with the same slave address into the same second set; Establishing N third sets, and sequentially allocating each optical module in the second set to the corresponding third set in the order of the number of elements contained from more to less, and using each third set after the allocation is completed as the first set; where, the optical module is preferentially allocated to the third set with the least number of elements, and multiple optical modules in one second set are allocated to different third sets; N is the number of elements in the second set with the most number of elements.

10. The optical module testing method according to claim 8, characterized in that, When multiple optical modules respectively match different communication interfaces, the method further includes: Configuring the corresponding pins of the test board according to the communication interface requirements of the optical modules, and connecting the optical modules to the corresponding communication interfaces to test multiple optical modules.

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