Method and system for rapidly reading TDC chip data in ATE equipment
By allocating independent data channels to each TDC chip and reading TDC chip data in parallel according to predefined grouping rules, the problem of inefficient reading in ATE devices is solved, and efficient data acquisition and calibration cycle shortening is achieved.
Patent Information
- Application Number
- CN202510458854.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-14
- Publication Date
- 2025-07-25
AI Technical Summary
Existing ATE devices are inefficient and consume severe time when reading TDC chip data. Especially in high-density chip scenarios, it is difficult to meet the needs of high throughput and fast response, and it is easy to cause data loss or errors.
Each TDC chip is allocated independent data channels and divided into at least two groups according to predefined grouping rules. Multiple chips in the same group are synchronized by chip selection signals, data in the same group is read in parallel, and other groups are processed in turn, combining FIFO buffers and status monitoring mechanisms to ensure data integrity.
The calibration cycle is greatly shortened, and the efficiency is increased to about 26 times that of the traditional serial method. At the same time, data overflow is effectively avoided in high concurrency scenarios and ensure data integrity.
Smart Images
Figure CN120371626A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor automatic test equipment, and particularly to a method and system for quickly reading data of a TDC chip in an ATE device. Background Art
[0002] In the field of semiconductor testing, automatic test equipment (ATE) is widely used for calibrating and collecting data of time-to-digital converter (TDC) chips. In traditional solutions, the ATE device reads the sampling data of each TDC chip one by one through a serial communication interface. For example, when there are multiple TDC chips on a calibration board, it is necessary to sequentially select and read the data of each chip in order, resulting in a linear increase in the overall calibration time with the number of chips. This serial method is not only inefficient but also significantly extends the test cycle in high-density chip scenarios, making it difficult to meet the requirements of modern semiconductor testing for high throughput and fast response. In addition, data loss or errors are likely to occur during the serial reading process due to the complexity of the communication protocol and timing conflicts, further affecting the reliability of the test results. Therefore, how to optimize the reading efficiency of TDC chip data, reduce the calibration time, and ensure data integrity and system stability has become a technical problem that urgently needs to be solved in this field. Summary of the Invention
[0003] The purpose of the present invention is to provide a method and system for quickly reading data of a TDC chip in an ATE device to solve the problems of low efficiency and time consumption caused by serial reading when the current ATE device reads data of the TDC chip.
[0004] To achieve the above object, in the first aspect of the present invention, a method for quickly reading data of a TDC chip in an ATE device is provided, including the following steps:
[0005] Allocate an independent data channel for each TDC chip;
[0006] Divide all TDC chips into at least two groups according to a predefined grouping rule;
[0007] Select all TDC chips within the same group as target TDC chips, send sampling instructions to the target TDC chips simultaneously, read the sampling data of the target TDC chips in parallel, and record the corresponding relationship between the data channel and the target TDC chip to obtain the sampling data corresponding to the data channel;
[0008] Select the TDC chips of the remaining groups as new target TDC chips respectively, and sequentially read the sampling data of the target TDC chips within the same group until all the data of all groups are read.
[0009] Preferably, in the method for quickly reading data of a TDC chip in the ATE device, each data channel of the TDC chip includes an independent data line, a chip select signal line, and a corresponding FIFO buffer.
[0010] Preferably, in the method for quickly reading data of a TDC chip in the ATE device, all the TDC chips in the same group are selected as target TDC chips, and a sampling instruction is sent to the target TDC chips simultaneously. Parallel reading of the sampling data of the selected TDC chips includes selecting all the TDC chips in the same group as target TDC chips through the chip select signal line, writing the data into the corresponding FIFO buffer in real time through the independent data line in the target TDC chip, and the main control system parallel reads the data in multiple FIFO buffers in the same group.
[0011] Preferably, in the method for quickly reading data of a TDC chip in the ATE device, when the main control system parallel reads the data in multiple FIFO buffers in the same group, data aggregation processing is performed based on the corresponding relationship between the data channel and the target TDC chip.
[0012] Preferably, in the method for quickly reading data of a TDC chip in the ATE device, the predefined grouping rule is to group according to the parity of the TDC chip address.
[0013] Preferably, in the method for quickly reading data of a TDC chip in the ATE device, the parity grouping rule is specifically:
[0014] The TDC chips with the least significant bit of the address code being 0 are divided into the even group;
[0015] The TDC chips with the least significant bit of the address code being 1 are divided into the odd group.
[0016] Preferably, in the method for quickly reading data of a TDC chip in the ATE device, after allocating an independent data channel for each TDC chip, it further includes the steps of configuring and soft resetting each TDC chip.
[0017] Preferably, in the method for quickly reading data of a TDC chip in the ATE device, the FIFO buffer is provided with a status monitoring circuit, and when it detects that the data volume in the buffer reaches a preset threshold, it sends an interrupt request signal to the main control system to trigger a data reading operation.
[0018] In the second aspect of the present invention, there is also provided a system for quickly reading data of a TDC chip in an ATE device, and the system includes:
[0019] A data channel allocation module, which is used to establish independent data channels for each TDC chip. The data channels include independent data lines, chip select signal lines, and corresponding FIFO buffers;
[0020] A grouping control module, configured to divide multiple TDC chips into at least two groups according to a predefined grouping rule;
[0021] A parallel sampling control module, connected to the grouping control module, is used to simultaneously select all TDC chips within the same group as target TDC chips through the chip select signal lines, and send synchronous sampling instructions to the target TDC chips;
[0022] Preferably, in the system for quickly reading TDC chip data in the ATE device, there is also a data acquisition and processing module, and the data acquisition and processing module includes:
[0023] A multi-channel read / write unit, connected to the FIFO buffers of each TDC chip, is used to parallelly read the data in the FIFO buffers of multiple TDC chips within the same group;
[0024] A channel mapping unit, which records the binding relationship between each data channel and the corresponding TDC chip;
[0025] A data reorganization unit, which classifies and aggregates the original sampling data according to the binding relationship;
[0026] An inter-group switching module, which is used to switch the chip select signal to the next group and trigger the parallel sampling operation of this group after the data reading of the current group is completed.
[0027] Compared with the prior art, the present invention has at least the following technical effects:
[0028] In the present invention, by allocating independent data channels for each TDC chip, and dividing all TDC chips into at least two groups according to a predefined grouping rule, combined with the chip select signal to synchronously trigger the parallel sampling of multiple chips within the same group, and simultaneously parallelly read the data within the same group, and then process other groups in turn. Compared with the traditional serial method, the total reading time of this solution is reduced from linear complexity to being related to the number of groupings (for example, when N chips are grouped into odd and even groups, the time is shortened to about 2 / N of the original scheme), greatly shortening the calibration cycle. At the same time, the status monitoring and interruption mechanism of the FIFO buffer can effectively avoid data overflow, thus ensuring data integrity in high-concurrency scenarios. Description of the Drawings
[0029] Figure 1 It is a flowchart of the method for AC calibration of the ATE device client in an embodiment of the present invention. Detailed Embodiments
[0030] The following will describe in more detail a method and system for AC calibration of the client of an ATE device according to the present invention with reference to schematic diagrams. The preferred embodiments of the present invention are shown, and it should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as broad knowledge for those skilled in the art and not as a limitation to the present invention.
[0031] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would obscure the present invention with unnecessary details. It should be considered that in the development of any actual embodiment, a large number of implementation details must be made to achieve the specific goals of the developer, such as changing from one embodiment to another according to the relevant system or business limitations. Additionally, it should be considered that such development work may be complex and time-consuming, but it is only routine work for those skilled in the art.
[0032] In the following paragraphs, the present invention will be described more specifically by way of example with reference to the accompanying drawings. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.
[0033] In the field of automatic test equipment (ATE), the calibration and data reading of the TDC (time-to-digital converter) chip are key steps to ensure test accuracy. Traditional ATE devices usually consist of a host and multiple resource boards, where the calibration board interacts with the TDC chip through a serial communication interface. In the prior art, the data reading of the TDC chip adopts a serial mode: the host sequentially selects a single TDC chip, sends a sampling instruction through the serial interface and waits for its return data, and then switches to the next chip after completion. When there are multiple TDC chips in the system, sequential operations need to be performed one by one, resulting in the overall calibration time increasing linearly with the number of chips. For example, if the reading time of a single chip is T seconds, the total time for N chips is NT seconds. This method is inefficient, especially in scenarios that require high-density and high-frequency calibration, seriously restricting the test throughput.
[0034] In view of this, as Figure 1 shown, in view of these limitations of the prior art, this embodiment proposes a method for quickly reading data of a TDC chip in an ATE device to solve the problems of low efficiency and time consumption caused by serial reading when the current ATE device reads data of the TDC chip. The method includes the following steps:
[0035] S1: Allocate an independent data channel for each TDC chip;
[0036] S2: Divide all TDC chips into at least two groups according to a predefined grouping rule;
[0037] S3: Select all TDC chips within the same group as target TDC chips, send sampling instructions to the target TDC chips simultaneously, read the sampling data of the target TDC chips in parallel, and record the corresponding relationship between the data channels and the target TDC chips to obtain the sampling data corresponding to the data channels;
[0038] S4: Select the TDC chips of the remaining groups as new target TDC chips respectively, and sequentially read the sampling data of the target TDC chips within the same group until all the data of all groups are read.
[0039] Further, in the method for quickly reading TDC chip data in the ATE device, each of the data channels of each TDC chip includes an independent data line, a chip select signal line, and a corresponding FIFO buffer.
[0040] For step S1, allocate independent data channels for each TDC chip. Each of the data channels of each TDC chip includes an independent data line, a chip select signal line, and a corresponding FIFO buffer. The independent data line is used to transmit the sampling data of the TDC chip to ensure that the data of each chip does not interfere with each other. The chip select signal line (CS) is used to select the target TDC chip, and the chips within the same group share the chip select signal line to achieve parallel operation. In addition, each data channel is configured with an independent FIFO buffer for temporarily storing sampling data to prevent data loss caused by the processing delay of the main control system.
[0041] It should be noted that a status monitoring circuit is provided in the FIFO buffer. When it is detected that the data volume in the buffer reaches a preset threshold (such as 80% capacity), an interrupt request signal is sent to the main control system to trigger the data reading operation.
[0042] In addition, after allocating independent data channels for each TDC chip, it is also necessary to configure and perform a soft reset operation on each TDC chip. Specifically, configure each TDC chip by setting parameters such as the working mode and sampling frequency of the TDC chip through the main control system; and clear the cache and status register of the TDC chip by sending a reset instruction to ensure that the initial states are consistent.
[0043] Further, for the division of TDC chip groups according to the predefined grouping rule in step S2, the predefined grouping rule can be grouping according to the parity of the TDC chip address.
[0044] Specifically, the odd-even grouping rule is to group the TDC chips according to the least significant bit of the address code of the TDC chip: the TDC chips with the least significant bit of the address code being 0 are divided into the even group; the TDC chips with the least significant bit of the address code being 1 are divided into the odd group. For example, if the system includes 52 TDC chips (addresses 0 to 51), the even group includes addresses 0, 2, 4,......, 50, and the odd group includes addresses 1, 3, 5,......, 51.
[0045] For step S3, all the TDC chips in the same group are selected as the target TDC chips, and a sampling instruction is sent to the target TDC chips simultaneously. Parallelly reading the sampling data of the selected TDC chips includes selecting all the TDC chips in the same group as the target TDC chips through the chip select signal line, writing the data into the corresponding FIFO buffer in real time through the independent data lines in the target TDC chips, and the main control system parallelly reads the data in multiple FIFO buffers in the same group.
[0046] Further, in the method for quickly reading the data of the TDC chip in the ATE device, when the main control system parallelly reads the data in multiple FIFO buffers in the same group, data aggregation processing is performed based on the correspondence between the data channels and the target TDC chips.
[0047] Specifically, the core of step S3 is to efficiently collect the data of the TDC chip through the grouped parallel mechanism. The detailed process is as follows:
[0048] First, the chip select signal triggers and the target group is selected. The main control system simultaneously activates all the TDC chips in the same group (for example, 26 chips in the even group) through the shared chip select signal line (such as active low). The chip select signal is broadcast to the chip select pins of all the TDC chips in the group through the bus to ensure synchronous selection.
[0049] Next, the synchronous sampling instruction is sent. The main control system sends a synchronous sampling instruction to the target group, triggering all the selected chips to start the time interval measurement simultaneously and convert the results into digital signals. The instruction is strictly synchronized through a synchronous communication protocol (such as SPI broadcast mode) or a hardware trigger signal to ensure that all the chips start sampling in the same clock cycle.
[0050] Subsequently, it enters the data parallel acquisition and FIFO writing stage. Each TDC chip writes the generated sampling data into the corresponding FIFO buffer in real time through an independent data line (such as a dedicated SPI channel). The buffer is equipped with a status monitoring circuit. When the data volume reaches a preset threshold (such as 80% capacity), an interrupt request is sent to the main control system to trigger the data reading operation.
[0051] In the parallel reading and data processing section of the main control system, the multi-channel reading and writing unit reads the data of all FIFO buffers in the same group in parallel through DMA (Direct Memory Access) or multi-threading technology. At the same time, based on a preset static mapping table (such as channel 1 corresponding to address 1, channel 2 corresponding to address 2, etc.), the original data is classified and aggregated according to the chip address to ensure that the sampled data corresponds one-to-one with the data channels.
[0052] Finally, data integrity and timing verification are ensured through the global clock synchronization and verification mechanism. The main control system verifies the timing tags (such as timestamps) of the data in each channel to ensure that the sampling times are strictly synchronized. If data loss or errors are detected, the system can actively read the remaining data or trigger the retransmission mechanism to ensure data reliability.
[0053] For step S4, after reading the data of the current group, the chip select signal is switched to the remaining groups, and the operations in step S3 are repeated until the data collection of all groups is completed.
[0054] Taking 52 TDC chips as an example, the traditional serial method requires 52 operations and takes 52T seconds, while this method performs parallel operations by grouping into odd and even groups, only requiring two reads (26 chips per group), and the time consumption is reduced to 2T seconds, with the efficiency increased by 26 times. This process realizes the efficient acquisition and processing of data from a large number of TDC chips in the ATE device through hardware synchronization, independent data channel design, and FIFO buffer management.
[0055] In the second aspect of the present invention, there is also provided a system for quickly reading data of TDC chips in an ATE device, and the system includes:
[0056] A data channel allocation module for establishing independent data channels for each TDC chip, and the data channels include independent data lines, chip select signal lines, and corresponding FIFO buffers;
[0057] A grouping control module configured to divide multiple TDC chips into at least two groups according to predefined grouping rules;
[0058] A parallel sampling control module connected to the grouping control module for simultaneously selecting all TDC chips in the same group as target TDC chips through the chip select signal line and sending synchronous sampling instructions to the target TDC chips;
[0059] Furthermore, in the system for quickly reading data of TDC chips in the ATE device, there is also a data acquisition and processing module, and the data acquisition and processing module includes:
[0060] A multi-channel reading and writing unit connected to the FIFO buffers of each TDC chip for parallel reading of the data in the FIFO buffers of multiple TDC chips in the same group;
[0061] Channel mapping unit, which records the binding relationship between each of the data channels and the corresponding TDC chip;
[0062] Data recombination unit, which classifies and aggregates the original sampled data according to the binding relationship;
[0063] Inter-group switching module, which is used to switch the chip select signal to the next group and trigger the parallel sampling operation of this group after the data reading of the current group is completed.
[0064] In summary, in a method and system for AC calibration of an ATE device client provided by an embodiment of the present invention, by allocating independent data channels to each TDC chip, and dividing all TDC chips into at least two groups according to a predefined grouping rule, combining the chip select signal to synchronously trigger parallel sampling of multiple chips within the same group, simultaneously reading the data within the same group in parallel, and then processing other groups in sequence. Compared with the traditional serial method, the total reading time of this solution is reduced from linear complexity to being related to the number of groupings (for example, when N chips are grouped into odd and even groups, the time is shortened to about 2 / N of the original solution), greatly shortening the calibration cycle. At the same time, the status monitoring and interruption mechanism of the FIFO buffer can effectively avoid data overflow, thereby ensuring data integrity in high-concurrency scenarios.
[0065] The above is only a preferred embodiment of the present invention and does not impose any limitation on the present invention. Any person skilled in the art within the technical field, without departing from the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed by the present invention, all of which belong to the content of the technical solution of the present invention and still fall within the protection scope of the present invention.
Claims
1. A method for quickly reading data of a TDC chip in an ATE device, characterized in that, Including the following steps: Allocating an independent data channel for each TDC chip; Dividing all TDC chips into at least two groups according to a predefined grouping rule; Selecting all TDC chips within the same group as target TDC chips, simultaneously sending a sampling instruction to the target TDC chips, parallelly reading the sampling data of the target TDC chips, and recording the correspondence between the data channel and the target TDC chips to obtain the sampling data corresponding to the data channel; Respectively selecting the TDC chips of the remaining groups as new target TDC chips, and sequentially reading the sampling data of the target TDC chips within the same group until all the data of all groups are read.
2. The method for quickly reading data of a TDC chip in the ATE device according to claim 1, wherein Each data channel of each TDC chip includes an independent data line, a chip select signal line, and a corresponding FIFO buffer.
3. The method for quickly reading data of a TDC chip in the ATE device according to claim 2, wherein Said selecting all TDC chips within the same group as target TDC chips, simultaneously sending a sampling instruction to the target TDC chips, and parallelly reading the sampling data of the selected TDC chips includes selecting all TDC chips within the same group as target TDC chips through the chip select signal line, writing data into the corresponding FIFO buffer in real time through the independent data line in the target TDC chip, and the main control system parallelly reading the data in multiple FIFO buffers within the same group.
4. The method for quickly reading data of the TDC chip in the ATE device according to claim 3, wherein When the main control system parallelly reads the data in multiple FIFO buffers within the same group, data aggregation processing is performed based on the correspondence between the data channel and the target TDC chip.
5. The method for quickly reading data of a TDC chip in the ATE device according to claim 1, wherein The predefined grouping rule is to group according to the parity of the TDC chip address.
6. The method for quickly reading data of a TDC chip in the ATE device according to claim 5, characterized in that, The specific parity grouping rule is: Dividing the TDC chips with the least significant bit of the address code being 0 into the even group; Dividing the TDC chips with the least significant bit of the address code being 1 into the odd group.
7. The method for quickly reading data of a TDC chip in the ATE device according to claim 1, wherein After allocating an independent data channel for each TDC chip, it further includes the steps of configuring and soft resetting each TDC chip.
8. The method for quickly reading data of the TDC chip in the ATE device according to claim 2, characterized in that, The FIFO buffer is provided with a status monitoring circuit, and when it detects that the buffer data volume reaches a preset threshold, it sends an interrupt request signal to the main control system to trigger a data reading operation.
9. A system for quickly reading data of a TDC chip in an ATE device, characterized in that, The system includes: A data channel allocation module, configured to establish an independent data channel for each TDC chip, and the data channel includes an independent data line, a chip select signal line, and a corresponding FIFO buffer; A grouping control module, configured to divide multiple TDC chips into at least two groups according to a predefined grouping rule; A parallel sampling control module, connected to the grouping control module, and configured to simultaneously select all TDC chips within the same group as target TDC chips through the chip select signal line, and send a synchronous sampling instruction to the target TDC chips.
10. The system for quickly reading data of the TDC chip in the ATE device according to claim 9, wherein, The system further includes a data acquisition and processing module, and the data acquisition and processing module includes: A multi-channel reading and writing unit, connected to the FIFO buffer of each TDC chip, and configured to parallelly read the data in the FIFO buffers of multiple TDC chips within the same group; A channel mapping unit, recording the binding relationship between each data channel and the corresponding TDC chip; A data recombination unit that classifies and aggregates the original sampled data according to the binding relationship; An inter-group switching module for switching the chip select signal to the next group and triggering the parallel sampling operation of the group after completing the data reading of the current group.