Memory allocation and data processing method and device based on double-die cross storage

Abstract

The present application provides a memory allocation and data processing method and device based on dual-Die cross-storage, the method comprising: applying for a continuous logical memory address space for an operator task, and allocating the continuous logical memory address space alternately to Die0 and Die1 by hardware in units of byte blocks with a preset number of bytes; remapping each logical memory address space allocated to Die0 and Die1 to the physical memory address space of Die0 and Die1 respectively, and cross-storing the data associated with the operator task into the physical memory address space of Die0 and Die1; applying for thread resources for the operator task and dividing them into TG0 and TG1, binding TG0 and TG1 to Die0 and Die1 respectively; in the order in which the continuous logical memory address space is alternately allocated to Die0 and Die1, using TG0 and TG1 to alternately load byte blocks with a preset number of bytes from Die0 and Die1 respectively, calculating the data loaded alternately each time and storing the calculation results.

Description

Technical Field

[0001] The present application relates to the field of artificial intelligence chip design technology, and specifically to a memory allocation and data processing method based on dual-die cross storage. Background Art

[0002] In the field of artificial intelligence, an operator refers to the basic unit used to perform specific computing tasks. A chip unit (Die) is an independent computing unit on a physical chip (including hardware resources such as ALU and cache). Each operator must ultimately be mapped to a specific circuit on the Die for execution.

[0003] In related technologies, when the computing resources of a single die cannot meet the parallel computing requirements of an operator (such as matrix multiplication or convolution), the operator must be split into multiple subtasks and assigned to multiple dies for collaborative execution. Multi-die collaborative execution typically requires cross-die data transmission. Due to the limitations of die-to-die interconnect bandwidth, cross-die data transmission speed cannot keep up with the computing speed, thus slowing the overall performance of the operator and failing to maximize the hardware's performance. Summary of the Invention

[0004] In view of this, the present application provides a memory allocation and data processing method and device based on double-die cross storage, which can bring out the strongest performance of hardware and improve the overall performance of operator tasks.

[0005] To solve the above technical problems, the technical solution of this application is implemented as follows:

[0006] In one embodiment, a memory allocation and data processing method based on dual-die cross-storage is provided, the method comprising:

[0007] Apply for a continuous logical memory address space for the operator task, and alternately allocate the continuous logical memory address space to the first chip unit Die0 and the second chip unit Die1 in units of byte blocks of a preset number of bytes;

[0008] Remap the logical memory address spaces allocated to Die0 and Die1 to the physical memory address spaces of Die0 and Die1 respectively, and store the data associated with the operator tasks crosswise in the physical memory address spaces of Die0 and Die1;

[0009] Apply for thread resources for the operator task and divide it into a first thread group TG0 and a second thread group TG1, and bind the TG0 and TG1 to the Die0 and Die1 respectively;

[0010] According to the order in which the continuous logical memory address space is alternately allocated to the Die0 and the Die1, the TG0 and the TG1 are used to alternately load byte blocks of a preset number of bytes from the Die0 and the Die1 respectively, and the data loaded alternately each time is calculated and the calculation result is stored.

[0011] In one possible implementation, the alternating allocation includes:

[0012] The byte block with the Nth preset byte number of the continuous logical memory address space is allocated to the Die0, and the byte block with the N+1th preset byte number of the continuous logical memory address space is allocated to the Die1, where N is an even number.

[0013] In one possible embodiment, the remapping is achieved by deploying an address translator PAGEN module between the system direct memory access device SDMA and the physical memory address space of Die0 and Die1, or by deploying an address translator PAGEN module between the host aperture HA and the physical memory address space of Die0 and Die1.

[0014] In one possible implementation, the remapping includes:

[0015] Perform a hash operation on the partition identifier and the secondary cache identifier in each logical memory address assigned to the Die0; replace the original partition identifier and the original secondary cache identifier in the logical memory address with the hash operation result of the partition identifier and the hash operation result of the secondary cache identifier respectively; and use the logical memory address after the above replacement process as the physical memory address of the Die0 corresponding to the logical memory address;

[0016] Perform a hash operation on the partition identifier and the secondary cache identifier in each logical memory address assigned to the Die1; replace the original partition identifier and the original secondary cache identifier in the logical memory address with the hash operation result of the partition identifier and the hash operation result of the secondary cache identifier, respectively; and use the logical memory address after the above replacement processing as the physical memory address of the Die1 corresponding to the logical memory address.

[0017] In one possible implementation, the thread resources applied for the operator task are used to execute multiple subtasks obtained by splitting the operator task, wherein the subtasks to be executed by the thread resources allocated to the TG0 are independent of the subtasks to be executed by the thread resources allocated to the TG1.

[0018] In one possible implementation, the thread group binding satisfies:

[0019] All memory access instructions of TG0 are executed only in Die0, and all memory access instructions of TG1 are executed only in Die1.

[0020] In one possible implementation, the alternating loading includes:

[0021] The starting address of the continuous logical memory address space is used as the base address, and the following operations are performed cyclically until the loading process of all cross-stored data is completed:

[0022] The TG0 performs a load operation on the Die0 to obtain a preset number of bytes of data, and the load address is: the base address;

[0023] The TG1 performs a load operation on the Die1 to obtain data of a preset number of bytes, and the load address is: the base address plus the preset number of bytes;

[0024] Calculate the data loaded by the TG0 and the TG1, and store the calculation results;

[0025] The base address is incremented by 2×a preset number of bytes.

[0026] In another embodiment, a memory allocation and data processing device based on double-die cross storage is provided, the device comprising:

[0027] an allocation unit, configured to apply for a continuous logical memory address space for an operator task, and to alternately allocate the continuous logical memory address space to the first chip unit Die0 and the second chip unit Die1 in units of byte blocks of a preset number of bytes;

[0028] A mapping unit, configured to remap the logical memory address spaces allocated to Die0 and Die1 to the physical memory address spaces of Die0 and Die1, respectively, and store the data associated with the operator tasks in the physical memory address spaces of Die0 and Die1 in an interleaved manner;

[0029] a binding unit, configured to apply for thread resources for the operator task and divide the resources into TG0 and TG1, and bind TG0 and TG1 to Die0 and Die1 respectively;

[0030] A processing unit is configured to alternately load byte blocks of a preset number of bytes from Die0 and Die1 using TG0 and TG1 in the order in which the continuous logical memory address space is alternately allocated to Die0 and Die1, calculate the data loaded alternately each time, and store the calculation results.

[0031] In one possible implementation, the allocating unit performing the alternating allocation includes:

[0032] The byte block with the Nth preset byte number of the continuous logical memory address space is allocated to the Die0, and the byte block with the N+1th preset byte number of the continuous logical memory address space is allocated to the Die1, where N is an even number.

[0033] In one possible embodiment, the mapping unit implements the remapping by deploying an address translator PAGEN module between the system direct memory access device SDMA and the physical memory address space of Die0 and Die1, or by deploying an address translator PAGEN module between the host aperture HA and the physical memory address space of Die0 and Die1.

[0034] In a possible implementation, the mapping unit performing the remapping includes:

[0035] Perform a hash operation on the partition identifier and the secondary cache identifier in each logical memory address assigned to the Die0; replace the original partition identifier and the original secondary cache identifier in the logical memory address with the hash operation result of the partition identifier and the hash operation result of the secondary cache identifier respectively; and use the logical memory address after the above replacement process as the physical memory address of the Die0 corresponding to the logical memory address;

[0036] Perform a hash operation on the partition identifier and the secondary cache identifier in each logical memory address assigned to the Die1; replace the original partition identifier and the original secondary cache identifier in the logical memory address with the hash operation result of the partition identifier and the hash operation result of the secondary cache identifier, respectively; and use the logical memory address after the above replacement processing as the physical memory address of the Die1 corresponding to the logical memory address.

[0037] In one possible implementation, the thread resources applied for the operator task are used to execute multiple subtasks obtained by splitting the operator task, wherein the subtasks to be executed by the thread resources allocated to the TG0 are independent of the subtasks to be executed by the thread resources allocated to the TG1.

[0038] In one possible implementation, the thread group binding satisfies:

[0039] All memory access instructions of TG0 are executed only in Die0, and all memory access instructions of TG1 are executed only in Die1.

[0040] In a possible implementation, the processing unit executing the alternate loading includes:

[0041] The starting address of the continuous logical memory address space is used as the base address, and the following operations are performed cyclically until the loading process of all cross-stored data is completed:

[0042] The TG0 performs a load operation on the Die0 to obtain a preset number of bytes of data, and the load address is: the base address;

[0043] The TG1 performs a load operation on the Die1 to obtain data of a preset number of bytes, and the load address is: the base address plus the preset number of bytes;

[0044] Calculate the data loaded by the TG0 and the TG1, and store the calculation results;

[0045] The base address is incremented by 2×a preset number of bytes.

[0046] In another embodiment, an electronic device is provided, including:

[0047] processor;

[0048] a memory for storing executable instructions for the processor;

[0049] The processor is configured to execute the executable instructions to implement the above-mentioned memory allocation and data processing method based on double Die cross storage.

[0050] In another embodiment, a computer-readable storage medium is provided. When at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, the electronic device can implement the memory allocation and data processing method based on double Die cross storage as described above.

[0051] In another embodiment, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the computer program implements the above-mentioned memory allocation and data processing method based on double Die cross storage.

[0052] It can be seen from the above technical solution that in the above embodiment, in order to execute the operator task, a continuous logical memory address space is first applied for, and then allocated to Die0 and Die1 alternately according to fixed-length blocks; then each logical memory address space allocated to Die0 is remapped to a different physical memory address space of Die0, and each logical memory address space allocated to Die1 is remapped to a different physical memory address space of Die1, and the data associated with the operator task is cross-stored in the physical memory address space of Die0 and Die1, which can make the data evenly arranged in Die0 and Die1 instead of concentratedly arranged, which helps to improve the memory access efficiency of the data in Die0 and Die1, thereby fully utilizing the memory resources of the Die0 and Die1. To bring out the strongest performance of the hardware; then, thread resources are applied for the operator task and divided into the first thread group TG0 and the second thread group TG1, and the TG0 and TG1 are bound to the Die0 and the Die1 respectively, so that TG0 can only access the data on Die0, and TG1 can only access the data on Die1, thereby ensuring that when the continuous logical memory address space is alternately allocated to Die0 and Die1 in the order in which TG0 and TG1 are used to alternately load byte blocks of a preset number of bytes from Die0 and Die1 respectively, and process the loaded data, the data communication between Die0 and Die1 can be reduced, thereby improving the overall performance of the operator task. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0054] Figure 1 Schematic diagram of the flow of the memory allocation and data processing method based on double-die cross storage in an embodiment of the present application;

[0055] Figure 2 An example diagram of deploying the PAGEN module in an embodiment of the present application;

[0056] Figure 3 A flowchart illustrating how to alternately allocate continuous logical memory address space to Die0 and Die1 according to an embodiment of the present application;

[0057] Figure 4 This is a schematic diagram showing the result of a continuous logical memory address space being alternately allocated to Die0 and Die1 according to an embodiment of the present application;

[0058] Figure 5 This is a schematic diagram of the format of the logical memory address according to an embodiment of the present application;

[0059] Figure 6 This is an example diagram of the distribution of the physical memory address spaces of Die0 and Die1 corresponding to each logical memory address space after remapping in an embodiment of the present application;

[0060] Figure 7 A schematic diagram of a process for remapping a logical memory address space of Die0 to a physical memory address space of Die0 according to an embodiment of the present invention;

[0061] Figure 8 Schematic diagram of remapping a logical memory address space of Die to the physical memory address space of Die in an embodiment of the present application;

[0062] Figure 9 This is a flow chart of an embodiment of the present application using TG0 and TG1 to alternately load byte blocks of a preset number of bytes from Die0 and Die1 respectively;

[0063] Figure 10 This is a structural diagram of a memory allocation and data processing device based on dual-die cross-storage according to an embodiment of the present application;

[0064] Figure 11 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0066] The terms "first," "second," "third," "fourth," and so on (if any) in the description and claims of the present invention and in the drawings described above are used to distinguish similar objects and are not necessarily used to describe the order or precedence of objects. It should be understood that the terms used in this way are interchangeable where appropriate, so that the implementation of the invention described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units expressly listed, but may include other steps or units not expressly listed or inherent to such processes, methods, products, or apparatus.

[0067] In related technologies, complex operators usually need to be executed across dies. Cross-die communication results in a longer data transmission path, which significantly increases the communication latency compared to a single die. In addition, due to the limitation of the die-to-die interconnection bandwidth, the cross-die data transmission speed does not match the computing speed, thereby affecting the execution efficiency of the operator task, reducing the overall performance of the operator task, and failing to unleash the highest performance of the hardware.

[0068] Based on the above technical problems, an embodiment of the present application discloses a memory allocation and data processing method based on dual-die cross storage. For operator tasks, a continuous logical memory address space is first applied for, and the continuous logical memory address space is alternately allocated to two chip units: Die0 and Die1 in units of byte blocks with a preset number of bytes. Then, each logical memory address space allocated to Die0 and Die1 is remapped to the physical memory address space of Die0 and Die1 respectively, and the data associated with the operator tasks is cross-stored in the physical memory address space of Die0 and Die1. Through remapping, the data is evenly arranged in Die0 and Die1, which helps to improve the memory access efficiency of the data in Die0 and Die1 and can give full play to the strongest performance of the hardware. Next, thread resources are applied for the operator task and divided into TG0 and TG1, and TG0 and TG1 are bound to Die0 and Die1 respectively, so that TG0 can only access the data on Die0 and TG1 can only access the data on Die1; finally, according to the order in which continuous logical memory address space is alternately allocated to Die0 and Die1, TG0 and TG1 are used to alternately load byte blocks of a preset number of bytes from Die0 and Die1 respectively, calculate the data loaded alternately each time and store the calculation results. In the process of alternating data loading, since TG0 only accesses the data on Die0 and TG1 only accesses the data on Die1, cross-Die data communication between Die0 and Die1 is avoided, thereby improving the execution efficiency of the operator task and improving the overall performance of the operator task.

[0069] The specific implementation of the memory allocation and data processing method based on dual-die cross storage in an embodiment of the present invention is described in detail below with reference to the accompanying drawings.

[0070] See also Figure 1 , Figure 1 This is a flow chart of a memory allocation and data processing method based on double Die cross storage in an embodiment of the present application. Figure 1 As shown, the method specifically includes the following steps:

[0071] Step 101: Apply for a continuous logical memory address space for the operator task, and alternately allocate the continuous logical memory address space to the first chip unit (Die0) and the second chip unit (Die1) in units of byte blocks with a preset number of bytes.

[0072] In an embodiment of the present application, logical memory address space with a fixed block length can be alternately allocated to Die0 and Die1, and the fixed block length can be pre-set according to needs. For example, the fixed block length can be pre-set to 512 bytes, that is, the preset number of bytes is 512 bytes.

[0073] In the embodiment of the present application, the operation of alternately allocating continuous logical memory address space to Die0 and Die1 can be implemented by hardware.

[0074] Step 102: Remap the logical memory address spaces allocated to Die0 and Die1 to the physical memory address spaces of Die0 and Die1 respectively, and store the data associated with the operator tasks in the physical memory address spaces of Die0 and Die1 in an interleaved manner.

[0075] In an embodiment of the present application, by remapping each logical memory address space assigned to Die0 to a different physical memory address space of Die0, and remapping each logical memory address space assigned to Die1 to a different physical memory address space of Die1, and then cross-storing the data associated with the operator task in the physical memory address space of Die0 and Die1, the arrangement of the data on Die0 and Die1 is no longer continuous, but dispersed and uniform, so that data access will not be concentrated in similar physical memory address spaces, which helps to read data in parallel, and thus helps to improve the memory access efficiency of data in Die0 and Die1, and can give full play to the strongest performance of the hardware.

[0076] In actual applications, the physical memory of the device can be directly operated through the CPU (i.e., the host side), or the physical memory of the device can be accessed through the GPU.

[0077] In one possible implementation of the present application, the physical memory of the device is accessed through the GPU. In this case, the remapping of the logical memory address space to the physical memory address space can be achieved by deploying a PAGEN module between the System Direct Memory Access (SDMA) and the physical memory of the device (such as the physical memory of Die0 and Die1). Figure 2 Shows the PAGEN module deployed between SDMA and the device's physical memory.

[0078] In another possible implementation of the present application, the physical memory of the device is accessed through the CPU. In this case, the remapping of the logical memory address space to the physical memory address space can be achieved by deploying a PAGEN module between the host aperture (HA) and the physical memory of the device (such as the physical memory of Die0 and Die1). Figure 2 Shows the PAGEN module deployed between SDMA and the device's physical memory.

[0079] The PAGEN module is an operating system memory management module used to implement address conversion from logical memory addresses to physical memory addresses.

[0080] Step 103: Apply for thread resources for the operator task and divide it into the first thread group (TG0) and the second thread group (TG1), and bind TG0 and TG1 to Die0 and Die1 respectively;

[0081] In the embodiment of the present application, an operator task can be split into multiple subtasks, and different subtasks are used to complete different functions.

[0082] In an embodiment of the present application, the thread resources applied for the operator task are used to execute multiple subtasks obtained by splitting the operator task, wherein the subtask to be executed by the thread resources allocated to TG0 is independent of the subtask to be executed by the thread resources allocated to TG1. The two subtasks are independent of each other, indicating that the two subtasks are executed independently of each other and do not need to communicate with each other during execution. Therefore, the subtask to be executed by the thread resources allocated to TG0 is independent of the subtask to be executed by the thread resources allocated to TG1, which can avoid mutual communication between TG0 and TG1 during execution, that is, there is no need to execute cross-Die data communication between Die0 and Die1, thereby improving the execution efficiency of the operator task and improving the overall performance of the operator task.

[0083] In an embodiment of the present application, binding a thread group to a chip unit (Die) allows the thread group to only access the chip unit, that is, all memory access instructions of the thread group are only executed on the chip unit. Therefore, binding TG0 and TG1 to Die0 and Die1 respectively satisfies the following conditions: all memory access instructions of TG0 are only executed on Die0, and all memory access instructions of TG1 are only executed on Die1. By binding TG0 to Die0 and TG1 to Die1, cross-Die data communication between Die0 and Die1 can be further avoided, thereby further improving the execution efficiency of operator tasks and improving the overall performance of operator tasks.

[0084] Step 104 : in the order in which the continuous logical memory address space is alternately allocated to Die0 and Die1 , TG0 and TG1 are used to alternately load byte blocks of a preset number of bytes from Die0 and Die1 respectively, calculate the data loaded alternately each time and store the calculation results.

[0085] In an embodiment of the present application, after the data associated with the operator task is cross-stored in the physical memory address space of Die0 and Die1, and after thread resources are applied for the operator task and divided into TG0 and TG1 and TG0 and TG1 are bound to Die0 and Die1 respectively, TG0 and TG1 can be used to load data from the physical memory address space of Die0 and Die1 respectively and perform computing operations and storage operations, wherein the data can be alternately loaded starting from the starting address of the above-mentioned continuous logical memory address space.

[0086] In some embodiments, in step 101, the continuous logical memory address space is alternately allocated to Die0 and Die1. For specific implementation, see Figure 3 .

[0087] Figure 3 This is a flowchart of an embodiment of the present application for alternately allocating continuous logical memory address space to Die0 and Die1. The specific steps are as follows:

[0088] Step 301: Allocate the Nth byte block of a preset number of bytes in the continuous logical memory address space to Die0; where N is an even number.

[0089] Step 302: Allocate the N+1th preset byte block in the continuous logical memory address space to Die1.

[0090] Taking the preset number of bytes as 512 as an example, the continuous logical memory address space is alternately allocated to Die0 and Die1, and the results are as follows:

[0091] The 0th, 2nd, 4th, 6th, ... 512-byte blocks in the continuous logical memory address space are allocated to Die0.

[0092] The 1st, 3rd, 5th, 7th, ... 512-byte blocks in the continuous logical memory address space are allocated to Die1.

[0093] Figure 4 The schematic diagram shows the result of continuous logical memory address space being alternately allocated to Die0 and Die1, as shown in FIG. Figure 4 As shown, Die0 and Die1 are alternately allocated to a plurality of byte blocks of a preset number of bytes, any two byte blocks belonging to Die0 are not adjacent to each other, and any two byte blocks belonging to Die1 are not adjacent to each other.

[0094] In the embodiment of the present application, after the continuous logical memory address space is alternately allocated to Die0 and Die1, a logical memory address can be expressed as Figure 5 The format shown, such as Figure 5 As shown, the logical memory address includes a segment offset (section_offset), a partition identifier (Partion_ID), a secondary cache identifier (L2ID), a chip unit identifier (Die_ID), and a page offset (Byte_offset), wherein section_offset occupies bits 13-38; Partion_ID indicates a resource partition of Die, occupying bit 12; L2ID indicates a secondary cache in a resource partition of Die (indicated by Partion_ID), occupying bits 10-11; Die_ID indicates a Die, occupying bit 9; and Byte_offset occupies bits 0-8.

[0095] In the embodiment of the present application, after the continuous logical memory address space is alternately allocated to Die0 and Die1, the logical memory address spaces allocated to Die0 and Die1 can be further remapped to the physical memory address spaces of Die0 and Die1 respectively. Figure 6 An example diagram of the distribution of the physical memory address spaces of Die0 and Die1 corresponding to each logical memory address space after remapping is shown, as shown in FIG. Figure 6 As shown, the continuous logical memory address space is scattered after being remapped to the physical memory address space.

[0096] In some embodiments, step 102 remaps the logical memory address spaces assigned to Die0 and Die1 to the physical memory address spaces of Die0 and Die1, respectively, including: remapping the logical memory address spaces assigned to Die0 to different physical memory address spaces of Die0, and remapping the logical memory address spaces assigned to Die1 to different physical memory address spaces of Die1. The remapping process of each logical memory address space to the physical memory address space is consistent. The following takes the remapping of a logical memory address space of Die0 to a physical memory address space of Die0 as an example to illustrate the remapping process. For specific implementation, see Figure 7 .

[0097] Figure 7 This is a flow chart of remapping a logical memory address space of Die0 to a physical memory address space of Die0 according to an embodiment of the present invention. The specific steps are as follows:

[0098] Step 701: Perform a hash operation on the partition identifier and the L2 cache identifier in the logical memory address allocated to Die0.

[0099] Step 702: Replace the original partition identifier and the original L2 cache identifier in the logical memory address with the hash operation result of the partition identifier and the hash operation result of the L2 cache identifier respectively.

[0100] Step 703: Use the logical memory address after the above replacement process as the physical memory address of Die0 corresponding to the logical memory address.

[0101] Figure 8 A schematic diagram of remapping a logical memory address space of Die to the physical memory address space of Die is shown, as shown in FIG. Figure 8 As shown, a hash operation is performed only on the Partion_ID and L2ID in the logical memory address, so that only the partition identifier (Partion_ID) and the secondary cache identifier (L2ID) are different between the logical memory address and its corresponding physical memory address.

[0102] In some embodiments, step 104 uses TG0 and TG1 to alternately load byte blocks of a preset number of bytes from Die0 and Die1 respectively, which is specifically implemented as follows: Figure 9 shown.

[0103] Figure 9 This is a flow chart of an embodiment of the present application using TG0 and TG1 to alternately load byte blocks of a preset number of bytes from Die0 and Die1, respectively, specifically including the following steps:

[0104] Step 901: Use the starting address of the continuous logical memory address space as the base address and loop through the following steps 902-905 until the loading process of all cross-stored data is completed.

[0105] Step 902: TG0 performs a load operation on Die0 to obtain data of a preset number of bytes. The load address is: base address.

[0106] In an embodiment of the present application, the base address is a predefined logical memory address. When executing data loading, it is necessary to first remap the logical memory address to a physical memory address, and then load a preset number of bytes of data starting from the physical memory address. The preset number of bytes can be, for example, 512 bytes.

[0107] Step 903: TG1 performs a load operation on Die1 to obtain data of a preset number of bytes. The load address is: the base address plus the preset number of bytes.

[0108] In an embodiment of the present application, the base address plus a preset number of bytes corresponds to a logical memory address. When executing data loading, the logical memory address can be first remapped to a physical memory address, and then the data of the preset number of bytes starting from the physical memory address can be loaded.

[0109] Step 904: Calculate the data loaded by TG0 and TG1, and store the calculation results;

[0110] Step 905 : Increment the base address by 2×the preset number of bytes (ie, base address=base address+2×the preset number of bytes).

[0111] In an embodiment of the present application, the base address can increase as the number of loop operations for loading cross-storage data increases. Taking the preset number of bytes as 512 bytes as an example, each time a loop operation is executed, the base address will be increased by 1024 bytes (i.e., base address = base address + 1024 bytes).

[0112] In this step, the base address is updated, and the process returns to step 902 to execute a new round of alternate data loading until all cross-stored data are loaded and processed (including calculation and storage of the loaded data).

[0113] As can be seen from the above embodiments, in this application, by allocating continuous logical memory address space for operator tasks, the continuous logical memory address space is alternately allocated to two chip units: Die0 and Die1 in units of byte blocks with a preset number of bytes; then, each logical memory address space allocated to Die0 and Die1 is remapped to the physical memory address space of Die0 and Die1 respectively, and the data associated with the operator task is cross-stored in the physical memory address space of Die0 and Die1, so that the data is evenly arranged in Die0 and Die1, which helps to improve the memory access efficiency of the data in Die0 and Die1 and can give full play to the strongest performance of the hardware; then, apply for line 2 for the operator task The program resources are divided into TG0 and TG1, and TG0 and TG1 are bound to Die0 and Die1 respectively, so that TG0 can only access the data on Die0 and TG1 can only access the data on Die1; finally, in the order in which the continuous logical memory address space is alternately allocated to Die0 and Die1, TG0 and TG1 are used to alternately load byte blocks of a preset number of bytes from Die0 and Die1 respectively, and the data loaded alternately each time is calculated and the calculation results are stored. Since TG0 only accesses the data on Die0 and TG1 only accesses the data on Die1, cross-Die data communication between Die0 and Die1 is avoided, thereby improving the execution efficiency of the operator task and improving the overall performance of the operator task.

[0114] All the above optional technical solutions can be arbitrarily combined to form optional embodiments of the present disclosure, and will not be described in detail here.

[0115] Based on the same inventive concept, the embodiment of the present application also provides a memory allocation and data processing device based on double Die cross storage. Figure 10 , Figure 10 This is a structural diagram of a memory allocation and data processing device based on double Die cross storage according to an embodiment of the present application. Figure 10 As shown, the device includes:

[0116] An allocation unit 1001 is configured to apply for a continuous logical memory address space for an operator task, and to alternately allocate the continuous logical memory address space to a first chip unit Die0 and a second chip unit Die1 in units of byte blocks of a preset number of bytes.

[0117] A mapping unit 1002 is configured to remap the logical memory address spaces allocated to Die0 and Die1 to the physical memory address spaces of Die0 and Die1, respectively, and store the data associated with the operator tasks in the physical memory address spaces of Die0 and Die1 in an interleaved manner;

[0118] A binding unit 1003 is configured to apply for thread resources for the operator task and divide the resources into TG0 and TG1, and bind TG0 and TG1 to Die0 and Die1 respectively;

[0119] The processing unit 1004 is used to alternately load byte blocks of a preset number of bytes from Die0 and Die1 using TG0 and TG1 in the order in which the continuous logical memory address space is alternately allocated to Die0 and Die1, calculate the data loaded alternately each time and store the calculation results.

[0120] In some embodiments, the allocating unit 1001 performing the alternating allocation includes:

[0121] The byte block with the Nth preset byte number of the continuous logical memory address space is allocated to the Die0, and the byte block with the N+1th preset byte number of the continuous logical memory address space is allocated to the Die1, where N is an even number.

[0122] In some embodiments, the mapping unit 1002 implements the remapping by deploying an address translator PAGEN module between the system direct memory access device SDMA and the physical memory address space of Die0 and Die1, or implements the remapping by deploying an address translator PAGEN module between the host aperture HA and the physical memory address space of Die0 and Die1.

[0123] In some embodiments, the mapping unit 1002 performs the remapping, including:

[0124] Perform a hash operation on the partition identifier and the secondary cache identifier in each logical memory address assigned to the Die0; replace the original partition identifier and the original secondary cache identifier in the logical memory address with the hash operation result of the partition identifier and the hash operation result of the secondary cache identifier respectively; and use the logical memory address after the above replacement process as the physical memory address of the Die0 corresponding to the logical memory address;

[0125] Perform a hash operation on the partition identifier and the secondary cache identifier in each logical memory address assigned to the Die1; replace the original partition identifier and the original secondary cache identifier in the logical memory address with the hash operation result of the partition identifier and the hash operation result of the secondary cache identifier, respectively; and use the logical memory address after the above replacement processing as the physical memory address of the Die1 corresponding to the logical memory address.

[0126] In some embodiments, the thread resources applied for the operator task are used to execute multiple subtasks obtained by splitting the operator task, wherein the subtasks to be executed by the thread resources allocated to the TG0 are independent of the subtasks to be executed by the thread resources allocated to the TG1.

[0127] In some embodiments, the thread group binding satisfies:

[0128] All memory access instructions of TG0 are executed only in Die0, and all memory access instructions of TG1 are executed only in Die1.

[0129] In some embodiments, the processing unit 1004 executing the alternate loading includes:

[0130] The starting address of the continuous logical memory address space is used as the base address, and the following operations are performed cyclically until the loading process of all cross-stored data is completed:

[0131] The TG0 performs a load operation on the Die0 to obtain a preset number of bytes of data, and the load address is: the base address;

[0132] The TG1 performs a load operation on the Die1 to obtain data of a preset number of bytes, and the load address is: the base address plus the preset number of bytes;

[0133] Calculate the data loaded by the TG0 and the TG1, and store the calculation results;

[0134] The base address is incremented by 2×a preset number of bytes.

[0135] Figure 11 It is a structural diagram of an electronic device provided in an embodiment of the present application. In some embodiments, the electronic device is a test platform. The electronic device 1100 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 1101 and one or more memories 1102, wherein the memory 1102 stores at least one program code, and the at least one program code is loaded and executed by the processor 1101 to implement the method for testing the processor provided in each of the above embodiments. Of course, the electronic device 1100 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The electronic device 1100 may also include other components for realizing device functions, which will not be described here.

[0136] In an exemplary embodiment, a computer-readable storage medium including at least one instruction is also provided, such as a memory including at least one instruction. The above at least one instruction can be executed by a processor in a computer device to complete the memory allocation and data processing method based on double Die cross storage in the above embodiment.

[0137] Optionally, the above-mentioned computer-readable storage medium may be a non-temporary computer-readable storage medium, for example, the non-temporary computer-readable storage medium may include ROM (Read-Only Memory), RAM (Random-Access Memory), CD-ROM (Compact Disc Read-Only Memory), magnetic tape, floppy disk and optical data storage device, etc.

[0138] In an exemplary embodiment, a computer program product is further provided, including a computer program. When the computer program is executed by a processor, the memory allocation and data processing method based on double-die cross storage provided in the above embodiments is implemented.

[0139] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0140] The flowcharts and block diagrams in the accompanying drawings of the present application show the possible implementation architecture, functions and operations of the systems, methods and computer program products according to the various embodiments disclosed in the present application. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in the order of the standards in different figures. For example, the boxes represented by two connections can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of the boxes in the block diagram or flowchart, can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0141] Those skilled in the art will appreciate that the features described in the various embodiments and / or claims disclosed in this application may be combined and / or coupled in various ways, even if such combinations and / or couplings are not explicitly disclosed in this application. In particular, without departing from the spirit and teachings of this application, the features described in the various embodiments and / or claims of this application may be combined and / or coupled in various ways, and all such combinations and / or couplings fall within the scope disclosed in this application.

[0142] The principles and implementation methods of the present invention are described herein using specific embodiments. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas, and is not intended to limit this application. For those skilled in the art, changes can be made in the specific implementation methods and application scope based on the ideas, spirit and principles of the present invention. Any modifications, equivalent replacements, improvements, etc. made therein should be included within the scope of protection of this application.

Claims

1. A memory allocation and data processing method based on double-die cross storage, characterized in that: The method comprises: Apply for a continuous logical memory address space for the operator task, and alternately allocate the continuous logical memory address space to the first chip unit Die0 and the second chip unit Die1 in units of byte blocks of a preset number of bytes; Remap the logical memory address spaces allocated to Die0 and Die1 to the physical memory address spaces of Die0 and Die1 respectively, and store the data associated with the operator tasks crosswise in the physical memory address spaces of Die0 and Die1; Apply for thread resources for the operator task and divide it into a first thread group TG0 and a second thread group TG1, and bind the TG0 and TG1 to the Die0 and Die1 respectively; According to the order in which the continuous logical memory address space is alternately allocated to the Die0 and the Die1, the TG0 and the TG1 are used to alternately load byte blocks of a preset number of bytes from the Die0 and the Die1 respectively, and the data loaded alternately each time is calculated and the calculation result is stored.

2. The method according to claim 1, wherein The alternating allocation includes: The byte block with the Nth preset byte number of the continuous logical memory address space is allocated to the Die0, and the byte block with the N+1th preset byte number of the continuous logical memory address space is allocated to the Die1, where N is an even number.

3. The method according to claim 1, characterized in that The remapping is achieved by deploying an address translator PAGEN module between the system direct memory access device SDMA and the physical memory address space of Die0 and Die1; Alternatively, the remapping is achieved by deploying an address translator PAGEN module between the host aperture HA and the physical memory address spaces of Die0 and Die1.

4. The method according to claim 1, wherein The remapping includes: Perform a hash operation on the partition identifier and the secondary cache identifier in each logical memory address assigned to the Die0; replace the original partition identifier and the original secondary cache identifier in the logical memory address with the hash operation result of the partition identifier and the hash operation result of the secondary cache identifier respectively; and use the logical memory address after the above replacement process as the physical memory address of the Die0 corresponding to the logical memory address; Perform a hash operation on the partition identifier and the secondary cache identifier in each logical memory address assigned to the Die1; replace the original partition identifier and the original secondary cache identifier in the logical memory address with the hash operation result of the partition identifier and the hash operation result of the secondary cache identifier, respectively; and use the logical memory address after the above replacement processing as the physical memory address of the Die1 corresponding to the logical memory address.

5. The method according to claim 1, wherein The thread resources applied for the operator task are used to execute multiple subtasks obtained by splitting the operator task, wherein the subtasks to be executed by the thread resources allocated to the TG0 are independent of the subtasks to be executed by the thread resources allocated to the TG1.

6. The method according to claim 1, characterized in that The binding satisfies: All memory access instructions of TG0 are executed only in Die0, and all memory access instructions of TG1 are executed only in Die1.

7. The method according to claim 1, characterized in that The alternating loading includes: The starting address of the continuous logical memory address space is used as the base address, and the following operations are performed cyclically until the loading process of all cross-stored data is completed: The TG0 performs a load operation on the Die0 to obtain a preset number of bytes of data, and the load address is: the base address; The TG1 performs a load operation on the Die1 to obtain data of a preset number of bytes, and the load address is: the base address plus the preset number of bytes; Calculate the data loaded by the TG0 and the TG1, and store the calculation results; The base address is incremented by 2×a preset number of bytes.

8. A memory allocation and data processing device based on double-die cross storage, characterized in that: The device comprises: an allocation unit, configured to apply for a continuous logical memory address space for an operator task, and to alternately allocate the continuous logical memory address space to the first chip unit Die0 and the second chip unit Die1 in units of byte blocks of a preset number of bytes; A mapping unit, configured to remap the logical memory address spaces allocated to Die0 and Die1 to the physical memory address spaces of Die0 and Die1, respectively, and store the data associated with the operator tasks in the physical memory address spaces of Die0 and Die1 in an interleaved manner; a binding unit, configured to apply for thread resources for the operator task and divide the thread resources into a first thread group TG0 and a second thread group TG1, and bind the TG0 and TG1 to the Die0 and the Die1 respectively; A processing unit is configured to alternately load byte blocks of a preset number of bytes from Die0 and Die1 using TG0 and TG1 in the order in which the continuous logical memory address space is alternately allocated to Die0 and Die1, calculate the data loaded alternately each time, and store the calculation results.

9. The device according to claim 8, characterized in that The allocating unit performing the alternating allocation includes: The byte block with the Nth preset byte number of the continuous logical memory address space is allocated to the Die0, and the byte block with the N+1th preset byte number of the continuous logical memory address space is allocated to the Die1, where N is an even number.

10. The device according to claim 8, characterized in that The mapping unit implements the remapping by deploying an address translator PAGEN module between the system direct memory access device SDMA and the physical memory address space of Die0 and Die1, or by deploying an address translator PAGEN module between the host aperture HA and the physical memory address space of Die0 and Die1.

11. The device according to claim 8, characterized in that The mapping unit performing the remapping includes: Perform a hash operation on the partition identifier and the secondary cache identifier in each logical memory address assigned to the Die0; replace the original partition identifier and the original secondary cache identifier in the logical memory address with the hash operation result of the partition identifier and the hash operation result of the secondary cache identifier respectively; and use the logical memory address after the above replacement process as the physical memory address of the Die0 corresponding to the logical memory address; Perform a hash operation on the partition identifier and the secondary cache identifier in each logical memory address assigned to the Die1; replace the original partition identifier and the original secondary cache identifier in the logical memory address with the hash operation result of the partition identifier and the hash operation result of the secondary cache identifier, respectively; and use the logical memory address after the above replacement processing as the physical memory address of the Die1 corresponding to the logical memory address.

12. The device according to claim 8, characterized in that The thread resources applied for the operator task are used to execute multiple subtasks obtained by splitting the operator task, wherein the subtasks to be executed by the thread resources allocated to the TG0 are independent of the subtasks to be executed by the thread resources allocated to the TG1.

13. The device according to claim 8, characterized in that The binding satisfies: All memory access instructions of TG0 are executed only in Die0, and all memory access instructions of TG1 are executed only in Die1.

14. The device according to claim 8, characterized in that The processing unit executing the alternate loading includes: The starting address of the continuous logical memory address space is used as the base address, and the following operations are performed cyclically until the loading process of all cross-stored data is completed: The TG0 performs a load operation on the Die0 to obtain a preset number of bytes of data, and the load address is: the base address; The TG1 performs a load operation on the Die1 to obtain data of a preset number of bytes, and the load address is: the base address plus the preset number of bytes; Calculate the data loaded by the TG0 and the TG1, and store the calculation results; The base address is incremented by 2×a preset number of bytes.

15. An electronic device, characterized in that: include: processor; a memory for storing executable instructions for the processor; The processor is configured to execute the executable instructions to implement the method according to any one of claims 1 to 7.

16. A computer-readable storage medium, characterized in that When at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, the electronic device is enabled to implement the method according to any one of claims 1 to 7.

17. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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