Method and system for processing interruption of sending MSIx to server by PCIe (Peripheral Component Interface Express) equipment

Abstract

The invention relates to a processing method and device for sending MSIx interruption to a server by PCIe equipment, computer equipment, a storage medium and a computer program product. The method comprises the following steps: acquiring interrupt request information and sending the interrupt request information to an interrupt request arbitration module; the interrupt request information permitted by the interrupt request arbitration module is converted into an MSIx interrupt request, and the MSIx interrupt request is sent to the PCIe IP unit; and the PCIe IP unit generates a corresponding memory write TLP operation based on the MSIx interrupt request and sends the memory write TLP operation to the PCIe bus. By adopting the method, the problem that the PLIC interrupt system interface in the PCIe equipment function card cannot be directly integrated and connected with the MSIx interrupt interface is solved, and a solution is provided for forwarding the output interrupt of the PLIC system to the server HOST; a message channel is provided for the PCIe equipment function card to actively report information to the HOST, and a solution is provided for the server HOST to manage the PCIe equipment function card at the downstream; different types of interrupts output by the PLIC interrupt system are effectively identified, and an MSIx interrupt forwarding request is sent out.

Description

Technical Field

[0001] This application relates to the technical field of PCIe, and particularly to a method, device, equipment, and storage medium for a PCIe device to send MSIx interrupts to a server. Background Art

[0002] As a chip-level peripheral interface technology, PCIe uses point-to-point connections between various endpoint devices. Data transmission between PCIe interface devices features high bandwidth throughput and low latency. Therefore, in a server cluster system interconnected by PCIe interface slots, data transmission between each endpoint device has high bandwidth and is stable and reliable. At the same time, the number of components required in the data processing system is small, greatly improving the cost-effectiveness of the PCIe slot cluster system.

[0003] The PCIe slot is located on the server motherboard, and different types of PCIe device function cards are inserted into the PCIe slots of the server. The PCIe device function card is connected to the server HOST processor through the PCIe bus in the motherboard slot. When the server system is working, the HOST executes management and scheduling tasks. The PCIe function card notifies the HOST in an interrupt manner. The HOST learns about the abnormal conditions and chip working status of its downstream PCIe device function cards based on the interrupt information and then takes corresponding handling measures. In a server system interconnected by PCIe interface slots, since MSIx interrupts can provide higher performance and scalability, PCIe function cards all use the MSIx interrupt mechanism to notify the HOST.

[0004] The existing central processor design is completed through the open instruction set architecture of RISC-V. However, the PLIC platform system based on RISC-V does not support MSIx interrupts. At the same time, the internal working status information and abnormal conditions of the PCIe device function card need to be notified to the HOST through the MSIx interrupt method, resulting in the HOST being unable to receive the internal working status information and abnormal condition information of the PCIe device function card in a timely manner. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a method, device, computer equipment, computer-readable storage medium, and computer program product that can timely notify the HOST about the internal working status and abnormal conditions of PCIe.

[0006] In a first aspect, this application provides a method for processing MSIx interrupts sent by a PCIe device to a server. The method includes:

[0007] Obtain interrupt request information and send it to the interrupt request arbitration module;

[0008] Convert the interrupt request information permitted by the interrupt request arbitration module into an MSIx interrupt request and send it to the PCIe IP unit;

[0009] The PCIe IP unit generates a corresponding memory write TLP operation based on the MSIx interrupt request and sends it to the PCIe bus.

[0010] In one embodiment, the PLIC system acquires the interrupt request signal sent by the PCIe device, and sets the indication register used to indicate that the PCIe device sends the interrupt request signal to a high level until all the interrupt request signals in the PCIe device are sent to the PLIC system;

[0011] Converting the interrupt request information permitted by the interrupt request arbitration module into an MSIx interrupt request and sending it to the PCIe IP unit includes:

[0012] The PLIC system generates a corresponding MSIx interrupt forwarding request based on the interrupt request signal and sends the MSIx interrupt sending request to the interrupt request arbitration module;

[0013] The interrupt request arbitration module permits the interrupt request signal of the PLIC system, and sends the MSIx interrupt forwarding request to the PCIe IP unit through a preset interrupt processing unit. The interrupt forwarding request includes address information and data information, and sets the corresponding REQ interrupt request signal of the interrupt processing unit's interrupt forwarding request to a high level;

[0014] The interrupt processing unit sends the MSIx interrupt forwarding request to the HOST server. At the same time, the interrupt processing unit sets the corresponding register TX-SW register to a high level, and closes the register TX-SW register corresponding to the sending channel for sending MSIx to the HOST server to a high level;

[0015] The PCIe IP unit responds to the MSIx interrupt forwarding request of the interrupt processing unit, converts the MSIx interrupt forwarding request into a memory write TLP mode and sends it to the PCI bus, and permits and responds to the corresponding MSIx interrupt forwarding request;

[0016] The HOST server receives the memory write TLP and performs corresponding interrupt processing operations;

[0017] After the HOST server completes the processing of the MSIx interrupt forwarding request, set the TX-SW register to a low level.

[0018] In one embodiment, after the HOST server finishes processing the MSIx interrupt forwarding request, the REQ interrupt request signal is still at a high level, and the PLIC system generates a corresponding secondary MSIx interrupt forwarding request based on the interrupt request signal;

[0019] Repeat the process of converting the interrupt request information that has obtained the permission of the interrupt request arbitration module into an MSIx interrupt request and sending it to the PCIe IP unit until the REQ interrupt request signal is at a low level after the HOST server finishes processing the MSIx interrupt forwarding request.

[0020] In one embodiment, the central processing unit sends interrupt request information and sends it to a preset interrupt register;

[0021] The preset interrupt register provides a corresponding vector interrupt according to the interrupt request information;

[0022] The central processing unit sends the vector interrupt to a preset configuration interrupt cache pool;

[0023] The interrupt vector in the configuration interrupt cache pool sends an arbitration permission request to the interrupt arbitration module, and the MSIx interrupt processing device forwards the configured interrupt that has obtained the arbitration permission as an MSIx interrupt and sends it to the HOST server.

[0024] In one embodiment, the central processing unit sends an interrupt request signal and sets the indication register for indicating that the central processing unit sends the interrupt request signal to a high level until all the interrupt request signals in the central processing unit are sent to the interrupt register;

[0025] Converting the interrupt request information that has obtained the permission of the interrupt request arbitration module into an MSIx interrupt request and sending it to the PCIe IP unit includes:

[0026] The PLIC system generates a corresponding MSIx interrupt forwarding request based on the interrupt request signal and sends the MSIx interrupt sending request to the interrupt request arbitration module;

[0027] The interrupt request arbitration module permits the interrupt request signal of the central processing unit, and sends the MSIx interrupt forwarding request to the PCIe IP unit through a preset interrupt processing unit. The interrupt forwarding request includes address information and data information, and sets the corresponding REQ interrupt request signal of the interrupt forwarding request of the interrupt processing unit to a high level;

[0028] The interrupt processing unit sends the MSIx interrupt forwarding request to the HOST server. At the same time, the interrupt processing unit sets the corresponding register TX-SW register to a high level, and closes the register TX-SW register corresponding to the sending channel for sending MSIx to the HOST server and sets it to a high level;

[0029] The PCIe IP unit responds to the MSIx interrupt forwarding request from the interrupt processing unit, converts the MSIx interrupt forwarding request into a memory write TLP mode and sends it to the PCI bus, and gives a permission response to the corresponding MSIx interrupt forwarding request;

[0030] The HOST server receives the memory write TLP and performs corresponding interrupt processing operations;

[0031] After the HOST server completes the processing of the MSIx interrupt forwarding request, the TX-SW register is set to a low level.

[0032] In one embodiment, when the PLIC system and the configured interrupt cache pool simultaneously send interrupt request information to the interrupt request arbitration module, the interrupt request arbitration module determines whether to send the arbitration permission for this cycle based on the arbitration permission in the preset previous cycle;

[0033] If the arbitration permission in the previous cycle is the interrupt request of the PLIC system, and the arbitration permission for this cycle is the interrupt request of the configured interrupt cache pool, then the arbitration permission for this cycle is sent to the configured interrupt cache pool;

[0034] If the arbitration permission in the previous cycle is the interrupt request of the configured interrupt cache pool, then the arbitration permission for this cycle is the interrupt request of the PLIC system;

[0035] If the interrupt request arbitration module sends the arbitration permission for the first time, the arbitration permission is the interrupt request of the PLIC system.

[0036] In a second aspect, the present application also provides a processing device for a PCIe device to send an MSIx interrupt to a server. The device includes:

[0037] An interrupt request acquisition module, configured to acquire interrupt request information and send it to the interrupt request arbitration module;

[0038] An interrupt request conversion module, configured to convert the interrupt request information that has obtained the permission of the interrupt request arbitration module into an MSIx interrupt request and send it to the PCIe IP unit;

[0039] An interrupt request forwarding module, configured to generate a corresponding memory write TLP operation based on the MSIx interrupt request by the PCIe IP unit and send it to the PCI bus.

[0040] In a third aspect, the present application also provides a computer device. The computer device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0041] Obtain interrupt request information and send it to the interrupt request arbitration module;

[0042] Convert the interrupt request information permitted by the interrupt request arbitration module into an MSIx interrupt request and send it to the PCIe IP unit;

[0043] The PCIe IP unit generates a corresponding memory write TLP operation based on the MSIx interrupt request and sends it to the PCIe bus.

[0044] Fourthly, the present application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0045] Obtain interrupt request information and send it to the interrupt request arbitration module;

[0046] Convert the interrupt request information permitted by the interrupt request arbitration module into an MSIx interrupt request and send it to the PCIe IP unit;

[0047] The PCIe IP unit generates a corresponding memory write TLP operation based on the MSIx interrupt request and sends it to the PCIe bus.

[0048] Fifthly, the present application also provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0049] Obtain interrupt request information and send it to the interrupt request arbitration module; convert the interrupt request information permitted by the interrupt request arbitration module into an MSIx interrupt request and send it to the PCIe IP unit; the PCIe IP unit generates a corresponding memory write TLP operation based on the MSIx interrupt request and sends it to the PCIe bus. For the above-mentioned method, device, computer device, storage medium and computer program product for a PCIe device to send an MSIx interrupt to a server, the present application adopts the above method to solve the problem that the PLIC interrupt system interface in the PCIe device function card cannot be directly integrated and connected to the MSIx interrupt interface, and provides a solution for forwarding the output interrupt of the PLIC system to the server HOST; provides a message channel for the PCIe device function card to actively report information to the HOST, and provides a solution for the server HOST to manage the downstream PCIe device function card; effectively identifies different types of interrupts output by the PLIC interrupt system and issues a request for processing the forwarding of the MSIx interrupt. Description of the Drawings

[0050] Figure 1 It is a hardware schematic diagram of a method for a PCIe device to send an MSIx interrupt to a server in the prior art;

[0051] Figure 2 Hardware schematic diagram of the method for a PCIe device to send MSIx interrupts to a server in an embodiment;

[0052] Figure 3 Flowchart of the method for a PCIe device to send MSIx interrupts to a server in an embodiment;

[0053] Figure 4 Timing diagram of the PLIC system interrupt request and configuration interrupt request processed by the MSIx interrupt processing device in an embodiment;

[0054] Figure 5 Timing diagram of implementing two MSIx transmissions of PCIe interrupts for PCIe interrupt requests in an embodiment;

[0055] Figure 6 Structural block diagram of the device for a PCIe device to send MSIx interrupts to a server in an embodiment. Detailed implementation manners

[0056] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0057] In the method for a PCIe device to send MSIx interrupts to a server provided by the embodiments of the present application, in the prior art, as Figure 1 shown, in a server system interconnected based on a PCIe interface card slot, the data processing and storage functions of the server are allocated to different function cards under the PCIe card slot. Some of these PCIe device function cards have powerful data computing capabilities, and some have powerful image computing and storage functions. Therefore, different types of CPUs are integrated on the PCIe device function cards.

[0058] The PCIe slot is located on the server motherboard, and different types of PCIe device function cards are inserted into the PCIe slots of the server. The PCIe device function card is connected to the server HOST processor through the PCIe bus in the motherboard card slot.

[0059] When the server system is working, the HOST executes management and scheduling tasks. The PCIe function card notifies the HOST in an interrupt manner. Based on the interrupt information, the HOST learns about the abnormal conditions of the PCIe device function cards downstream of it and the working status of the chips, and then takes corresponding handling measures. In a server system interconnected by PCIe interface card slots, since MSIx interrupts can provide higher performance and scalability, PCIe function cards all use the MSIx interrupt mechanism to notify the HOST.

[0060] MSIx is the abbreviation of Message Signaled Interrupt eXtended. MSIx interrupt is a common interrupt mechanism in the PCIe protocol, which allows different hardware and software components to transfer relevant information when an interrupt event occurs. By analyzing the Message Data in the interrupt, the operating system or driver can better understand the source and characteristics of the interrupt event, and thus take appropriate response measures. On the PCIe device function card, the implementation method of MSIx interrupt is that the PCIe device function card performs a memory write TLP packet operation to the server system memory. The memory write address of the MSIx interrupt is the Message Address allocated when the system initializes the PCIe device. The write data Message Data refers to the data related to the interrupt event, which contains some additional information about the interrupt source or interrupt request.

[0061] The RC is the root node between the server HOST and the PCIe card slot. When the RC receives the memory write operation to the Message Address by the PCIe device function card downstream, the RC can accurately identify it as an MSIx interrupt request. It first converts the memory write operation TLP into an Interrupt Message bus transaction and sends it to the bus connected to the HOST. After receiving the Interrupt Message bus transaction through the bus, the HOST directly obtains the interrupt vector number from this bus transaction, and then the software responds to this interrupt and starts the interrupt service program for processing.

[0062] In one embodiment, as Figure 2 and Figure 3 shown, in this embodiment, based on the form of the PCIe card slot between the chip and the server to perform data interaction between the PCIe setting and the server, the method includes the following steps:

[0063] Step 202, obtain the interrupt request information and send it to the interrupt request arbitration module.

[0064] Among them, the interrupt processing device of the PCIe device function card supports forwarding two types of interrupts to MSIx interrupt processing. One is the interrupt processing output by the PLIC interrupt system, and the other is the interrupt processing in which the internal CPU of the chip actively reports messages to the HOST. The PLIC interrupt request information and the configuration interrupt information generated by the local CPU are obtained and sent to the request arbitration module.

[0065] Step 204: Perform arbitration processing on the interrupt request and obtain the corresponding interrupt request information.

[0066] Among them, the interrupt request arbitration module arbitrates the interrupt requests received by the PLIC system and the interrupt requests sent by the local CPU to the interrupt cache pool to obtain the corresponding interrupt request information.

[0067] Step 206: Convert the interrupt request information permitted by the interrupt request arbitration module into an MSIx interrupt request and send it to the PCIe IP unit.

[0068] Among them, after the two types of interrupt requests are arbitrated by RoundRobin, the permitted interrupt requests are converted into MSIx interrupt requests, sent to the PCIe IP unit to generate a system memory write TLP operation, and sent to the PCIe bus. After passing through the RC, it finally reaches the server HOST. At the same time, the TX-SW register in the interrupt forwarding module is set to low level.

[0069] Step 208: The PCIe IP unit generates a corresponding memory write TLP operation based on the MSIx interrupt request and sends it to the PCIe bus.

[0070] Step 210: After the HOST server receives and processes the MSIx interrupt request, clear the interrupt source.

[0071] Among them, after the HOST server receives and processes the MSIx interrupt request, clear the interrupt source in the PLIC system or the local CPU cache pool, and set the TX-SW register forwarded by the interrupt forwarding module to low level.

[0072] In the above method for processing the MSIx interrupt sent by the PCIe device to the server, for the central processing unit in the cluster system that does not support receiving the memory write operation interrupt interface, after being processed by this design invention, the problem that the PLIC interrupt system interface in the PCIe device function card cannot be directly integrated and connected to the MSIx interrupt interface is solved, providing a solution for forwarding the output interrupt of the PLIC system to the server HOST; providing a message channel for the PCIe device function card to actively report information to the HOST, and providing a solution for the server HOST to manage the downstream PCIe device function cards; effectively identifying different types of interrupts output by the PLIC interrupt system and issuing a processing request for forwarding the MSIx interrupt.

[0073] In one embodiment, as Figure 4 shown, it specifically includes:

[0074] The PLIC system obtains the interrupt request signal sent by the PCIe device, sets the indication register used to indicate the PCIe device to send the interrupt request signal to high level until all the interrupt request signals in the PCIe device are sent to the PLIC system; converts the interrupt request information permitted by the interrupt request arbitration module into an MSIx interrupt request and sends it to the PCIe IP unit. The unit includes: the PLIC system generates a corresponding MSIx interrupt forwarding request based on the interrupt request signal and sends the MSIx interrupt sending request to the interrupt request arbitration module; the interrupt request arbitration module permits the interrupt request signal of the PLIC system, and sends the MSIx interrupt forwarding request to the PCIe IP unit through a preset interrupt processing unit. The interrupt forwarding request includes address information and data information, and sets the corresponding REQ interrupt request signal of the interrupt forwarding request of the interrupt processing unit to high level; the interrupt processing unit sends the MSIx interrupt forwarding request to the HOST server, and at the same time the interrupt processing unit sets the corresponding register TX-SW register to high level, closing the sending channel corresponding to sending the MSIx to the HOST server. The corresponding register TX-SW register is set to high level; the PCIe IP unit responds to the MSIx interrupt forwarding request of the interrupt processing unit and converts the MSIx interrupt forwarding request into a memory write TLP mode and sends it to the PCI bus, and performs a permission response to the corresponding MSIx interrupt forwarding request; the HOST server receives the memory write TLP and performs corresponding interrupt processing operations; after the HOST server completes the processing of the MSIx interrupt forwarding request, it sets the TX-SW register to low level.

[0075] In one embodiment, as Figure 4 shown, the specific processing process of the central processing unit, that is, the CPU, sending interrupt request information is:

[0076] The central processing unit sends interrupt request information to a preset interrupt register; the preset interrupt register provides a corresponding vector interrupt according to the interrupt request information; the central processing unit sends the vector interrupt to a preset configuration interrupt buffer pool; the interrupt vector in the configuration interrupt buffer pool sends an arbitration permission request to an interrupt arbitration module, and the MSIx interrupt processing device forwards the configured interrupt with the obtained arbitration permission as an MSIx interrupt and sends it to the HOST server. It is worth mentioning that the specific processing procedure for the central processing unit, that is, the CPU, to send interrupt request information can also be: the central processing unit sends an interrupt request signal, sets the indication register for indicating the central processing unit to send the interrupt request signal to a high level until all the interrupt request signals in the central processing unit are sent to the interrupt register; converts the interrupt request information permitted by the interrupt request arbitration module into an MSIx interrupt request and sends it to the PCIe IP unit. The unit includes: the PLIC system generates a corresponding MSIx interrupt forwarding request based on the interrupt request signal and sends the MSIx interrupt sending request to the interrupt request arbitration module; the interrupt request arbitration module permits the interrupt request signal of the central processing unit and sends the MSIx interrupt forwarding request to the PCIe IP unit through a preset interrupt processing unit. The interrupt forwarding request includes address information and data information, and sets the corresponding REQ interrupt request signal of the interrupt forwarding request of the interrupt processing unit to a high level; the interrupt processing unit sends the MSIx interrupt forwarding request to the HOST server, and at the same time, the interrupt processing unit sets the corresponding register TX-SW register to a high level to close the sending channel corresponding to sending the MSIx to the HOST server, and sets the corresponding register TX-SW register to a high level; the PCIe IP unit responds to the MSIx interrupt forwarding request of the interrupt processing unit and converts the MSIx interrupt forwarding request into a memory write TLP method and sends it to the PCI bus, and performs a permission response to the corresponding MSIx interrupt forwarding request; the HOST server receives the memory write TLP and performs corresponding interrupt processing operations; after the HOST server completes the processing of the MSIx interrupt forwarding request, the TX-SW register is set to a low level.

[0077] In one embodiment, when the PLIC system and the configuration interrupt buffer pool simultaneously send interrupt request information to the interrupt request arbitration module, the interrupt request arbitration module determines to send the arbitration permission of this cycle based on the arbitration permission in the preset previous cycle; if the arbitration permission in the previous cycle is the interrupt request of the PLIC system, then the arbitration permission of this cycle is the interrupt request of the configuration interrupt buffer pool, and the arbitration permission of this cycle is sent to the configuration interrupt buffer pool; if the arbitration permission in the previous cycle is the interrupt request of the configuration interrupt buffer pool, then the arbitration permission of this cycle is the interrupt request of the PLIC system; if the interrupt request arbitration module sends the arbitration permission for the first time, the arbitration permission is the interrupt request of the PLIC system.

[0078] As Figure 4 shown, in the T1 cycle, the PLIC interrupt and the configuration interrupt cache pool simultaneously issue interrupt requests to forward MSIx. The interrupt processing unit arbitrates the PLIC_INT_REQ and CFG_INT_REQ requests;

[0079] In the T2 cycle, the PLIC_INT_REQ interrupt obtains arbitration permission. The interrupt processing unit sends an MSIx interrupt forwarding request to the PCIe IP unit, and MSIx_REQ is set to valid. The address that the interrupt processing unit sends to the PCIe IP unit for the MSIx interrupt is MSIx_ADDR[63:0] of the system-defined PLIC interrupt system, that is, a 64-bit address, and the data is the data MSIx_DATA[31:0] related to the PLIC interrupt event, that is, a 32-bit address. MSIx_DATA can include device ID, interrupt vector, and other status information, etc.

[0080] In the T3 cycle, the interrupt processing unit sets the MSIx_TX_SW register to high, indicating that the current interrupt processing unit has sent an MSIx interrupt request to the HOST, and the HOST has not finished processing the MSIx interrupt yet;

[0081] After receiving the MSIx interrupt forwarding request, the PCIe IP unit takes several cycles. In the T4 cycle, the PCIe IP unit gives an allow response MSIx_GRANT valid to the MSIx interrupt forwarding request sent by the interrupt processing unit, and the PCIe IP unit sends the MSIx interrupt to the PCI bus in the form of a memory write TLP;

[0082] In the T5 cycle, the HOST receives the MSIx interrupt transaction request sent by the PCIe device function card, and the software starts to enter the interrupt service routine to process the interrupt. At the same time, both PLIC_INT_REQ and MSIx_REQ are set to 0, indicating that both of these interrupt forwarding requests have received the response permission from the PCIe IP unit;

[0083] In the T6 cycle, after the software processes the MSIx interrupt for several cycles, the MSIx interrupt processing is completed. In the next T7 cycle, the software sets the MSIx_TX_SW register to low, indicating that the software has processed the MSIx interrupt transaction request sent by the PCIe device function card.

[0084] In the previous interrupt request arbitration, the configuration interrupt request CFG_INT_REQ did not obtain the permission of the interrupt sending request arbiter, and the CFG_INT_REQ request remains valid.

[0085] In the T8 cycle, after the MSIx interrupt handling requested by PLIC_INT_REQ is completed, CFG_INT_REQ obtains the permission of the interrupt transmission request arbiter.

[0086] In the T9 cycle, the interrupt handling unit sends an MSIx interrupt forwarding request to the PCIe IP unit, and MSIx_REQ is set to valid. The address of the MSIx interrupt sent by the interrupt handling unit to the PCIe IP unit is MSIX_ADDR[63:0] of the system-defined CFG interrupt, and the data is MSIX_DATA[31:0] of the CFG interrupt. MSIx_DATA contains the information related to this configuration interrupt, including device ID, error code, or other device status information, etc.

[0087] In the subsequent timing diagram, the processing process of the second CFG_INT_REQ interrupt request is similar to that of the first PLIC interrupt.

[0088] As Figure 5 shown, in this timing diagram, the process of the first forwarding of the MSIx interrupt request is the same as that described in the previous timing diagram, and the processing of the first forwarding of the MSIx interrupt request is completed in the T7 cycle.

[0089] In the T8 cycle, PLIC_INT_REQ is still valid, the second PLIC forwarding of the MSIx interrupt request processing is started, and the permission of the interrupt transmission request arbiter is obtained.

[0090] In the T9 cycle, the interrupt handling unit sends an MSIx interrupt forwarding request to the PCIe IP unit, and MSIx_REQ is set to valid. The address and data of the MSIx interrupt sent by the interrupt handling unit to the PCIe IP unit are MSIX_ADDR[63:0] of the system-defined PLIC interrupt, and the MSIx interrupt data MSIX_DATA[31:0] is information related to the interrupt vector and device ID, etc.

[0091] In the subsequent timing diagram, the timing description of the interrupt request processing process is the same as that of the first PLIC interrupt.

[0092] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least some of the steps or stages in other steps or other steps.

[0093] Based on the same inventive concept, an embodiment of the present application further provides a processing device for a PCIe device to send an MSIx interrupt to a server, which is used to implement the processing method for a PCIe device to send an MSIx interrupt to a server described above. The implementation solutions provided by this device to solve problems are similar to the implementation solutions described in the above method. Therefore, the specific limitations in one or more embodiments of the processing device for a PCIe device to send an MSIx interrupt to a server provided below can refer to the limitations on the processing method for a PCIe device to send an MSIx interrupt to a server in the above text, and will not be repeated here.

[0094] In one embodiment, as Figure 6 shown, a processing device for a PCIe device to send an MSIx interrupt to a server is provided, including: an interrupt request acquisition module, an interrupt request arbitration module, an interrupt request conversion module, an interrupt request forwarding module, and an interrupt request processing module, where:

[0095] In one embodiment, the interrupt request conversion module is further configured to enable the PLIC system to obtain the interrupt request signal sent by the PCIe device, set the indication register for indicating the PCIe device to send the interrupt request signal to a high level until all the interrupt request signals in the PCIe device are sent to the PLIC system; convert the interrupt request information permitted by the interrupt request arbitration module into an MSIx interrupt request and send it to the PCIe IP unit. The unit includes: the PLIC system generates a corresponding MSIx interrupt forwarding request based on the interrupt request signal and sends the MSIx interrupt sending request to the interrupt request arbitration module; the interrupt request arbitration module permits the interrupt request signal of the PLIC system, and sends the MSIx interrupt forwarding request to the PCIe IP unit through a preset interrupt processing unit. The interrupt forwarding request includes address information and data information, and sets the corresponding REQ interrupt request signal of the interrupt processing unit to a high level; the interrupt processing unit sends the MSIx interrupt forwarding request to the HOST server, and at the same time, the interrupt processing unit sets the corresponding register TX-SW register to a high level, and closes the sending channel corresponding to sending the MSIx to the HOST server, and sets the corresponding register TX-SW register to a high level; the PCIe IP unit responds to the MSIx interrupt forwarding request of the interrupt processing unit and converts the MSIx interrupt forwarding request into a memory write TLP mode and sends it to the PCI bus, and performs a permission response to the corresponding MSIx interrupt forwarding request; the HOST server receives the memory write TLP and performs corresponding interrupt processing operations; after the HOST server completes the processing of the MSIx interrupt forwarding request, the TX-SW register is set to a low level.

[0096] In one embodiment, after the HOST server completes the processing of the MSIx interrupt forwarding request, if the REQ interrupt request signal is still at a high level, the PLIC system generates a corresponding secondary MSIx interrupt forwarding request based on the interrupt request signal; repeatedly convert the interrupt request information permitted by the interrupt request arbitration module into an MSIx interrupt request and send it to the PCIe IP unit until after the HOST server completes the processing of the MSIx interrupt forwarding request, the REQ interrupt request signal is at a low level.

[0097] In one embodiment, the interrupt request conversion module is further configured to enable the central processing unit to send interrupt request information and send it to a preset interrupt register; the preset interrupt register provides a corresponding vector interrupt according to the interrupt request information; the central processing unit sends the vector interrupt to a preset configuration interrupt cache pool; the interrupt vector in the configuration interrupt cache pool sends an arbitration permission request to the interrupt arbitration module, and the MSIx interrupt processing device forwards the configuration interrupt permitted by the arbitration to an MSIx interrupt and sends it to the HOST server.

[0098] In one embodiment, the interrupt request conversion module is further configured to send an interrupt request signal to the central processing unit, set the indication register for indicating the central processing unit to send the interrupt request signal to a high level until all the interrupt request signals in the central processing unit are sent to the interrupt register;

[0099] Converting the interrupt request information permitted by the interrupt request arbitration module into an MSIx interrupt request and sending it to the PCIe IP unit, the unit includes:

[0100] The PLIC system generates a corresponding MSIx interrupt forwarding request based on the interrupt request signal and sends the MSIx interrupt sending request to the interrupt request arbitration module; the interrupt request arbitration module permits the interrupt request signal of the central processing unit, and sends the MSIx interrupt forwarding request to the PCIe IP unit through a preset interrupt processing unit, the interrupt forwarding request includes address information and data information, and sets the corresponding REQ interrupt request signal of the interrupt forwarding request sent by the interrupt processing unit to a high level; the interrupt processing unit sends the MSIx interrupt forwarding request to the HOST server, and at the same time the interrupt processing unit sets the corresponding register TX-SW register to a high level, closing the sending channel for sending MSIx to the HOST server, and setting the corresponding register TX-SW register to a high level; the PCIe IP unit responds to the MSIx interrupt forwarding request of the interrupt processing unit and converts the MSIx interrupt forwarding request into a memory write TLP mode and sends it to the PCI bus, and performs a permission response to the corresponding MSIx interrupt forwarding request; the HOST server receives the memory write TLP and performs corresponding interrupt processing operations; after the HOST server completes the processing of the MSIx interrupt forwarding request, the TX-SW register is set to a low level.

[0101] In one embodiment, when the PLIC system and the configured interrupt cache pool simultaneously send interrupt request information to the interrupt request arbitration module, the interrupt request arbitration module determines to send the arbitration permission of this cycle based on the arbitration permission in the preset previous cycle; if the arbitration permission in the previous cycle is the interrupt request of the PLIC system, and the arbitration permission of this cycle is the interrupt request of the configured interrupt cache pool, then the arbitration permission of this cycle is sent to the configured interrupt cache pool; if the arbitration permission in the previous cycle is the interrupt request of the configured interrupt cache pool, then the arbitration permission of this cycle is the interrupt request of the PLIC system; if the interrupt request arbitration module sends the arbitration permission for the first time, the arbitration permission is the interrupt request of the PLIC system.

[0102] Each module in the above-mentioned method and apparatus for processing MSIx interrupts sent by a PCIe device to a server can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above modules can be embedded in the processor of a computer device in hardware form or independent thereof, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each of the above modules.

[0103] In one embodiment, a computer device is provided. The computer device may be a server. The computer device includes a processor, a memory, and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it implements a method for coordinated investment in a power transmission and energy storage system.

[0104] Those skilled in the art can understand that only the block diagram of some structures related to the solution of the present application does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0105] In one embodiment, a computer device is provided, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, it implements the steps in the above-mentioned method embodiments.

[0106] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps in the above-mentioned method embodiments.

[0107] In one embodiment, a computer program product is provided, including a computer program. When the computer program is executed by a processor, it implements the steps in the above-mentioned method embodiments.

[0108] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or fully authorized by all parties.

[0109] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0110] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0111] The above-described embodiments merely represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method for processing an MSIx interrupt sent by a PCIe device to a server, characterized in that, The method includes: Obtaining interrupt request information and sending it to the interrupt request arbitration module; Converting the interrupt request information permitted by the interrupt request arbitration module into an MSIx interrupt request and sending it to the PCIe IP unit; The PCIe IP unit generates a corresponding memory write TLP operation based on the MSIx interrupt request and sends it to the PCIe bus.

2. The method according to claim 1, wherein the interrupt request information converges on the PLIC interrupt system, characterized in that The method further includes: The PLIC system obtains the interrupt request signal sent by the PCIe device, and sets the indication register for indicating that the PCIe device sends the interrupt request signal to a high level until all the interrupt request signals in the PCIe device are sent to the PLIC system; Converting the interrupt request information permitted by the interrupt request arbitration module into an MSIx interrupt request and sending it to the PCIe IP unit includes: The PLIC system generates a corresponding MSIx interrupt forwarding request based on the interrupt request signal and sends the MSIx interrupt sending request to the interrupt request arbitration module; The interrupt request arbitration module permits the interrupt request signal of the PLIC system, and sends the MSIx interrupt forwarding request to the PCIe IP unit through a preset interrupt processing unit. The interrupt forwarding request includes address information and data information, and sets the corresponding REQ interrupt request signal of the interrupt processing unit to a high level; The interrupt processing unit sends the MSIx interrupt forwarding request to the HOST server. At the same time, the interrupt processing unit sets the corresponding register TX-SW register to a high level, and closes the register TX-SW register corresponding to the sending channel for sending MSIx to the HOST server to a high level; The PCIe IP unit responds to the MSIx interrupt forwarding request of the interrupt processing unit and converts the MSIx interrupt forwarding request into a memory write TLP mode and sends it to the PCI bus, and performs a permission response to the corresponding MSIx interrupt forwarding request; The HOST server receives the memory write TLP and performs corresponding interrupt processing operations; After the HOST server completes the processing of the MSIx interrupt forwarding request, the TX-SW register is set to a low level.

3. The method according to claim 2, wherein The method further includes: After the HOST server completes the processing of the MSIx interrupt forwarding request, if the REQ interrupt request signal is still at a high level, the PLIC system generates a corresponding secondary MSIx interrupt forwarding request based on the interrupt request signal; Repeat converting the interrupt request information permitted by the interrupt request arbitration module into an MSIx interrupt request and sending it to the PCIe IP unit until after the HOST server completes the processing of the MSIx interrupt forwarding request, the REQ interrupt request signal is at a low level.

4. The method according to claim 2, wherein The method further includes: The central processing unit sends interrupt request information and sends it to a preset interrupt register; The preset interrupt register provides a corresponding vector interrupt according to the interrupt request information; The central processing unit sends the vector interrupt to a preset configuration interrupt cache pool; The interrupt vector in the configured interrupt cache pool sends an arbitration permission request to the interrupt arbitration module, and the MSIx interrupt processing device forwards the configured interrupt that obtains the arbitration permission as an MSIx interrupt and sends it to the HOST server.

5. The method according to claim 4, wherein The method further includes: The central processing unit sends an interrupt request signal, sets the indication register for indicating that the central processing unit sends the interrupt request signal to a high level until all the interrupt request signals in the central processing unit are sent to the interrupt register; Converting the interrupt request information that obtains the permission of the interrupt request arbitration module into an MSIx interrupt request and sending it to the PCIe IP unit includes: The PLIC system generates a corresponding MSIx interrupt forwarding request based on the interrupt request signal and sends the MSIx interrupt sending request to the interrupt request arbitration module; The interrupt request arbitration module permits the interrupt request signal of the central processing unit, and sends the MSIx interrupt forwarding request to the PCIe IP unit through a preset interrupt processing unit. The interrupt forwarding request includes address information and data information, and sets the corresponding REQ interrupt request signal of the interrupt forwarding request of the interrupt processing unit to a high level; The interrupt processing unit sends the MSIx interrupt forwarding request to the HOST server. At the same time, the interrupt processing unit sets the corresponding register TX-SW register to a high level, closes the sending channel for sending MSIx to the HOST server, and sets the corresponding register TX-SW register to a high level; The PCIe IP unit responds to the MSIx interrupt forwarding request of the interrupt processing unit and converts the MSIx interrupt forwarding request into a memory write TLP mode and sends it to the PCI bus, and performs a permission response to the corresponding MSIx interrupt forwarding request; The HOST server receives the memory write TLP and performs corresponding interrupt processing operations. After the interrupt processing is completed, the HOST server clears the interrupt source corresponding to the interrupt source in the PLIC system or the interrupt source that generates an interrupt by the local chip CPU, and sets the REQ signal of the interrupt forwarding request of the corresponding interrupt processing unit to a low level; After the HOST server completes the processing of the MSIx interrupt forwarding request, the TX-SW register is set to a low level.

6. The method according to claim 5, wherein The method further includes: When the PLIC system and the configured interrupt cache pool send interrupt request information to the interrupt request arbitration module at the same time, the interrupt request arbitration module judges to send the arbitration permission of this cycle based on the arbitration permission in the preset previous cycle; If the arbitration permission in the previous cycle is the interrupt request of the PLIC system, and the arbitration permission of this cycle is the interrupt request of the configured interrupt cache pool, then the arbitration permission of this cycle is sent to the configured interrupt cache pool; If the arbitration permission in the previous cycle is the interrupt request of the configured interrupt cache pool, then the arbitration permission of this cycle is the interrupt request of the PLIC system; If the interrupt request arbitration module sends the arbitration permission for the first time, the arbitration permission is the interrupt request of the PLIC system.

7. A processing device for a PCIe device to send MSIx interrupts to a server, characterized in that, The device includes: An interrupt request acquisition module for acquiring interrupt request information and sending it to the interrupt request arbitration module; An interrupt request conversion module, configured to convert the interrupt request information obtained with the permission of the interrupt request arbitration module into an MSIx interrupt request and send it to the PCIeIP unit; An interrupt request forwarding module, configured to generate a corresponding memory write TLP operation based on the MSIx interrupt request by the PCIeIP unit and send it to the PCIe bus.

8. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method described in any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the method described in any one of claims 1 to 6.

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