Etching method of semiconductor laminated structure, manufacturing method of device and equipment

Abstract

The invention provides an etching method of a semiconductor laminated structure, a manufacturing method of a device and equipment, and the etching method comprises the steps: carrying out the selective etching of a side wall of a first semiconductor layer in the semiconductor laminated structure through employing a first process gas, so as to enable the side wall of the first semiconductor layer to be recessed relative to a second semiconductor layer in a second direction, the second direction is perpendicular to the first direction; wherein the first process gas comprises a first etching gas, and the first etching gas comprises a first fluorine-containing gas and a second fluorine-containing gas; the etching selection ratio of the first fluorine-containing gas to the first semiconductor layer relative to the second semiconductor layer is higher than the etching selection ratio of the second fluorine-containing gas to the first semiconductor layer relative to the second semiconductor layer; the etching rate of the second fluorine-containing gas to the first semiconductor layer is higher than that of the first fluorine-containing gas to the first semiconductor layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to an etching method for a semiconductor stacked structure, a manufacturing method for a semiconductor device, and a semiconductor process equipment. Background Art

[0002] With the continuous advancement of Moore's Law, after the semiconductor process develops to the 3nm node, the gate-all-around (GAA) transistor is considered an effective alternative to the fin field-effect transistor (FinFET).

[0003] The semiconductor stacked structure of the GAA FET is as shown in Figure 1 and Figure 2 It is formed on a substrate 100. There can be multiple semiconductor stacked structures 200, and the multiple semiconductor stacked structures 200 are arranged along a direction parallel to the X1 axis in Figure 1 . The semiconductor stacked structure 200 includes alternately stacked first semiconductor layers 201 and second semiconductor layers 202. The first semiconductor layer 201 includes, for example, Ge, and the second semiconductor layer 202 includes, for example, Si. In the GAA manufacturing process, it is necessary to selectively etch the sidewalls of the first semiconductor layer 201 or the second semiconductor layer 202 in the semiconductor stacked structure 200 on both sides along the direction parallel to the X2 axis in Figure 1 . Taking the etching of the first semiconductor layer 201 as an example, the etched morphology is as shown in Figure 2 .

[0004] In order to reduce the subsequent negative impact on the device, it is necessary for one of the first semiconductor layer 201 and the second semiconductor layer 202 to have a very high selectivity ratio relative to the other during the etching process to avoid or reduce damage to the channel. Currently, how to control the etching selectivity ratio and etching rate of the first semiconductor layer / second semiconductor layer is an urgent problem to be solved. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides an etching method for a semiconductor stacked structure, a manufacturing method for a semiconductor device, and a semiconductor process equipment, which can control the etching selectivity ratio and etching rate of the first semiconductor layer / second semiconductor layer.

[0006] To achieve the object of the present invention, there is provided an etching method for a semiconductor stacked structure. The semiconductor stacked structure includes a first semiconductor layer and a second semiconductor layer alternately stacked in a first direction. The first semiconductor layer contains Ge, and the materials of the first semiconductor layer and the second semiconductor layer are different. The method includes:

[0007] Selectively etch the sidewalls of the first semiconductor layer in the semiconductor stack structure with a first process gas, so that the sidewalls of the first semiconductor layer are recessed relative to the second semiconductor layer in a second direction perpendicular to the first direction;

[0008] Wherein, the first process gas includes a first etching gas, and the first etching gas includes a first fluorine-containing gas and a second fluorine-containing gas;

[0009] The etching selectivity ratio of the first fluorine-containing gas to the first semiconductor layer relative to the second semiconductor layer is higher than that of the second fluorine-containing gas to the first semiconductor layer relative to the second semiconductor layer; and,

[0010] The etching rate of the second fluorine-containing gas to the first semiconductor layer is higher than that of the first fluorine-containing gas to the first semiconductor layer.

[0011] In some embodiments, the first semiconductor layer is Si x Ge y , where 0.05 ≤ y ≤ 0.3, and x + y = 1; and / or

[0012] The second semiconductor layer is one of Si, SiN, SiO, SiON, SiCON.

[0013] In some embodiments, the first fluorine-containing gas includes F2 and / or ClF3, and the second fluorine-containing gas includes a fluorine-containing gas with a bond energy less than that of F2 or ClF3.

[0014] In some embodiments, the second fluorine-containing gas includes at least one of XeF2, XeF4, XeF6, KrF2, BrF3.

[0015] In some embodiments, the first etching process includes a plurality of etching sub-steps, and the flow rate ratio of the first fluorine-containing gas to the second fluorine-containing gas is different in two adjacent etching sub-steps.

[0016] In some embodiments, the first process gas further includes a first auxiliary gas, and the first auxiliary gas contains at least one of hydrogen element, oxygen element, and nitrogen element.

[0017] In some embodiments, the first auxiliary gas includes at least one of HF, O2, H2, N2.

[0018] In some embodiments, the selective etching is pure chemical etching.

[0019] In some embodiments, selectively etching the sidewalls of the first semiconductor layer in the semiconductor stack structure with a first process gas includes:

[0020] A pretreatment step of pretreating the sidewalls of the semiconductor stack structure with the first auxiliary gas;

[0021] An etching step of etching the sidewalls of the first semiconductor layer with the first etching gas;

[0022] A purging step of purging the process chamber;

[0023] Repeat the pretreatment step, the etching step, and the purging step at least once.

[0024] In some embodiments, in the step of selectively etching the sidewalls of the first semiconductor layer in the semiconductor stack structure with the first process gas,

[0025] The temperature range of the wafer carrier device is 0°C - 80°C; and / or,

[0026] The flow rate of the first fluorine-containing gas is greater than 0 sccm and less than or equal to 1000 sccm; and / or,

[0027] The pressure of the process chamber is greater than or equal to 0.1 Torr and less than or equal to 10 Torr.

[0028] In some embodiments, it further includes: performing plasma cleaning on the process chamber before or after performing the selective etching.

[0029] In some embodiments, before selectively etching the sidewalls of the first semiconductor layer in the semiconductor stack structure with the first process gas, it further includes:

[0030] Removing the native oxide layer on the sidewall surface of the semiconductor stack structure by pure chemical etching.

[0031] In some embodiments, the removing the native oxide layer on the sidewall surface of the semiconductor stack structure by pure chemical etching includes:

[0032] Etching the native oxide layer with a second process gas, where the second process gas includes a second etching gas containing HF - pyridine.

[0033] In some embodiments, the second process gas further includes a second auxiliary gas, and the second auxiliary gas includes at least one of N2, Ar, He, and H2.

[0034] In some embodiments, in the step of removing the native oxide layer on the sidewall surface of the semiconductor stack structure:

[0035] The temperature range of the wafer carrier device is 0°C - 80°C; and / or,

[0036] The pressure in the process chamber is greater than or equal to 10 Torr and less than or equal to 40 Torr.

[0037] As another technical solution, the present invention further provides a method for manufacturing a semiconductor device, including:

[0038] Forming a semiconductor stack structure on a substrate, the semiconductor stack structure including a first semiconductor layer and a second semiconductor layer alternately stacked in a first direction, the first semiconductor layer containing Ge, and the materials of the first semiconductor layer and the second semiconductor layer being different;

[0039] Etching the semiconductor stack structure by using the etching method provided by the present invention;

[0040] Filling the space where the first semiconductor layer is recessed relative to the second semiconductor layer with an isolation layer;

[0041] Forming a source region and a drain region on both sides of the semiconductor stack structure along a second direction;

[0042] Removing the first semiconductor layer;

[0043] Forming a gate structure around the second semiconductor layer.

[0044] In some embodiments, the process gas used in the step of removing the first semiconductor layer includes the first fluorine-containing gas and the second fluorine-containing gas.

[0045] As another technical solution, the present invention further provides a semiconductor process equipment, including: a front-end module, a load lock chamber, a transfer chamber, and at least one first process module, the first process module being connected to the transfer chamber, the first process module being used for selectively etching a first semiconductor layer, which includes a first controller, the first controller including a processor and a memory, the memory storing a computer program, and the computer program implementing the above etching method provided by the present invention when executed by the processor.

[0046] In some embodiments, it further includes:

[0047] At least one second process module, the second process module being connected to the transfer chamber, the second process module including a second controller, the second controller including a processor and a memory, the memory storing a computer program, and the computer program implementing the above etching method provided by the present invention when executed by the processor.

[0048] The present invention has the following beneficial effects:

[0049] In the technical solutions of the etching method for a semiconductor stacked structure, the manufacturing method for a semiconductor device, and the semiconductor process equipment provided by the present invention, a first process gas is used to selectively etch the sidewalls of a first semiconductor layer in the semiconductor stacked structure, so that the sidewalls of the first semiconductor layer are recessed relative to a second semiconductor layer in a second direction. Wherein, the first process gas includes a first etching gas, and the first etching gas includes a first fluorine-containing gas and a second fluorine-containing gas. The etching selectivity ratio of the first fluorine-containing gas for the first semiconductor layer relative to the second semiconductor layer is higher than that of the second fluorine-containing gas for the first semiconductor layer relative to the second semiconductor layer; moreover, the etching rate of the second fluorine-containing gas for the first semiconductor layer is higher than that of the first fluorine-containing gas for the first semiconductor layer. Thus, by using the first fluorine-containing gas and the second fluorine-containing gas in combination, not only can the etching selectivity ratio of the first semiconductor layer / second semiconductor layer be increased to achieve selective etching of the sidewalls of the first semiconductor layer, but also the etching rate of the first semiconductor layer can be controlled, so that the magnitude of the etching selectivity ratio of the first semiconductor layer / second semiconductor layer and the etching rate of the first semiconductor layer reach a balance, thereby enabling the profile of the recessed space formed after selective etching of the sidewalls of the first semiconductor layer to meet the requirements. In addition, by using the second fluorine-containing gas, during the process of selectively etching the sidewalls of the first semiconductor layer, high-speed etching of the first semiconductor layer can be achieved without using a plasma or a catalyst, so the damage to the device is also relatively small. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 is a vertical cross-sectional view of the semiconductor stacked structure of the GAA FET according to an embodiment of the present invention along a direction parallel to the X1 axis;

[0051] Figure 2 is a vertical cross-sectional view of the semiconductor stacked structure of the GAA FET according to an embodiment of the present invention along a direction parallel to the X2 axis;

[0052] Figure 3 is a perspective view of the semiconductor stacked structure of the GAA FET according to an embodiment of the present invention;

[0053] Figure 4 is a flowchart of step S200 of the etching method for the semiconductor stacked structure provided by an embodiment of the present invention;

[0054] Figure 5 is a structural diagram of a first process module used to execute step S200 in an embodiment of the present invention;

[0055] Figure 6 is a structural diagram of a relevant gas path connected to a first gas mixing chamber used in an embodiment of the present invention;

[0056] Figure 7It is a specific flowchart of step S200 in the embodiment of the present invention;

[0057] Figure 8 It is a specific flowchart of step S100 and step S200 in the embodiment of the present invention;

[0058] Figure 9 It is a schematic topographic view of the semiconductor stack structure before removing the native oxide layer;

[0059] Figure 10 It is a flowchart of the manufacturing method of the semiconductor device provided by the embodiment of the present invention;

[0060] Figure 11 It is a schematic topographic view of the semiconductor stack structure after filling the isolation layer;

[0061] Figure 12 It is a schematic topographic view of the semiconductor stack structure after forming the source region and the drain region;

[0062] Figure 13 It is a schematic topographic view of the semiconductor stack structure after removing the first semiconductor layer;

[0063] Figure 14 It is a schematic topographic view of the semiconductor stack structure after forming the gate structure;

[0064] Figure 15 It is a structural diagram of the second process module used to execute step S100 in the embodiment of the present invention;

[0065] Figure 16 It is a structural diagram of the semiconductor process equipment provided by the embodiment of the present invention. Detailed implementation manners

[0066] To make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0067] Those skilled in the art should understand that the embodiments of the present application are only illustrative of the structures and methods claimed in the present application that can be implemented in various forms. In addition, each example given in combination with various embodiments is intended to be illustrative, not restrictive. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show details of specific components. Therefore, the specific structural and functional details in the embodiments of the present application should not be construed as restrictive, but merely as a representative basis for teaching those skilled in the art to adopt the methods and structures of the embodiments of the present application in different ways. It should also be noted that the same and corresponding elements are denoted by the same reference numerals.

[0068] In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of the various embodiments of the present application. However, those skilled in the art should understand that the various embodiments of the present application can be practiced without these specific details. In other instances, well-known structures or processing steps are not described in detail to avoid obscuring the present application.

[0069] For the purposes of the following description, the terms "upper", "right", "left", "vertical", "horizontal", "top", "bottom", and their derivatives shall relate to the orientation in the structures and methods disclosed in the accompanying drawings of the specification. It should be understood that when an element, such as a layer, region, or substrate, is referred to as being on another element, the element can be directly on the other element, or intervening elements may also be present. Conversely, when an element is referred to as being directly on another element, no intervening elements are present between the two. It should also be understood that when an element is referred to as being under another element, the element can be directly under the other element, or intervening elements may be present. Conversely, when an element is referred to as being directly under another element, no intervening elements are present between the two.

[0070] Figure 1 A vertical cross-sectional view of the semiconductor stack structure of the GAA FET according to an embodiment of the present invention in a direction parallel to the X1 axis. Figure 2 A vertical cross-sectional view of the semiconductor stack structure of the GAA FET according to an embodiment of the present invention in a direction parallel to the X2 axis. As Figure 1 and Figure 2 shown, the semiconductor stack structure is formed on the substrate 100. There can be multiple semiconductor stack structures 200, and the multiple semiconductor stack structures 200 are arranged in a direction parallel to Figure 1 the X1 axis in, and isolation trenches are formed in the substrate 100 between every two adjacent semiconductor stack structures 200 for forming a shallow trench isolation (STI) structure 101. The STI structure 101 is used to electrically isolate adjacent GAA-FETs, as Figure 3 shown.Figures 1 to 3 Only one semiconductor stack structure 200 is shown.

[0071] In some embodiments, as Figures 1 to 3 shown, after the preparation step of the STI structure 101 is completed, it is also necessary to form a protective layer 203 covering the semiconductor stack structure 200 and the STI structure 101 on both sides and the top surface of the semiconductor stack structure 200 along the direction parallel to the Figure 1 X1 axis in. The protective layer 203 specifically covers the top surface of the semiconductor stack structure 200 and the side surfaces on both sides along the direction parallel to the Figure 1 X1 axis in, as well as the top surface of the STI structure 101. The protective layer 203 can protect the side surfaces of the semiconductor stack structure 200 from being laterally etched during the etching process of the substrate 100 in subsequent steps.

[0072] The semiconductor stack structure 200 includes alternately stacked first semiconductor layers 201 and second semiconductor layers 202. Among them, the first semiconductor layer 201 contains Ge, and the materials of the first semiconductor layer 201 and the second semiconductor layer 202 are different. In some embodiments, the first semiconductor layer 201 is removed in subsequent steps. The region where the second semiconductor layer 202 is located serves as the channel region of the GAA FET (such as the Figure 14 channel region 220 shown in), for realizing the functions of the semiconductor structure. The gate structure (such as the Figure 14 gate structure 600 shown in) is formed around each channel region 220 in subsequent steps. Those skilled in the art should understand that this application is not limited to this. In different application scenarios, the second semiconductor layer 202 can also realize other functions. The second semiconductor layer 202 and the first semiconductor layer 201 can be formed on the substrate surface by epitaxial growth.

[0073] Exemplarily, the material of the first semiconductor layer 201 can be Si x Ge y , where 0.05 ≤ y ≤ 0.3, and x + y = 1; the material of the second semiconductor layer 202 can be one of Si, SiN, SiO, SiON, SiCON.

[0074] The substrate 100 includes a single-crystalline semiconductor layer on at least its surface portion. The material of the single-crystalline semiconductor layer includes, but is not limited to: Si, Ge, SiGe, GaAs, InSb, GaP, GaN, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP, etc. In some embodiments, the substrate 100 can be made of crystalline Si. There can also be other layers between the substrate 100 and the semiconductor stack structure 200. The material of the substrate 100 can be the same as or different from that of the first semiconductor layer 201 or the second semiconductor layer 202. When the material of the substrate 100 is different from that of the first semiconductor layer 201 or the second semiconductor layer 202, there can also be a buffer layer between the substrate 100 and the semiconductor stack structure 200, and the buffer layer can be used to gradually change the lattice constant from the lattice constant of the substrate 100 to the lattice constant of the first semiconductor layer 201 or the second semiconductor layer 202.

[0075] Please refer to Figure 4 , and in combination with Figures 1 to 3 , the etching method of the semiconductor stack structure provided by the embodiment of the present invention includes:

[0076] S200. Selectively etch the sidewalls of the first semiconductor layer 201 in the semiconductor stack structure 200 using a first process gas, so that the first semiconductor layer 201 is recessed relative to the second semiconductor layer 202 in the second direction.

[0077] Wherein, the above-mentioned second direction is perpendicular to the first direction. The first direction is the stacking direction of the first semiconductor layer 201 and the second semiconductor layer 202, for example, the vertical direction in Figures 1 to 3 , that is, the direction parallel to the Z-axis. The second direction is, for example, the direction parallel to the X2 axis in Figure 2 and Figure 3 . This second direction is, for example, perpendicular to the arrangement direction of the plurality of semiconductor stack structures 200 (that is, the direction parallel to the X1 axis in Figure 1 in Figure 1 and Figure 3 ), and is perpendicular to the Z-axis.

[0078] Before performing step S200, the width of the first semiconductor layer 201 in the second direction is equal to the width of the second semiconductor layer 202 in the second direction; after completing step S200, as shown in Figure 2 and Figure 3As shown, the sidewalls of the first semiconductor layer 201 are recessed relative to the second semiconductor layer 202 in the second direction. That is, step S200 is used to selectively etch the sidewalls of the first semiconductor layer 201 in the second direction on both sides of the semiconductor stack structure 200 along the second direction, so as to form a recessed space 206 between every two adjacent second semiconductor layers 202. This recessed space 206 is used to fill and form an isolation layer in subsequent steps. The depth of the recessed space 206 recessed in the second direction is about 3 nm to 10 nm, more preferably about 5 nm.

[0079] In step S200, the first process gas includes a first etching gas, and the first etching gas includes a first fluorine-containing gas and a second fluorine-containing gas. The first fluorine-containing gas is used to increase the etching selectivity of the first semiconductor layer 201 relative to the second semiconductor layer 202, and the second fluorine-containing gas is used to increase the etching rate of the first semiconductor layer 201, so as to control the profile of the recessed space 206. Specifically, the etching selectivity of the first fluorine-containing gas for the first semiconductor layer 201 relative to the second semiconductor layer 202 is higher than that of the second fluorine-containing gas for the first semiconductor layer 201 relative to the second semiconductor layer 202; moreover, the etching rate of the second fluorine-containing gas for the first semiconductor layer 201 is higher than that of the first fluorine-containing gas for the first semiconductor layer 202.

[0080] In addition, the above-mentioned first fluorine-containing gas is also used to increase the etching selectivity of the first semiconductor layer 201 relative to the protective layer 203. In some embodiments, the protective layer 203 may include a silicon nitride-based material formed by CVD (including LPCVD and PECVD), PVD, ALD or other suitable processes, such as silicon nitride, SiON, SiOCN or SiCN and their combinations.

[0081] In the embodiments of the present invention, by using the first fluorine-containing gas and the second fluorine-containing gas in combination, not only can the etching selectivity of the first semiconductor layer / second semiconductor layer be improved to achieve selective etching of the sidewalls of the first semiconductor layer, but also the etching rate of the first semiconductor layer can be controlled, so that the etching selectivity of the first semiconductor layer / second semiconductor layer and the etching rate of the first semiconductor layer 201 reach a balance, so that the profile of the recessed space 206 formed after selective etching of the sidewalls of the first semiconductor layer 201 can meet the requirements. In addition, in step S200, by using the second fluorine-containing gas, during the selective etching of the sidewalls of the first semiconductor layer, high-speed etching of the first semiconductor layer can be achieved without using plasma or a catalyst, so the damage to the device is also small.

[0082] Taking the first semiconductor layer 201 as Si x Ge y, taking the second semiconductor layer 202 as Si for example, by using the first fluorine-containing gas (such as F2), which has an etching rate of up to 4000 nm / min for Si x Ge y and an etching rate of only 40 nm / min for Si, with a selectivity as high as 100:1. It can be considered that during the etching of Si x Ge y , Si is basically not etched, so that selective etching of the sidewalls of the first semiconductor layer can be achieved.

[0083] It should be noted that taking the first semiconductor layer 201 as Si x Ge y and the second semiconductor layer 202 as Si for example, currently, in the prior art, only when the proportion of Ge element contained in Si x Ge y is relatively large can a relatively high etching selectivity of Si x Ge y / Si be obtained. However, in this application, by using the first fluorine-containing gas and the second fluorine-containing gas in combination, when etching Si x Ge y (for example, 0.05 ≤ y ≤ 0.3 and x + y = 1) with a relatively small proportion of Ge element, a relatively high etching selectivity of Si x Ge y / Si can also be obtained. Thus, within a relatively wide range where the proportion of Ge element in SiGe is greater than or equal to 5% and less than or equal to 30%, a relatively high etching selectivity of SiGe / Si can be obtained.

[0084] Furthermore, in some embodiments, the second fluorine-containing gas can be of a type with a bond energy less than that of the first fluorine-containing gas, so that the second fluorine-containing gas is more easily dissociated, and thus can react with the first semiconductor layer 201 more quickly, so that the material of the first semiconductor layer in the recess can be etched off better, and the junction between the sidewall of the first semiconductor layer 201 forming the recess space 206 and the surface of the adjacent second semiconductor layer 202 is closer to a right angle.

[0085] In some embodiments, the first fluorine-containing gas is F2 and / or ClF3. In this case, the second fluorine-containing gas can, for example, be a fluorine-containing gas with a bond energy less than that of F2 or ClF3.

[0086] In some embodiments, the second fluorine-containing gas is at least one of XeF2, XeF4, XeF6, KrF2, BrF3.

[0087] In some embodiments, the first process gas may further include a carrier gas. Exemplarily, the carrier gas may be an inert gas, such as Ar and / or He. The percentage of the second fluorine-containing gas in the total flow rate of the carrier gas and the second fluorine-containing gas is greater than or equal to 0.01% and less than 10%. In this way, the percentage within this range can satisfy the following corresponding relationship: the larger the percentage within this range, the larger the etching selectivity of the first semiconductor layer / second semiconductor layer, and the lower the etching rate of the first semiconductor layer 201. Based on this corresponding relationship, by selecting an appropriate percentage within the above range, the magnitude of the etching selectivity of the first semiconductor layer / second semiconductor layer and the etching rate of the first semiconductor layer 201 can be balanced, so that the profile of the recessed space 206 formed after selectively etching the sidewalls of the first semiconductor layer 201 can meet the requirements. For example, the requirement is that the projection shape of the recessed space 206 on the cross-section in the vertical direction (e.g., Figure 2 the cross-section of the recessed space 206 shown) is a square with a specified width.

[0088] As described above, taking the first semiconductor layer as Si x Ge y and the second semiconductor layer as Si as an example, currently, in the prior art, only when the proportion of Ge element in the first semiconductor layer is relatively large can a high etching selectivity of SiGe / Si be obtained. However, in this application, by using the second fluorine-containing gas and the carrier gas in combination and controlling their flow rates and proportions, a high etching selectivity of SiGe / Si can be obtained within a relatively wide range where the proportion of Ge element in SiGe is greater than or equal to 5% and less than or equal to 30%. That is, during the etching of SiGe, Si is hardly etched. In addition, for materials such as SiN, SiO, SiON, and SiCON in this application, a high etching selectivity of Si x Ge y and these materials can be obtained. That is, during the etching of Si x Ge y SiN, SiO, SiON, and SiCON are hardly etched.

[0089] Further, in some embodiments, the percentage of the second fluorine-containing gas in the total flow rate of the carrier gas and the second fluorine-containing gas is between 1% and 5%. By selecting an appropriate percentage within this range, the profile of the recessed space 206 formed after selectively etching the sidewalls of the first semiconductor layer 201 can meet the requirements.

[0090] In some embodiments, the carrier gas includes at least one of He, Ar, and N2.

[0091] In step S200, the first fluorine-containing gas can affect the etching selectivity of the first semiconductor layer / the second semiconductor layer, that is, the greater the flow rate of the first fluorine-containing gas, the higher the etching selectivity of the first semiconductor layer / the second semiconductor layer. The second fluorine-containing gas can affect the profile of the recessed space 206, that is, the greater the flow rate of the second fluorine-containing gas, the closer the profile of the recessed space 206 is to the target profile.

[0092] Further, in some embodiments, during the process of performing step S200, the flow rate ratio of the first fluorine-containing gas to the second fluorine-containing gas is changed. That is to say, this flow rate ratio can be adjusted during the process to more precisely control the etching selectivity of the first semiconductor layer / the second semiconductor layer and the profile of the recessed space 206.

[0093] Specifically, step S200 may include multiple etching sub-steps, and the flow rate ratio of the first fluorine-containing gas to the second fluorine-containing gas is different in two adjacent etching sub-steps; that is, the flow rates of the first fluorine-containing gas and the second fluorine-containing gas are switched multiple times through multiple etching sub-steps, so as to more precisely control the above-mentioned etching selectivity and the profile of the recessed space 206.

[0094] In some embodiments, in step S200, the flow rate of the first fluorine-containing gas is greater than 0 sccm and less than or equal to 1000 sccm.

[0095] The inventors of the present invention also found that in the technical solution of selectively etching the first semiconductor layer 201, the pressure in the process chamber also affects the etching rate and the morphology of the semiconductor stack structure 200 after etching. Increasing the pressure in the process chamber can increase the etching rate, but if the pressure in the process chamber is too high, the morphology of the semiconductor stack structure 200 after etching will deteriorate. In some alternative embodiments of the embodiments of the present invention, the pressure in the process chamber is greater than or equal to 0.1 torr and less than or equal to 10 torr. This can further control the etching rate of the first semiconductor layer 201.

[0096] In some embodiments, in step S200, the temperature range of the wafer carrier device is 0°C - 80°C. This temperature range is relatively low compared to the prior art. By adopting a lower temperature range, the selectivity of etching with the second fluorine-containing gas (such as XeF2 gas) can be significantly improved.

[0097] In some embodiments, in step S200, the etching equipment does not apply a bias voltage to generate plasma. That is, the sidewalls of the first semiconductor layer 201 in the semiconductor stack structure 200 are chemically etched with the first process gas, and no plasma is generated during this process, so no damage will be caused.

[0098] Specifically, please refer to Figure 5 and Figure 6, the process chamber used in performing the above step S200 includes a first process module, which includes a first chamber body 300, a first gas inlet assembly, and a first carrier device 301. Among them, the first carrier device 301 is disposed in the first chamber body 300 for carrying wafers. The first gas inlet assembly includes a first shower head 302 disposed on the top of the first chamber body 300 for uniformly delivering process gas (and / or plasma provided by the first remote plasma source (RPS) 313) into the first chamber body 300. On this basis, the first gas inlet assembly further includes a first gas mixing chamber 303, a first liquid or solid source 304, and a first gas cabinet 305. Among them, the outlet end of the first gas path 309 for delivering carrier gas is communicated with the inlet end of the first gas mixing chamber 303; a third on-off valve 321, a fourth on-off valve 322, and a mass flow controller 323 ( Figure 5 not shown) are provided on the first gas path 309. The inlet end of the second gas path 311 for delivering other gases (such as but not limited to auxiliary gas, purge gas, etc.) is communicated with the first gas cabinet 305, and the outlet end of the second gas path 311 is connected in parallel with the first gas path 309 to be communicated with the inlet end of the first gas mixing chamber 303; the inlet end of the third gas path 310 for delivering the main etching gas (including the first fluorine-containing gas) is communicated with the first gas cabinet 305, and the outlet end of the third gas path 310 is communicated with the inlet end of the gas mixing path 312. The outlet end of the first gas mixing chamber 303 is communicated with the inlet end of the gas mixing path 312 through a connecting gas path 315. The outlet end of the gas mixing path 312 is communicated with the first shower head 302 to introduce the mixed first process gas into the first chamber body 300. It should be noted that Figure 6 not shown Figure 5 the gas mixing path 312, the connecting gas path 315, the third gas path 310, the second gas path 311, and the first gas cabinet 305 in

[0099] In some embodiments, as Figure 6 shown, a fifth gas path 320 is further provided between the outlet end of the first gas mixing chamber 303 and the connecting gas path 315, and a first on-off valve 319, a pressure switch 318, and a mass flow controller 317 are provided on the fifth gas path 320. Figure 5 The fifth gas path 320 and the above components thereon are not shown in

[0100] As Figure 5 and Figure 6As shown, the first gas mixing chamber 303 is connected to the liquid or solid source 304 for generating the second fluorine-containing gas through the fourth gas path 316. A second on-off valve 325 is provided on the fourth gas path 316. In addition, the first gas mixing chamber 303 is also connected to the vacuum pump 307 through a bypass 314. A fifth on-off valve 324 is also provided on the bypass 314. The first chamber body 300 is also provided with an exhaust pipeline and an exhaust valve 306 provided on the exhaust pipeline for controlling the pressure of the first chamber body 300. The outlet end of the exhaust pipeline is used to communicate with the first vacuum pump 307. Pressure sensors 307 and OES (Optical Emission Spectrometer) 308 can also be provided in both the first gas mixing chamber 303 and the first chamber body 300.

[0101] Before performing the above step S200, first open the fifth on-off valve 324 to extract the gas in the first gas mixing chamber 303 through the vacuum pump 307; then, according to the pressure of the first gas mixing chamber 303 detected by the pressure sensor 307, determine whether the current pressure of the first gas mixing chamber 303 is equal to the preset bottom pressure (the pressure required to form a vacuum environment). If not, continue to pump air; if so, close the fifth on-off valve 324, open the first on-off valve 319, and after a preset time period (such as 10 s), close the first on-off valve 319; then, open the second on-off valve 325 to introduce the second fluorine-containing gas into the first gas mixing chamber 303; according to the pressure of the first gas mixing chamber 303 detected by the pressure sensor 307, determine whether the current pressure of the first gas mixing chamber 303 is equal to the first preset pressure (such as 1 Torr). If not, continue to introduce the second fluorine-containing gas; if so, close the second on-off valve 325; thereafter, open the third on-off valve 321 and the fourth on-off valve 322 to introduce the carrier gas into the first gas mixing chamber 303, and control the flow rate of the carrier gas in the first gas path 309 through the mass flow controller 323; according to the pressure of the first gas mixing chamber 303 detected by the pressure sensor 307, determine whether the current pressure of the first gas mixing chamber 303 is equal to the second preset pressure, and the second preset pressure is greater than the first preset pressure. For example, the second preset pressure is 4 Torr. If not, continue to introduce the carrier gas; if so, close the third on-off valve 312 and the fourth on-off valve 314, and start to perform the above step S200.

[0102] By performing the above process before starting the above step S200, it is possible to ensure that the carrier gas and the second fluorine-containing gas are continuously introduced into the first chamber body 300 during the process of performing the above step S200. Moreover, the percentage of the second fluorine-containing gas in the total flow rate of the carrier gas and the second fluorine-containing gas can be controlled by the pressure of the first gas mixing chamber 303 detected by the pressure sensor 307 and the flow rate detected by the mass flow controller 313.

[0103] When starting the above-mentioned step S200, the first on-off valve 319 is opened to connect the fifth gas path 320; at the same time, the second gas path 311, the third gas path 310, the connecting gas path 315 and the gas mixing path 312 are connected. At this time, the mixed gas containing the carrier gas and the second fluorine-containing gas in the first gas mixing chamber 303 sequentially passes through the fifth gas path 320 and the connecting gas path 315 into the gas mixing path 312. In the case of having auxiliary gas, the auxiliary gas is introduced into the first gas mixing chamber 303 through the second gas path 311. When the carrier gas and the auxiliary gas are introduced simultaneously, the carrier gas can be mixed with the auxiliary gas and then introduced into the first gas mixing chamber 303, and then mixed with the second fluorine-containing gas, and then sequentially passes through the fifth gas path 320 and the connecting gas path 315 into the gas mixing path 312. Meanwhile, the first fluorine-containing gas provided by the first gas cabinet 305 is introduced into the gas mixing path 312 through the third gas path 310. The first fluorine-containing gas, the second fluorine-containing gas, the carrier gas and the auxiliary gas are mixed in the gas mixing path 312 and then enter the first chamber body 300 through the first spray cover 302.

[0104] The above-mentioned step S200 is used for pure chemical etching of the side wall of the first semiconductor layer 201 (this process is a dry chemical etching process, and there is no plasma in the first chamber body 300 during the etching process).

[0105] In some embodiments, the first process module further includes a first remote plasma source (RPS) 313, which is used for plasma cleaning of the first chamber body 300 during the process gap to maintain stability during mass production. Specifically, the first remote plasma source (RPS) 313 is arranged above the first spray cover 302, and the channel outlet for transporting process gas and / or plasma in the first remote plasma source (RPS) 313 is communicated with the air inlet of the first spray cover 302, and the air outlet end of the gas mixing path 312 is communicated with the channel inlet for transporting process gas and / or plasma in the first remote plasma source (RPS) 313. During the chamber cleaning process, gases such as H2, O2, and halogens can be ionized by the excitation of the first remote plasma source 313 to generate plasma, and the plasma enters the first chamber body 300 through the first spray cover 302, so as to remove the deposits generated in the process on the remaining parts of the first chamber body 300 except the substrate surface.

[0106] In some embodiments, the first process gas further includes a first auxiliary gas, which is used to adjust the etching selectivity of the first semiconductor layer / second semiconductor layer. Further, in some embodiments, the first auxiliary gas contains at least one of hydrogen element, oxygen element, and nitrogen element. Further, the first auxiliary gas includes, for example, at least one of HF, O2, H2, and N2. The addition of these auxiliary gases can further help improve the etching selectivity of the first semiconductor layer / second semiconductor layer.

[0107] In some embodiments, referring to Figure 7 , the above step S200 may specifically include:

[0108] Pretreatment step S2001, using the above first auxiliary gas to pretreat the sidewalls of the semiconductor stack structure 200;

[0109] Etching step S2002, using a first etching gas to etch the sidewalls of the first semiconductor layer 201;

[0110] Purge step S2003, purging the process chamber;

[0111] Repeat the above pretreatment step S2001, etching step S2002, and purge step S2003 at least once.

[0112] The pretreatment step S2001 is used to pretreat the sidewalls of the semiconductor stack structure 200 to remove by-products on the sidewalls of the semiconductor stack structure 200; in this pretreatment step S2001, the first auxiliary gas is ionized into plasma by the first remote plasma source (RPS) 313 and transported into the first chamber body 300 to etch the by-products on the sidewalls of the semiconductor stack structure 200. The purge step S2003 is used to purge the process chamber and pipelines to further remove by-products.

[0113] Specifically, during the purge step S2003, the purge gas sequentially passes through the second gas path 311, the first gas mixing chamber 303, the connecting gas path 315, and the gas mixing gas path 312 into the channel for transporting process gas and / or plasma in the first remote plasma source (RPS) 313. The first auxiliary gas is ionized into plasma by the first remote plasma source (RPS) 313 and transported into the first chamber body 300.

[0114] In some embodiments, referring to Figure 8 , the above pretreatment step S2001, etching step S2002, and purge step S2003 are cyclically executed at least once. By controlling the number of cycles of the above pretreatment step S2001, etching step S2002, and purge step S2003, the etching profile can be better controlled.

[0115] In some embodiments, continue to refer to Figure 8 , before step S200, the etching method further includes:

[0116] S100, using pure chemical etching to remove the natural oxide layer on the sidewall surface of the semiconductor stack structure 200;

[0117] Specifically, Figure 9The morphology of the native oxide layer 205 on the semiconductor stack structure 200 before being removed is shown. The above pure chemical etching is, for example, a dry chemical etching process.

[0118] In some embodiments, the above step S100 specifically includes:

[0119] Etching the native oxide layer using a second process gas.

[0120] In some embodiments, the second process gas includes a second etching gas containing HF-pyridine.

[0121] In some embodiments, the second process gas further includes a second auxiliary gas. The second auxiliary gas includes at least one of N2, Ar, He, and H2.

[0122] In some embodiments, in the above step S100, the temperature range of the wafer carrier device is 0°C - 80°C.

[0123] In some embodiments, in the above step S100, the pressure in the process chamber is greater than or equal to 10 Torr and less than or equal to 40 Torr.

[0124] In some embodiments, in the above step S100, the etching equipment does not apply a bias voltage that generates plasma. That is, the native oxide layer is etched using the second process gas in a pure chemical etching process, and no plasma is generated during this process, so no damage will be caused.

[0125] As another technical solution, an embodiment of the present invention further provides a manufacturing method of a semiconductor device, as Figure 10 shown, including:

[0126] S301, forming a semiconductor stack structure 200 on a substrate, the semiconductor stack structure 200 including a first semiconductor layer 201 and a second semiconductor layer 202 that are alternately stacked in a first direction (i.e., the direction parallel to Figure 1 the Z-axis in

[0127] Among them, the first semiconductor layer 201 contains Ge, and the materials of the first semiconductor layer 201 and the second semiconductor layer 202 are different.

[0128] In some embodiments, the above step S301 may specifically include: First, using a patterned hard mask layer, etching the first semiconductor layer 201, the second semiconductor layer 202, and the substrate 100 to obtain the semiconductor stack structure 200, and at the same time forming isolation trenches in the substrate 100 on both sides of the semiconductor stack structure 200; then, forming a shallow trench isolation structure 101 in the isolation trenches on both sides of the semiconductor stack structure 200; after that, along the parallel direction of the semiconductor stack structure 200 Figure 1 and Figure 3On both sides and the top surface in the direction of the X1 axis, a protective layer 203 covering the semiconductor stack structure 200 and the substrate 100 is formed.

[0129] S302, use the above etching method provided by the embodiment of the present invention to etch the semiconductor stack structure 200;

[0130] As shown in Figure 2 and Figure 3 shown, the above step S302 is used to selectively etch the sidewalls of the first semiconductor layer 201 in the semiconductor stack structure 200 in the second direction (i.e., parallel to the direction of the X2 axis in Figure 2 ), so that the first semiconductor layer 201 is recessed relative to the second semiconductor layer 202 in the second direction;

[0131] S303, as shown in Figure 11 shown, use the isolation layer 204 to fill the space where the first semiconductor layer 201 is recessed relative to the second semiconductor layer 202, that is, the recessed space 206 shown in Figure 2 and Figure 3 ;

[0132] S304, as shown in Figure 12 shown, form source regions and drain regions 500 on both sides of the semiconductor stack structure 200 along the above second direction;

[0133] S305, as shown in Figure 13 shown, remove the first semiconductor layer 201;

[0134] S306, as shown in Figure 14 shown, form a gate structure 600 around the second semiconductor layer 202.

[0135] In some embodiments, as shown in Figure 14 shown, the second semiconductor layer 202 constitutes the channel region 220 of the GAA FET, and the gate structure 600 includes a gate dielectric layer 602 disposed around the second semiconductor layer 202 and a gate electrode layer 601 disposed around the gate dielectric layer 602.

[0136] As another technical solution, the embodiment of the present invention also provides another semiconductor process equipment. Please refer to Figure 15 , the above step S100 is performed in the second process module shown in Figure 15 . As an example, it includes a second chamber body 400, a second gas inlet assembly, and a second carrier device 401. Among them, the second carrier device 401 is disposed in the second chamber body 400 and is used to carry the wafer.

[0137] The second intake assembly includes a second spray cover 402 disposed on the top of the second chamber body 400, which is used to uniformly deliver process gas and / or plasma provided by the second remote plasma source (RPS) 415 into the second chamber body 400.

[0138] In some embodiments, the above-mentioned second intake assembly includes a first pipeline for directly communicating with the source 403 and / or the steam generator 404. For example, in some specific embodiments, the first pipeline serves as an edge intake pipeline and includes: a seventh gas path 412 and an eighth gas path 413. One end of each of them is connected to the source 403 and the steam generator 404 respectively, and the other ends are both connected to the edge intake port of the second spray cover 402. In some embodiments, the source 403 can also be an HF-pyridine source or other fluorine-based sources. The steam generator 404 is used to provide one of H2O and CH3OH steam.

[0139] In some embodiments, the second intake assembly further includes a second pipeline that communicates with the central intake port of the second spray cover 402. For example, in some specific embodiments, the second pipeline serves as a central intake pipeline and includes: a fifth gas path 410 and a sixth gas path 411. One end of the fifth gas path 410 and the sixth gas path 411 is connected to the second gas cabinet 405, and the other end is connected to the central intake port of the second spray cover 402. In some embodiments, the fifth gas path 410 is used to transport HF gas, while the sixth gas path 411 is used to transport other gases (including auxiliary gases, purge gases, etc.).

[0140] In some embodiments, the second chamber body 400 is further provided with an exhaust pipeline and an exhaust valve 406 disposed on the exhaust pipeline, which is used to control the chamber pressure. The outlet end of the exhaust pipeline is used to communicate with the second vacuum pump 407. In addition, the source 403 is also connected to the second vacuum pump 407 through a second bypass 414.

[0141] In some embodiments, the second process module further includes a second remote plasma source (RPS) 415 for performing plasma cleaning on the second chamber body 400 during a process gap to maintain stability during mass production. Specifically, the second remote plasma source (RPS) 415 is disposed above the second showerhead 402, and the channel outlet of the second remote plasma source (RPS) 415 for delivering process gas and / or plasma communicates with the central gas inlet of the second showerhead 402. The other ends of the fifth gas path 410 and the sixth gas path 411 are connected to the channel inlet of the second remote plasma source (RPS) 415 for delivering process gas and / or plasma. During the chamber cleaning process, gases such as H2, O2, and halogens can be ionized by the excitation of the remote plasma source 415 to generate plasma, and the plasma enters the second chamber body 400 through the second showerhead 402, thereby removing the deposits generated on the other parts of the second chamber body 400 except the substrate surface during the process.

[0142] As another technical solution, as Figure 16 shown, an embodiment of the present invention further provides a semiconductor processing apparatus, which includes a front-end module 70, a load lock chamber 60, a transfer chamber 50, and at least one process module; the process module is used to execute the above-mentioned at least one process flow.

[0143] As Figure 16 shown, in some embodiments, a plurality of process modules are provided. For example, it includes a first process module 10, a second process module 20, a third process module 30, and a fourth process module 40; the second process module 20 and the first process module 10 are respectively used to execute step S100 and step S200 in the above embodiments, and the first process module 10 can also be used to execute, for example, the etching process in the above step 305; the third process module 30 and the fourth process module 40 can be selected according to process requirements. For example, they can be the same process modules as the first process module 10 or the second process module 20 respectively, or other process modules, which are not limited here.

[0144] In the prior art, the natural oxide layer on the sidewall surface of a semiconductor stack structure is generally removed using a wet etching process. After this process is completed, the wafer is placed in an etching chamber for etching. However, during the process of transferring the wafer with the natural oxide layer removed to the etching chamber, due to the long transfer time, a new natural oxide layer often re-forms on the surface of the semiconductor stack structure, thereby affecting the performance of subsequent devices. To solve this problem, the embodiment of the present invention uses the second process module 20 to perform the above step S100. That is, in the second process module 20, pure chemical etching is used to remove the natural oxide layer on the sidewall surface of the semiconductor stack structure 200. In this way, the wafer with the natural oxide layer removed in the second process module 20 can be transferred by a vacuum manipulator (not shown in the figure) in the transfer chamber 50 to the first process module 10 to perform step S200. This process is carried out in a vacuum environment, thereby avoiding the wafer with the natural oxide layer removed from being exposed to the atmospheric environment. At the same time, the transfer path and transfer time can be shortened, thereby improving the process efficiency.

[0145] The semiconductor process equipment provided by the embodiment of the present invention can integrate different process modules in the same equipment. The first process module 10, the second process module 20, the third process module 30, and the fourth process module 40 are respectively coupled to the transfer chamber 50, and can transfer the wafer in one process module to another process module through the vacuum manipulator in the transfer chamber 50. During the transfer process between two process modules, since the wafer only passes through the transfer chamber in a vacuum state and does not need to perform the conversion between the vacuum and atmospheric environments, the working efficiency and process consistency are greatly improved.

[0146] In some specific embodiments, the transfer chamber 50 has a hexagonal structure. Two load lock chambers 60 are located at two adjacent sides of the transfer chamber 50. The first process module 10 and the third process module 30 are respectively arranged opposite to the two load lock chambers 60, and the first process module 10 is located between the second process module 20 and the third process module 30.

[0147] In some specific embodiments, the first process module 10 can be, for example, Figure 5 the structure shown. In some other specific embodiments, the second process module 20 can be, for example, Figure 15 the structure shown.

[0148] The first process module 10 further includes a first controller. The first controller includes at least one processor and at least one memory. A computer program is stored in the memory. When the computer program is executed by the processor, the step S200 in the above etching method of the semiconductor stack structure is implemented.

[0149] The second process module 20 further includes a second controller, which includes at least one processor and at least one memory. A computer program is stored in the memory, and when the computer program is executed by the processor, the steps S100 in the manufacturing method of the semiconductor device described above are implemented.

[0150] Exemplarily, both the first controller and the second controller can be a host computer or a slave computer.

[0151] By using the semiconductor process equipment integrating multiple process modules in the above embodiments, the manufacturing efficiency of the device can be greatly improved.

[0152] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. An etching method for a semiconductor stacked structure, characterized in that, The semiconductor stack structure includes a first semiconductor layer and a second semiconductor layer alternately stacked in a first direction. The first semiconductor layer contains Ge, and the materials of the first semiconductor layer and the second semiconductor layer are different. The method includes: Selectively etching the sidewalls of the first semiconductor layer in the semiconductor stack structure with a first process gas, so that the sidewalls of the first semiconductor layer are recessed relative to the second semiconductor layer in a second direction perpendicular to the first direction; Wherein, the first process gas includes a first etching gas, and the first etching gas includes a first fluorine-containing gas and a second fluorine-containing gas; The etching selectivity ratio of the first fluorine-containing gas for the first semiconductor layer relative to the second semiconductor layer is higher than that of the second fluorine-containing gas for the first semiconductor layer relative to the second semiconductor layer; and, The etching rate of the second fluorine-containing gas for the first semiconductor layer is higher than that of the first fluorine-containing gas for the first semiconductor layer.

2. The etching method according to claim 1, wherein The first semiconductor layer is Si x Ge y , where 0.05 ≤ y ≤ 0.3, and x + y = 1; and / or The second semiconductor layer is one of Si, SiN, SiO, SiON, SiCON.

3. The etching method according to claim 1, wherein The first fluorine-containing gas includes F2 and / or ClF3, and the second fluorine-containing gas includes a fluorine-containing gas with a bond energy less than that of F2 or ClF3.

4. The etching method according to claim 3, wherein The second fluorine-containing gas includes at least one of XeF2, XeF4, XeF 6、 2, KrF2, and BrF3.

5. The etching method according to claim 1, characterized in that, The first etching process includes a plurality of etching sub-steps, and the flow rate ratio of the first fluorine-containing gas to the second fluorine-containing gas is different in two adjacent etching sub-steps.

6. The etching method according to claim 1, wherein The first process gas further includes a first auxiliary gas, and the first auxiliary gas contains at least one of hydrogen element, oxygen element, and nitrogen element.

7. The etching method according to claim 6, wherein The first auxiliary gas includes at least one of HF, O2, H2, N2.

8. The etching method according to claim 1, wherein The selective etching is pure chemical etching.

9. The etching method according to claim 6, wherein Selectively etching the sidewalls of the first semiconductor layer in the semiconductor stack structure with a first process gas includes: A pretreatment step of pretreating the sidewalls of the semiconductor stack structure with the first auxiliary gas; An etching step of etching the sidewalls of the first semiconductor layer with the first etching gas; A purging step of purging the process chamber; Repeating the pretreatment step, the etching step, and the purging step at least once.

10. The etching method according to claim 1, wherein In the step of selectively etching the sidewalls of the first semiconductor layer in the semiconductor stack structure with a first process gas, The temperature range of the wafer carrier device is 0°C - 80°C; and / or, The flow rate of the first fluorine-containing gas is greater than 0 sccm and less than or equal to 1000 sccm; and / or, The pressure of the process chamber is greater than or equal to 0.1 Torr and less than or equal to 10 Torr.

11. The etching method according to claim 1, wherein It further includes: Performing plasma cleaning on the process chamber before or after performing the selective etching.

12. The etching method according to any one of claims 1-11, characterized in that, Before selectively etching the sidewalls of the first semiconductor layer in the semiconductor stack structure with a first process gas, it further includes: Removing the native oxide layer on the sidewall surface of the semiconductor stack structure by pure chemical etching.

13. The etching method according to claim 12, wherein The removing the native oxide layer on the sidewall surface of the semiconductor stack structure by pure chemical etching includes: Etch the natural oxide layer using a second process gas, where the second process gas includes a second etch gas containing HF-pyridine.

14. The etching method according to claim 13, wherein The second process gas further includes a second assist gas, where the second assist gas includes at least one of N2, Ar, He, and H2.

15. The etching method according to claim 12, characterized in that In the step of removing the natural oxide layer on the sidewall surface of the semiconductor stack structure: The temperature range of the wafer carrier device is 0°C - 80°C; and / or, The pressure in the process chamber is greater than or equal to 10 Torr and less than or equal to 40 Torr.

16. A method for manufacturing a semiconductor device, characterized in that, Includes: Form a semiconductor stack structure on a substrate, where the semiconductor stack structure includes a first semiconductor layer and a second semiconductor layer alternately stacked in a first direction, the first semiconductor layer contains Ge, and the materials of the first semiconductor layer and the second semiconductor layer are different; Etch the semiconductor stack structure using the etching method according to any one of claims 1-15; Fill the space where the first semiconductor layer is recessed relative to the second semiconductor layer with an isolation layer; Form source regions and drain regions on both sides of the semiconductor stack structure along the second direction; Remove the first semiconductor layer; Form a gate structure around the second semiconductor layer.

17. The manufacturing method according to claim 16, characterized in that, The process gas used in the step of removing the first semiconductor layer includes the first fluorine-containing gas and the second fluorine-containing gas.

18. A semiconductor process equipment, characterized in that, Includes: A front-end module, a load lock chamber, a transfer chamber, and at least one first process module, where the first process module is connected to the transfer chamber, the first process module is used to selectively etch the first semiconductor layer, and it includes a first controller, the first controller includes a processor and a memory, and the memory stores a computer program, and when the computer program is executed by the processor, it implements the etching method according to any one of claims 1-11.

19. The semiconductor processing equipment according to claim 18, wherein, Further includes: At least one second process module, where the second process module is connected to the transfer chamber, the second process module includes a second controller, the second controller includes a processor and a memory, and the memory stores a computer program, and when the computer program is executed by the processor, it implements the etching method according to any one of claims 12-15.

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