Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof, and the method for manufacturing the semiconductor element mainly comprises the steps: firstly defining a cutting channel on the front surface of a wafer, then forming an intermetallic dielectric layer on the wafer, forming a staggered stacking structure on the intermetallic dielectric layer, removing the staggered stacking structure to form a groove, and finally forming a semiconductor element on the groove. And forming a protective layer extending from the staggered stacked structure to the groove, and cutting the protective layer and the wafer by a cutting process along the cutting channel.

Description

Technical Field

[0001] The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming a dielectric layer and / or a protective layer on sidewalls and a top surface of an interleaved stack structure before dicing a wafer. Background Art

[0002] With the development of technology, technologies such as Augmented Reality (AR) and Virtual Reality (VR) have gradually matured. In the foreseeable future, technologies such as augmented reality and virtual reality will be widely applied to human life, such as in the fields of education, logistics, medical care, and military.

[0003] Currently, augmented reality and virtual reality are mainly implemented by a head-mounted display device. Among them, the current head-mounted display device usually connects a display driver integrated circuit (DDIC) including high-voltage components, medium-voltage components, and / or low-voltage components to a display module via very long wires or metal interconnections. Usually, the product presented by this design is relatively large in size, not only occupying space but also increasing the difficulty of wearing. Therefore, how to provide a display that can be used in an AR or VR environment by improving the current manufacturing process is an important issue at present. Summary of the Invention

[0004] An embodiment of the present invention discloses a method for fabricating a semiconductor device. First, a dicing lane is defined on a front surface of a wafer, then an intermetal dielectric layer is formed on the wafer, an interleaved stack structure is formed on the intermetal dielectric layer, the interleaved stack structure is removed to form a groove, a protective layer is formed extending from the interleaved stack structure to the groove, and then a dicing process is performed along the dicing lane to dice the protective layer and the wafer.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a chip obtained after a dicing process. The chip includes an interleaved stack structure disposed on a substrate and a dielectric layer disposed on a top surface and sidewalls of the interleaved stack structure. Brief Description of the Drawings

[0006] Figures 1 to 5 Schematic diagram of a method for fabricating a microdisplay according to an embodiment of the present invention;

[0007] Figure 6 Top view of a lower wafer after pad fabrication according to an embodiment of the present invention;

[0008] Figure 7Schematic cross-sectional view of the lower wafer after the formation of bonding pads in an embodiment of the present invention;

[0009] Figure 8 Flowchart when the upper wafer is being diced;

[0010] Figures 9 to 11 Schematic cross-sectional view of dicing the upper wafer in an embodiment of the present invention;

[0011] Figures 12 to 13 Schematic cross-sectional view of dicing the upper wafer in an embodiment of the present invention.

[0012] Symbol description

[0013] 12: Wafer

[0014] 14: Wafer

[0015] 16: Substrate

[0016] 18: First region

[0017] 20: Second region

[0018] 22: Third region

[0019] 24: Intermetal dielectric

[0020] 26: Metal interconnect

[0021] 28: Bonding pad

[0022] 30: Bonding pad

[0023] 32: Bonding pad

[0024] 34: Chip

[0025] 36: Microdisplay

[0026] 38: Display pixel

[0027] 40: Conductor

[0028] 52: Die area

[0029] 62: Circuit area

[0030] 64: Bonding area

[0031] 66: Bonding pad area

[0032] 70: Sub-bonding area

[0033] 72: Bonding pad

[0034] 74: Bonding pad

[0035] 76: Stop layer

[0036] 78: Intermetal dielectric layer

[0037] 80: Stop layer

[0038] 82: Intermetal dielectric layer

[0039] 84: Stop layer

[0040] 86: Intermetal dielectric layer

[0041] 88: Stop layer

[0042] 92: Lower half

[0043] 94: Upper half

[0044] 96: Lower half

[0045] 98: Upper half

[0046] 100: Bond pad

[0047] 102: Lower half

[0048] 104: Upper half

[0049] 106: Metal wiring

[0050] 112: Interleaved stacked structure

[0051] 114: Ultra-low dielectric constant dielectric layer

[0052] 116: Barrier layer

[0053] 118: Groove

[0054] 120: Dielectric layer

[0055] 122: Protective layer

[0056] 128: Saw cut

[0057] 130: First part

[0058] 132: Second part

[0059] 134: Air hole

[0060] 140: Lamination manufacturing process

[0061] 142: Stealth laser cutting manufacturing process

[0062] 144: Grinding manufacturing process

[0063] 146: Expansion manufacturing process Detailed implementation manners

[0064] Although specific configurations and arrangements are discussed herein, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the disclosure herein. It will be apparent to those skilled in the relevant art that the disclosure herein can also be used in a variety of other applications.

[0065] Note that references in the specification to "an embodiment", "embodiments", "exemplary embodiments", "some embodiments", etc. indicate that the described embodiments may include particular features, structures, or characteristics, but each embodiment may not necessarily include the particular features, structures, or characteristics. Moreover, such language does not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, implementation of such feature, structure, or characteristic in connection with other embodiments is within the knowledge of those skilled in the relevant art, whether or not explicitly described.

[0066] Generally, terms can be understood, at least in part, based on their usage in context. For example, as used herein, the term "one or more" (at least in part depending on the context) can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe a plural combination of features, structures, or characteristics. Similarly, terms such as "a", "an", or "the" can again be understood to convey a singular usage or a plural usage, at least in part depending on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors and can instead allow for the existence of additional factors that may not be explicitly described, and at least in part depending on the context.

[0067] It should be readily understood that the meanings of "above", "upon", and "over" in the disclosure herein should be construed in the broadest manner such that "above" means not only "directly" on something but also includes the meaning of on something with intervening features or layers therebetween, and "upon" or "over" means not only the meaning of above or over something but also can include the meaning of without intervening features or layers (i.e., directly on something).

[0068] In addition, for ease of description, as represented in the figures, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used to describe the relationship of one element or feature to another element or feature (one or more). Except for the directions depicted in the figures, spatial relative terms are intended to encompass different orientations of the element in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein can be interpreted accordingly.

[0069] As used herein, the term "substrate" refers to a material on which a layer of material is subsequently deposited. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0070] As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. A layer may extend over the entire underlying or overlying structure, or may have an extent less than the extent of the underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (where contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0071] Please refer to Figures 1 to 5 , Figures 1 to 5 a schematic diagram of a method for fabricating a microdisplay according to an embodiment of the present invention. As Figure 1 shown, first, wafers 12 and 14 made of semiconductor materials are provided. Preferably, medium-voltage elements, high-voltage elements, and pixel circuits, etc. are provided on wafer 12, and low-voltage elements of a low-voltage drive circuit and / or a graphics processing unit (GPU) are provided on wafer 14. More specifically, each of wafers 12 and 14 includes a substrate 16 made of a semiconductor material, and each substrate 16 may be selected from semiconductor substrates such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, etc., or even a substrate made of silicon-on-insulator (SOI). These material selections are all within the scope covered by the present invention.

[0072] It should be noted that since the wafer 12 is preferably used to carry or connect the cut parts of the low-voltage components and the display module of the wafer 14 in subsequent manufacturing processes, a plurality of die areas 52 can be defined on the wafer 12 in advance to be cut after being bonded to other chips. The area or size of each die area 52 is preferably much larger than the chips to be bonded subsequently. And preferably three areas are defined on each die area 52, including a first area 18, a second area 20, and a third area 22. The first area 18 includes a bonding area for subsequently connecting to an external circuit. The second area 20 includes a chip-to-wafer area for subsequently bonding the cut wafer 14 into a plurality of dies or chips. And the third area 22 is a micro-display area for connecting to a micro-display module.

[0073] In addition, on each of the wafers 12 and 14 in this embodiment, active (active) components such as metal oxide semiconductor (MOS) transistors, oxide semiconductor field effect transistors (OS FETs), fin structure transistors (FinFETs), or other active components and / or other passive (passive) components can be included according to the manufacturing process or product selection. Taking the manufacture of metal oxide semiconductor transistors as an example, it may include a gate structure disposed on the substrate 16, spacer walls (not shown in the figure) disposed on the sidewalls of the gate structure, source / drain regions disposed in the substrate on both sides of the spacer walls, an interlayer dielectric layer or an intermetal dielectric layer 24 disposed on each metal oxide semiconductor transistor, and metal interconnects 26 disposed in the interlayer dielectric layer or the intermetal dielectric layer 24 and connecting each metal oxide semiconductor transistor. In this embodiment, the components on the wafer 12 are preferably manufactured using a 65-80 nanometer technology node, while the components on the wafer 14 are preferably manufactured using a 28-40 nanometer technology node.

[0074] In addition, before bonding other cut chips to the wafer 12 at this stage or in the future, a plurality of pads 28, 30, 32 are preferably provided on the wafer 12 and are electrically connected to the aforementioned active or passive components in the first area 18, the second area 20, and the third area 22. In order to achieve the best connection with subsequent components, the pads 28, 30, 32 in the first area 18, the second area 20, and the third area 22 on the wafer 12 can be selected to be made of the same or different materials as the objects connecting to the pads 28, 30, 32 subsequently, and the pads 28, 30, 32 between the first area 18, the second area 20, and the third area 22 can also be made of the same or different materials.

[0075] For example, in this embodiment, the pads 28 disposed in the first region 18 and the pads 30 in the second region 20 may comprise the same or different materials. The pads 28 in the first region 18 and the pads 32 in the third region 22 may comprise the same or different materials, and the pads 30 in the second region 20 and the pads 32 in the third region 22 may comprise the same or different materials. In this embodiment, since the pads 28 in the first region 18 are subsequently used for external circuit connections, it is preferably made of a material with a lower impedance, such as but not limited to gold. The pads 30 in the second region 20 are preferably made of copper, and the pads 32 in the third region 22 are used to connect the subsequent solder balls or bumps of the micro display module and thus may be made of copper or aluminum. It should be noted that compared with the wafer 12 on which a plurality of pads 28, 30, 32 are provided in each of the first region 18, the second region 20, and the third region 22 at this stage, only the aforementioned active components and the metal interconnections 26 connecting the active components are provided on the wafer 14 at this stage, and there are no pads.

[0076] In addition, the pads 28, 30, 32 in each of the first region 18, the second region 20, and the third region 22 preferably have different line widths (pitches) or spacings. For example, in this embodiment, the line width or spacing between the pads 28 in the first region 18 is preferably greater than the line width or spacing between the pads 30 in the second region 20 and the line width or spacing between the pads 32 in the third region 22. The line width or spacing between the pads 30 in the second region 20 may be equal to or slightly less than the line width or spacing between the pads 32 in the third region 22. In this embodiment, the line width or spacing between the pads 28 in the first region 18 is preferably between 20 - 200 microns, the line width or spacing between the pads 30 in the second region 20 is preferably between 1 - 20 microns, and the line width or spacing between the pads 32 in the third region 22 is preferably between 2 - 20 microns.

[0077] It should also be noted that the line width or spacing between the pads 28, 30, 32 in the above-mentioned regions preferably means that the line width or spacing between each of the pads 28, 30, 32 in each region is less than or greater than the line width or spacing between each of the pads 28, 30, 32 in other regions. That is, the line width or spacing between the pads 28 in the first region 18 being greater than the line width or spacing between the pads 30 in the second region 20 and the line width or spacing between the pads 32 in the third region 22 preferably means that the line width or spacing between each of the pads 28 in the first region 18 is greater than the line width or spacing between each of the pads 30 in the second region 20 and the line width or spacing between each of the pads 32 in the third region 22.

[0078] Then as Figure 2 shown, a thinning process is performed on the wafer 14 to remove a part of the substrate 16 of the wafer 14 to slightly reduce its total thickness, and then a wafer dicing process is performed to divide the wafer 14 into a plurality of dies or chips 34.

[0079] As shown Figure 3 in the figure, the previously cut chip 34 is then flipped and a bonding manufacturing process is performed to bond components such as a low-voltage driving circuit and / or a graphics processor to the uncut wafer 12 provided with medium-voltage components and high-voltage components. In this embodiment, the metal interconnections 26 on the chip 34 and the like are preferably bonded to the pads 30 in the second region 20 on the wafer 12 by a hybrid bonding manufacturing process. Among them, the metal interconnections 26 on the chip 34 are preferably composed of copper, and the pads 30 in the second region 20 are also preferably composed of copper. Therefore, the two are preferably butt-jointed by face-to-face hybrid bonding.

[0080] As shown Figure 4 in the figure, a display module manufacturing process is then performed to form a micro-display 36 on the third region 22 of the wafer 12 and connect the micro-display 36 to the pads 32 on the third region 22. In this embodiment, the micro-display 36 may include display elements such as an organic light emitting diode display (OLED display), a mini light emitting diode display, or a micro light emitting diode display according to the manufacturing process or product requirements, and each micro-display 36 may include display pixels 38 such as red, green, and blue.

[0081] Afterwards, as shown Figure 5 in the figure, a wire 40 connecting to an external circuit is formed and the wire 40 is connected to the pad 28 provided on the first region 18 of the wafer 12. Then, according to the manufacturing process requirements, the wafer 12 is cut into grains or chips of the required size along the grain region 52 defined at the beginning for subsequent packaging. In this embodiment, the wire 40 used to connect to the external circuit is preferably composed of copper, and the pad 28 on the first region 18 is preferably composed of a low-impedance material such as gold. Thus, the manufacturing of a micro-display of the present invention is completed.

[0082] Please refer to Figures 6 to 7 , Figures 6 to 7 which are respectively the top view and the cross-sectional schematic view of the lower wafer after the pad manufacturing in the foregoing embodiments of the present invention. Among them Figure 6 the right half is the overall top view of the lower wafer, and the left half is the top view of the secondary bonding region in the bonding region of the right half. As shown Figure 6As shown, the semiconductor component mainly includes a circuit region 62 disposed on a substrate 16 or a wafer 12, a bonding region 64 surrounding the circuit region 62, and a pad region 66 surrounding the bonding region 64. A plurality of pads 28 are provided on the right half of the pad region 66. The bonding region 64 further includes a plurality of sub-bonding regions 70 in detail, and each sub-bonding region 70 further includes pads 72 and 74 in detail as shown in the left half.

[0083] If compared with the previous manufacturing process diagram, the pad region 66 is preferably the aforementioned first region 18, and the pads 28 are preferably the pads 28 of the first region 18. The bonding region 64 is the second region 20 or the third region 22 on the aforementioned die region 52, and the pads 72 and 74 can be the pads 30 on the second region 20 or the pads 32 on the third region 22.

[0084] Looking in detail, a plurality of sub-bonding regions 70 are preferably evenly distributed on the bonding region 64 and surround the circuit region 62. Each sub-bonding region 70 is approximately rectangular from a top view. Each sub-bonding region 70 further includes a plurality of pads 72 and 74, and the pads 72 and 74 are provided on different layers. The pads 72 and 74 preferably have different shapes from a top view. For example, the pad 72 includes a square from a top view, and the pad 74 includes a hexagon from a top view.

[0085] In this embodiment, the distance a from the edge of the pad 72 to the edge of the pad 74 is preferably between 0 and 6 microns, or more preferably about 0.3 microns. The distance b from the edge of the sub-bonding region 70 to the edge of the pad 28 in the pad region 66 is preferably between 0 and 8 microns, or optimally 4 microns, and the distance c from the edge of the sub-bonding region 70 to the edge of the circuit region 62 is preferably between 0 and 6 microns, or optimally 3 microns.

[0086] From Figure 7 From a cross-sectional view, first, active components such as MOS transistors can be formed on the substrate 16 of the substrate or wafer 12 according to the manufacturing process or product requirements as described above. Then, an interlayer dielectric layer or an intermetallic dielectric layer 24 is formed on each metal oxide semiconductor transistor, and metal interconnects 26 are disposed in the interlayer dielectric layer or the intermetallic dielectric layer 24 and connect each metal oxide semiconductor transistor. In this embodiment, the circuit region 62 is provided with a plurality of dummy pads such as pads 100 and metal traces 106. The bonding region 64 is provided with pads 72 and 74, and the pad region 66 is provided with pads 28. Each of the pads 28, 72, and 74 is preferably disposed on the active components and connected to the metal interconnects 26. The structures of the upper metal interlayer dielectric layer and the like disposed on the metal interconnects 26 and surrounding the pads 28, 72, 74, and 100 may include a stop layer 76, a metal interlayer dielectric layer 78, a stop layer 80, a metal interlayer dielectric layer 82, a stop layer 84, a metal interlayer dielectric layer 86, and a stop layer 88.

[0087] Looking at the details, the metal interconnect 26 preferably extends from the bonding region 64 to the pad region 66 and the metal interconnect 26 preferably connects to the pads 72, 74 respectively provided in the bonding region 64 and the pad 28 provided in the pad region 66 at the same time. Among them, the pad 72 in the bonding region 64 includes a lower half 92 connecting to the metal interconnect 26 and an upper half 94 provided on the lower half 92. The pad 74 includes a lower half 96 connecting to the upper half 94 of the pad 72 and an upper half 98 provided on the lower half 96. The pad 28 provided in the pad region 66 also includes a lower half 102 connecting to the metal interconnect 26 and an upper half 104 provided on the lower half 102.

[0088] Overall, the top surface of the lower half 92 of the pad 72 in the bonding region 64 is preferably flush with the top surface of the intermetal dielectric layer 78 and the top surface of the lower half 102 of the pad 28 in the pad region 66. The top surface of the upper half 94 of the pad 72 in the bonding region 64 is preferably flush with the top surface of the upper half 104 of the pad 28 in the pad region 66. The top surface of the lower half 96 of the pad 74 in the bonding region 64 is preferably flush with the top surface of the intermetal dielectric layer 82. And the top surface of the upper half 98 of the pad 74 in the bonding region 64 is preferably flush with the top surface of the pad 100 in the circuit region 62. The distance a from the left sidewall of the lower half 92 of the pad 72 in the bonding region 64 to the right sidewall of the lower half 96 of the upper pad 74 is as described above Figure 6 Preferably, it is between 0 and 6 microns or more preferably about 0.3 microns. The distance b from the approximate left sidewall of the upper half 94 of the pad 72 in the bonding region 64 to the approximate right sidewall of the upper half 104 of the pad 28 in the pad region 66 is preferably between 0 and 8 microns or optimally 4 microns. And the distance c from the right sidewall of the upper half 98 of the pad 74 in the bonding region 64 to the left sidewall of the pad 100 in the circuit region 62 is preferably between 0 and 6 microns or optimally 3 microns.

[0089] From the material aspect, each of the solder pads 28, 72, 74, 100 may further include in more detail a barrier layer and a metal layer. The barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. In this example, the solder pads 28, 72 that are directly in contact with and connected to the metal interconnection 26 preferably include the same material, such as being composed of aluminum, and the upper layer including the solder pads 74 and 100 are preferably composed of copper. However, it is not limited thereto. According to other embodiments of the present invention, the solder pad 28 may also be composed of gold as described in the foregoing embodiments. Additionally, the inter-metal dielectric layers 78, 82, 86 preferably include silicon oxide or ultra-low dielectric constant dielectric layers, and the stop layers 76, 80, 84, 88 include nitrogen doped carbide (NDC) layers, silicon nitride, or silicon carbon nitride (SiCN), but are not limited thereto.

[0090] Please continue to refer to Figures 8 to 11 , Figures 8 to 11 for the foregoing Figures 1 to 2 manufacturing process schematic diagram of dicing the wafer 14, where Figure 8 is the flow chart for dicing the wafer 14 as described above, and Figures 9 to 11 is the cross-sectional schematic diagram after dicing and separating the wafer 14. Generally speaking, the foregoing Figures 1 to 5 manufacturing process is preferably prepared separately in a wafer fab or an outsourced semiconductor assembly and test (OSAT) foundry. For example, the manufacturing processes such as forming active components and solder pads on the wafer 12 are preferably performed in the wafer fab, and the bonding of the separated wafer 14 to the wafer 12 is preferably performed in the outsourced semiconductor assembly and test foundry.

[0091] As Figures 8 to 9 shown, the present invention in the foregoing Figure 2Before the manufacturing process or after the fabrication of active or passive components on the wafer 14, a staggered stack structure 112 is preferably provided on the multiple inter-metal dielectric layers 24 and metal interconnects 26 of the front-end manufacturing process. The staggered stack structure 112 further includes a plurality of ultra-low dielectric constant dielectric layers 114 and a plurality of metal barrier layers or barrier layers 116 that are stacked alternately. In this embodiment, the ultra-low dielectric constant dielectric layer 114 preferably includes a dielectric material with a dielectric constant of 2.4 to 3.6, which may include a porous dielectric material such as, but not limited to, silicon oxycarbide (SiOC) or silicon oxycarbide hydride (SiOCH). The barrier layer 116 preferably includes a dielectric material with a dielectric constant of 3.8 to 7.5, such as a nitrogen-doped carbide layer (NDC), silicon nitride, or silicon carbonitride (SiCN).

[0092] Then, a plurality of scribe lines 128 required in the dicing manufacturing process can be defined on the wafer 14 first, and then a photolithography and etching manufacturing process is performed to remove part of the staggered stack structure 112 and divide it into a first part 130 and a second part 132, and at the same time, a groove 118 is formed between the first part 130 and the second part 132 on the front surface of the wafer 14. It should be noted that the width of the groove 118 formed at this stage is preferably greater than the width of the scribe line 128. According to an embodiment of the present invention, the width of the scribe line 128 is preferably less than 50% or less of the width of the groove 118. For example, the width of the groove 118 is preferably between 20 and 80 microns, and the width of the scribe line 128 is preferably less than 10 microns or more preferably between 5 and 10 microns.

[0093] As Figure 10 shown, then a dielectric layer 120 is formed to extend from the top surface of the first part 130 of the patterned staggered stack structure 112 along its sidewalls to the bottom surface of the groove 118 and to the sidewalls and top surface of the second part 132 of the patterned staggered stack structure 112 on the other side, and then a protective layer 122 is formed on the dielectric layer 120. It should be noted that when the dielectric layer 120 extends from the sidewalls of the first part 130 to the sidewalls of the second part 132, it only covers the bottom surface of the groove 118 but does not fill the groove 118. And since the protective layer 122 preferably conformally covers the surface of the dielectric layer 120, the protective layer 122 also does not fill the groove 118 when it extends from the dielectric layer 120 on the sidewalls of the first part 130 to the dielectric layer 120 on the sidewalls of the second part 132. In this embodiment, the dielectric layer 120 and the protective layer 122 preferably include different materials. Among them, the dielectric layer 120 preferably includes silicon oxide, and the protective layer 122 may include silicon nitride, silicon oxide, or other dielectric materials. These variations are all within the scope covered by the present invention.

[0094] After that, as Figure 8 and Figure 11As shown, it is possible to separate the first part 130 and the second part 132 of the interleaved stacked structure 112 along the previously defined dicing lane 128 by using a blade saw or laser dicing such as stealth dicing on the front or back side of the wafer 14 to form dies or chips 34.

[0095] According to an embodiment of the present invention, if dicing is selected to be performed on the back side of the wafer 14, a laminating manufacturing process 140 can be carried out in a cooperating outsourced packaging and testing foundry to form a tape and attach it to the front side of the wafer 14 to prevent the surface of the wafer 14 from being contaminated during subsequent grinding. Then, a dicing manufacturing process or more specifically a stealth dicing manufacturing process 142 can be carried out to cut the substrate 16 part of the wafer 14 starting from the back side of the wafer 14, but the wafer 14 is still not completely separated into multiple chips. Next, a grinding manufacturing process 144 is continued to remove a part of the wafer 14, the tape on the front side of the wafer 14 is removed, and then an expanding manufacturing process 146 is carried out to divide the wafer 14 into multiple dies or chips 34 by using an instrument such as a wafer expander.

[0096] As Figure 11 shown, in this embodiment, after the wafer 14 is divided into multiple chips 34 by using the expanding manufacturing process 146 in the blade saw or stealth dicing method, each chip 34 preferably includes an intermetal dielectric layer 24 disposed on the substrate 16, an interleaved stacked structure 112 disposed on the intermetal dielectric layer 24, a dielectric layer 120 disposed on the top surface and side walls of the interleaved stacked structure 112, and a protective layer 122 disposed on the top surface and side walls of the dielectric layer 120. Looking in detail, since the dielectric layer 120 and the protective layer 122 in the dicing lane 128 are preferably only cut when the substrate 16 is cut along the dicing lane 128 by using the aforementioned dicing manufacturing process, after the wafer 14 is divided into multiple chips 34, the top surface and side walls of each chip 34 are covered with the dielectric layer 120, and the protective layer 122 is disposed on the top surface and side walls of the dielectric layer 120, wherein the thickness of the dielectric layer 120 disposed on the top surface of the chip 34 is preferably equal to the thickness of the dielectric layer 120 on the side walls of the chip 34 and the thickness of the dielectric layer 120 on the top surface of the substrate 16. The protective layer 122 preferably has an inverted U-shaped cross-section, the thickness of the protective layer 122 disposed on the top surface of the dielectric layer 120 is preferably equal to the thickness of the protective layer 122 on the side walls of the dielectric layer 120, and the side walls of the protective layer 122 are preferably flush with the side walls of the dielectric layer 120 and the side walls of the substrate 16.

[0097] Please continue to refer to Figures 12 to 13 , Figures 12 to 13This is a schematic diagram of the manufacturing process for dicing a wafer after forming an interleaved stacked structure in an embodiment of the present invention. As Figure 12 shown, in this embodiment, first, similar to the Figure 9 manufacturing process, before the aforementioned Figure 2 manufacturing process or after fabricating active or passive components on the wafer 14, an interleaved stacked structure 112 is disposed on the multiple inter-metal dielectrics 24 and metal inner connections 26 of the front-end manufacturing process. The interleaved stacked structure 112 further includes multiple ultra-low dielectric constant dielectric layers 114 and multiple metal barrier layers or barrier layers 116 that are interleaved and stacked with each other. Similar to the previous embodiment, the ultra-low dielectric constant dielectric layer 114 preferably includes a dielectric material with a dielectric constant of 2.4 to 3.6, which may include porous dielectric materials such as, but not limited to, silicon oxycarbide (SiOC) or silicon oxycarbide hydride (SiOCH). The barrier layer 116 preferably includes a dielectric material with a dielectric constant of 3.8 to 7.5, such as a nitrogen-doped carbide layer (NDC), silicon nitride, or silicon carbonitride (SiCN).

[0098] Then, multiple scribe lines 128 required in the dicing manufacturing process are defined on the wafer 14. Next, a lithography and etching manufacturing process is performed to remove a part of the interleaved stacked structure 112 and separate it into a first part 130 and a second part 132, and at the same time, a groove 118 is formed between the first part 130 and the second part 132 on the front surface of the wafer 14. Similar to the previous embodiment, the width of the groove 118 formed at this stage is preferably greater than the width of the scribe line 128.

[0099] Next, a dielectric layer 120 is formed to extend from the top surface of the first part 130 of the patterned interleaved stacked structure 112 along its sidewalls to the bottom surface of the groove 118 and to the sidewalls and top surface of the second part 132 of the patterned interleaved stacked structure 112 on the other side. A lithography and etching manufacturing process is performed to remove most of the dielectric layer 120 between the first part 130 and the second part 132 and expose the surface of the substrate 16. Then, a protective layer 122 is formed on the dielectric layer 120. It should be noted that, compared with the dielectric layer 120 in the previous embodiment that continuously extends from the sidewall of the first part 130 to the sidewall of the second part 132, the dielectric layer 120 in this embodiment is only disposed on the top surface and sidewalls of the first part 130 and the second part 132 but not on the surface of the substrate 16 between the two. In addition, when the protective layer 122 formed in this embodiment extends from the first part 130 to the second part 132, it is preferably not filled into the groove 118 but spans the space between the first part 130 and the second part 132 in a suspended manner from the top surface of the first part 130 to the top surface of the second part 132. Therefore, after forming the protective layer 122, a large air hole 134 is preferably formed between the protective layer 122 and the substrate 16.

[0100] After that, asFigure 13 As shown, the first part 130 and the second part 132 of the interleaved stacked structure 112 can be separated along the dicing lane 128 by using a blade saw or laser dicing such as stealth dicing on the front or back side of the wafer 14 to form dies or chips 34. In this embodiment, each chip 34 preferably includes an intermetal dielectric layer 24 disposed on the substrate 16, an interleaved stacked structure 112 disposed on the intermetal dielectric layer 24, a dielectric layer 120 disposed on the top surface and sidewalls of the interleaved stacked structure 112, and a protective layer 122 disposed on the top surface of the dielectric layer 120 but not extending downward to the sidewalls of the dielectric layer 120. In detail, when cutting the substrate 16 along the dicing lane 128 using the aforementioned cutting manufacturing process, it is preferably to cut only the protective layer 122 in the dicing lane 128 without cutting the dielectric layer 120. Therefore, after the wafer 14 is divided into multiple chips 34, the top surface and sidewalls of each chip 34 are covered with the dielectric layer 120, while the protective layer 122 is only disposed on the top surface of the dielectric layer 120. The thickness of the dielectric layer 120 disposed on the top surface of the chip 34 is preferably equal to the thickness of the dielectric layer 120 on the sidewalls of the chip 34. The protective layer 122 preferably has a rectangular cross-section, and the sidewalls of the protective layer 122 are preferably flush with the sidewalls of the dielectric layer 120 and the substrate 16.

[0101] In summary, the present invention mainly removes a part of the interleaved stacked structure on the wafer to form a groove before dicing the wafer, sequentially forms a dielectric layer 120 and a protective layer 122 in the groove but does not fill the groove, and then performs a cutting manufacturing process along the dicing lane to divide the wafer into multiple chips. After cutting, the top surface and sidewalls of the obtained chips are preferably provided with a dielectric layer, and the protective layer can be disposed on the top surface and sidewalls of the dielectric layer or only on the top surface of the dielectric layer according to the aspects in the foregoing embodiments. In this embodiment, the dielectric layer 120 preferably includes silicon oxide, and the protective layer 122 can include silicon nitride, silicon oxide, or other dielectric materials, and the dielectric constants of both are preferably greater than the dielectric constant of the ultra-low dielectric constant dielectric layers 114 on both sides of the dicing lane. Since it is easy to generate debris contamination when separating materials with a lower dielectric constant using an expansion manufacturing process in the later stage during general cutting manufacturing processes, the present invention first disposes the dielectric layer 120 and / or the protective layer 122 with a higher dielectric constant on the top surface and sidewalls of the interleaved stacked structure and does not fill the grooves on both sides of the dicing lane. In this way, when cutting and separating the wafer from the front or back side of the wafer subsequently, the generation and contamination of debris can be significantly reduced and the overall chip quality can be improved.

[0102] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention should fall within the scope covered by the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Comprising: Defining scribe lanes on the front side of the wafer; Forming an intermetal dielectric layer on the wafer; Forming an interleaved stacked structure on the intermetal dielectric layer; Removing the interleaved stacked structure to form a groove; Forming a protective layer extending from the interleaved stacked structure to the groove; And Performing a cutting process along the scribe lanes to cut the protective layer and the wafer.

2. The method according to claim 1, further comprising: Performing a lamination process to form a tape on the front side of the wafer; and Performing the cutting process to separate the wafer into a plurality of chips.

3. The method according to claim 1, further comprising: Forming a dielectric layer extending from the top surface of the interleaved stacked structure to the bottom surface of the groove; and Forming the protective layer on the dielectric layer.

4. The method according to claim 3, further comprising forming the dielectric layer from the top surface of the interleaved stacked structure to the sidewalls of the interleaved stacked structure.

5. The method according to claim 3, wherein the dielectric layer and the protective layer comprise different materials.

6. The method according to claim 1, further comprising: Removing the interleaved stacked structure to form the groove and separating the interleaved stacked structure into a first part and a second part; Forming a dielectric layer on the top surface and sidewalls of the first part and the second part; And Forming the protective layer extending from the first part to the second part.

7. The method according to claim 6, further comprising forming the protective layer from the first part to the second part and forming air holes between the first part and the second part.

8. The method according to claim 1, wherein the interleaved stacked structure comprises a plurality of ultra-low dielectric constant dielectric layers and a plurality of barrier layers interleaved with each other.

9. The method according to claim 1, wherein the width of the groove is greater than the width of the scribe lane.

10. A semiconductor device, characterized in that, Comprising: A chip obtained after a cutting process, the chip comprising: An interleaved stacked structure disposed on a substrate; and A dielectric layer disposed on the top surface and sidewalls of the interleaved stacked structure.

11. The semiconductor device according to claim 10, further comprising: An intermetal dielectric layer disposed on the substrate; and The interleaved stacked structure disposed on the intermetal dielectric layer.

12. The semiconductor device according to claim 10, further comprising a protective layer disposed on the dielectric layer.

13. The semiconductor device according to claim 12, wherein the protective layer is disposed on the sidewalls of the dielectric layer.

14. The semiconductor device according to claim 12, wherein the sidewalls of the protective layer are flush with the sidewalls of the dielectric layer.

15. The semiconductor device according to claim 12, wherein the dielectric layer and the protective layer comprise different materials.

16. The semiconductor device according to claim 10, wherein the interleaved stacked structure comprises a plurality of ultra-low dielectric constant dielectric layers and a plurality of barrier layers interleaved with each other.

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