An embedded multi-chip interconnection bridge and its preparation method and application

Abstract

The present invention provides an embedded multi-chip interconnect bridge (EMIB) and its preparation method and application, belonging to the field of integrated circuit packaging technology. The present invention uses ABF resin material as a substrate of insulating material to replace the traditional EMIB with silicon as insulating material. Using coreless as a carrier board, ABF material is pressed layer by layer, and the copper circuit layer is manufactured using the SAP process. After the split board is symmetrically split, it is pressed together to meet the board thickness, and then cut along the center of the circuit to obtain two completely symmetrical embedded multi-die interconnect bridges with ABF as the medium. The cross-section thereof is a matrix-type pad that can serve as the interface between the EMIB and the chip package. Since ABF resin is used, its dielectric material is consistent with the IC package substrate to be embedded, which can greatly reduce the stress unevenness of the EMIB and the risk of cracking of the silicon bridge. In addition, the EMIB made of ABF has a significant cost advantage because the material cost and processing cost of ABF are much lower than those of silicon-based materials.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to an embedded multi-chip interconnection bridge and a preparation method and application thereof. Background Art

[0002] EMIB (Embedded Multi-die Interconnect Bridge) is an embedded multi-chip interconnect bridge technology. By embedding a small silicon bridge containing high-density interconnect channels within the package substrate, this bridge enables high-bandwidth, low-latency interconnection between two chips. Designed for selective high-density electrical connections, it provides high-speed communication between heterogeneous chips within the same package. More practically, EMIB technology allows for the placement of heterogeneous chips and mixed components within the same package to meet system / product performance requirements. Multiple silicon bridges can be embedded in different locations on the package substrate, significantly increasing design flexibility. It is compatible with different silicon technology nodes and enables large-scale chip splicing. EMIB advanced packaging technology is currently being widely adopted by Intel in FPGAs, discrete GPUs, artificial intelligence (AI), servers, and other data-centric high-performance computing (HPC) market segments.

[0003] When using EMIB, a silicon bridge with ultra-high wiring density must be embedded into the substrate. Specifically, this involves creating a window in the substrate and attaching the silicon bridge to a receiving slot in the substrate using DAF (die attach film). However, conventional EMIB is made of silicon, while the substrate is primarily made of aromatic dibenzaldehyde resin (ABF resin). After embedding, the EMIB is prone to expansion and contraction mismatches with the substrate. Excessive external pressure or temperature fluctuations can lead to uneven stress distribution in the silicon bridge, which can lead to the risk of cracking in the substrate structure. Summary of the Invention

[0004] In view of this, the present invention aims to provide an embedded multi-chip interconnect bridge, its preparation method, and its application. The embedded multi-chip interconnect bridge produced by the present invention uses ABF resin, whose dielectric material is consistent with the IC package substrate into which it is embedded, significantly reducing the risk of uneven stress and silicon bridge cracking in the EMIB.

[0005] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0006] The present invention provides a method for preparing an embedded multi-chip interconnect bridge, comprising the following steps:

[0007] ABF materials are symmetrically pressed on both sides of the carrier plate to obtain a pressed plate;

[0008] Drilling positioning holes at the four corners of the press plate, and then performing double-sided copper deposition to obtain a copper seed layer;

[0009] laminating, exposing and developing the two sides of the copper seed layer in sequence to obtain a dry film graphic board;

[0010] Performing pattern electroplating on both sides of the dry film pattern plate to form electroplated copper circuits, and then sequentially performing film stripping, flash etching, and palladium removal to form a copper circuit layer to obtain a copper circuit board;

[0011] The surfaces of both sides of the copper circuit board are subjected to super-roughening, pressing and shooting in sequence to obtain a board to be split; the pressing is to press ABF resin on the surface after the super-roughening;

[0012] The board to be split is sequentially subjected to symmetrical splitting and whole-board etching to obtain a split board; only one layer of copper foil remains on the board obtained after the symmetrical splitting;

[0013] After pressing ABF resin on both sides of the split board, target shooting, symmetrical molding and nickel-gold deposition are carried out in sequence to obtain the embedded multi-chip interconnection bridge. The symmetrical molding is cut at the center of the copper circuit layer, and the cross-section of the symmetrically molded circuit is a matrix-type pad.

[0014] Preferably, the carrier board is a coreless board, and the thickness of the coreless board is 0.1-1 mm.

[0015] Preferably, the coreless board includes an intermediate dielectric layer and an outer copper foil layer, and the thickness of the outer copper foil layer is 2-18 μm.

[0016] Preferably, the thickness of the symmetrically pressed ABF material is 5-30 μm.

[0017] Preferably, the positioning hole is a through hole or a blind hole.

[0018] Preferably, the copper seed layer has a thickness of 0.5-1 μm.

[0019] Preferably, the thickness, line width and spacing of the copper circuit layer are independently 5-30 μm.

[0020] Preferably, the thickness of the plate obtained after laminating the ABF resin is 0.2-2 mm.

[0021] The present invention also provides an embedded multi-chip interconnection bridge prepared by the preparation method described in the above technical solution.

[0022] The present invention also provides an application of the embedded multi-chip interconnection bridge described in the above technical solution in the field of integrated circuit packaging.

[0023] The present invention provides a method for preparing an embedded multi-chip interconnection bridge, comprising the following steps: symmetrically pressing ABF materials on both sides of a carrier plate to obtain a pressed plate; drilling positioning holes at the four corners of the pressed plate, and then performing double-sided copper deposition to obtain a copper seed layer; sequentially laminating, exposing, and developing on both sides of the copper seed layer to obtain a dry film graphic board; performing pattern electroplating on both sides of the dry film graphic board to form electroplated copper circuits, and then sequentially performing film stripping, flash etching, and palladium removal to form a copper circuit layer to obtain a copper circuit board; and treating the copper circuit board. The two side surfaces of the split board are sequentially subjected to ultra-roughening, pressing and targeting to obtain a board to be split; the pressing is to press ABF resin on the surface after the ultra-roughening; the board to be split is sequentially symmetrically split and whole-board etching to obtain a split board; only one layer of copper foil is retained on the board obtained after the symmetrical splitting; after pressing ABF resin on the two side surfaces of the split board respectively, targeting, symmetrical forming and nickel-gold precipitation are sequentially performed to obtain the embedded multi-chip interconnection bridge, the symmetrical forming is cut with the center of the circuit of the copper circuit layer, and the circuit section of the symmetrical forming is a matrix-type pad.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The present invention uses an ABF resin substrate as an insulating material to replace the traditional embedded multi-die interconnect bridge using silicon as an insulating material. The ABF material is laminated layer by layer to obtain an embedded multi-chip interconnect bridge. The copper circuit layer is manufactured using a SAP process. After the board is symmetrically split, it is laminated to meet the board thickness and then cut along the center of the circuit to obtain two completely symmetrical embedded multi-die interconnect bridges. The cross-section of the circuit forms a matrix-shaped pad that can serve as the interface between the EMIB and the chip package. Because ABF resin is used, its dielectric material is consistent with the IC package substrate to be embedded, which can greatly reduce the EMIB's stress unevenness and the risk of silicon bridge cracking. Furthermore, since the material cost and processing cost of the silicon bridge are much higher than the cost of the ABF material, the EMIB of the present invention has a significant cost advantage and is suitable for mass production with high production efficiency.

[0026] The present invention also provides an embedded multi-chip interconnect bridge (EMIB) produced by the preparation method described in the above technical solution. The EMIB in the related art uses silicon as the insulating material. In this case, the EMIB is essentially a chip with a relatively simple design. The related art embeds the chip into a groove in the substrate and glues the chip and groove together. When temperature or external force causes stress at the junction to increase, the two materials, a silicon chip and a polymer, will inevitably have significant differences in physical properties such as expansion and contraction. Large deformations can lead to cracking risks. The present invention uses ABF resin material as the insulating substrate and presses the ABF material together. The resulting EMIB has the same physical properties as the substrate, without physical differences such as expansion and contraction, thus avoiding the risk of cracking in traditional silicon chips. Furthermore, the EMIB of the present invention is essentially a substrate, offering better anti-collision and toughness properties than silicon chips. Furthermore, the material and processing costs of ABF are much lower than those of silicon-based materials, and the EMIB of the present invention also offers significant cost advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of the structure of the coreless board in the embodiment;

[0028] Figure 2 Schematic diagram of the structure of the press plate in the embodiment;

[0029] Figure 3 It is a structural diagram of single-sided drilling;

[0030] Figure 4 It is a schematic diagram of the structure of single-sided copper deposition;

[0031] Figure 5 This is a schematic diagram of the structure of a single-sided dry film graphic board;

[0032] Figure 6 It is a top view of a single-sided electroplated copper circuit;

[0033] Figure 7 This is a schematic diagram of the cross-sectional structure of a plate obtained by single-sided copper electroplating circuit;

[0034] Figure 8 It is a structural diagram of a single-sided copper circuit board;

[0035] Figure 9 This is a schematic diagram of the structure after single-sided shooting;

[0036] Figure 10 This is a structural diagram of a single-sided split board;

[0037] Figure 11 Schematic diagram of the cross section of a single-sided split board that has been laminated layer by layer five times;

[0038] Figure 12 This is a schematic cross-sectional view of the entire plate after etching;

[0039] Figure 13 Schematic diagram of the structure of the plate after pressing;

[0040] Figure 14 It is a top view when cutting at the center of the line;

[0041] Figure 15 It is a schematic diagram of the cross section after Y' cutting;

[0042] Figure 16 This is the top view after forming;

[0043] Figure 17 A top view of EMIB. DETAILED DESCRIPTION

[0044] The present invention provides a method for preparing an embedded multi-chip interconnect bridge, comprising the following steps:

[0045] ABF materials are symmetrically pressed on both sides of the carrier plate to obtain a pressed plate;

[0046] Drilling positioning holes at the four corners of the press plate, and then performing double-sided copper deposition to obtain a copper seed layer;

[0047] laminating, exposing and developing the two sides of the copper seed layer in sequence to obtain a dry film graphic board;

[0048] Performing pattern electroplating on both sides of the dry film pattern plate to form electroplated copper circuits, and then sequentially performing film stripping, flash etching, and palladium removal to form a copper circuit layer to obtain a copper circuit board;

[0049] The surfaces of both sides of the copper circuit board are subjected to super-roughening, pressing and shooting in sequence to obtain a board to be split; the pressing is to press ABF resin on the surface after the super-roughening;

[0050] The board to be split is sequentially subjected to symmetrical splitting and whole-board etching to obtain a split board; only one layer of copper foil remains on the board obtained after the symmetrical splitting;

[0051] After pressing ABF resin on both sides of the split board, target shooting, symmetrical molding and nickel-gold deposition are carried out in sequence to obtain the embedded multi-chip interconnection bridge. The symmetrical molding is cut at the center of the copper circuit layer, and the cross-section of the symmetrically molded circuit is a matrix-type pad.

[0052] In the present invention, unless otherwise specified, the raw materials used are commercially available products in the art.

[0053] The present invention symmetrically presses ABF materials on both sides of a bearing plate to obtain a pressed plate.

[0054] In the present invention, the carrier board is preferably a coreless board, and the thickness of the coreless board is preferably 0.1-1 mm, specifically 0.14, 0.19 or 0.24 mm.

[0055] In the present invention, the coreless board preferably includes an intermediate dielectric layer and an outer copper foil layer. The thickness of the outer copper foil layer is preferably 2-18 μm, specifically 2, 3, 5, 12, or 18 μm. The thickness of the intermediate dielectric layer is preferably 0.1-0.5 mm, specifically 0.1, 0.15, or 0.2 mm. In a specific embodiment of the present invention, the coreless board preferably has a structure of 3 μm copper foil, 18 μm copper foil, an intermediate dielectric layer, 18 μm copper foil, and 3 μm copper foil.

[0056] In the present invention, the thickness of the symmetrically pressed ABF material is preferably 5-30 μm, specifically 5, 10, 15, 20, 25 or 30 μm.

[0057] The present invention has no particular limitation on the specific method of symmetrically pressing the ABF material, and a method well known to those skilled in the art may be used.

[0058] After obtaining the pressed plate, the present invention drills positioning holes at the four corners of the pressed plate, and then performs double-sided copper deposition to obtain a copper seed layer.

[0059] In the present invention, the positioning hole is preferably a through hole or a blind hole.

[0060] After the positioning holes are drilled, the present invention preferably removes the glue residue in the holes to ensure that the subsequent copper plating process proceeds smoothly.

[0061] In the present invention, the thickness of the copper seed layer is preferably 0.5-1 μm, specifically 0.5, 0.6, 0.8 or 1 μm.

[0062] In the present invention, the double-sided copper plating is preferably carried out in the positioning hole, that is, the copper seed layer is also formed in the positioning hole. If the copper seed layer in the positioning hole needs to be removed, the copper seed layer is preferably etched away through a subsequent step. The subsequent step refers to the dry film being retained in the positioning hole during exposure and development. In this way, copper will not be plated in the hole during graphic electroplating, and the copper seed layer in the graphic electroplating can be removed through flash etching.

[0063] After the copper seed layer is obtained, the present invention sequentially performs film lamination, exposure and development on both sides of the copper seed layer to form a dry film, thereby obtaining a dry film graphic board.

[0064] The present invention has no particular limitation on the specific methods of film lamination, exposure and development, and methods well known to those skilled in the art may be used.

[0065] After obtaining the dry film graphic board, the present invention performs graphic electroplating on both sides of the dry film graphic board to form electroplated copper circuits, and then sequentially performs film stripping, flash etching and palladium removal to form a copper circuit layer to obtain a copper circuit board.

[0066] In the present invention, the thickness, line width and spacing of the copper circuit layer are independently preferably 5~30μm, specifically 5, 10, 15, 20, 25 or 30μm. The copper circuit layer is a multi-turn fine circuit, and the pattern is designed according to the customer, corresponding to the welding points of the two chips connected in the package.

[0067] In the present invention, the function of the film stripping is to remove the dry film and expose the copper seed layer underneath the dry film; the thickness of the flash etching is preferably 0.5 to 1.5 mm to remove the exposed copper seed layer; the function of the palladium removal is to remove the trace palladium element left during copper deposition to obtain the copper circuit layer.

[0068] After obtaining the copper circuit board, the present invention sequentially performs super-roughening, pressing and targeting on both sides of the copper circuit board to obtain a board to be split; the pressing is pressing ABF resin on the super-roughened surface.

[0069] In the present invention, the function of the super-roughening is to increase the bonding strength between the pressed copper surface and the ABF. The super-roughening is preferably micro-etching, and the micro-etching amount is preferably 0.8-1.0 μm.

[0070] In the present invention, the thickness of the ABF resin laminated with the ABF resin is preferably 5 to 30 μm, specifically 5, 10, 15, 20, 25 or 30 μm.

[0071] After the target shooting is completed, the present invention preferably repeats the steps of double-sided copper deposition, dry film formation, pattern electroplating, copper circuit layer formation, super-roughening and lamination to obtain a multilayer circuit board.

[0072] After obtaining the board to be split, the present invention sequentially performs symmetrical splitting and whole-board etching on the board to be split to obtain a split board; only one layer of copper foil is retained on the board obtained after the symmetrical splitting.

[0073] In the present invention, the vertical structure of the board to be split is ABF material / electroplated copper circuit / coreless board / electroplated copper circuit / ABF material. Taking the structure of the coreless board as 3μm copper foil, 18μm copper foil, intermediate dielectric layer, 18μm copper foil and 3μm copper foil as an example, the symmetrical splitting is explained. The symmetrical splitting is split between the two 3μm copper foils / 18μm copper foils of the coreless board to obtain three structures: the first pressed core board (that is, the split board), the middle 18μm copper foil / intermediate dielectric layer / 18μm copper foil and the second pressed core board (also the split board). The middle 18μm copper foil / intermediate dielectric layer / 18μm copper foil is discarded, that is, the symmetrical splitting obtains two split boards, and the vertical structure of the split board is ABF material / electroplated copper circuit / 3μm copper foil.

[0074] In the present invention, the function of the whole-plate etching is to remove the copper foil left after the symmetrical splitting.

[0075] After obtaining the split board, the present invention presses ABF resin on both sides of the split board respectively, and then performs target shooting, symmetrical molding and nickel-gold deposition in sequence to obtain the embedded multi-chip interconnection bridge. The symmetrical molding is cut with the center of the copper circuit layer, and the circuit section of the symmetrical molding is a matrix-type pad.

[0076] In the present invention, the thickness of the plate obtained after laminating the ABF resin is preferably 0.2-2 mm, specifically 0.2, 1, 1.25, 1.5 or 2 mm.

[0077] In the present invention, the target shooting serves as positioning; and the circuit section can serve as the interface between the EMIB and the chip package.

[0078] In the present invention, the symmetrical molding preferably obtains small-particle EMIB, the line width and spacing of the small-particle EMIB are preferably 5 μm, and the size of the structure obtained by the symmetrical molding is preferably 2×2×0.9 mm.

[0079] In the present invention, the immersion nickel gold is preferably performed on the surface of the pad. For the EMIB of the small particles, the immersion nickel gold is preferably performed by barrel plating.

[0080] The present invention also provides an embedded multi-chip interconnection bridge prepared by the preparation method described in the above technical solution.

[0081] The present invention also provides an application of the embedded multi-chip interconnect bridge described in the above technical solution in the field of integrated circuit packaging. The present invention has no particular limitation on the specific manner of the application, and any manner familiar to those skilled in the art can be used.

[0082] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions of the present invention. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0083] Example 1

[0084] The method for preparing an embedded multi-chip interconnect bridge comprises the following steps:

[0085] Step 1: Cutting: Select a coreless board with a thickness of 0.19mm as the carrier board. The structure of the coreless board is 3μm copper foil, 18μm copper foil, 150μm intermediate dielectric layer, 18μm copper foil and 3μm copper foil. See the structure. Figure 1 .

[0086] Step 2: Lamination: On both sides of the coreless board, 5μm thick ABF material is symmetrically laminated to obtain a laminated board. The structure is shown in Figure 2 .

[0087] Step 3: Drilling: Drill positioning holes at the four corners of the laminate and drill through holes in the board. Figure 3 Schematic diagram of the single-sided drilling structure.

[0088] Step 4: Glue removal and copper deposition: Deglue the above board to remove the glue residue in the hole and the glue remaining on the ABF surface; deposit 0.5μm of copper on both sides of the board as the copper seed layer for subsequent copper plating. Figure 4 This is a schematic diagram of the structure of single-sided copper deposition. In fact, copper is deposited on both sides of the board. Since the two sides are symmetrical, only one side is shown as an example.

[0089] Step 5: Make the circuit: directly apply film on the copper seed layer, expose, develop, form a dry film, and obtain a dry film graphic board. Figure 5 This is a schematic diagram of the structure of a single-sided dry film graphic board.

[0090] Step 6: Graphic electroplating: The above board is subjected to graphic electroplating of 5μm to obtain electroplated copper circuits, which are multi-circle rectangular fine circuits. Figure 6 This is a top view of a single-sided electroplated copper circuit. Figure 7 This is a schematic diagram of the cross-sectional structure of the board obtained by single-sided copper electroplating circuit.

[0091] Step 7: Stripping, flash etching, and palladium removal: Stripping the film to remove the dry film and expose the copper layer (copper seed layer) underneath the dry film; flash etching 0.5mm to remove the exposed copper layer; performing palladium removal to remove the trace palladium elements left by the copper deposition to form copper circuits and obtain copper circuit boards (line width and spacing are both 5μm). Figure 8 This is a schematic diagram of the structure of a single-sided copper circuit board.

[0092] Step 8: Super roughening, pressing, and shooting: Super roughening the above plate (micro etching amount 0.8μm), and then press ABF material with a thickness of 5μm on the upper and lower surfaces respectively, and then shooting, Figure 9 This is a schematic diagram of the structure after single-sided shooting.

[0093] Step 9: Repeat steps 4 to 8 (the number of times depends on the design) 4 times to obtain a multi-layer circuit board that has been laminated layer by layer 5 times.

[0094] Step 10: Symmetrically split the above-mentioned board to obtain a split board. The vertical structure of the board to be split is ABF material / electroplated copper circuit / 3μm copper foil / 18μm copper foil / intermediate dielectric layer / 18μm copper foil / 3μm copper foil / electroplated copper circuit / ABF material. The symmetrical splitting is split between two 3μm copper foils / 18μm copper foils to obtain three structures: the first pressed core board (i.e., the split board), the middle 18μm copper foil / intermediate dielectric layer / 18μm copper foil, and the second pressed core board (also the split board). The middle 18μm copper foil / intermediate dielectric layer / 18μm copper foil is discarded, that is, the symmetrical splitting obtains two split boards. The vertical structure of the split board is ABF material / electroplated copper circuit / 3μm copper foil. Figure 10 This is a structural diagram of a single-sided split board. Figure 11 This is a schematic cross-sectional view of a single-sided split board that has been laminated layer by layer five times.

[0095] Step 11: Whole board etching: remove the copper foil (3μm) left after symmetrical splitting, Figure 12 This is a schematic cross-sectional view of the entire plate after etching.

[0096] Step 12: Pressing: Press ABF resin on both sides to obtain the required board thickness. Figure 13 Schematic diagram of the structure of the plate after pressing.

[0097] Step 13: Targeting and Forming: Targeting is used for positioning; cutting along the center of the circuit can produce two completely symmetrical substrates. The circuit cross-section is a matrix-shaped pad, which serves as the interface between the EMIB and the chip package. The completed EMIB is a small-particle EMIB. (The completed EMIB has a line width and spacing of 5μm and a size of 2×2×0.9mm after cutting). Figure 14 This is a top view when cutting at the center of the line. Figure 15 It is a schematic diagram of the cross section after Y' cutting, Figure 15 Connect two chips on the left and right sides respectively, so that EMIB can connect the two chips. Figure 16 This is a top view after molding.

[0098] Step 14: Immersion nickel gold: Use the barrel plating method to perform immersion nickel gold surface treatment on the exposed pad to obtain EMIB. Figure 17 A top view of EMIB.

[0099] The present invention uses an ABF resin substrate as an insulating material to replace the traditional embedded multi-die interconnect bridge using silicon as an insulating material. The ABF material is laminated layer by layer to obtain an embedded multi-chip interconnect bridge. The copper circuit layer is manufactured using the SAP process. After the carrier board is symmetrically split and laminated to meet the board thickness, it is then cut along the center of the circuit to obtain two completely symmetrical embedded multi-die interconnect bridges. The cross-section of the cross-section forms a matrix-shaped pad that can serve as the interface between the EMIB and the chip package. Due to the use of ABF resin, its dielectric material is consistent with the IC package substrate to be embedded, which can greatly reduce the EMIB's stress unevenness and the risk of silicon bridge cracking. Furthermore, since the material cost and processing cost of the silicon bridge of the EMIB made of ABF material are much higher than the cost of the ABF material, the EMIB of the present invention has a significant cost advantage and is suitable for mass production with high production efficiency.

[0100] The above description is merely a preferred embodiment of the present invention and does not constitute any limitation thereto. It should be noted that those skilled in the art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications shall also be considered within the scope of protection of the present invention.

Claims

1. A method for preparing an embedded multi-chip interconnect bridge, characterized in that: The following steps are involved: ABF materials are symmetrically pressed on both sides of a carrier plate to obtain a pressed plate; the carrier plate is a coreless plate, and the structure of the coreless plate is 3μm copper foil, 18μm copper foil, an intermediate dielectric layer, 18μm copper foil and 3μm copper foil; Drilling positioning holes at the four corners of the press plate, and then performing double-sided copper deposition to obtain a copper seed layer; laminating, exposing and developing the two sides of the copper seed layer in sequence to obtain a dry film graphic board; Performing pattern electroplating on both sides of the dry film pattern plate to form electroplated copper circuits, and then sequentially performing film stripping, flash etching, and palladium removal to form a copper circuit layer to obtain a copper circuit board; The surfaces of both sides of the copper circuit board are subjected to super-roughening, pressing and shooting in sequence to obtain a board to be split; the pressing is to press ABF resin on the surface after the super-roughening; The board to be split is sequentially symmetrically split and etched throughout to obtain a split board; after the symmetrical splitting, only one layer of copper foil is retained in the resulting board; the symmetrical splitting is performed by splitting between two 3μm copper foils / 18μm copper foils of the coreless board to obtain three structures: a first laminated core board, a middle 18μm copper foil / intermediate dielectric layer / 18μm copper foil, and a second laminated core board; the split board includes the first laminated core board and the second laminated core board, and the middle 18μm copper foil / intermediate dielectric layer / 18μm copper foil is discarded. The symmetrical splitting obtains two split boards, and the vertical structure of the split board is ABF material / electroplated copper circuit / 3μm copper foil; After pressing ABF resin on both sides of the split board, target shooting, symmetrical molding and nickel-gold deposition are carried out in sequence to obtain the embedded multi-chip interconnection bridge. The symmetrical molding is cut at the center of the copper circuit layer, and the cross-section of the symmetrically molded circuit is a matrix-type pad.

2. The preparation method according to claim 1, characterized in that The thickness of the coreless board is 0.1-1 mm.

3. The preparation method according to claim 1, characterized in that The thickness of the ABF material of the symmetrically pressed ABF material is 5-30 μm.

4. The preparation method according to claim 1, characterized in that The positioning hole is a through hole or a blind hole.

5. The preparation method according to claim 1, characterized in that The thickness of the copper seed layer is 0.5-1 μm.

6. The preparation method according to claim 1, characterized in that The thickness, line width and spacing of the copper circuit layer are independently 5-30 μm.

7. The preparation method according to claim 1, characterized in that The thickness of the plate obtained after laminating the ABF resin is 0.2-2 mm.

8. An embedded multi-chip interconnect bridge, characterized in that: Prepared by the preparation method according to any one of claims 1 to 7.

9. An application of an embedded multi-chip interconnect bridge, characterized in that: The embedded multi-chip interconnect bridge according to claim 8 is applied in the field of integrated circuit packaging.

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