Layer transfer heterogeneous integration method

Abstract

The invention relates to a layer transfer heterogeneous integration method, which relates to the technical field of semiconductor processes, and comprises the following steps: S1, spin-coating PMMA on the surface of a discrete chip to form a protective agent layer; s2, removing a first part of the protective agent layer; s3, spin-coating PI on the surface of the second part to form a protective support layer; s4, spin-coating an adhesive on the front surface of the support slide to form an adhesive layer; s5, bonding the bonding layer and the protective supporting layer; s6, removing the first substrate and the chip self-stop layer; s7, spin-coating a permanent bonding material to form a bonding layer; s8, bonding the bonding layer and the second substrate; and S9, removing the supporting slide glass, the bonding layer, the protection supporting layer and the second part. The thermal stability of the protective support layer is higher than that of the protective agent layer, so that the bonding pressure is more uniformly transmitted to the chip device layer, and the bonding effect of the chip device layer is further improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor process technologies, and particularly to a layer transfer heterogeneous integration method. Background Art

[0002] Semiconductor heterogeneous integration technology (Heterogeneous Integration) is an advanced technology that integrates semiconductor devices with different materials, processes, or functions into the same system. It breaks through the limitations of traditional single materials or processes and realizes higher-performance, smaller-volume, and lower-power-consuming electronic systems by optimizing the combination of the advantages of multiple materials.

[0003] The authorized publication number CN115223876A discloses a batch high-precision layer transfer heterogeneous integration method. By using a temporary bonding process, the screened discrete chips are reconstructed on the support carrier with high precision, and then by using a substrate peeling process, the extremely thin chip device layer is peeled off from the substrate and bonded and transferred to the target substrate. In the related prior art, the protective layer is selected as PMMA, the bonding temperature of its chip device layer is 250°C, and the bonding pressure needs to be transmitted to the chip device layer through the protective layer. The protective layer softens or decomposes at the bonding temperature, on the one hand, which will lead to the failure of the protective layer and reduce the protection effect, and on the other hand, the uniformity of the bonding pressure transmitted to the chip device layer is poor, resulting in a poor bonding effect of the chip device layer. Summary of the Invention

[0004] In order to improve the problem that the protective layer softens or decomposes at the bonding temperature, resulting in poor uniformity of the bonding pressure transmitted to the chip device layer and thus a poor bonding effect of the chip device layer, this application provides a layer transfer heterogeneous integration method.

[0005] The layer transfer heterogeneous integration method provided by this application adopts the following technical solution: A layer transfer heterogeneous integration method includes the following steps: S1 Spin-coat a polymethyl methacrylate (PMMA) material on the surface of the split chip to form a protective layer, and the protective layer can cover the chip device layer of the split chip; S2 Remove the first part of the protective layer on the chip device layer so that the front side of the chip device layer is exposed. The second part of the protective layer is located on the chip self-stop layer of the split chip and does not cover the front side of the chip device layer; S3 Spin-coat a polyimide (PI) material on the surface of the second part to form a protective support layer, and the protective support layer can cover the front side of the chip device layer; S4 Spin-coat an adhesive on the front side of the support wafer to form an adhesive layer; S5 Bond the surface of the adhesive layer to the surface of the protective support layer so that the front side of the chip device layer faces the front side of the support wafer; S6 Remove the first substrate and the chip self-stop layer in the split chip so that the back side of the chip device layer is exposed; S7 Spin-coat a permanent bonding material on the back side of the chip device layer to form a bonding layer; S8 Bond the bonding surface of the bonding layer to the surface of the second substrate; S9 Remove the support wafer, the adhesive layer, the protective support layer, and the second part in sequence so that the chip device layer is exposed.

[0006] By adopting the above technical solutions, during semiconductor heterogeneous integration, the protective support layer and the second part protect the chip device layer during the integration process, avoiding damage to the fine structure of the chip device layer due to mechanical stress or corrosive liquid. When the chip device layer is bonded to the second substrate, since the protective support layer uses a PI material, its thermal stability temperature can reach up to 400 °C at most, which is higher than 100 °C - 300 °C of PMMA. Therefore, at the bonding temperature during the bonding process of the chip device layer and the second substrate, the thermal stability of the protective support layer is higher than that of the protective layer, making the bonding pressure more evenly transmitted to the chip device layer, thereby improving the bonding effect of the chip device layer.

[0007] Preferably, in step S2, a grinding process is used to remove the first part, and the grinding process includes: Rough grinding stage: Use a diamond grinding wheel to grind and remove 2 / 3 - 3 / 4 of the first part; Fine grinding stage: Use a fine-grained alumina grinding wheel or polishing cloth to polish the remaining first part to the front side of the chip device layer to remove the first part.

[0008] By adopting the above technical solutions, in the rough grinding stage, using a diamond grinding wheel to remove 2 / 3 - 3 / 4 of the first part can efficiently remove most of the material, improve the processing efficiency, and at the same time reduce the potential damage risk to the chip device layer. In the fine grinding stage, a fine-grained alumina grinding wheel or polishing cloth is used to perform fine processing on the remaining part to ensure the grinding accuracy and avoid damage to the chip device layer caused by over-grinding, thereby improving the yield and device performance.

[0009] Preferably, during the fine grinding stage of the first part, the grinding depth is monitored by an in-situ laser interferometer or an acoustic emission sensor, and the process is automatically stopped when the device layer signal is detected.

[0010] By adopting the above technical solution, the grinding depth is monitored by an in-situ laser interferometer or an acoustic emission sensor, so that the depth information during the grinding process can be obtained in real time, avoiding damage to the chip device layer caused by over-grinding; when the device layer signal is detected, the process is automatically stopped, ensuring that the grinding accurately stops on the surface of the chip device layer, improving the processing accuracy and protecting the chip device layer from damage.

[0011] Preferably, in step S5, the placement accuracy during the bonding of the bonding layer and the protective support layer is within ±0.5μm - 5μm, the bonding temperature is 100 - 250°C, the pressure is 20MPa - 100MPa, and the time is 20 - 60 minutes.

[0012] By adopting the above technical solution, the placement accuracy is controlled within the range of ±0.5μm - 5μm, significantly improving the bonding accuracy and reducing the risk of device failure caused by alignment deviation; the bonding temperature is set at 100 - 250°C, ensuring that the materials are fully combined in a suitable thermal environment and enhancing the bonding strength; the bonding pressure range is 20MPa - 100MPa, which can avoid damaging the device while ensuring the bonding quality; the bonding time is controlled within 20 - 60 minutes, optimizing the process efficiency and ensuring the reliability and stability of the bonding at the same time.

[0013] Preferably, in step S8, the bonding temperature between the bonding layer and the second substrate is 100°C to 350°C, the bonding time is 1 minute to 2 hours, and the bonding pressure is 200N to 60000N.

[0014] By adopting the above technical solution, the bonding temperature range is 100°C to 350°C, which can adapt to the differences in the thermal expansion coefficients of different materials and avoid bonding failure caused by too high or too low temperature; the bonding time range is 1 minute to 2 hours, providing enough time for sufficient chemical or physical bonding reactions; the bonding pressure range is 200N to 60000N, which can ensure the close contact of the bonding interface, reduce the generation of voids and defects, and thus improve the mechanical strength and electrical performance of the overall structure.

[0015] Preferably, in step S9, the protective support layer is first thinned to 1 - 2μm by mechanical grinding, and then the remaining protective support layer and the second part are removed by oxygen plasma dry etching.

[0016] By adopting the above technical solutions, mechanically grinding and thinning the protective support layer to 1 - 2 μm can effectively reduce the processing time required for subsequent etching, improve the processing efficiency, and at the same time reduce the risk of damaging the chip device layer during the etching process. The introduction of the oxygen plasma dry etching method ensures the precise removal of the remaining protective support layer and the second part.

[0017] Preferably, the oxygen plasma dry etching method includes: rinsing the surface of the protective support layer with deionized water, and then placing the protective support layer and the second part into an inductively coupled plasma (ICP) etching machine for etching.

[0018] By adopting the above technical solutions, rinsing the surface of the protective support layer with deionized water can remove surface impurities, avoid contamination during the etching process, and ensure the etching quality. Placing the protective support layer and the second part into an inductively coupled plasma (ICP) etching machine for etching can achieve high-precision and high-selectivity material removal, ensuring the integrity of the chip device layer.

[0019] Preferably, the etching gas in the inductively coupled plasma (ICP) etching machine uses a mixed gas of O2 / CF4 = 4:1.

[0020] By adopting the above technical solutions, using the mixed gas to etch the protective support layer and the second part can improve the PI etching rate.

[0021] Preferably, the etched chip device layer is immersed in an acetone solution for 5 minutes.

[0022] By adopting the above technical solutions, using the acetone solution to remove the remaining PMMA makes the removal of PMMA more thorough.

[0023] Preferably, the soaked chip device layer is immersed in deionized water and ultrasonically cleaned for 2 minutes to remove etching residues, and then the surface of the chip device layer is dried with nitrogen.

[0024] By adopting the above technical solutions, ultrasonic cleaning can generate a cavitation effect, causing the tiny bubbles in the deionized water to burst during vibration, forming microjets to impact the chip surface, thereby efficiently removing the impurities and contaminants remaining during the etching process; the nitrogen drying step can quickly evaporate the moisture on the chip surface, avoid water stain residues, ensure the cleanliness and dryness of the chip device layer, and provide a good surface state for subsequent processes.

[0025] In summary, the present application includes at least one of the following beneficial technical effects: 1. When the chip device layer is bonded to the second substrate, since the protective support layer uses PI material, its maximum thermal stability temperature can reach 400 °C, which is higher than the 100 °C - 300 °C of PMMA. Therefore, at the bonding temperature during the bonding process between the chip device layer and the second substrate, the thermal stability of the protective support layer is higher than that of the protective agent layer, enabling the bonding pressure to be more evenly transmitted to the chip device layer, thereby improving the bonding effect of the chip device layer; 2. Mechanically grinding and thinning the protective support layer to 1 - 2 μm can effectively reduce the processing time required for subsequent etching, improve processing efficiency, and at the same time reduce the risk of damage to the chip device layer during etching. The introduction of the oxygen plasma dry etching method ensures the precise removal of the remaining protective support layer and the second part; 3. Flushing the surface of the protective support layer with deionized water can remove surface impurities, avoid contamination during etching, and ensure etching quality. Placing the protective support layer and the second part into an inductively coupled plasma (ICP) etching machine for etching can achieve high-precision and high-selectivity material removal, ensuring that the chip device layer remains intact. Description of the Drawings

[0026] Figure 1 is a flowchart of a layer transfer heterogeneous integration method according to an embodiment of the present application.

[0027] Figure 2 is a schematic structural diagram showing the protective agent layer.

[0028] Figure 3 is a schematic structural diagram of removing the first part of the protective agent layer.

[0029] Figure 4 is a schematic structural diagram showing the protective support layer.

[0030] Figure 5 is a schematic structural diagram showing the support carrier and the adhesive layer.

[0031] Figure 6 is a schematic structural diagram of the temporary bonding of the adhesive layer and the support protective layer.

[0032] Figure 7 is a schematic structural diagram of removing the first substrate and the self-stop layer.

[0033] Figure 8 is a schematic structural diagram showing the bonding layer.

[0034] Figure 9 is a schematic structural diagram of the bonding between the chip device layer and the second substrate.

[0035] Figure 10 Schematic structural diagram of removing the support carrier, adhesive layer, protective support layer, and the second part.

[0036] Description of reference numerals: 1. Split chip; 11. First substrate; 12. Self-stop layer; 13. Chip device layer; 2. Protective agent layer; 21. First part; 22. Second part; 3. Protective support layer; 4. Support carrier; 5. Adhesive layer; 6. Bonding layer; 7. Second substrate; 71. Bonding structure. Detailed implementation manners

[0037] The following further describes the present application in conjunction with Figure 1-10 the accompanying drawings.

[0038] An embodiment of the present application discloses a layer transfer heterogeneous integration method.

[0039] Referring to Figure 1 , a layer transfer heterogeneous integration method includes the following steps: Referring to Figure 1 , Figure 2 , S1: Spin-coat a polymethyl methacrylate (PMMA) material on the surface of the split chip 1 to form a protective agent layer 2, and the protective agent layer 2 can cover the chip device layer 13 of the split chip 1.

[0040] The split chip 1 is composed of a plurality of independent individuals formed by etching a single chip structure. The size of each split chip 1 is between 10 μm × 10 μm and 5 cm × 5 cm, and the total thickness of the split chip 1 is between 30 μm and 725 μm. Each split chip 1 includes a first substrate 11 made of GaAs, a self-stop layer 12 made of InGaP, and a chip device layer 13 of GaAs pHEMT. The thickness of the chip device layer 13 is 5 μm. The protective agent is made of a polymethyl methacrylate (PMMA) polymer material, and its thermal stability temperature is 100 °C - 300 °C. The thickness of the protective agent layer 2 is 10 μm, so that the protective agent layer 2 forms a first part 21 that extends beyond the chip device layer 13 and a second part 22 that is in the same position as the chip device layer 13. The thickness of the first part 21 is 5 μm, and the thickness of the second part 22 is 5 μm.

[0041] Referring to Figure 3 , S2: Remove the first part 21 of the protective agent layer 2 on the chip device layer 13, so that the front surface of the chip device layer 13 is exposed. The second part 22 of the protective agent layer 2 is located on the chip self-stop layer 12 of the split chip 1 and does not cover the front surface of the chip device layer 13.

[0042] When removing the first part 21, a grinding process is used to remove the first part 21. The grinding process includes: rough grinding stage: Use a diamond grinding wheel to grind and remove 2 / 3 - 3 / 4 of the first part 21. The particle size of the diamond grinding wheel is 2000#. It can efficiently remove most of the material, improve the processing efficiency, and at the same time reduce the potential damage risk to the chip device layer 13.

[0043] Fine grinding stage: Use a fine-grained alumina grinding disc or polishing cloth to polish the remaining first part 21 to the front surface of the chip device layer 13, removing the first part 21. The grain size of the fine-grained alumina grinding disc is 8000#, and it is polished at a low speed (<100 rpm) and low pressure (<0.5 MPa), gradually approaching the surface of the chip device layer 13. Ensure the grinding accuracy and avoid damaging the chip device layer 13 due to excessive grinding, thereby improving the yield and device performance.

[0044] Monitor the grinding depth through an in-situ laser interferometer or acoustic emission sensor, and automatically stop when the signal of the chip device layer 13 is detected. By monitoring the grinding depth through an in-situ laser interferometer or acoustic emission sensor, the depth information during the grinding process can be obtained in real time, avoiding damaging the chip device layer 13 due to excessive grinding. After the first part 21 is removed by the grinding process, immerse the chip device layer 13 in ionized water and clean it by ultrasonic waves to remove the residual impurities on the chip device layer 13, ensuring the subsequent bonding quality.

[0045] Refer to Figure 4 , S3 Spin-coat a polyimide (PI) material on the surface of the second part 22 to form a protective support layer 3, and the protective support layer 3 can cover the front surface of the chip device layer 13. The protective support layer 3 is made of polyimide (PI) material, its thermal stability temperature is between 200°C and 400°C, and the thickness is 5μm.

[0046] Refer to Figure 5 , S4 Spin-coat an adhesive on the front surface of the support wafer 4 to form an adhesive layer 5. The support wafer 4 is a 4-inch sapphire wafer, and the adhesive is a high-temperature wax (HT10.10), its thickness is 15μm, the spin-coating speed is 1500 revolutions per minute, the spin-coating time is 60s, the pre-baking temperature is 110°C, and the time is 2 minutes.

[0047] Refer to Figure 6 , S5 Align the front surface of the support wafer 4 with the surface of the protective support layer 3, so that the front surface of the chip device layer 13 is opposite to the front surface of the support wafer 4, and then use a Die to Wafer chip bonder to temporarily bond the adhesive layer and the protective support layer 3. The placement accuracy is within ±0.5μm - 5μm, significantly improving the bonding accuracy and reducing the risk of device failure caused by alignment deviation. The bonding temperature is 100 - 250°C, ensuring that the materials are fully combined in a suitable thermal environment and enhancing the bonding strength. The pressure is 20MPa - 100MPa, which can avoid damaging the device while ensuring the bonding quality. The time is 20 - 60 minutes, optimizing the process efficiency and ensuring the reliability and stability of the bonding at the same time.

[0048] Refer to Figure 7, in S6, the first substrate 11 and the chip self-stop layer 12 in the split chip 1 are removed, so that the back surface of the chip device layer 13 is exposed. The first substrate 11 is ground and thinned from the back surface to 80 μm by mechanical grinding, and then the remaining 80 μm of the first substrate 11 is completely removed by etching with a sulfuric acid-based etching solution until the chip self-stop layer 12 is exposed and then the etching stops. When removing the chip self-stop layer 12, the chip self-stop layer 12 is removed by etching with a hydrochloric acid-based etching solution, and the back surface of the chip device layer 13 is exposed.

[0049] Refer to Figure 8 , in S7, a permanent bonding material is spin-coated on the back surface of the chip device layer 13 to form a bonding layer 6. The permanent bonding material in this embodiment includes but is not limited to one of gold-tin and gold-indium. The thickness of the bonding layer 6 is 2 μm, and the spin-coating speed of the permanent bonding material is about 2000 revolutions per minute.

[0050] Refer to Figure 9 , in S8, the bonding surface of the bonding layer 6 is bonded to the surface of the second substrate 7. The bonding surface on the bonding layer 6 on the support carrier 4 is opposed to the bonding structure 71 formed by the convexity on the second substrate 7, and they are placed in a bonding machine for bonding. The bonding temperature is from 100 °C to 350 °C, which can adapt to the differences in the thermal expansion coefficients of different materials and avoid bonding failure caused by too high or too low temperature. The bonding time is from 1 minute to 2 hours, providing sufficient time to achieve a sufficient chemical or physical bonding reaction. The bonding pressure is from 200 N to 60000 N, which can ensure the close contact of the bonding interface, reduce the generation of voids and defects, and thus improve the mechanical strength and electrical performance of the overall structure.

[0051] Refer to Figure 10 , in S9, the support carrier 4, the adhesive layer 5, the protective support layer 3, and the second part 22 are removed in sequence, so that the chip device layer 13 is exposed.

[0052] When the support carrier 4 and the second substrate 7 are placed on a heating table and heated, the heating temperature is 250 °C, and the support carrier 4 and the adhesive layer 5 are separated by the thermal sliding peeling method.

[0053] The adhesive layer 5 is cleaned with a de-bonding agent to remove the adhesive layer 5.

[0054] When removing the protective support layer 3 and the second part 22, first, the protective support layer 3 is ground and thinned to 1 - 2 μm by mechanical grinding, which can effectively reduce the processing time required for subsequent etching, improve the processing efficiency, and at the same time reduce the risk of damage to the chip device layer 13 during the etching process. Then, the remaining protective support layer 3 and the second part 22 are removed by the oxygen plasma dry etching method. The introduction of the oxygen plasma dry etching method ensures the precise removal of the remaining protective support layer 3 and the second part 22.

[0055] Mechanical grinding and thinning is to thin the protective support layer 3 to 1-2 μm through CMP wet polishing. The specific process of CMP wet polishing is as follows: 1. Chemical reaction stage Select a polishing liquid that can chemically react with the surface of the protective support layer 3. The components of the polishing liquid in this embodiment are: Component Concentration range Function KOH or TMAH 0.5–3 wt% Alkaline hydrolysis of the PI surface <![CDATA[H2O2]]> 3–8 wt% Oxidative decomposition of the aromatic structure <![CDATA[SiO2 nanoparticles]]> 1–3 wt% Mechanical grinding NMP 1–3 wt% Swelling of the PI layer to assist penetration PEG-400 0.1–0.5 wt% Disperse abrasives and stabilize the slurry Deionized water Balance Solvent base The chemical substances in the polishing liquid chemically react with the material of the protective support layer 3, converting insoluble substances into soluble substances or softening high-hardness substances.

[0056] 2. Mechanical grinding stage The polishing head presses the protective support layer 3 onto the rotating polishing pad with a certain pressure, and a thin film of grinding liquid is formed between the polishing pad and the surface of the protective support layer 3.

[0057] The abrasive grains in the grinding liquid are evenly distributed under the action of the transmission and centrifugal force of the polishing pad, and mechanically rub against the surface of the protective support layer 3 to remove the easily removable substances generated by the chemical reaction.

[0058] 3. Circulation process The chemical reaction and mechanical grinding are carried out alternately, continuously removing the excess material on the surface of the protective support layer 3 until the required flatness is achieved.

[0059] By utilizing the dissolution and softening effect between the polishing liquid and the protective support layer 3, the global planarization ability of the surface of the protective support layer 3 can be improved, and high-precision and high flatness of the grinding of the protective support layer 3 can be achieved. At the same time, the difference in the removal rate between hard materials and soft materials is minimized to the greatest extent, avoiding problems such as surface damage caused by pure mechanical polishing and slow polishing speed and poor surface flatness caused by chemical polishing, making the material removal rate more uniform.

[0060] The oxygen plasma dry etching method includes: 1. First, rinse the surface of the protective support layer 3 with deionized water, which can remove surface impurities, avoid contamination during the etching process, and ensure the etching quality.

[0061] 2. Then, place the protective support layer 3 and the second part 22 into an inductively coupled plasma (ICP) etching machine for etching. The etching gas in the inductively coupled plasma (ICP) etching machine uses a mixed gas of O2 / CF4 = 4:1. The mixed gas is used to etch the protective support layer 3 and the second part 22 to improve the PI etching rate.

[0062] 3. Then, soak the etched chip device layer in an acetone solution for 5 minutes to remove the residual PMMA with the acetone solution, making the removal of PMMA more thorough.

[0063] 4. Then immerse the soaked chip device layer 13 in deionized water and ultrasonically clean it for 2 minutes to remove the etching residues. Ultrasonic cleaning can generate cavitation effect, causing the tiny bubbles in the deionized water to burst during vibration, forming microjets to impact the chip surface, thereby efficiently removing the impurities and contaminants remaining during the etching process.

[0064] 5. Then use nitrogen to dry the surface of the chip device layer 13. The nitrogen drying step can quickly evaporate the moisture on the chip surface, avoid water stain residues, ensure the cleanliness and dryness of the chip device layer 13, and provide a good surface state for the subsequent process.

[0065] The implementation principle of the layer transfer heterogeneous integration method in the embodiment of this application is as follows: When the chip device layer 13 is bonded to the second substrate 7, since the protective support layer 3 uses PI material and its maximum thermal stability temperature can reach 400 °C, which is higher than 100 °C - 300 °C of PMMA, therefore, at the bonding temperature during the bonding process between the chip device layer 13 and the second substrate 7, the thermal stability of the protective support layer 3 is higher than that of the protective agent layer 2, enabling the bonding pressure to be more evenly transmitted to the chip device layer 13, and further improving the bonding effect of the chip device layer 13.

[0066] The above are all the preferred embodiments of this application. The protection scope of this application is not limited by this. Therefore, all equivalent changes made according to the structure, shape, and principle of this application should be covered within the protection scope of this application.

Claims

1. A layer transfer heterogeneous integration method, characterized in that: It includes the following steps: S1 Spin-coat a polymethyl methacrylate (PMMA) material on the surface of the split chip (1) to form a protective layer (2), and the protective layer (2) can cover the chip device layer (13) of the split chip (1); S2 Remove the first part (21) of the protective layer (2) on the chip device layer (13) so that the front surface of the chip device layer (13) is exposed. The second part (22) of the protective layer (2) is located on the chip self-stop layer (12) of the split chip (1) and does not cover the front surface of the chip device layer (13); S3 Spin-coat a polyimide (PI) material on the surface of the second part (22) to form a protective support layer (3), and the protective support layer (3) can cover the front surface of the chip device layer (13); S4 Spin-coat an adhesive on the front surface of the support carrier (4) to form an adhesive layer (5); S5 Bond the surface of the adhesive layer (5) to the surface of the protective support layer (3) so that the front surface of the chip device layer (13) faces the front surface of the support carrier (4); S6 Remove the first substrate (11) and the chip self-stop layer (12) in the split chip (1) so that the back surface of the chip device layer (13) is exposed; S7 Spin-coat a permanent bonding material on the back surface of the chip device layer (13) to form a bonding layer (6); S8 Bond the bonding surface of the bonding layer (6) to the surface of the second substrate (7); S9 Remove the support carrier (4), the adhesive layer (5), the protective support layer (3), and the second part (22) in sequence so that the chip device layer (13) is exposed.

2. The layer transfer heterogeneous integration method according to claim 1, wherein: In step S2, a grinding process is used to remove the first part (21), and the grinding process includes: Rough grinding stage: Use a diamond grinding wheel to grind and remove 2 / 3 - 3 / 4 of the first part (21); Fine grinding stage: Use a fine-grained alumina grinding wheel or polishing cloth to polish the remaining first part (21) to the front surface of the chip device layer (13) to remove the first part (21).

3. The layer transfer heterogeneous integration method according to claim 2, wherein: In the fine grinding stage of the first part (21), the grinding depth is monitored by an in-situ laser interferometer or an acoustic emission sensor, and the process automatically stops when the device layer signal is detected.

4. The layer transfer heterogeneous integration method according to claim 1, wherein: In step S5, the bonding accuracy when the adhesive layer (5) is bonded to the protective support layer (3) is within ±0.5μm - 5μm, the bonding temperature is 100 - 250°C, the pressure is 20MPa - 100MPa, and the time is 20 - 60 minutes.

5. The layer transfer heterogeneous integration method according to claim 1, wherein: In step S8, the bonding temperature between the bonding layer (6) and the second substrate (7) is 100°C to 350°C, the bonding time is 1 minute to 2 hours, and the bonding pressure is 200N to 60000N.

6. The layer transfer heterogeneous integration method according to claim 1, wherein: In step S9, first mechanically grind and thin the protective support layer (3) to 1 - 2 μm, and then use oxygen plasma dry etching to remove the remaining protective support layer (3) and the second part (22).

7. The layer transfer heterogeneous integration method according to claim 6, wherein: The oxygen plasma dry etching method includes: first, rinsing the surface of the protective support layer (3) with deionized water, and then putting the protective support layer (3) and the second part (22) into an inductively coupled plasma (ICP) etching machine for etching.

8. The layer transfer heterogeneous integration method according to claim 7, wherein: The etching gas in the inductively coupled plasma (ICP) etching machine uses a mixed gas of O2 / CF4 = 4:

1.

9. The layer transfer heterogeneous integration method according to claim 7, wherein: Put the etched chip device layer (13) into an acetone solution and soak it for 5 minutes.

10. The layer transfer heterogeneous integration method according to claim 9, wherein: Immerse the soaked chip device layer (13) in deionized water and ultrasonically clean it for 2 minutes to remove etching residues, and then dry the surface of the chip device layer (13) with nitrogen.

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