Air gap semiconductor structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and discloses an air gap semiconductor structure and a preparation method thereof, and the preparation method comprises the steps: forming a gate structure, a dielectric layer, and a first metal interconnection structure and a second metal interconnection structure located at the two sides of the gate structure on the surface of a substrate layer; the dielectric layer coats the surface of one side, back on to the substrate layer, of the gate structure and the side surface of the gate structure, and coats the side surfaces of the first metal interconnection structure and the second metal interconnection structure; forming a sacrificial layer in the dielectric layer on one side, back to the substrate layer, of the gate structure through a photoetching process; the sacrificial layer is at least located between the first metal interconnection structure and the second metal interconnection structure; forming a cover layer and at least one release hole on the surface of the sacrificial layer; and removing the sacrificial layer through the release hole, and at least forming a cavity at a position corresponding to the gate structure. According to the invention, the parasitic capacitance between the first metal interconnection structure and the second metal interconnection structure can be reduced, the delay and crosstalk of the device are reduced, and the electrical performance, stability and reliability of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to an air-gap semiconductor structure and a preparation method thereof. Background Art

[0002] With the increase in the integration density of integrated circuits, the number of conductor connections is also increasing. The resistance-capacitance delay phenomenon (RC delay) caused by metal connection lines not only affects the speed of the chip but also poses a serious threat to the working reliability. The RC delay not only hinders the frequency growth but also increases the power consumption of the useless work of the circuit. The transmission speed of circuit signals depends on the product of the parasitic resistance and the parasitic capacitance. To solve the problem of RC delay, it is necessary to reduce the parasitic resistance (replacing aluminum interconnects with copper interconnects) and the parasitic capacitance. The parasitic capacitance is proportional to the dielectric constant k of the insulating medium between circuit layers. Therefore, using a low-k material (k < 3) as the insulating medium between different circuit layers can achieve the purpose of reducing the parasitic capacitance. The best low-k is "no material", so the scheme of using an air gap to replace the insulating material dielectric layer can more effectively reduce the parasitic capacitance.

[0003] However, in the prior art, it is difficult to control the size of the air gap formed in the dielectric layer, which is affected by the loading effect, resulting in difficulty in controlling the parasitic capacitance. It may also damage the device structure, leading to low reliability and yield of the device. Summary of the Invention

[0004] In view of this, the present invention provides an air-gap semiconductor structure and a preparation method thereof to solve the problems in the related art that it is difficult to control the size of the air gap formed in the dielectric layer, which is affected by the loading effect, resulting in difficulty in controlling the parasitic capacitance. It may also damage the device structure, leading to low reliability and yield of the device; and the process of forming the air gap also requires additional etching processes and masks, with complex processes and high costs.

[0005] In a first aspect, the present invention provides a preparation method of an air-gap semiconductor structure, and the preparation method includes:

[0006] Providing a base layer;

[0007] Forming a gate structure, a dielectric layer, a first metal interconnect structure and a second metal interconnect structure on one side surface of the base layer; the dielectric layer covers the side surface of the gate structure facing away from the base layer and the side surface of the gate structure, and covers the side surfaces of the first metal interconnect structure and the second metal interconnect structure;

[0008] Forming a sacrificial layer in the dielectric layer on the side of the gate structure facing away from the base layer by a photolithography process; the sacrificial layer is at least located between the first metal interconnect structure and the second metal interconnect structure; there is a part of the dielectric layer between the gate structure and the sacrificial layer;

[0009] A capping layer is formed on the side of the sacrificial layer facing away from the base layer;

[0010] At least one release hole is formed in the capping layer corresponding to the sacrificial layer; the release hole longitudinally penetrates the capping layer and exposes the surface of the sacrificial layer;

[0011] The sacrificial layer is removed through the release hole to form a cavity at least at the position corresponding to the gate structure; the cavity is at least located between the first metal interconnect structure and the second metal interconnect structure.

[0012] The method for preparing the air-gap semiconductor structure provided by the present invention first forms a sacrificial layer in the dielectric layer on the side of the gate structure facing away from the base layer through a photolithography process; the sacrificial layer is at least located between the first metal interconnect structure and the second metal interconnect structure; there is a part of the dielectric layer between the gate structure and the sacrificial layer; secondly, at least one release hole is formed in the capping layer corresponding to the sacrificial layer; finally, the sacrificial layer is removed through the release hole to form a cavity at least at the position corresponding to the gate structure; the cavity is at least located between the first metal interconnect structure and the second metal interconnect structure. On the one hand, forming the sacrificial layer through the photolithography process can better control the width and depth of the sacrificial layer, and then precisely control the size of the cavity, so as to better reduce the parasitic capacitance between the first metal interconnect structure and the second metal interconnect structure, thereby reducing the delay and crosstalk of the gate structure device, avoiding the influence of the load effect, improving the electrical performance, stability and reliability of the device, while improving the process efficiency and yield, and not easily damaging the device structure during the process; on the other hand, there is a part of the dielectric layer between the gate structure and the sacrificial layer, so that there is a part of the dielectric layer between the gate structure and the cavity, which can better protect the gate structure and improve the stability of the gate structure.

[0013] In an optional embodiment, the dielectric layer includes a first dielectric layer and a second dielectric layer; the first metal interconnect structure includes a first metal structure and a first metal via; the second metal interconnect structure includes a second metal structure and a second metal via; the cross-sectional area of the first metal structure is larger than that of the first metal via; the cross-sectional area of the second metal structure is larger than that of the second metal via; the distance between the first metal structure and the second metal structure is less than the distance between the first metal via and the second metal via;

[0014] The steps of forming a gate structure, a dielectric layer, a first metal interconnect structure and a second metal interconnect structure on both sides of the gate structure on one side of the base layer include:

[0015] A gate structure and a first dielectric layer are formed on one side of the base layer; the first dielectric layer covers the surface of the side of the gate structure facing away from the base layer and the side surface of the gate structure;

[0016] A first metal via and a second metal via are formed in the first dielectric layer on both sides of the gate structure; the first metal via and the second metal via longitudinally penetrate the first dielectric layer;

[0017] A second dielectric layer is formed on the side of the first dielectric layer facing away from the base layer;

[0018] A first metal structure and a second metal structure are formed on the surfaces of the first metal via hole and the second metal via hole facing away from the base layer; the first metal structure and the second metal structure longitudinally penetrate the second dielectric layer; the first metal structure is connected to the first metal via hole, and the second metal structure is connected to the second metal via hole;

[0019] The steps of forming the sacrificial layer and the capping layer are after the step of forming the second dielectric layer and before the step of forming the first metal structure and the second metal structure; the sacrificial layer at least longitudinally penetrates the second dielectric layer; the first metal structure and the second metal structure longitudinally penetrate the capping layer, the second dielectric layer and / or the sacrificial layer.

[0020] In the method for preparing the air-gap semiconductor structure provided by the present invention, since the cross-sectional area of the first metal structure is larger than that of the first metal via hole; the cross-sectional area of the second metal structure is larger than that of the second metal via hole; the distance between the first metal structure and the second metal structure is smaller than the distance between the first metal via hole and the second metal via hole; the first metal structure and the second metal structure contribute a large proportion to the parasitic capacitance, and the sacrificial layer at least longitudinally penetrates the second dielectric layer, the formed cavity can at least longitudinally penetrate the second dielectric layer between the first metal structure and the second metal structure, which can effectively reduce the parasitic capacitance between the first metal structure and the second metal structure, and further reduce the parasitic capacitance between the first metal interconnect structure and the second metal interconnect structure, so as to reduce the delay and crosstalk of the gate structure device, avoid the influence of the load effect, and improve the electrical performance, stability and reliability of the device, while improving the process efficiency and yield.

[0021] In an alternative embodiment, the sacrificial layer is located between the first metal interconnect structure and the second metal interconnect structure, surrounds the side of the first metal interconnect structure facing away from the second metal interconnect structure, and surrounds the side of the second metal interconnect structure facing away from the first metal interconnect structure;

[0022] The mask used in the step of forming at least one release hole is the same as the mask used in the step of forming the first metal structure and the second metal structure.

[0023] In the method for preparing the air-gap semiconductor structure provided by the present invention, the mask used in the step of forming at least one release hole is the same as the mask used in the step of forming the first metal structure and the second metal structure, which can reduce the number of masks, lower the process cost, and simplify the process flow; at the same time, the sacrificial layer surrounds the first metal interconnect structure and the second metal interconnect structure, making the cavity between the first metal interconnect structure and the second metal interconnect structure large enough to further reduce the parasitic capacitance and improve the electrical performance, reliability and stability of the semiconductor structure.

[0024] In an alternative embodiment, the steps of forming the first metal structure and the second metal structure include:

[0025] Using a first mask and a first etching process to form a first metal groove and a second metal groove in the sacrificial layers corresponding to the first metal via and the second metal via respectively; the first metal groove and the second metal groove longitudinally penetrate the capping layer and the sacrificial layer;

[0026] Using a metal deposition process to fill the first metal groove and the second metal groove to form the first metal structure and the second metal structure.

[0027] In an alternative embodiment, the release holes include a first release hole, a second release hole, a third release hole, and a fourth release hole;

[0028] The steps of forming at least one release hole include:

[0029] Using a first mask and a second etching process to form the first release hole and the second release hole on both sides of the first metal structure respectively, and form the third release hole and the fourth release hole on both sides of the second metal structure respectively; the first release hole is located on the side of the first metal structure facing away from the second metal structure; the fourth release hole is located on the side of the second metal structure facing away from the first metal structure; the second release hole and the third release hole are located between the first metal structure and the second metal structure;

[0030] The steps of removing the sacrificial layer through the release holes to form a cavity at least at the position corresponding to the gate structure include:

[0031] Removing the sacrificial layer on the side of the first metal interconnect structure facing away from the second metal interconnect structure through the first release hole, removing the sacrificial layer on the side of the second metal interconnect structure facing away from the first metal interconnect structure through the fourth release hole, and removing the sacrificial layer between the first metal interconnect structure and the second metal interconnect structure through the second release hole and the third release hole to form a cavity; the cavity surrounds the first metal interconnect structure and the second metal interconnect structure.

[0032] In an alternative embodiment, the first etching process includes:

[0033] Forming a first photoresist with a first thickness on the surface of the capping layer facing away from the second dielectric layer;

[0034] Using the first mask to expose, develop, and remove the photoresist on the first photoresist to form a first groove and a second groove on the first photoresist; the first groove and the second groove expose the capping layers corresponding to the first metal structure and the second metal structure respectively; the exposure energy in the first etching process is the first exposure energy, and the development time is the first development time;

[0035] The capping layer and the sacrificial layer at the corresponding positions exposed by the first groove and the second groove are etched away through an anisotropic etching process to form a first metal groove and a second metal groove;

[0036] The second etching process includes:

[0037] A second photoresist with a second thickness is formed on the surface of the capping layer on the side facing away from the second dielectric layer;

[0038] The second photoresist is exposed, developed, and stripped using a first mask to form a third groove and a fourth groove on the second photoresist; the third groove and the fourth groove respectively expose the first metal structure and part of the capping layer on both sides thereof and the second metal structure and part of the capping layer on both sides thereof; the exposure energy in the second etching process is the second exposure energy, and the development time is the second development time; the width of the third groove is greater than that of the first groove, and the width of the fourth groove is greater than that of the second groove;

[0039] The capping layer exposed by the third groove and the fourth groove is etched away through an anisotropic etching process to form a first release hole and a second release hole on both sides of the first metal structure respectively, and a third release hole and a fourth release hole on both sides of the second metal structure respectively.

[0040] In an optional implementation manner, the second thickness is less than the first thickness;

[0041] And / or: the second exposure energy is greater than the first exposure energy;

[0042] And / or: the second development time is greater than the first development time.

[0043] In the method for preparing the air-gap semiconductor structure provided by the present invention, by controlling that the second thickness in the parameters of the first etching process and the second etching process is less than the first thickness; and / or: the second exposure energy is greater than the first exposure energy; and / or: the second development time is greater than the first development time, the third groove and the fourth groove formed by the second etching process can be made respectively larger than the first groove and the second groove formed by the first etching process at the same position, so as to form a first release hole and a second release hole on both sides of the first metal structure respectively, and a third release hole and a fourth release hole on both sides of the second metal structure respectively. By reusing the first mask to form the release holes, the number of masks can be reduced, the process cost can be lowered, and the process flow can be simplified; at the same time, the sacrificial layer surrounds the first metal interconnect structure and the second metal interconnect structure, so that the cavity between the first metal interconnect structure and the second metal interconnect structure is large enough, which can further reduce the parasitic capacitance and improve the electrical performance, reliability, and stability of the semiconductor structure.

[0044] In an optional implementation manner, the sacrificial layer is located between the first metal interconnect structure and the second metal interconnect structure; the sacrificial layer also longitudinally penetrates into part of the first dielectric layer;

[0045] Steps of forming a first metal structure and a second metal structure, including:

[0046] Using a first mask and a first etching process to form a first metal groove and a second metal groove in the second dielectric layer corresponding to the first metal via and the second metal via respectively; the first metal groove and the second metal groove longitudinally penetrate the capping layer and the second dielectric layer;

[0047] Using a metal deposition process to fill the first metal groove and the second metal groove to form the first metal structure and the second metal structure;

[0048] Steps of forming at least one release hole at the position of the capping layer corresponding to the sacrificial layer, including:

[0049] Using a second mask and a third etching process to form at least one release hole in the capping layer corresponding to the sacrificial layer.

[0050] The method for preparing the air-gap semiconductor structure provided by the present invention, the sacrificial layer is located between the first metal interconnect structure and the second metal interconnect structure; the sacrificial layer also longitudinally penetrates into part of the first dielectric layer; it can make the formed cavity longitudinally penetrate the second dielectric layer and part of the first dielectric layer between the first metal structure and the second metal structure, effectively control the size of the cavity, thereby effectively reducing the parasitic capacitance between the first metal structure and the second metal structure, and at the same time reducing the parasitic capacitance between the first metal via and the second metal via, and further reducing the parasitic capacitance between the first metal interconnect structure and the second metal interconnect structure, so as to reduce the delay and crosstalk of the gate structure device, avoid the influence of the load effect, improve the electrical performance, stability and reliability of the device, and at the same time improve the process efficiency and yield.

[0051] In an optional embodiment, the step of removing the sacrificial layer through the release hole includes:

[0052] Adopting an isotropic etching process to etch and remove the sacrificial layer through the release hole.

[0053] In an optional embodiment, the material of the sacrificial layer is amorphous carbon;

[0054] The isotropic etching process includes:

[0055] By introducing oxygen in a radio frequency environment to form oxygen plasma, the oxygen plasma etches the amorphous carbon in all directions through the release hole, and an oxidation reaction occurs to form carbon dioxide and discharge it from the release hole.

[0056] The manufacturing method of the air-gap semiconductor structure provided by the present invention uses amorphous carbon as the material of the sacrificial layer. An isotropic etching process is adopted to etch and remove the sacrificial layer through the release holes. By introducing oxygen in a radio frequency environment to form oxygen plasma, the oxygen plasma etches the amorphous carbon in all directions through the release holes, and an oxidation reaction occurs to form carbon dioxide and discharge it from the release holes. The sacrificial layer can be completely removed without damaging the semiconductor structure, the dielectric constant between metal interconnect structures can be reduced, thereby reducing parasitic capacitance, the efficiency of forming cavities can be improved, the process cost can be reduced, and the process flow can be simplified.

[0057] In an alternative embodiment, the step of forming a gate structure and a first dielectric layer on one side of the base layer includes:

[0058] Forming an etch stop layer on the side of the gate structure and its sidewalls on one side of the base layer; the etch stop layer covers part of the side surfaces of the gate structure;

[0059] Forming a first dielectric layer on the surface of the etch stop layer facing away from the base layer; the first dielectric layer covers the surface of the gate structure facing away from the base layer and the remaining side surfaces; the gate structure is embedded in the etch stop layer and part of the first dielectric layer.

[0060] In an alternative embodiment, the steps of forming a first metal via and a second metal via include:

[0061] Opening holes on the surface of the first dielectric layer facing away from the base layer to form a first opening and a second opening. The first opening and the second opening longitudinally penetrate the first dielectric layer and the etch stop layer and expose the surface of the base layer; the first opening and the second opening are respectively located on both sides of the gate.

[0062] Filling the first opening and the second opening with a metal material to form a first metal via and a second metal via.

[0063] In a second aspect, the present invention provides an air-gap semiconductor structure, which includes:

[0064] A base layer;

[0065] A gate structure located on one side surface of the base layer;

[0066] A dielectric layer located on one side surface of the base layer and covering the gate structure;

[0067] A first metal interconnect structure and a second metal interconnect structure, partially penetrating into the dielectric layer and respectively located on both sides of the gate structure, and partially located on the surface of the dielectric layer;

[0068] A cover layer located on the surface of the dielectric layer facing away from the base layer;

[0069] There is a cavity in the dielectric layer, and the cavity is at least located between the first metal interconnect structure and the second metal interconnect structure; there is a part of the dielectric layer between the cavity and the gate structure;

[0070] A release hole is located on the side of the capping layer corresponding to the cavity, and the release hole longitudinally penetrates the capping layer.

[0071] For the air-gap semiconductor structure provided by the present invention, a cavity is arranged at the position of the dielectric layer corresponding to the gate structure between the first metal interconnect structure and the second metal interconnect structure. On the one hand, the size of the cavity can be precisely controlled, so as to better reduce the parasitic capacitance between the first metal interconnect structure and the second metal interconnect structure, thereby reducing the delay and crosstalk of the gate structure device, avoiding the influence of the load effect, improving the electrical performance, stability and reliability of the device, and at the same time improving the process efficiency and yield; on the other hand, a part of the dielectric layer is arranged between the gate structure and the cavity, which can better protect the gate structure and improve the stability of the gate structure.

[0072] In an optional embodiment, the dielectric layer includes a first dielectric layer and a second dielectric layer;

[0073] The first metal interconnect structure includes a first metal structure and a first metal via; the second metal interconnect structure includes a second metal structure and a second metal via; the cross-sectional area of the first metal structure is larger than that of the first metal via; the cross-sectional area of the second metal structure is larger than that of the second metal via; the distance between the first metal structure and the second metal structure is less than the distance between the first metal via and the second metal via;

[0074] The first dielectric layer is located on the side surface of the gate structure facing away from the base layer, and the first dielectric layer also covers the side surface of the gate structure; the first metal via and the second metal via longitudinally penetrate the first dielectric layer;

[0075] The second dielectric layer is located on the side surface of the first dielectric layer facing away from the base layer; the first metal structure and the second metal structure longitudinally penetrate the capping layer, the second dielectric layer and / or the cavity;

[0076] The first metal structure is connected to the first metal via, and the second metal structure is connected to the second metal via;

[0077] The cavity at least longitudinally penetrates the second dielectric layer.

[0078] In an optional embodiment, the cavity is located between the first metal interconnect structure and the second metal interconnect structure, surrounds the side of the first metal interconnect structure facing away from the second metal interconnect structure, and surrounds the side of the second metal interconnect structure facing away from the first metal interconnect structure;

[0079] The release holes include a first release hole, a second release hole, a third release hole, and a fourth release hole; the first release hole is located on the side of the first metal structure facing away from the second metal structure; the fourth release hole is located on the side of the second metal structure facing away from the first metal structure; the second release hole and the third release hole are located between the first metal structure and the second metal structure.

[0080] In an alternative embodiment, the cavity is located between the first metal interconnect structure and the second metal interconnect structure; the cavity also longitudinally penetrates part of the second dielectric layer.

[0081] In an alternative embodiment, the material of the first dielectric layer is silicon oxide;

[0082] The material of the second dielectric layer is silicon oxide;

[0083] The materials of the first metal via and the second metal via are tungsten;

[0084] The materials of the first metal structure and the second metal structure are copper;

[0085] The material of the capping layer is silicon nitride;

[0086] The gate structure includes a gate sidewall structure and gate polysilicon; the gate sidewall structure is a composite structure of silicon nitride and silicon oxide. BRIEF DESCRIPTION OF THE DRAWINGS

[0087] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the related art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0088] Figure 1 It is a schematic flowchart of a method for manufacturing an air-gap semiconductor structure according to an embodiment of the present invention.

[0089] Figure 2 It is a specific flowchart of a method for manufacturing an air-gap semiconductor structure according to an embodiment of the present invention.

[0090] Figure 3 It is a specific flowchart of a method for manufacturing an air-gap semiconductor structure according to Example 1 of an embodiment of the present invention.

[0091] Figure 4 It is a schematic diagram of the structure of forming the second dielectric layer in a method for manufacturing an air-gap semiconductor structure according to Example 1 of an embodiment of the present invention.

[0092] Figure 5is a schematic structural diagram of forming a sacrificial layer based on the method for preparing an air-gap semiconductor structure according to Example 1 of the embodiments of the present invention Figure 4 in the

[0093] Figure 6 is a schematic structural diagram of forming a capping layer in the method for preparing an air-gap semiconductor structure according to Example 1 of the embodiments of the present invention

[0094] Figure 7 is a schematic structural diagram of forming a first groove and a second groove in the method for preparing an air-gap semiconductor structure according to Example 1 of the embodiments of the present invention

[0095] Figure 8 is a schematic structural diagram of forming a first metal groove and a second metal groove in the method for preparing an air-gap semiconductor structure according to Example 1 of the embodiments of the present invention

[0096] Figure 9 is a schematic structural diagram of forming a first metal structure and a second metal structure in the method for preparing an air-gap semiconductor structure according to Example 1 of the embodiments of the present invention

[0097] Figure 10 is a schematic structural diagram of forming a third groove and a fourth groove in the method for preparing an air-gap semiconductor structure according to Example 1 of the embodiments of the present invention

[0098] Figure 11 is a schematic structural diagram of forming a first release hole, a second release hole, a third release hole and a fourth release hole in the method for preparing an air-gap semiconductor structure according to Example 1 of the embodiments of the present invention

[0099] Figure 12 is a schematic structural diagram of forming a cavity in the method for preparing an air-gap semiconductor structure according to Example 1 of the embodiments of the present invention

[0100] Figure 13 is a schematic flow diagram of the method for preparing an air-gap semiconductor structure according to Example 2 of the embodiments of the present invention

[0101] Figure 14 is a schematic structural diagram of forming a second dielectric layer in the method for preparing an air-gap semiconductor structure according to Example 2 of the embodiments of the present invention

[0102] Figure 15 is in the Figure 4 is a schematic structural diagram of forming a sacrificial layer based on the method for preparing an air-gap semiconductor structure according to Example 2 of the embodiments of the present invention

[0103] Figure 16 is a schematic structural diagram of forming a capping layer in the method for preparing an air-gap semiconductor structure according to Example 1 of the embodiments of the present invention

[0104] Figure 17 It is a schematic structural diagram of forming a first groove and a second groove in the manufacturing method of an air-gap semiconductor structure according to Example 1 of the embodiments of the present invention.

[0105] Figure 18 It is a schematic structural diagram of forming a first metal groove and a second metal groove in the manufacturing method of an air-gap semiconductor structure according to Example 1 of the embodiments of the present invention.

[0106] Figure 19 It is a schematic structural diagram of forming a first metal structure and a second metal structure in the manufacturing method of an air-gap semiconductor structure according to Example 1 of the embodiments of the present invention.

[0107] Figure 20 It is a schematic structural diagram of forming a fifth groove in the manufacturing method of an air-gap semiconductor structure according to Example 1 of the embodiments of the present invention.

[0108] Figure 21 It is a schematic structural diagram of forming a release hole in the manufacturing method of an air-gap semiconductor structure according to Example 1 of the embodiments of the present invention.

[0109] Figure 22 It is a schematic structural diagram of forming a cavity in the manufacturing method of an air-gap semiconductor structure according to Example 1 of the embodiments of the present invention.

[0110] Figure 23 It is a schematic structural diagram of an air-gap semiconductor structure according to the embodiments of the present invention.

[0111] Figure 24 It is a schematic structural diagram of another air-gap semiconductor structure according to the embodiments of the present invention.

[0112] Reference numerals:

[0113] 10, base layer; 11, etch stop layer; 20, gate structure; 21, gate sidewall structure; 22, gate polysilicon; 30, dielectric layer; 31, first dielectric layer; 32, second dielectric layer; 40, first metal interconnect structure; 41, first metal via; 42, first metal structure; 50, second metal interconnect structure; 51, second metal via; 52, second metal structure; 60, sacrificial layer; 61, cavity; 70, capping layer; 81, first photoresist; 82, second photoresist; 83, third photoresist; 90, release hole; 91, first release hole; 92, second release hole; 93, third release hole; 94, fourth release hole; A1, first groove; A2, second groove; A3, third groove; A4, fourth groove; A5, fifth groove; B1, first metal groove; B2, second metal groove; 100, air-gap semiconductor structure; 200, air-gap semiconductor structure. Detailed implementation manners

[0114] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only for explaining the present invention, rather than limiting the present invention. Additionally, it should be noted that for the sake of description, only the parts related to the present invention rather than all the structures are shown in the drawings.

[0115] In the following description, the description of well-known structures and technologies is omitted to avoid unnecessarily confusing the concept of the present invention. Various schematic structural diagrams according to embodiments of the present invention are shown in the drawings. These figures are not drawn to scale, and for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element can be "under" the other layer / element.

[0116] As the integration density of integrated circuits increases, the number of conductor connections also increases. The resistance-capacitance delay phenomenon (RC delay) caused by metal connection lines not only affects the speed of the chip but also poses a serious threat to the working reliability. RC delay not only hinders frequency growth but also increases the power consumption of useless work in the circuit. The transmission speed of circuit signals depends on the product of parasitic resistance and parasitic capacitance. To solve the problem of RC delay, it is necessary to reduce parasitic resistance (replacing aluminum interconnects with copper interconnects) and parasitic capacitance.

[0117] In a semiconductor structure, the capacitance between the wires connecting transistors must be reduced to reduce delay and crosstalk. Among the various factors that determine the capacitance of a capacitor, when the structure remains unchanged, reducing the k value of the dielectric can reduce the capacitance. Therefore, using a low-k dielectric as the ILD to replace traditional silicon dioxide can effectively reduce the distributed capacitance between interconnects, thereby improving the overall performance of the chip by about 10%. Since the parasitic capacitance is proportional to the dielectric constant k of the insulating medium between circuit layers, using a low-k material (k < 3) as the insulating medium between different circuit layers can achieve the purpose of reducing parasitic capacitance. The best low-k is "no material", so the solution of using an air gap to replace the insulating material dielectric layer can more effectively reduce parasitic capacitance.

[0118] However, in the prior art, it is difficult to control the size of the air gap formed in the dielectric layer, which is affected by the load effect, resulting in difficulty in controlling the parasitic capacitance. It may also damage the device structure, leading to low reliability and yield of the device.

[0119] As Figure 1 shown, this embodiment provides a method for manufacturing an air-gap semiconductor structure, which includes but is not limited to steps S101 to S103.

[0120] Step S101: Provide a base layer 10;

[0121] Step S102: Form a gate structure 20, a dielectric layer, a first metal interconnect structure 40 and a second metal interconnect structure 50 on one side surface of the base layer 10; the dielectric layer covers the side surface of the gate structure 20 facing away from the base layer 10 and the side surface of the gate structure 20, and covers the side surfaces of the first metal interconnect structure 40 and the second metal interconnect structure 50.

[0122] Step S103: Form a sacrificial layer 60 in the dielectric layer on the side of the gate structure 20 facing away from the base layer 10 through a photolithography process; the sacrificial layer 60 is at least located between the first metal interconnect structure 40 and the second metal interconnect structure 50; there is a part of the dielectric layer between the gate structure 20 and the sacrificial layer 60.

[0123] Step S104: Form a capping layer 70 on the side of the sacrificial layer 60 facing away from the base layer 10;

[0124] Step S105: Form at least one release hole in the capping layer 70 corresponding to the sacrificial layer 60, and the release hole longitudinally penetrates the capping layer 70 and exposes the surface of the sacrificial layer 60;

[0125] Step S106: Remove the sacrificial layer 60 through the release hole, and form a cavity 61 at least at the position corresponding to the gate structure 20; the cavity 61 is at least located between the first metal interconnect structure 40 and the second metal interconnect structure 50.

[0126] Specifically, when the air-gap semiconductor structure works, the first metal interconnect structure, the second metal interconnect structure and the dielectric layer therebetween together form a parasitic capacitor.

[0127] The manufacturing method of the air-gap semiconductor structure provided in this embodiment first forms a sacrificial layer in the dielectric layer on the side of the gate structure facing away from the base layer through a lithography process; the sacrificial layer is at least located between the first metal interconnect structure and the second metal interconnect structure; there is a part of the dielectric layer between the gate structure and the sacrificial layer; secondly, at least one release hole is formed in the capping layer corresponding to the sacrificial layer; finally, the sacrificial layer is removed through the release hole, and a cavity is formed at least at the position corresponding to the gate structure; the cavity is at least located between the first metal interconnect structure and the second metal interconnect structure. On the one hand, forming the sacrificial layer through the lithography process can better control the width and depth of the sacrificial layer, and then precisely control the size of the cavity, so as to better reduce the parasitic capacitance between the first metal interconnect structure and the second metal interconnect structure, thereby reducing the delay and crosstalk of the gate structure device, avoiding the influence of the load effect, improving the electrical performance, stability and reliability of the device, while improving the process efficiency and yield, and not easily damaging the device structure during the process; on the other hand, there is a part of the dielectric layer between the gate structure and the sacrificial layer, so that there is a part of the dielectric layer between the gate structure and the cavity, which can better protect the gate structure and improve the stability of the gate structure.

[0128] In some alternative embodiments, the dielectric layer includes a first dielectric layer 31 and a second dielectric layer 32; the first metal interconnect structure 40 includes a first metal structure 42 and a first metal via 41; the second metal interconnect structure 50 includes a second metal structure 52 and a second metal via 51; the cross-sectional area of the first metal structure 42 is larger than that of the first metal via 41; the cross-sectional area of the second metal structure 52 is larger than that of the second metal via 51; the distance between the first metal structure 42 and the second metal structure 52 is less than the distance between the first metal via 41 and the second metal via 51;

[0129] The steps of forming the gate structure 20, the dielectric layer, the first metal interconnect structure 40 and the second metal interconnect structure 50 on both sides of the gate structure 20 on one side of the base layer 10 include:

[0130] Form the gate structure 20 and the first dielectric layer 31 on one side of the base layer 10, and the first dielectric layer 31 covers the surface of the side of the gate structure 20 facing away from the base layer 10 and the side surface of the gate structure 20;

[0131] Form the first metal via 41 and the second metal via 51 in the first dielectric layer 31 on both sides of the gate structure 20; the first metal via 41 and the second metal via 51 longitudinally penetrate the first dielectric layer 31;

[0132] Form the second dielectric layer 32 on the side of the first dielectric layer 31 facing away from the base layer 10;

[0133] On the side surface of the first metal via 41 and the second metal via 51 facing away from the base layer 10, a first metal structure 42 and a second metal structure 52 are formed. The first metal structure 42 and the second metal structure 52 longitudinally penetrate the second dielectric layer 32; the first metal structure 42 is connected to the first metal via 41, and the second metal structure 52 is connected to the second metal via 51;

[0134] The step of forming the sacrificial layer 60 and the step of forming the capping layer 70 are after the steps of forming the first metal via 41 and the second metal via 51 and before the steps of forming the first metal structure 42 and the second metal structure 52; the sacrificial layer 60 at least longitudinally penetrates the second dielectric layer 32; the first metal structure 42 and the second metal structure 52 longitudinally penetrate the capping layer 70, the second dielectric layer 32, and / or the sacrificial layer 60.

[0135] In specific implementation, for the parasitic capacitor formed by the first metal interconnect structure and the second metal interconnect structure. Since the cross-sectional areas of the first metal structure and the second metal structure are larger, and the distance between the first metal structure and the second metal structure is smaller, the first metal structure and the second metal structure contribute a large proportion to the parasitic capacitance. While the cross-sectional areas of the first metal via and the second metal via are smaller, and the distance between the first metal via and the second metal via is farther, so the first metal via and the second metal via contribute a small proportion to the parasitic capacitance. Therefore, in the solution of this embodiment, a cavity is formed between the first metal structure and the second metal structure, which can reduce the dielectric constant between adjacent metal interconnect structures, thereby effectively reducing the parasitic capacitance between the metal interconnect structures.

[0136] In the preparation method of the air-gap semiconductor structure provided in this embodiment, since the cross-sectional area of the first metal structure is larger than that of the first metal via; the cross-sectional area of the second metal structure is larger than that of the second metal via; the distance between the first metal structure and the second metal structure is smaller than the distance between the first metal via and the second metal via; the first metal structure and the second metal structure contribute a large proportion to the parasitic capacitance, and the sacrificial layer at least longitudinally penetrates the second dielectric layer, so that the formed cavity at least longitudinally penetrates the second dielectric layer between the first metal structure and the second metal structure, which can effectively reduce the parasitic capacitance between the first metal structure and the second metal structure, and further reduce the parasitic capacitance between the first metal interconnect structure and the second metal interconnect structure, and further reduce the delay and crosstalk of the gate structure device, avoid the influence of the load effect, and can improve the electrical performance, stability and reliability of the device, and at the same time improve the process efficiency and yield.

[0137] In some alternative implementation manners, after the steps of forming the first metal structure 42 and the second metal structure 52, it further includes: performing a chemical mechanical polishing process on the first metal structure 42 and the second metal structure 52 to make the edge of the capping layer closely fit the two sides of the top of the first metal structure 42 and the second metal structure 52.

[0138] The surface of the metal structure is planarized by CMP (Chemical Mechanical Polishing process), and the edges of the capping layer are closely attached to both sides of the top of the metal structure.

[0139] In some alternative embodiments, the sacrificial layer 60 is located between the first metal interconnect structure 40 and the second metal interconnect structure 50, surrounds the side of the first metal interconnect structure 40 facing away from the second metal interconnect structure 50, and surrounds the side of the second metal interconnect structure 50 facing away from the first metal interconnect structure 40;

[0140] The mask used in the step of forming at least one release hole is the same as the mask used in the step of forming the first metal structure 42 and the second metal structure 52.

[0141] In the method for preparing the air-gap semiconductor structure provided in this embodiment, the mask used in the step of forming at least one release hole is the same as the mask used in the step of forming the first metal structure and the second metal structure. By reusing the first mask to form the release hole, the number of masks can be reduced, the process cost can be lowered, and the process flow can be simplified; at the same time, the sacrificial layer surrounds the first metal interconnect structure and the second metal interconnect structure, making the cavity between the first metal interconnect structure and the second metal interconnect structure large enough to further reduce the parasitic capacitance and improve the electrical performance, reliability, and stability of the semiconductor structure.

[0142] In some alternative embodiments, the step of forming the first metal structure 42 and the second metal structure 52 includes:

[0143] Using the first mask and the first etching process to form a first metal groove B1 and a second metal groove B2 in the sacrificial layer 60 corresponding to the first metal via 41 and the second metal via 51 respectively; the first metal groove B1 and the second metal groove B2 longitudinally penetrate the capping layer 70 and the sacrificial layer 60;

[0144] Using the metal deposition process to fill the first metal groove B1 and the second metal groove B2 to form the first metal structure 42 and the second metal structure 52.

[0145] In some alternative embodiments, the release holes include a first release hole 91, a second release hole 92, a third release hole 93, and a fourth release hole 94;

[0146] The step of forming at least one release hole includes:

[0147] Using a first mask and a second etching process, a first release hole 91 and a second release hole 92 are respectively formed on both sides of the first metal structure 42, and a third release hole 93 and a fourth release hole 94 are respectively formed on both sides of the second metal structure 52; the first release hole 91 is located on the side of the first metal structure 42 facing away from the second metal structure 52; the fourth release hole 94 is located on the side of the second metal structure 52 facing away from the first metal structure 42; the second release hole 92 and the third release hole 93 are located between the first metal structure 42 and the second metal structure 52;

[0148] The step of removing the sacrificial layer 60 through the release holes to form a cavity 61 at least at the position corresponding to the gate structure 20 includes:

[0149] Removing the sacrificial layer 60 on the side of the first metal interconnect structure 40 facing away from the second metal interconnect structure 50 through the first release hole 91, removing the sacrificial layer 60 on the side of the second metal interconnect structure 50 facing away from the first metal interconnect structure 40 through the fourth release hole 94, and removing the sacrificial layer 60 between the first metal interconnect structure 40 and the second metal interconnect structure 50 through the second release hole 92 and the third release hole 93 to form a cavity 61; the cavity 61 surrounds the first metal interconnect structure 40 and the second metal interconnect structure 50.

[0150] In some alternative embodiments, the first etching process includes:

[0151] Forming a first photoresist 81 with a first thickness on the surface of the capping layer 70 facing away from the second dielectric layer 32;

[0152] Exposing, developing, and removing the photoresist of the first photoresist 81 using the first mask to form a first groove A1 and a second groove A2 on the first photoresist 81; the first groove A1 and the second groove A2 respectively expose the capping layer 70 corresponding to the first metal structure 42 and the second metal structure 52; the exposure energy in the first etching process is the first exposure energy, and the development time is the first development time;

[0153] Etching and removing the capping layer 70 exposed by the first groove A1 and the second groove A2 and the sacrificial layer 60 at the corresponding positions through an anisotropic etching process to form a first metal groove B1 and a second metal groove B2;

[0154] The second etching process includes:

[0155] Forming a second photoresist 82 with a second thickness on the surface of the capping layer 70 facing away from the second dielectric layer 32;

[0156] Expose, develop, and strip the second photoresist 82 using the first mask, forming a third groove A3 and a fourth groove A4 on the second photoresist 82; the third groove A3 and the fourth groove A4 respectively expose the first metal structure 42 and parts of the capping layer 70 on both sides thereof and the second metal structure 52 and parts of the capping layer 70 on both sides thereof; the exposure energy in the second etching process is the second exposure energy, and the development time is the second development time; the width of the third groove A3 is greater than that of the first groove A1, and the width of the fourth groove A4 is greater than that of the second groove A2;

[0157] Etch and remove the capping layer 70 exposed by the third groove A3 and the fourth groove A4 through an anisotropic etching process, forming a first release hole 91 and a second release hole 92 on both sides of the first metal structure 42 respectively, and forming a third release hole 93 and a fourth release hole 94 on both sides of the second metal structure 52 respectively.

[0158] In some alternative embodiments, the second thickness is less than the first thickness;

[0159] and / or: the second exposure energy is greater than the first exposure energy;

[0160] and / or: the second development time is greater than the first development time.

[0161] In specific implementation, the width of the third groove A3 can be made greater than that of the first groove A1 and the width of the fourth groove A4 can be made greater than that of the second groove A2 in various ways.

[0162] (1) The second thickness is less than the first thickness, that is, the second photoresist is thinner than the first photoresist. With the same remaining lithography process parameters and complete alignment of the first mask with the first metal structure 42 and the second metal structure 52 during exposure, the effect of increasing the etching width can be achieved, so that the width of the third groove A3 is greater than that of the first groove A1 and the width of the fourth groove A4 is greater than that of the second groove A2.

[0163] (2) The second exposure energy is greater than the first exposure energy. With the same remaining lithography process parameters and complete alignment of the first mask with the first metal structure 42 and the second metal structure 52 during exposure, the effect of increasing the etching width can be achieved, so that the width of the third groove A3 is greater than that of the first groove A1 and the width of the fourth groove A4 is greater than that of the second groove A2.

[0164] (3) The second development time is greater than the first development time, that is, the second photoresist is thinner than the first photoresist. With the same remaining lithography process parameters and complete alignment of the first metal structure 42 and the second metal structure 52 on the first mask during exposure, the effect of increasing the etching width can be achieved, so that the width of the third groove A3 is greater than that of the first groove A1 and the width of the fourth groove A4 is greater than that of the second groove A2.

[0165] (4) Multiple of the above three methods can be selected for parameter setting, and the remaining lithography process parameters are the same.

[0166] In the method for preparing the air-gap semiconductor structure provided by the present invention, by controlling that the second thickness in the parameters of the first etching process and the second etching process is less than the first thickness; and / or: the second exposure energy is greater than the first exposure energy; and / or: the second development time is greater than the first development time, the third groove and the fourth groove formed by the second etching process can be made larger than the first groove and the second groove formed by the first etching process at the same position, so that a first release hole and a second release hole are respectively formed on both sides of the first metal structure, and a third release hole and a fourth release hole are respectively formed on both sides of the second metal structure. By reusing the first mask to form the release holes, the number of mask plates can be reduced, the process cost can be reduced, and the process flow can be simplified; at the same time, the sacrificial layer surrounds the first metal interconnect structure and the second metal interconnect structure, so that the cavity between the first metal interconnect structure and the second metal interconnect structure is large enough, which can further reduce the parasitic capacitance and improve the electrical performance, reliability and stability of the semiconductor structure.

[0167] In some alternative embodiments, the sacrificial layer 60 is located between the first metal interconnect structure 40 and the second metal interconnect structure 50; the sacrificial layer 60 also longitudinally penetrates into a part of the first dielectric layer 31;

[0168] The steps of forming the first metal structure 42 and the second metal structure 52 include:

[0169] Using the first mask and the first etching process to respectively form a first metal groove B1 and a second metal groove B2 in the sacrificial layer 60 corresponding to the first metal via 41 and the second metal via 51; the first metal groove B1 and the second metal groove B2 longitudinally penetrate through the capping layer 70 and the second dielectric layer 32;

[0170] Using the metal deposition process to fill the first metal groove B1 and the second metal groove B2 to form the first metal structure 42 and the second metal structure 52;

[0171] The steps of forming at least one release hole at the position of the capping layer 70 corresponding to the sacrificial layer 60 include:

[0172] Using the second mask and the third etching process to form at least one release hole in the capping layer 70 corresponding to the sacrificial layer 60.

[0173] During specific implementation, as Figure 19 shown, the sacrificial layer 60 longitudinally penetrates through the second dielectric layer 32 and also longitudinally penetrates into a part of the first dielectric layer 31.

[0174] The manufacturing method of the air-gap semiconductor structure provided by the present invention has a sacrificial layer located between the first metal interconnect structure and the second metal interconnect structure; the sacrificial layer also longitudinally penetrates into a part of the first dielectric layer; it can make the formed cavity longitudinally penetrate the second dielectric layer and a part of the first dielectric layer between the first metal structure and the second metal structure, effectively control the size of the cavity, thereby effectively reducing the parasitic capacitance between the first metal structure and the second metal structure, and at the same time can also reduce the parasitic capacitance between the first metal via and the second metal via, further reducing the parasitic capacitance between the first metal interconnect structure and the second metal interconnect structure, so as to reduce the delay and crosstalk of the gate structure device, avoid the influence of the load effect, improve the electrical performance, stability and reliability of the device, and at the same time improve the process efficiency and yield.

[0175] In some alternative embodiments, the step of removing the sacrificial layer 60 through the release hole includes:

[0176] Etch the sacrificial layer 60 removed through the release hole using an isotropic etching process.

[0177] Specifically, during implementation, the sacrificial layer 60 can be removed through the release hole during the isotropic plasma etching process. During the isotropic plasma etching process, the etching rate of the sacrificial layer in all directions is the same, that is, the plasma can etch the sacrificial layer in all directions through the etching hole to fully etch and remove the sacrificial layer to form a cavity.

[0178] In some alternative embodiments, the material of the sacrificial layer 60 is amorphous carbon;

[0179] The isotropic etching process includes:

[0180] By introducing oxygen in a radio frequency environment to form oxygen plasma, the oxygen plasma etches the amorphous carbon in all directions through the release hole and undergoes an oxidation reaction to form carbon dioxide and discharge it from the release hole.

[0181] Specifically, during implementation, since amorphous carbon can be removed by an oxidation process, in this solution, oxygen is introduced in a radio frequency environment to form oxygen plasma. The oxygen plasma enters the amorphous carbon through the etching hole and etches the sacrificial layer in all directions to fully etch and remove the sacrificial layer to form a cavity; during the etching process, the plasma reacts with the amorphous carbon to form carbon dioxide and discharges it from the etching hole.

[0182] In the manufacturing method of the air-gap semiconductor structure provided in this embodiment, the material of the sacrificial layer is amorphous carbon. An isotropic etching process is used to etch and remove the sacrificial layer through the release holes. By introducing oxygen in a radio frequency environment to form oxygen plasma, the oxygen plasma etches the amorphous carbon in all directions through the release holes, and an oxidation reaction occurs to form carbon dioxide and discharge it from the release holes. The sacrificial layer can be completely removed without damaging the semiconductor structure. It can reduce the dielectric constant between metal interconnect structures, thereby reducing parasitic capacitance. It can also improve the efficiency of forming the cavity, reduce the process cost, and simplify the process flow.

[0183] In some alternative embodiments, the step of forming the gate structure 20 and the first dielectric layer 31 on one side of the base layer 10 includes:

[0184] Forming the gate structure 20 and the etch stop layer 11 on the side thereof on one side of the base layer 10; the etch stop layer 11 covers part of the side surface of the gate structure 20;

[0185] Forming the first dielectric layer 31 on the surface of the etch stop layer 11 facing away from the base layer 10; the first dielectric layer 31 covers the surface of the gate structure 20 facing away from the base layer 10 and the remaining side surfaces; the gate structure 20 is embedded in the etch stop layer 11 and part of the first dielectric layer 31.

[0186] In some alternative embodiments, the steps of forming the first metal via 41 and the second metal via 51 include:

[0187] Opening holes on the surface of the first dielectric layer 31 facing away from the base layer 10 to form a first opening and a second opening. The first opening and the second opening longitudinally penetrate the first dielectric layer 31 and the etch stop layer 11 and expose the surface of the base layer 10; the first opening and the second opening are respectively located on both sides of the gate.

[0188] Filling the first opening and the second opening with a metal material to form the first metal via 41 and the second metal via 51.

[0189] As Figure 2 shown, the present invention also provides a specific flow schematic diagram of a manufacturing method of an air-gap semiconductor structure, including but not limited to steps S201 to step S212.

[0190] Step S201, providing the base layer 10.

[0191] Step S202, forming the gate structure 20 and the first dielectric layer 31 on one side of the base layer 10; the first dielectric layer 31 covers the surface of the gate structure 20 facing away from the base layer 10 and the side surface of the gate structure 20.

[0192] In specific implementation, first, a gate structure 20 and an etch stop layer 11 on its side are formed on one side of the base layer 10; the etch stop layer 11 covers part of the side surfaces of the gate structure 20; then, a first dielectric layer 31 is formed on the surface of the etch stop layer 11 facing away from the base layer 10; the first dielectric layer 31 covers the surface and the remaining side surfaces of the gate structure 20; the gate structure 20 is embedded in the etch stop layer 11 and part of the first dielectric layer 31.

[0193] Step S203: Form a first metal via 41 and a second metal via 51 in the first dielectric layer 31 on both sides of the gate structure 20; the first metal via 41 and the second metal via 51 longitudinally penetrate the first dielectric layer 31.

[0194] In specific implementation, first, openings are formed on the surface of the first dielectric layer 31 facing away from the base layer 10 to form a first opening and a second opening, the first opening and the second opening longitudinally penetrate the first dielectric layer and the etch stop layer 11, and expose the surface of the base layer; the first opening and the second opening are respectively located on both sides of the gate structure 20; then, the first opening and the second opening are filled with a metal material to form a first metal via 41 and a second metal via 51.

[0195] Step S204: Form a second dielectric layer 32 on the surface of the first dielectric layer 31 facing away from the base layer 10; the first dielectric layer 31 and the second dielectric layer 32 together form a dielectric layer, as Figure 4 and Figure 14 shown.

[0196] Step S205: Form a sacrificial layer 60 in the dielectric layer on the side of the gate structure 20 facing away from the base layer 10 through a photolithography process, the sacrificial layer 60 is at least located between the first metal interconnect structure 40 and the second metal interconnect structure 50; there is a part of the dielectric layer between the gate structure 20 and the sacrificial layer 60; the sacrificial layer 60 at least longitudinally penetrates the second dielectric layer 32, as Figure 5 and Figure 15 shown.

[0197] Step S206: Form a capping layer 70 on the side of the sacrificial layer 60 facing away from the base layer 10, as Figure 6 and Figure 16 shown.

[0198] Step S207: Form a first metal structure 42 and a second metal structure 52 on the surface of the first metal via 41 and the second metal via 51 facing away from the base layer 10; the first metal structure 42 and the second metal structure 52 longitudinally penetrate the capping layer 70, the second dielectric layer 32 and / or the sacrificial layer 60; the first metal structure 42 is connected to the first metal via 41, and the second metal structure 52 is connected to the second metal via 51, as Figure 9 and Figure 19 shown.

[0199] In specific implementation, the distance between the first metal structure and the second metal structure is less than the distance between the first metal through-hole and the second metal through-hole.

[0200] Step S208, form at least one release hole in the capping layer 70 corresponding to the sacrificial layer 60. The release hole longitudinally penetrates through the capping layer 70 and exposes the surface of the sacrificial layer 60, as Figure 11 and Figure 21 shown.

[0201] Step S209, use an isotropic etching process to etch away the sacrificial layer 60 through the release hole, and form a cavity 61 at least at the position corresponding to the gate structure 20; the cavity 61 is at least located between the first metal interconnect structure 40 and the second metal interconnect structure 50, as Figure 12 and Figure 22 shown.

[0202] In specific implementation, the material of the sacrificial layer 60 is amorphous carbon; the isotropic etching process includes: forming oxygen plasma by introducing oxygen in a radio frequency environment. The oxygen plasma etches the amorphous carbon in all directions through the release hole, and an oxidation reaction occurs to form carbon dioxide and discharge it from the release hole, thereby forming a cavity.

[0203] The present invention also provides two specific implementation manners, namely Example 1 and Example 2, to respectively prepare and form a air-gap semiconductor structure 100 and an air-gap semiconductor structure 200.

[0204] Figure 3 The specific process schematic diagram of the preparation method of the air-gap semiconductor structure 100 provided for Example 1 includes, but is not limited to, steps S301 to S314.

[0205] Steps S301 to S304 are the same as steps S201 to S204, and will not be elaborated here.

[0206] Step S305, form a sacrificial layer 60 in the dielectric layer on the side of the gate structure 20 facing away from the base layer 10 through a photolithography process. The sacrificial layer 60 is located between the first metal interconnect structure 40 and the second metal interconnect structure 50, and surrounds the side of the first metal interconnect structure 40 facing away from the second metal interconnect structure 50, and surrounds the side of the second metal interconnect structure 50 facing away from the first metal interconnect structure 40; there is a part of the dielectric layer between the gate structure 20 and the sacrificial layer 60; the sacrificial layer 60 at least longitudinally penetrates the second dielectric layer 32, as Figure 5 shown.

[0207] Step S306, form a capping layer 70 on the side of the sacrificial layer 60 facing away from the base layer 10, as Figure 6 shown.

[0208] Step S307: Form a first photoresist 81 with a first thickness on the surface of the cover layer 70 facing away from the second dielectric layer 32.

[0209] Step S308: Use a first mask to expose, develop, and remove the photoresist from the first photoresist 81, forming a first groove A1 and a second groove A2 in the first photoresist 81; the first groove A1 and the second groove A2 respectively expose the cover layer 70 corresponding to the first metal structure 42 and the second metal structure 52, as Figure 7 shown; the exposure energy in the first etching process is the first exposure energy, and the development time is the first development time.

[0210] Step S309: Etch and remove the cover layer 70 exposed by the first groove A1 and the second groove A2 and the sacrificial layer 60 at the corresponding positions through an anisotropic etching process, forming a first metal groove B1 and a second metal groove B2; the first metal groove B1 and the second metal groove B2 longitudinally penetrate the cover layer 70 and the sacrificial layer 60, as Figure 8 shown.

[0211] Step S310: Fill the first metal groove B1 and the second metal groove B2 using a metal deposition process to form a first metal structure 42 and a second metal structure 52; the first metal structure 42 is connected to the first metal through-hole 41 to form a first metal interconnect structure 40, and the second metal structure 52 is connected to the second metal through-hole 51 to form a second metal interconnect structure 50, as Figure 9 shown.

[0212] Step S311: Form a second photoresist 82 with a second thickness on the surface of the cover layer 70 facing away from the second dielectric layer 32;

[0213] Step S312: Use the first mask to expose, develop, and remove the photoresist from the second photoresist 82, forming a third groove A3 and a fourth groove A4 in the second photoresist 82; the third groove A3 and the fourth groove A4 respectively expose the first metal structure 42 and the partial cover layer 70 on both sides thereof and the second metal structure 52 and the partial cover layer 70 on both sides thereof, as Figure 10 shown; the exposure energy in the second etching process is the second exposure energy, and the development time is the second development time; the width of the third groove A3 is greater than that of the first groove A1, and the width of the fourth groove A4 is greater than that of the second groove A2; the second thickness is less than the first thickness; and / or: the second exposure energy is greater than the first exposure energy; and / or: the second development time is greater than the first development time.

[0214] Step S313: Etch and remove the capping layer 70 exposed in the third groove A3 and the fourth groove A4 through an anisotropic etching process, respectively form a first release hole 91 and a second release hole 92 on both sides of the first metal structure 42, and respectively form a third release hole 93 and a fourth release hole 94 on both sides of the second metal structure 52; the release holes longitudinally penetrate the capping layer 70 and expose the surface of the sacrificial layer 60; the first release hole 91 is located on the side of the first metal structure 42 facing away from the second metal structure 52; the fourth release hole 94 is located on the side of the second metal structure 52 facing away from the first metal structure 42; the second release hole 92 and the third release hole 93 are located between the first metal structure 42 and the second metal structure 52, as Figure 11 shown.

[0215] Step S314: Use an isotropic etching process to remove the sacrificial layer 60 on the side of the first metal interconnect structure 40 facing away from the second metal interconnect structure 50 through the first release hole 91, remove the sacrificial layer 60 on the side of the second metal interconnect structure 50 facing away from the first metal interconnect structure 40 through the fourth release hole 94, and remove the sacrificial layer 60 between the first metal interconnect structure 40 and the second metal interconnect structure 50 through the second release hole 92 and the third release hole 93 to form a cavity 61; the cavity 61 surrounds the first metal interconnect structure 40 and the second metal interconnect structure 50, as Figure 12 shown.

[0216] Figure 13 FIG. is a schematic flow chart of the preparation method of the air-gap semiconductor structure 200 of Example 2, including but not limited to steps S401 to S410.

[0217] Steps S401 to S404 are the same as steps S201 to S204 and will not be elaborated here.

[0218] Step S405: Form a sacrificial layer 60 in the dielectric layer on the side of the gate structure 20 facing away from the base layer 10 through a photolithography process. The sacrificial layer 60 is located between the first metal interconnect structure 40 and the second metal interconnect structure 50; there is a part of the dielectric layer between the gate structure 20 and the sacrificial layer 60; the sacrificial layer 60 longitudinally penetrates the second dielectric layer 32 and longitudinally extends into a part of the first dielectric layer 31, as Figure 15 shown.

[0219] Step S406: Form a capping layer 70 on the side of the sacrificial layer 60 facing away from the base layer 10, as Figure 16 shown.

[0220] Step S407: Use the first mask and the first etching process to respectively form a first metal groove B1 and a second metal groove B2 in the second dielectric layer 32 corresponding to the first metal through hole 41 and the second metal through hole 51; the first metal groove B1 and the second metal groove B2 longitudinally penetrate the capping layer 70 and the second dielectric layer 32, asFigure 18 as shown

[0221] In specific implementation, first, a first photoresist 81 is formed on the surface of the capping layer 70 facing away from the second dielectric layer 32. Then, the first photoresist 81 is exposed, developed, and stripped using a first mask, and a first groove A1 and a second groove A2 are formed on the first photoresist 81; the first groove A1 and the second groove A2 respectively expose the capping layer 70 corresponding to the first metal structure 42 and the second metal structure 52, as Figure 17 shown. Finally, the capping layer 70 exposed by the first groove A1 and the second groove A2 and the sacrificial layer 60 at the corresponding positions are etched away through an anisotropic etching process to form a first metal groove B1 and a second metal groove B2; the first metal groove B1 and the second metal groove B2 longitudinally penetrate the capping layer 70 and the sacrificial layer 60, as Figure 18 shown

[0222] Step S408: Fill the first metal groove B1 and the second metal groove B2 using a metal deposition process to form a first metal structure 42 and a second metal structure 52; the first metal structure 42 is connected to the first metal via 41 to form a first metal interconnect structure 40, and the second metal structure 52 is connected to the second metal via 51 to form a second metal interconnect structure 50, as Figure 19 shown

[0223] Step S409: Form at least one release hole in the capping layer 70 corresponding to the sacrificial layer 60 using a second mask and a third etching process, as Figure 21 shown

[0224] In specific implementation, first, a third photoresist 83 is formed on the surface of the capping layer 70 facing away from the second dielectric layer 32; then, the third photoresist 83 is exposed, developed, and stripped using a second mask, and a fifth groove A5 is formed on the third photoresist 83. The fifth groove A5 exposes a part of the surface of the second dielectric layer between the first metal structure 42 and the second metal structure 52, as Figure 20 shown; finally, the capping layer 70 and a part of the second dielectric layer exposed by the fifth groove A5 are etched away through an anisotropic etching process to form a release hole 95, as Figure 21 shown

[0225] Step S410: Remove the sacrificial layer 60 through the release hole using an isotropic etching process to form a cavity 61 at least at the position corresponding to the gate structure 20; the cavity 61 is located between the first metal interconnect structure 40 and the second metal interconnect structure 50, as Figure 22 shown

[0226] This embodiment also provides a air-gap semiconductor structure, as Figure 18 shown, the air-gap semiconductor structure includes:

[0227] Substrate layer 10;

[0228] Gate structure 20, located on one side surface of the substrate layer 10;

[0229] Dielectric layer, located on one side surface of the substrate layer 10 and covering the gate structure 20;

[0230] First metal interconnect structure 40 and second metal interconnect structure 50, partially penetrating into the dielectric layer and located on both sides of the gate structure 20 respectively, and partially located on the surface of the dielectric layer;

[0231] Cover layer 70, located on the surface of the dielectric layer facing away from the substrate layer 10;

[0232] There is a cavity 61 in the dielectric layer, and the cavity 61 is at least located between the first metal interconnect structure 40 and the second metal interconnect structure 50; there is a partial dielectric layer between the cavity 61 and the gate structure 20;

[0233] Release hole, located on the side of the cover layer 70 corresponding to the cavity 61, and the release hole longitudinally penetrates the cover layer 70.

[0234] In some alternative embodiments, the dielectric layer includes a first dielectric layer 31 and a second dielectric layer 32;

[0235] The first metal interconnect structure 40 includes a first metal structure 42 and a first metal via 41; the second metal interconnect structure 50 includes a second metal structure 52 and a second metal via 51; the cross-sectional area of the first metal structure 42 is larger than that of the first metal via 41; the cross-sectional area of the second metal structure 52 is larger than that of the second metal via 51; the distance between the first metal structure 42 and the second metal structure 25 is less than the distance between the first metal via 41 and the second metal via 51;

[0236] The first dielectric layer 31 is located on the side surface of the gate structure 20 facing away from the substrate layer 10, and the first dielectric layer 31 also covers the side surface of the gate structure 20; the first metal via 41 and the second metal via 51 longitudinally penetrate the first dielectric layer 31;

[0237] The second dielectric layer 32 is located on the side surface of the first dielectric layer 31 facing away from the substrate layer 10; the first metal structure 42 and the second metal structure 52 longitudinally penetrate the cover layer 70, the second dielectric layer 32 and / or the cavity 61;

[0238] The first metal structure 42 is connected to the first metal via 41, and the second metal structure 52 is connected to the second metal via 51;

[0239] The cavity 61 at least longitudinally penetrates the second dielectric layer 32.

[0240] In some alternative embodiments, such as Figure 23In the shown air-gap semiconductor structure 100, a cavity 61 is located between a first metal interconnect structure 40 and a second metal interconnect structure 50, surrounds a side of the first metal interconnect structure 40 facing away from the second metal interconnect structure 50, and surrounds a side of the second metal interconnect structure 50 facing away from the first metal interconnect structure 40;

[0241] The release holes include a first release hole 91, a second release hole 92, a third release hole 93, and a fourth release hole 94; the first release hole 91 is located on a side of the first metal structure 42 facing away from the second metal structure 52; the fourth release hole 94 is located on a side of the second metal structure 52 facing away from the first metal structure 42; the second release hole 92 and the third release hole 93 are located between the first metal structure 42 and the second metal structure 52.

[0242] In some alternative embodiments, such as Figure 24 In the shown air-gap semiconductor structure 200, a cavity 61 is located between a first metal interconnect structure 40 and a second metal interconnect structure 50; the cavity 61 also longitudinally penetrates through a part of the second dielectric layer 32.

[0243] In an alternative embodiment, the material of the first dielectric layer 31 is silicon oxide;

[0244] The material of the second dielectric layer 32 is silicon oxide;

[0245] The materials of the first metal via 41 and the second metal via 51 are tungsten;

[0246] The materials of the first metal structure 42 and the second metal structure 52 are copper;

[0247] The material of the capping layer 70 is silicon nitride;

[0248] The gate structure 20 includes a gate sidewall structure 21 and a gate polysilicon 22; the gate sidewall structure 21 is a composite structure of silicon nitride and silicon oxide.

[0249] In the description of this specification, the descriptions referring to terms such as "this embodiment", "one embodiment", "some embodiments", "examples", "specific examples", or "some examples", etc., mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of such features. In the description of the present invention, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0250] In the above description, no detailed explanations are made for technical details such as the layout and etching of each layer. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the required shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0251] The above is only the preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the above specific embodiments, and various obvious changes, re-adjustments, combinations with each other, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the protection scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for preparing an air-gap semiconductor structure, characterized in that, Including: Providing a base layer; Forming a gate structure, a dielectric layer, a first metal interconnect structure and a second metal interconnect structure on both sides of the gate structure on one surface of the base layer; the dielectric layer covers one surface of the gate structure facing away from the base layer and the side surface of the gate structure, and covers the side surfaces of the first metal interconnect structure and the second metal interconnect structure; Forming a sacrificial layer in the dielectric layer on the side of the gate structure facing away from the base layer by a photolithography process; The sacrificial layer is at least located between the first metal interconnect structure and the second metal interconnect structure; there is a part of the dielectric layer between the gate structure and the sacrificial layer; Forming a capping layer on the side of the sacrificial layer facing away from the base layer; Forming at least one release hole in the capping layer corresponding to the sacrificial layer; the release hole longitudinally penetrates the capping layer and exposes the surface of the sacrificial layer; Removing the sacrificial layer through the release hole to form a cavity at least at the position corresponding to the gate structure; the cavity is at least located between the first metal interconnect structure and the second metal interconnect structure.

2. The method for preparing an air-gap semiconductor structure according to claim 1, wherein The dielectric layer includes a first dielectric layer and a second dielectric layer; the first metal interconnect structure includes a first metal structure and a first metal via; the second metal interconnect structure includes a second metal structure and a second metal via; the cross-sectional area of the first metal structure is larger than that of the first metal via; the cross-sectional area of the second metal structure is larger than that of the second metal via; the distance between the first metal structure and the second metal structure is less than the distance between the first metal via and the second metal via; The step of forming a gate structure, a dielectric layer, a first metal interconnect structure and a second metal interconnect structure on one side of the base layer includes: Forming the gate structure and the first dielectric layer on one side of the base layer; the first dielectric layer covers one surface of the gate structure facing away from the base layer and the side surface of the gate structure; Forming the first metal via and the second metal via in the first dielectric layer on both sides of the gate structure; the first metal via and the second metal via longitudinally penetrate the first dielectric layer; Forming the second dielectric layer on the side of the first dielectric layer facing away from the base layer; Forming the first metal structure and the second metal structure on the surface of the first metal via and the second metal via facing away from the base layer; the first metal structure and the second metal structure longitudinally penetrate the second dielectric layer; the first metal structure is connected to the first metal via, and the second metal structure is connected to the second metal via; The step of forming the sacrificial layer and the step of forming the capping layer are after the step of forming the second dielectric layer and before the step of forming the first metal structure and the second metal structure; the sacrificial layer at least longitudinally penetrates the second dielectric layer; the first metal structure and the second metal structure longitudinally penetrate the capping layer, the second dielectric layer and / or the sacrificial layer.

3. The manufacturing method of the air-gap semiconductor structure according to claim 2, characterized in that the sacrificial layer is located between the first metal interconnect structure and the second metal interconnect structure, and surrounds the side of the first metal interconnect structure facing away from the second metal interconnect structure, and surrounds the side of the second metal interconnect structure facing away from the first metal interconnect structure; the mask used in the step of forming at least one release hole is the same as the mask used in the step of forming the first metal structure and the second metal structure.

4. The manufacturing method of the air-gap semiconductor structure according to claim 3, characterized in that the step of forming the first metal structure and the second metal structure includes: forming a first metal groove and a second metal groove in the sacrificial layer corresponding to the first metal via and the second metal via respectively by using a first mask and a first etching process; the first metal groove and the second metal groove longitudinally penetrate the capping layer and the sacrificial layer; filling the first metal groove and the second metal groove by using a metal deposition process to form a first metal structure and a second metal structure.

5. The manufacturing method of the air-gap semiconductor structure according to claim 4, characterized in that the release holes include a first release hole, a second release hole, a third release hole and a fourth release hole; the step of forming at least one release hole includes: forming a first release hole and a second release hole on both sides of the first metal structure respectively, and forming a third release hole and a fourth release hole on both sides of the second metal structure respectively by using a first mask and a second etching process; the first release hole is located on the side of the first metal structure facing away from the second metal structure; the fourth release hole is located on the side of the second metal structure facing away from the first metal structure; the second release hole and the third release hole are located between the first metal structure and the second metal structure; the step of removing the sacrificial layer through the release holes to form a cavity at least at the position corresponding to the gate structure includes: removing the sacrificial layer on the side of the first metal interconnect structure facing away from the second metal interconnect structure through the first release hole, removing the sacrificial layer on the side of the second metal interconnect structure facing away from the first metal interconnect structure through the fourth release hole, and removing the sacrificial layer between the first metal interconnect structure and the second metal interconnect structure through the second release hole and the third release hole to form a cavity; the cavity surrounds the first metal interconnect structure and the second metal interconnect structure.

6. The manufacturing method of the air-gap semiconductor structure according to claim 5, characterized in that the first etching process includes: forming a first photoresist with a first thickness on the surface of the capping layer facing away from the second dielectric layer; Expose, develop, and remove the photoresist on the first photoresist using a first mask, forming a first groove and a second groove on the first photoresist; the first groove and the second groove respectively expose the capping layers corresponding to the first metal structure and the second metal structure; the exposure energy in the first etching process is the first exposure energy, and the development time is the first development time; Etch and remove the capping layer exposed by the first groove and the second groove and the sacrificial layer at the corresponding positions through an anisotropic etching process to form the first metal groove and the second metal groove; The second etching process includes: Form a second photoresist with a second thickness on the surface of the capping layer facing away from the second dielectric layer; Expose, develop, and remove the second photoresist using the first mask, forming a third groove and a fourth groove on the second photoresist; the third groove and the fourth groove respectively expose the first metal structure and a part of the capping layer on both sides thereof and the second metal structure and a part of the capping layer on both sides thereof; the exposure energy in the second etching process is the second exposure energy, and the development time is the second development time; the width of the third groove is greater than that of the first groove, and the width of the fourth groove is greater than that of the second groove; Etch and remove the capping layer exposed by the third groove and the fourth groove through an anisotropic etching process, forming a first release hole and a second release hole on both sides of the first metal structure respectively, and forming a third release hole and a fourth release hole on both sides of the second metal structure respectively.

7. The method for preparing the air-gap semiconductor structure according to claim 6, wherein The second thickness is less than the first thickness; And / or: the second exposure energy is greater than the first exposure energy; And / or: the second development time is greater than the first development time.

8. The method for preparing the air-gap semiconductor structure according to claim 2, wherein The sacrificial layer is located between the first metal interconnect structure and the second metal interconnect structure; the sacrificial layer also longitudinally penetrates into a part of the first dielectric layer; The step of forming the first metal structure and the second metal structure includes: Use a first mask and a first etching process to respectively form a first metal groove and a second metal groove in the second dielectric layer corresponding to the first metal via and the second metal via; the first metal groove and the second metal groove longitudinally penetrate the capping layer and the second dielectric layer; Use a metal deposition process to fill the first metal groove and the second metal groove to form the first metal structure and the second metal structure; The step of forming at least one release hole at the position of the capping layer corresponding to the sacrificial layer includes: Use a second mask and a third etching process to form at least one release hole in the capping layer corresponding to the sacrificial layer.

9. The method for preparing the air-gap semiconductor structure according to claim 1, wherein The step of removing the sacrificial layer through the release hole includes: Use an isotropic etching process to etch through the release hole to remove the sacrificial layer.

10. The manufacturing method of the air-gap semiconductor structure according to claim 9, characterized in that the material of the sacrificial layer is amorphous carbon; the isotropic etching process includes: forming oxygen plasma by introducing oxygen in a radio frequency environment, the oxygen plasma etching amorphous carbon in all directions through the release holes, and undergoing an oxidation reaction to form carbon dioxide and discharging it from the release holes.

11. The manufacturing method of the air-gap semiconductor structure according to claim 2, characterized in that the step of forming the gate structure and the first dielectric layer on one side of the base layer includes: forming the gate structure and the etch stop layer on the side thereof on one side of the base layer; the etch stop layer covers part of the side surface of the gate structure; forming the first dielectric layer on the surface of the etch stop layer facing away from the base layer; the first dielectric layer covers the surface of the gate structure facing away from the base layer and the remaining side surfaces; the gate structure is embedded in the etch stop layer and part of the first dielectric layer.

12. The method for preparing the air-gap semiconductor structure according to claim 11, wherein The step of forming the first metal via and the second metal via includes: opening holes on the surface of the first dielectric layer facing away from the base layer to form a first opening and a second opening, the first opening and the second opening longitudinally penetrate the first dielectric layer and the etch stop layer, and expose the surface of the base layer; the first opening and the second opening are respectively located on both sides of the gate structure; filling the first opening and the second opening with a metal material to form the first metal via and the second metal via.

13. An air-gap semiconductor structure, characterized in that, including: a base layer; a gate structure located on one side surface of the base layer; a dielectric layer located on one side surface of the base layer and covering the gate structure; a first metal interconnect structure and a second metal interconnect structure, partially penetrating into the dielectric layer and respectively located on both sides of the gate structure, and partially located on the surface of the dielectric layer; a cover layer located on the surface of the dielectric layer facing away from the base layer; a cavity is formed in the dielectric layer, and the cavity is at least located between the first metal interconnect structure and the second metal interconnect structure; there is a part of the dielectric layer between the cavity and the gate structure; a release hole is located on the side of the cover layer corresponding to the cavity, and the release hole longitudinally penetrates the cover layer.

14. The air-gap semiconductor structure according to claim 13, characterized in that the dielectric layer includes a first dielectric layer and a second dielectric layer; the first metal interconnect structure includes a first metal structure and a first metal via; the second metal interconnect structure includes a second metal structure and a second metal via; the cross-sectional area of the first metal structure is larger than that of the first metal via; the cross-sectional area of the second metal structure is larger than that of the second metal via; the distance between the first metal structure and the second metal structure is smaller than the distance between the first metal via and the second metal via; the first dielectric layer is located on the surface of the gate structure facing away from the base layer, and the first dielectric layer also covers the side surface of the gate structure; the first metal via and the second metal via longitudinally penetrate the first dielectric layer; The second dielectric layer is located on a surface of the first dielectric layer facing away from the base layer; the first metal structure and the second metal structure longitudinally penetrate through the capping layer, the second dielectric layer, and / or the cavity; The first metal structure is connected to the first metal via hole, and the second metal structure is connected to the second metal via hole; The cavity at least longitudinally penetrates through the second dielectric layer.

15. The air-gap semiconductor structure according to claim 14, wherein The cavity is located between the first metal interconnect structure and the second metal interconnect structure, surrounds a side of the first metal interconnect structure facing away from the second metal interconnect structure, and surrounds a side of the second metal interconnect structure facing away from the first metal interconnect structure; The release holes include a first release hole, a second release hole, a third release hole, and a fourth release hole; the first release hole is located on a side of the first metal structure facing away from the second metal structure; the fourth release hole is located on a side of the second metal structure facing away from the first metal structure; the second release hole and the third release hole are located between the first metal structure and the second metal structure.

16. The air-gap semiconductor structure according to claim 14, wherein The cavity is located between the first metal interconnect structure and the second metal interconnect structure; the cavity also longitudinally penetrates through a part of the second dielectric layer.

17. The air-gap semiconductor structure according to claim 14, wherein The material of the first dielectric layer is silicon oxide; The material of the second dielectric layer is silicon oxide; The materials of the first metal via hole and the second metal via hole are tungsten; The materials of the first metal structure and the second metal structure are copper; The material of the capping layer is silicon nitride; The gate structure includes a gate sidewall structure and gate polysilicon; The gate sidewall structure is a composite structure of silicon nitride and silicon oxide.

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