Welding type power semiconductor packaging piece with circular symmetrical structure

Abstract

The invention provides a welding type power semiconductor packaging piece with a circular symmetrical structure. The welding type power semiconductor packaging piece comprises a packaging box and a semiconductor device, the side wall of the packaging box is cylindrical; the lining plate comprises a first metal layer, an insulating layer and a second metal layer which are stacked in sequence, the second metal layer is connected with the bottom wall of the packaging box, is round and is matched with the inner side wall of the packaging box, and the insulating layer is arranged between the first metal layer and the second metal layer in an isolated mode; the first metal layer is used for respectively connecting the chip assembly, the bottom ends of the two signal electrodes and the bottom ends of the two power electrodes; the two power electrodes are respectively cylindrical and coaxially sleeved with each other, the two signal electrodes are located in the two power electrodes, and the two signal electrodes are symmetrically arranged along the axes of the power electrodes; the top ends of the two signal electrodes and the two power electrodes extend out of the top wall of the packaging box. According to the sealing piece, the space utilization rate in the packaging piece can be improved, a local high-electric-field area is prevented from appearing in the device, chip loss is reduced, and unbalanced heating of the chip is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of high-voltage high-power semiconductors, and particularly to a welded power semiconductor package with a circular symmetric structure. Background Art

[0002] The demand for power semiconductor modules is continuously increasing because they can reduce power waste. Power semiconductor modules are mainly used for power conversions such as changing voltage and frequency, converting alternating current to direct current or converting direct current to alternating current. Power semiconductor modules can transfer new energy sources such as solar energy and wind energy to power stations without waste or be used in the core equipment of high-voltage direct current transmission - converter stations. In addition, power semiconductor modules are also widely used in fields such as new energy vehicles, industrial control, and locomotive traction and play a great role as an indispensable main component.

[0003] Currently, there are mainly two types of packages for high-voltage power semiconductor modules, namely welded modules and press-fit modules. Among them, due to advantages such as large current capacity, convenient series connection, and failure short circuit, press-fit modules are mostly used in high-voltage high-power application scenarios. However, they have technical problems in pressure balance control, and pressure imbalance will lead to a series of problems such as increased contact thermal resistance. Compared with press-fit modules, welded modules have better packaging process consistency, lower packaging difficulty, richer internal circuit topologies, and can integrate more functions inside the module. These advantages enable welded modules to be applied in relatively wide scenarios.

[0004] Currently, the internal space utilization rate of existing welded modules is low, and chips often suffer from large losses and uneven heating, which may even lead to device failure and cannot fully utilize the heat dissipation performance of the module and the external heat source. Summary of the Invention

[0005] Aiming at the problems existing in the prior art, the present invention provides a welded power semiconductor package with a circular symmetric structure that can improve the internal space utilization rate of the package, avoid the occurrence of local high electric field regions inside the device, reduce chip losses, and avoid uneven chip heating.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows: A circularly symmetric structure welded power semiconductor package, comprising a package box and a semiconductor device; the semiconductor device includes a substrate, a chip assembly, two signal electrodes, and two power electrodes; the side wall of the package box is cylindrical; the substrate includes a first metal layer, an insulating layer, and a second metal layer arranged in layers in sequence, the second metal layer is connected to the bottom wall of the package box, the second metal layer is circular, the circular second metal layer matches the inner side wall of the package box, and the insulating layer is disposed between the first metal layer and the second metal layer in an isolated manner; the first metal layer is used to connect the chip assembly, the bottoms of the two signal electrodes, and the bottoms of the two power electrodes respectively; the two power electrodes are respectively cylindrical and sleeved coaxially with each other, the two signal electrodes are located inside the two power electrodes, and the two signal electrodes are symmetrically arranged along the axis of the power electrodes; the tops of the two signal electrodes and the two power electrodes extend out of the top wall of the package box.

[0007] In some embodiments, the first metal layer includes a substrate copper layer, a gate, a source, and a drain;

[0008] The drain and the source are respectively circular and concentrically arranged, the drain is located outside the source, and the substrate copper layer and the gate are respectively located inside the source.

[0009] In some embodiments, the substrate copper layer includes a C-shaped ring, a first proximity portion, and a first connection portion;

[0010] The C-shaped ring is concentrically arranged with the drain, the first proximity portion is disposed at a position inside the C-shaped ring away from the opening of the C-shaped ring, the first connection portion is connected between the first proximity portion and a first position, and the first position is located on the inner wall of the C-shaped ring away from the opening of the C-shaped ring;

[0011] The gate includes an O-shaped ring, a second proximity portion, and a second connection portion; the second proximity portion is located inside the O-shaped ring, and the second connection portion is connected between the second proximity portion and the inner wall of the O-shaped ring;

[0012] When the substrate copper layer cooperates with the gate, the second connection portion penetrates through the opening of the C-shaped ring, the first connection portion and the second connection portion are collinear, the end face of the first proximity portion and the end face of the second proximity portion are close to each other, and the first proximity portion and the second proximity portion are symmetric to each other.

[0013] In some embodiments, the chip assembly includes a chip, a bonding wire, and a copper clip;

[0014] The chip is in a circular ring shape and is concentrically arranged with the drain, and the chip is electrically connected to the drain;

[0015] The bonding wires include a second bonding wire and at least two first bonding wires. The first bonding wires are electrically connected between the gate and the drain, and the second bonding wire is electrically connected between the liner copper layer and the source;

[0016] The copper clip includes a conductive circular ring and at least two clip bodies. The conductive circular ring is concentrically arranged with the circular-ring-shaped chip, and one end of each clip body is electrically connected to the conductive circular ring and the other end is electrically connected to the source.

[0017] In some embodiments, the signal electrodes include a source signal electrode and a gate signal electrode;

[0018] The bottom end of the source signal electrode is electrically connected to the liner copper layer, and the bottom end of the gate signal electrode is electrically connected to the gate.

[0019] In some embodiments, the drain terminal includes a first cylinder, two first connecting plates and at least two first bending portions;

[0020] Two first connecting plates are symmetrically arranged inside one axial end of the first cylinder, one end of each of the two first connecting plates is fixedly connected to the first cylinder, and at least two first bending portions are connected to the outside of the other axial end of the first cylinder;

[0021] In use, the at least two first bending portions are electrically connected to the drain;

[0022] The source terminal includes a second cylinder, two second connecting plates and at least two second bending portions;

[0023] Two second connecting plates are symmetrically arranged outside one axial end of the second cylinder, one end of each of the two second connecting plates is fixedly connected to the second cylinder, and at least two second bending portions are connected to the inside of the other axial end of the second cylinder;

[0024] In use, the at least two second bending portions are electrically connected to the source.

[0025] In some embodiments, the encapsulation box includes a bottom plate and an encapsulation shell. The second metal layer is laid on the bottom plate, the encapsulation shell covers the semiconductor device, and the two signal electrodes and the two power electrodes extend out of the encapsulation shell.

[0026] In some embodiments, an insulating rib is arranged on the outside of the encapsulation shell. The insulating rib is in a ring shape and is located between the two power electrodes.

[0027] In some of these embodiments, the encapsulation shell is an integral structure.

[0028] In some of these embodiments, the encapsulation shell includes a sidewall cylinder and an upper cover, and the sidewall cylinder and the upper cover are detachably connected.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] The circularly symmetric structure welded type power semiconductor package provided by the present invention has a design in which power electrodes are sleeved coaxially in a cylindrical shape and are symmetrically arranged along the axis of the power electrodes inside the power electrodes, which greatly improves the space utilization rate inside the package. Since the circularly symmetric structure welded type power semiconductor package is a circular and highly symmetric structure as a whole, from the perspectives of current sharing and insulation, this highly symmetric circular structure is very conducive to current sharing in the device, and the circular shape has no right-angle electric field distribution and is very uniform, which can avoid the occurrence of local high electric field regions inside the device, reduce chip loss, avoid uneven chip heating, ensure the effective operation of the device, and can make full use of the heat dissipation performance of the module and the external heat source.

[0031] The present invention adopts a circular encapsulation form to make the electric field distribution inside the high-voltage power semiconductor module more uniform, which is beneficial to reducing the maximum electric field strength. At the same time, it can make the distribution of chips inside the device highly symmetric and improve the current sharing characteristics after parallel connection.

[0032] The present invention adopts an annular power terminal to reduce the area enclosed by the "loop" formed by the terminals - chips - terminals in the power electrodes, reduce parasitic inductance and loss. The heat source distribution inside the device is uniform, the temperature distribution is more uniform, and failures caused by local overheating are avoided.

[0033] The annular design of the copper layer of the lining plate of the present invention is beneficial to reducing the position of stress concentration and increasing the reliability of the long-term service of the lining plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic diagram of the external structure of the circularly symmetric structure welded type power semiconductor package of the present invention;

[0035] Figure 2 is a schematic diagram of the three-dimensional internal structure of the encapsulation shell of the present invention;

[0036] Figure 3 is an exploded schematic diagram of the circularly symmetric structure welded type power semiconductor package of the present invention;

[0037] Figure 4 is a schematic diagram of the structure of the lining plate in the present invention;

[0038] Figure 5 is a schematic diagram of the connection relationship between the lining plate, bonding wires and copper clips in the present invention;

[0039] Figure 6 It is a schematic structural diagram of the drain terminal in the present invention;

[0040] Figure 7 It is a schematic structural diagram of the source terminal in the present invention;

[0041] Figure 8 It is a top view of the internal structure of the encapsulation shell of the present invention;

[0042] Figure 9 It is a schematic diagram of the positional relationship between the fourth through hole and the first electrode groove, and the fifth through hole and the second electrode groove in the present invention.

[0043] Among them, the reference numerals are: 1, bottom plate; 2, liner plate; 21, copper layer of the liner plate; 211, C-shaped ring; 212, first approaching part; 213, first connecting part; 22, gate; 221, O-shaped ring; 222, second approaching part; 223, second connecting part; 23, source; 24, drain; 25, second metal layer; 3, chip; 4, bonding wire; 41, first bonding wire; 42, second bonding wire; 5, copper clip; 51, conductive circular ring; 52, clip body; 6, signal electrode; 61, source signal electrode; 62, gate signal electrode; 7, drain terminal; 71, first cylinder; 72, first connecting plate; 73, first through hole; 74, first bending part; 75, first groove; 8, source terminal; 81, second cylinder; 82, second connecting plate; 83, second through hole; 84, second bending part; 85, second groove; 9, encapsulation shell; 91, shell body; 92, third through hole; 93, fourth through hole; 94, fifth through hole; 95, insulating rib; 96, first electrode groove; 97, second electrode groove. Detailed implementation manners

[0044] To clearly illustrate the technical features of this solution, the following will combine the drawings and embodiments to detail the implementation manners of this application, so as to fully understand how this application uses technical means to solve technical problems and the implementation process of achieving corresponding technical effects and implement accordingly. Each feature in the embodiments of this application and the embodiments can be combined with each other on the premise of not conflicting, and the formed technical solutions are all within the protection scope of this application.

[0045] In view of the problems of low internal space utilization rate of current welded modules, and large chip losses and uneven heat generation often accompanying, the inventor found through countless experiments that since most current welded modules adopt a square appearance, mainly to match the chip shape and external installation conditions and maximize space utilization, but such a module with a square appearance also has a square liner 2, a bottom plate 1, terminals and other structures inside. Such a structure will inevitably adopt some right-angle designs. Even though most of these right-angles use arc chamfers, there are still high electric field regions at the chamfer corners. And such chamfers will reduce the internal space utilization rate of the module. Moreover, in the currently used square modules, the paths from the electrode terminals to the chips are often different, which may lead to uneven current in the device, resulting in increased losses, uneven chip heating, and even device failure. At the same time, the uneven distribution of chips inside the device leads to uneven heat generation inside the module, and the heat dissipation performance of the module and the external enthusiasm cannot be fully utilized.

[0046] See Figure 1 、 2 、3, to solve the problems of low internal space utilization rate of current welded modules, and large chip losses and uneven heat generation often accompanying, an embodiment of the present invention provides a welded power semiconductor package with a circular symmetric structure, including a package box and a semiconductor device; the side wall of the package box is cylindrical; in some embodiments, the package box includes a bottom plate 1 and a package shell 9. The bottom plate 1 is made of a metal material, and the bottom plate 1 provides mechanical support for the whole package and transfers the heat generated by the semiconductor device to the radiator. Preferably, the material of the bottom plate 1 is aluminum silicon carbide (AlSiC), which can be lighter than copper and has better thermal matching with other components. The lower part of the bottom plate 1 is connected to the radiator by means of a thermal coupling agent or the like, and the radiator dissipates heat by air cooling or water cooling to reduce the temperature of the power device. The upper part of the bottom plate 1 is connected to the package shell 9 by means of bonding or the like. The package shell 9 is made of an insulating material, and the package shell 9 covers the semiconductor device.

[0047] The semiconductor device includes a liner 2, a chip assembly, two signal electrodes 6 and two power electrodes;

[0048] The liner 2 includes a first metal layer, an insulating layer, and a second metal layer 25 arranged in a stacked manner in sequence. The second metal layer 25 is in contact with the bottom wall of the encapsulation box, that is, the second metal layer 25 is laid on the bottom plate 1, which can ensure the heat conduction between the power device and the radiator. The liner 2 has a sandwich structure of "first metal layer - insulating layer - second metal layer", taking into account the functions of upper-layer conduction, middle-layer insulation, and lower-layer heat dissipation. The second metal layer 25 is circular, and the circular second metal layer 25 matches the inner side wall of the encapsulation box. The insulating layer is disposed between the first metal layer and the second metal layer 25 for ensuring electrical insulation between the power device and the radiator. The second metal layer 25 is connected to the insulating layer by using DBC or AMB process. The material of the insulating layer is ceramic. Preferably, the material of the insulating layer is one or more ceramic materials such as aluminum nitride (AlN), silicon nitride (Si3N4), or aluminum oxide (Al2O3). In some embodiments, the material of the insulating layer is aluminum nitride (AlN), which has a higher thermal conductivity compared to silicon nitride (Si3N4) or aluminum oxide (Al2O3), so it can withstand a higher current and achieve a higher power density. Preferably, the insulating layer is also circular.

[0049] The first metal layer is used to connect the chip component, the bottoms of the two signal electrodes 6, and the bottoms of the two power electrodes respectively; the bottoms of the two power electrodes are respectively connected to different sub-blocks of the first metal layer through connection processes such as welding and sintering. The two power electrodes are respectively in a cylindrical shape and are coaxially sleeved with each other. The two signal electrodes 6 are located inside the two power electrodes, and the two signal electrodes 6 are symmetrically arranged along the axis of the power electrodes. The bottoms of the two signal electrodes 6 are connected to the first metal layer by means of welding, power bonding, etc.; the tops of the two signal electrodes 6 and the two power electrodes extend out of the top wall of the encapsulation box, that is, the two signal electrodes 6 and the two power electrodes extend out of the encapsulation shell 9. Further, the ends of the power electrodes extending out of the encapsulation shell 9 are subjected to a bending process.

[0050] In the circular symmetric structure welding type power semiconductor package provided by the present invention, the design of the power electrodes coaxially sleeved with each other in a cylindrical shape and the signal electrodes symmetrically arranged along the axis of the power electrodes inside the power electrodes greatly improves the space utilization rate inside the package. Since the circular symmetric structure welding type power semiconductor package as a whole is a circular and highly symmetric structure, from the perspective of current sharing and insulation, this highly symmetric circular structure is very conducive to current sharing of the device, and the circular shape has a very uniform electric field distribution without right angles, which can avoid the occurrence of local high electric field regions inside the device, reduce chip loss, avoid uneven chip heating, ensure the effective operation of the device, and make full use of the heat dissipation performance of the module and the external heat source.

[0051] See Figure 4 In some embodiments, the first metal layer includes a liner copper layer 21, a gate 22, a source 23, and a drain 24;

[0052] The drain 24 and the source 23 are respectively arranged in a circular ring shape and concentrically, the drain 24 is located outside the source 23, and the liner copper layer 21 and the gate 22 are respectively located inside the source 23.

[0053] In some embodiments, the liner copper layer 21 includes a C-shaped ring, a first approaching portion 212 and a first connecting portion 213;

[0054] The C-shaped ring is arranged concentrically with the drain 24. The first approaching portion 212 is arranged at the opening of the inner side of the C-shaped ring away from the C-shaped ring. The first connecting portion 213 is connected between the first approaching portion 212 and a first position, and the first position is located on the inner wall of the C-shaped ring away from the opening of the C-shaped ring; both the connection position of the first connecting portion 213 and the first approaching portion 212 and the connection position of the first connecting portion 213 and the C-shaped ring are in arc transition; stress concentration is avoided and the reliability of the liner 2 is increased;

[0055] The gate 22 includes an O-shaped ring 221, a second approaching portion 222 and a second connecting portion 223; the second approaching portion 222 is located inside the O-shaped ring 221, and the second connecting portion 223 is connected between the second approaching portion 222 and the inner wall of the O-shaped ring 221; both the connection position of the second connecting portion 223 and the second approaching portion 222 and the connection position of the second connecting portion 223 and the O-shaped ring 221 are in arc transition; stress concentration is avoided and the reliability of the liner 2 is increased;

[0056] When the liner copper layer 21 cooperates with the gate 22, the second connecting portion 223 penetrates through the opening of the C-shaped ring, the first connecting portion 213 and the second connecting portion 223 are collinear, the end face of the first approaching portion 212 and the end face of the second approaching portion 222 are close to each other, and the first approaching portion 212 and the second approaching portion 222 are symmetric to each other.

[0057] See Figure 5 、 8 , in some embodiments, the chip component includes a chip 3, a bonding wire 4 and a copper clip 5;

[0058] The chip 3 is in a circular ring shape, and the circular ring-shaped chip 3 is arranged concentrically with the drain 24, and the chip 3 is electrically connected to the drain 24; when traditional silicon carbide chips or silicon-based chips are arranged on the liner 2, all the chips 3 are distributed in a circular shape with the center of the module as the center, and the distances of all the chips 3 from the electrode terminals are the same. Due to the reduction of the chip dicing channels and chip terminals in the circular ring-shaped chip 3, the utilization rate of the wafer is greater and the source area ratio of the chip is greater compared with traditional chips.

[0059] The bonding wire 4 includes a second bonding wire 42 and at least two first bonding wires 41. The first bonding wires 41 are electrically connected between the gate 22 and the drain 24, and the second bonding wire 42 is electrically connected between the liner copper layer 21 and the source 23;

[0060] The copper clip 5 includes a conductive circular ring 51 and at least two clip bodies 52. The conductive circular ring 51 is concentrically arranged with the circular chip 3. One end of the clip body 52 is electrically connected to the conductive circular ring 51, and the other end is electrically connected to the source electrode 23.

[0061] During manufacturing, an insulating potting adhesive is added to the encapsulation box, and the potting height of the insulating potting adhesive is at least higher than the height of the bonding wire 4.

[0062] The interconnection methods between the power device and the substrate 2, between the substrate 2 and the bottom plate 1, between the copper clip 5 and the power device, and between the copper clip 5 and the copper layer 21 of the substrate include, but are not limited to, interconnection processes such as welding and sintering.

[0063] See Figure 3 、 5 、8, in some embodiments, the signal electrode 6 includes a source signal electrode 61 and a gate signal electrode 62;

[0064] The bottom end of the source signal electrode 61 is electrically connected to the copper layer 21 of the substrate, and the bottom end of the gate signal electrode 62 is electrically connected to the gate 22.

[0065] See Figure 7 、 8 ,In some embodiments, the drain terminal 7 includes a first cylinder 71, two first connecting plates 72, and at least two first bending portions 74;

[0066] Two first connecting plates 72 are symmetrically arranged inside one axial end of the first cylinder 71. One end of each of the two first connecting plates 72 is fixedly connected to the first cylinder 71. During use, the other ends of the two connecting portions 213 are away from each other. A first through hole 73 is formed in the middle of the first connecting plate 72 for nut installation. At least two first bending portions 74 are connected to the outside of the other axial end of the first cylinder 71;

[0067] During use, at least two first bending portions 74 are electrically connected to the drain 24; the first bending portions 74 can increase the welding area with the substrate 2.

[0068] A first groove 75 is formed in the first cylinder 71 between at least two first bending portions 74 for the bonding wire 4 or the clip body 52 to pass through; it is convenient for the connection structure to be connected to the substrate 2 inside and below the electrode;

[0069] See Figure 6 、 8 ,The source terminal 8 includes a second cylinder 81, two second connecting plates 82, and at least two second bending portions 84;

[0070] On the outer side of one axial end of the second cylinder 81, two second connecting plates 82 are symmetrically arranged. One ends of the two second connecting plates 82 are respectively fixedly connected to the second cylinder 81. During use, the other ends of the two second connecting parts 223 approach each other. A second through hole 83 is formed in the middle of the second connecting plate 82 for nut installation. At least two second bending parts 84 are connected to the inner side of the other axial end of the second cylinder 81;

[0071] During use, at least two second bending parts 84 are electrically connected to the source electrode 23. The second bending parts 84 can increase the welding area with the lining plate 2.

[0072] A second groove 85 is formed in the second cylinder 81 between at least two second bending parts 84 for the bonding wire 4 or the clip body 52 to pass through. The first groove 75 corresponds to the second groove 85 one by one; facilitating the connection structure to be connected to the lining plate 2 inside and below the electrode;

[0073] The two power electrodes are designed as concentric circles as a whole. In the case of alternating current or changing current (the application condition of the power semiconductor is repeated switching, which can be understood as the current is continuously turned on and off), the inductance of the conductor (the conductor formed by the terminal-chip-terminal after the chip is turned on) will form a certain impedance, and usually the higher the frequency, the greater the impedance and the greater the accompanying loss. The "loop" formed by the terminal-chip-terminal will enclose a certain area. According to the law of electromagnetic induction, if there is a changing magnetic field in the area enclosed by this loop, an induced current will be generated in the loop, forming interference and loss. The change of the spatial magnetic field is everywhere, so the larger the enclosed area, the more serious the loss. And in the design of the present disclosure, the enclosed area is the smallest, and the formed loop is the smallest, thus greatly reducing the parasitic inductance.

[0074] See Figure 1 、 3 As shown in FIGS. 9, the package case 9 includes a case body 91. A third through hole 92, a fourth through hole 93 and a fifth through hole 94 are respectively formed in the case body 91. The third through hole 92 is an extraction hole for the signal electrode 6, the fourth through hole 93 is an extraction hole for the drain terminal 7, and the fifth through hole 94 is an extraction hole for the source terminal 8. A first electrode groove 96 is arranged inside the fourth through hole 93. The first connecting plate 72 is bent and placed in the first electrode groove 96 after being led out from the fourth through hole 93 for convenient nut installation. A second electrode groove 97 is arranged outside the fifth through hole 94. The second connecting plate 82 is bent and placed in the second electrode groove 97 after being led out from the fifth through hole 94 for convenient nut installation. In some embodiments, an insulating rib 95 is arranged outside the package case 9. The insulating rib 95 is annular and is located between the two power electrodes. The insulating rib 95 can increase the creepage distance and the electrical clearance.

[0075] In some embodiments, the package case 9 is of an integral structure.

[0076] In some of these embodiments, the encapsulation shell 9 includes a sidewall cylinder and an upper cover, and the sidewall cylinder and the upper cover are detachably connected.

[0077] Through insulation experiments and electric field simulations of the present disclosure and traditional solutions, in traditional solutions, due to electric field concentration, the weak insulation points inside the device are often the corners of the liner copper layer 21. However, the circular symmetric structure welded type power semiconductor package provided by the present disclosure adopts a design without right angles, which is beneficial to the uniform distribution of the electric field and increases the insulation performance of the device.

[0078] In traditional device packages, the current paths of each chip are often different, resulting in different package design parameters on each chip path, which affects the current sharing characteristics of parallel chips and the consistency of each branch. In the circular symmetric structure welded type power semiconductor package of the present disclosure, the circular device structure is beneficial to the symmetric arrangement of chips inside it, making the current paths flowing to each chip the same, and making the package parasitic parameters of each chip branch the same, which helps the current sharing of parallel chips inside the device.

[0079] The corner of the liner copper layer 21 is a stress concentration point, and it is easy for the copper layer and the ceramic substrate to peel off during reliability tests such as temperature cycling or during long-term service. In actual situations, stress relief holes often need to be opened at stress concentration points such as stress corners to increase the reliability of the liner 2. Such a design will occupy the internal volume of the device, resulting in increased losses and an increase in the volume of the device. However, in the present disclosure, the liner copper layer 21 is annular and has no right angle design, avoiding stress concentration and increasing the reliability of the liner 2.

[0080] In the traditional device package structure, the chips cannot be completely symmetrically distributed, resulting in uneven internal heat distribution during device operation. Different chip temperatures will affect the electrical characteristics of the chips. However, the method of completely symmetrically arranging chips in the circular symmetric structure welded type power semiconductor package proposed by the present disclosure can make the temperature inside the device balanced, and further make the electrical characteristics of each chip consistent in actual use.

[0081] Finally, it should be noted that the above content is only used to illustrate the technical solution of the present invention, rather than a limitation on the protection scope of the present invention. Simple modifications or equivalent replacements made by those of ordinary skill in the art to the technical solution of the present invention do not depart from the essence and scope of the technical solution of the present invention.

Claims

1. A circularly symmetric structure welded type power semiconductor package, comprising a package box and a semiconductor device; the semiconductor device includes a substrate, a chip assembly, two signal electrodes and two power electrodes; characterized in that: The side wall of the encapsulation box is cylindrical; the liner includes a first metal layer, an insulating layer, and a second metal layer arranged in layers in sequence. The second metal layer is in contact with the bottom wall of the encapsulation box. The second metal layer is circular, and the circular second metal layer matches the inner side wall of the encapsulation box. The insulating layer is disposed between the first metal layer and the second metal layer in an isolated manner; the first metal layer is used to connect the chip assembly, the bottoms of the two signal electrodes, and the bottoms of the two power electrodes respectively; the two power electrodes are respectively cylindrical and sleeved coaxially with each other. The two signal electrodes are located inside the two power electrodes, and the two signal electrodes are symmetrically arranged along the axis of the power electrodes; the tops of the two signal electrodes and the two power electrodes extend out of the top wall of the encapsulation box.

2. The circularly symmetric structure soldered type power semiconductor package according to claim 1, wherein: The first metal layer includes a liner copper layer, a gate, a source, and a drain. The drain and the source are respectively circular and concentrically arranged. The drain is located outside the source, and the liner copper layer and the gate are respectively located inside the source.

3. The circularly symmetric structure soldered type power semiconductor package according to claim 2, wherein: The liner copper layer includes a C-shaped ring, a first approaching portion, and a first connecting portion. The C-shaped ring is concentrically arranged with the drain. The first approaching portion is arranged at the inner side of the C-shaped ring away from the opening of the C-shaped ring. The first connecting portion is connected between the first approaching portion and the first position, and the first position is located on the inner wall of the C-shaped ring away from the opening of the C-shaped ring. The gate includes an O-shaped ring, a second approaching portion, and a second connecting portion; the second approaching portion is located inside the O-shaped ring, and the second connecting portion is connected between the second approaching portion and the inner wall of the O-shaped ring. When the liner copper layer and the gate cooperate, the second connecting portion penetrates through the opening of the C-shaped ring. The first connecting portion and the second connecting portion are collinear. The end face of the first approaching portion and the end face of the second approaching portion are close to each other, and the first approaching portion and the second approaching portion are symmetric to each other.

4. The circularly symmetric structure welded type power semiconductor package according to claim 3, wherein: The chip assembly includes a chip, bonding wires, and copper clips. The chip is circular, and the circular chip is concentrically arranged with the drain, and the chip is electrically connected to the drain. The bonding wires include a second bonding wire and at least two first bonding wires. The first bonding wires are electrically connected between the gate and the drain, and the second bonding wire is electrically connected between the liner copper layer and the source. The copper clips include a conductive ring and at least two clip bodies. The conductive ring is concentrically arranged with the circular chip. One end of the clip body is electrically connected to the conductive ring, and the other end is electrically connected to the source.

5. The circularly symmetric structure soldered type power semiconductor package according to claim 4, characterized in that: The signal electrodes include a source signal electrode and a gate signal electrode. The bottom end of the source signal electrode is electrically connected to the liner copper layer, and the bottom end of the gate signal electrode is electrically connected to the gate.

6. The circularly symmetric structure soldered type power semiconductor package according to claim 5, characterized in that: The drain terminal includes a first cylinder, two first connecting plates, and at least two first bending portions. Two first connecting plates are symmetrically arranged inside one axial end of the first cylinder. One ends of the two first connecting plates are respectively fixedly connected to the first cylinder. At least two first bending portions are connected to the outer side of the other axial end of the first cylinder. In use, the at least two first bending portions are electrically connected to the drain electrode; The source terminal includes a second cylinder, two second connecting plates, and at least two second bending portions; Two second connecting plates are symmetrically arranged on the outer side of one axial end of the second cylinder. One ends of the two second connecting plates are respectively fixedly connected to the second cylinder, and at least two second bending portions are connected to the inner side of the other axial end of the second cylinder; In use, the at least two second bending portions are electrically connected to the source electrode.

7. The circularly symmetric structure welded type power semiconductor package according to claim 6, wherein: The encapsulation box includes a bottom plate and an encapsulation shell. The second metal layer is laid on the bottom plate. The encapsulation shell covers the semiconductor device, and the two signal electrodes and the two power electrodes extend out of the encapsulation shell.

8. The circular symmetric structure welded type power semiconductor package according to claim 7, wherein: An insulating rib is arranged on the outer side of the encapsulation shell. The insulating rib is annular and is located between the two power electrodes.

9. The circularly symmetric structure soldered type power semiconductor package according to claim 7, wherein: The encapsulation shell is of an integral structure.

10. The circularly symmetric structure welded type power semiconductor package according to claim 7, characterized in that: The encapsulation shell includes a side wall cylinder and an upper cover, and the side wall cylinder and the upper cover are detachably connected.

Images