Semiconductor device

Abstract

Provided is a semiconductor device in which the area of a die pad with respect to the area of the device can be increased and heat dissipation performance can be improved compared to conventional semiconductor devices. A semiconductor device (101) is provided with: at least three first die pads (11); at least three first semiconductor elements (21) respectively mounted on the first chip pads (11); a first wire (31) electrically connecting each of the first semiconductor elements (21); at least three second chip pads (12) arranged alternately with the first chip pads (11); at least three second semiconductor elements (22) mounted on the second die pads (12), respectively; and a second wire (32) electrically connecting each of the second semiconductor elements (22).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Conventionally, as a semiconductor device in which a plurality of semiconductor elements and a control integrated circuit are mounted in one package, there is known a semiconductor device in which a plurality of semiconductor elements are mounted on one chip pad. For example, in Patent Document 1, a plurality of sets of a pair of IGBT chips and a freewheeling diode, which are semiconductor elements, are mounted on one chip pad portion of a lead frame. Specifically, three sets of high-potential-side IGBTs and freewheeling diodes are mounted on one chip pad portion, and three sets of low-potential-side IGBTs and freewheeling diodes are respectively mounted on three chip pad portions. The IGBT chips and the freewheeling diodes are electrically connected to a predetermined lead frame by bonding wires. Prior Art Documents Patent Documents

[0003] Patent Document 1: Japanese Patent Laid-Open No. 2009-111154 Summary of the Invention Technical Problem to be Solved by the Invention

[0004] In the device of Patent Document 1, since three sets of high-potential-side IGBTs and freewheeling diodes are mounted on one chip pad portion, semiconductor elements on the high-potential side that need to be electrically connected to each other and semiconductor elements on the low-potential side are arranged at separated positions. Therefore, a lead terminal connected to the chip pad portion on which the low-potential-side semiconductor elements are mounted is bent and arranged so as to approach the direction where the high-potential-side semiconductor elements are located, and the bent portion of the lead terminal is used to electrically connect the high-potential-side semiconductor elements and the low-potential-side semiconductor elements by wire bonding.

[0005] Therefore, in the device of Patent Document 1, since a space for arranging the bent lead terminals is required, the area of the chip pad portion cannot be increased by an amount equivalent to the space for arranging the bent lead terminals with respect to the overall area of the device, and there is a problem that the heat dissipation performance of the semiconductor elements cannot be improved by increasing the area of the chip pad portion.

[0006] The present disclosure is formed to solve the above problems, and an object thereof is to provide a semiconductor device that can increase the area of the chip pad relative to the device area and can improve the heat dissipation performance as compared with the prior art. Technical Solution for Solving the Technical Problem

[0007] The semiconductor device of the present disclosure includes: at least three first chip pads; at least three second semiconductor elements, at least three of the second semiconductor elements are respectively mounted on the second chip pads; and a first wire, the first wire electrically connects the first semiconductor elements respectively; at least three second chip pads, at least three of the second chip pads are alternately arranged with the first chip pads; at least three second semiconductor elements, at least three of the second semiconductor elements are respectively mounted on the second chip pads; and a second wire, the second wire electrically connects the second semiconductor elements respectively. Advantages of the Invention

[0008] According to the semiconductor device of the present disclosure, since the area of the chip pads relative to the mounting area can be enlarged, improvement in heat dissipation performance can be achieved. Description of the Drawings

[0009] Figure 1 It is a top view showing the semiconductor device of Embodiment 1 of the present disclosure. Figure 2 It is a cross-sectional view showing the semiconductor device of Embodiment 1 of the present disclosure. Figure 3 It is a top view showing the semiconductor device of Embodiment 2 of the present disclosure. Figure 4 It is a cross-sectional view showing the semiconductor device of Embodiment 2 of the present disclosure. Figure 5 It is a cross-sectional view showing the semiconductor device of Embodiment 2 of the present disclosure. Figure 6 It is a top view showing the semiconductor device of Embodiment 3 of the present disclosure. Figure 7 It is a top view showing the semiconductor device of Embodiment 4 of the present disclosure. Figure 8 It is a top view showing the semiconductor device of Embodiment 5 of the present disclosure. Detailed Embodiments

[0010] Hereinafter, an example of the semiconductor device of the present disclosure will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and repeated description is omitted.

[0011] In this specification, a semiconductor device including a three-phase inverter circuit is described as an example of a semiconductor device in which a plurality of semiconductor elements and a control integrated circuit are mounted in one package. Here, the three-phase inverter circuit is a circuit that converts DC power into three-phase (U-phase, V-phase, W-phase) AC power.

[0012] Embodiment 1 Embodiment 1 of the present disclosure relates to a semiconductor device 101, which includes: at least three first chip pads; at least three first semiconductor elements respectively mounted on the first chip pads; first wires respectively electrically connecting the first semiconductor elements; at least three second chip pads alternately arranged with the first chip pads; at least three second semiconductor elements respectively mounted on the second chip pads; and second wires respectively electrically connecting the second semiconductor elements.

[0013] <Structure of Embodiment 1> Use Figure 1 And Figure 2 , the structure of the semiconductor device 101 according to Embodiment 1 of the present disclosure will be described. Figure 1 is a top view showing the semiconductor device 101, Figure 2 is Figure 1 a cross-sectional view taken along line A-A of Figure 1 In addition, in Figure 2 , in order to show the structure inside the encapsulation resin 70, the encapsulation resin 70 is omitted from the representation. Figure 1 And Figure 2 , the outline of the encapsulation resin 70 when it exists is shown by a dashed line.

[0014] As Figure 1 And Figure 2 shown, when viewed from above, the semiconductor device 101 has chip pads (11, 12, 51), semiconductor elements (21, 22), a control integrated circuit 52, wires (31, 32, 33, 34, 53), terminals (41, 42, 43, 54), and an insulating sheet 60 inside a quadrilateral encapsulation resin 70. In addition, a part of the terminals (41, 42, 43, 54) and at least a part of the lower surface of the insulating sheet 60 are encapsulated so as to be exposed to the outside of the encapsulation resin 70. Hereinafter, the details of each structure will be described.

[0015] The semiconductor device 101 includes three first chip pads 11 and three second chip pads 12. The shapes of the three first chip pads 11 and the three second chip pads 12 when viewed from above are quadrilateral and are alternately arranged. Specifically, the three first chip pads 11 and the three second chip pads 12 are arranged to be alternately arranged along the direction in which the first side 71 of the quadrilateral encapsulation resin 70 extends when viewed from above. In other words, when viewed from above, the first side 71 of the encapsulation resin 70 is the side extending in the direction in which the first chip pads 11 and the second chip pads 12 are alternately arranged.

[0016] In addition, in Figure 1In [description], among the sides of the encapsulation resin 70 when viewed from above, the first side 71, which is a side extending in the direction in which the first chip pads 11 and the second chip pads 12 are alternately arranged, is an example of the long side of the encapsulation resin 70 when viewed from above. However, as long as the first chip pads 11 and the second chip pads 12 are arranged to be alternately arranged along the direction of one of the four sides of the encapsulation resin 70 when viewed from above. That is, in Figure 1 In [description], regarding the first chip pads 11 and the second chip pads 12, it can also be three first chip pads 11 and three second chip pads 12 arranged, for example, along one short side of the encapsulation resin 70 ( Figure 1 the second side 72 or the third side 73 in [description]).

[0017] The first chip pads 11 and the second chip pads 12 are plate-like members having an upper surface and a lower surface. For the first chip pads 11 and the second chip pads 12, a material with electrical conductivity and good thermal conductivity, such as copper, is used.

[0018] Three first semiconductor elements 21 are respectively mounted on the upper surfaces of the three first chip pads 11. In addition, three second semiconductor elements 22 are respectively mounted on the upper surfaces of the three second chip pads 12.

[0019] The first semiconductor elements 21 and the second semiconductor elements 22 are components for constituting a three-phase inverter circuit that converts DC power into three-phase (U-phase, V-phase, W-phase) AC power, and are elements that perform switching operations. The first semiconductor elements 21 are electrically connected between a first main terminal 41 described later and an output terminal 43 described later to constitute the above three-phase inverter circuit. In addition, the second semiconductor elements 22 are connected between the output terminal 43 described later and a second main terminal 42 described later to constitute the above three-phase inverter circuit. In addition, the first semiconductor elements 21 are connected to an external substrate (not shown) located on the high potential side of the DC power in the three-phase inverter circuit. The second semiconductor elements 22 are connected to an external substrate (not shown) located on the low potential side of the DC power in the three-phase inverter circuit. In other words, a relatively higher potential is supplied to the first semiconductor elements 21 compared to the second semiconductor elements 22. A relatively lower potential is supplied to the second semiconductor elements 22 compared to the first semiconductor elements 21.

[0020] The first semiconductor element 21 and the second semiconductor element 22 are, for example, RC (reverse conducting)-IGBT (insulated gate bipolar transistor). The RC-IGBT is an element in which an IGBT and a freewheeling diode are formed on one chip, and performs two operations: a switching operation and a freewheeling operation. In addition, the first semiconductor element 21 and the second semiconductor element 22 only need to be able to perform a switching operation, and a combination of two or more elements may be used as the first semiconductor element 21 and the second semiconductor element 22. That is, as the first semiconductor element 21 or the second semiconductor element 22, a combination of a switch element and a diode connected in inverse parallel may be adopted. For example, as the first semiconductor element 21 or the second semiconductor element 22, an IGBT or a MOS transistor (metal oxide semiconductor) may be used in combination with a freewheeling diode.

[0021] Three first semiconductor elements 21 and three second semiconductor elements 22 are respectively provided corresponding to the three-phase AC power to be output. The structure of the three-phase inverter circuit constituted by the first semiconductor element 21 and the second semiconductor element 22 will be described later.

[0022] The semiconductor device 101 includes a first main terminal 41, a second main terminal 42, and three output terminals 43. The first main terminal 41 extends from a first chip pad 11 disposed on one end side in the direction in which the first chip pads 11 and the second chip pads 12 are alternately arranged among the three first chip pads 11. The second main terminal 42 is disposed on the other end side in the direction in which the first chip pads 11 and the second chip pads 12 are alternately arranged. Here, in Figure 1 the one end side in the direction in which the first chip pads 11 and the second chip pads 12 are alternately arranged is the left end side, and the other end side in the direction in which the first chip pads 11 and the second chip pads 12 are alternately arranged is the right end side. The three output terminals extend from at least three of the second chip pads.

[0023] The first main terminal 41, the second main terminal 42, and the output terminals 43 protrude to the outside from a first side surface of the encapsulation resin 70. The first side surface of the encapsulation resin 70 includes an edge extending in the direction in which the first chip pads 11 and the second chip pads 12 are alternately arranged, that is, a first edge 71.

[0024] In addition, Figure 1 an example is shown in which the first edge 71 included in the first side surface of the encapsulation resin 70 is the long side when the encapsulation resin 70 is viewed from above. However, the first side surface only needs to be a side surface including one of the four sides of the encapsulation resin 70 having a quadrilateral shape when viewed from above. That is, the first side surface may also be a side surface including the short side of the encapsulation resin 70 when viewed from above ( Figure 1 the second edge 72 or the third edge 73 inFigure 1 As shown, when the first side 71 included in the first side surface of the encapsulation resin 70 is the long side when the encapsulation resin 70 is viewed from above, compared with the case where it is the short side, the first main terminal 41, the second main terminal 42, and the output terminal 43 are respectively arranged separately from other terminals. Therefore, the creepage distance between the terminals can be reliably ensured.

[0025] In addition, Figure 1 shows an example where the shape of the portions of the first main terminal 41, the second main terminal 42, and the output terminal 43 protruding from the encapsulation resin 70 is a quadrilateral when viewed from above, but it is not limited thereto. The portions of the first main terminal 41, the second main terminal 42, and the output terminal 43 protruding from the encapsulation resin 70 may also be, for example, a polygonal or plate-shaped member with a rounded corner shape.

[0026] The first main terminal 41 and the second main terminal 42 are electrically connected to an external substrate (not shown) and are provided for inputting DC power. The output terminal 43 is electrically connected to an external substrate (not shown) and is provided for outputting AC power. Similar to the first chip pad 11 and the second chip pad 12, the first main terminal 41, the second main terminal 42, and the output terminal 43 are made of a material having conductivity and good thermal conductivity, for example, made of copper or the like.

[0027] In addition, as Figure 1 shown, the semiconductor device 101 may include inner leads 41a that extend from two of the three first chip pads 11 and are entirely encapsulated inside the encapsulation resin 70. Specifically, the inner leads 41a extend from the two first chip pads disposed on the other end side in the direction in which the first chip pads 11 and the second chip pads 12 are alternately arranged. The inner leads 41a are members extending from the first chip pads 11. However, different from the first main terminal 41, the inner leads 41a do not protrude to the outside of the encapsulation resin 70. The inner leads 41a are formed for making electrical connections inside the semiconductor device 101.

[0028] The semiconductor device 101 includes a plurality of wire materials for electrically connecting the three first semiconductor elements 21 and the three second semiconductor elements 22. Specifically, the semiconductor device 101 includes a first wire material 31, a second wire material 32, a third wire material 33, and a fourth wire material 34.

[0029] The first wire 31 is a wire that electrically connects three first semiconductor elements 21 respectively, and is respectively arranged to connect between two first chip pads 11 adjacent to the second chip pad 12 with the second chip pad 12 in between. Specifically, the first wire 31 includes a first wire 31a and a first wire 31b. The first wire 31a is arranged to connect between two first chip pads 11 on one end side in the direction where the first chip pads 11 and the second chip pad 12 are alternately arranged, and the first wire 31b is arranged to connect between two first chip pads 11 on the other end side in the direction where the first chip pads 11 and the second chip pad 12 are alternately arranged. Here, the two first chip pads 11 on one end side refer to the two first chip pads 11 arranged on the Figure 1 left end side in, and the two first chip pads 11 on the other end side refer to the two first chip pads 11 arranged on the Figure 1 right end side in. That is, the first wire 31 is a general term for wires arranged to connect between the first chip pads 11. The first wire 31 can be composed of multiple wires or can be arranged by connecting with one wire.

[0030] The second wire 32 is a wire that electrically connects three second semiconductor elements 22 respectively, and is respectively arranged to connect between two second semiconductor elements 22 mounted on two second chip pads 12 adjacent to the first chip pad 11 with the first chip pad 11 in between. Specifically, the second wire 32 includes a second wire 32a and a second wire 32b. The second wire 32a is arranged to connect between two second chip pads 22 on the other end side in the direction where the first chip pads 11 and the second chip pad 12 are alternately arranged, and the second wire 32b is arranged to connect between two second semiconductor elements 22 on one end side in the direction where the first chip pads 11 and the second chip pad 12 are alternately arranged. Here, the two second semiconductor elements 22 on one end side refer to the two second semiconductor elements 22 arranged on the Figure 1 left end side in, and the two second semiconductor elements 22 on the other end side refer to the two second semiconductor elements 22 arranged on the Figure 1 right end side in. That is, the second wire 32 is a general term for wires arranged to connect between the second semiconductor elements 22. The second wire 32 can be composed of multiple wires or can be arranged by connecting with one wire.

[0031] The third wire 33 is a wire that electrically connects the second main terminal 42 and the second semiconductor element 22. The third wire 33 is arranged to connect between the second semiconductor element 22 on the other end side in the direction where the first chip pads 11 and the second chip pad 12 are alternately arranged and the second main terminal 42.

[0032] The fourth wire 34 is a wire that electrically connects the first semiconductor element 21 and the second semiconductor element 22, and is respectively arranged to connect between the adjacent first semiconductor element 21 and the second chip pad 12.

[0033] The first wire 31, the second wire 32, the third wire 33, and the fourth wire 34 are, for example, bonding wires made of aluminum wires.

[0034] In addition, the semiconductor device 101 includes three control integrated circuits 52 for controlling the first semiconductor element 21 and the second semiconductor element 22. Specifically, the control integrated circuit 52 receives an operation instruction from the outside and generates and outputs a control signal for the first semiconductor element 21 and the second semiconductor element 22. The three control integrated circuits 52 are respectively mounted on the upper surface of a third chip pad 51.

[0035] In addition, in Figure 1 and Figure 2 an example of having three control integrated circuits 52 is shown, however, the number of control integrated circuits 52 is not limited thereto. For example, it may have two.

[0036] In addition, the semiconductor device 101 includes a plurality of control terminals 54 electrically connected to the control integrated circuit 52. The control terminals 54 protrude from the fourth side to the outside of the encapsulation resin 70, and the fourth side includes a fourth side 74 that faces the first side 71 when the encapsulation resin 70 is viewed from above. The plurality of control terminals 54 are electrically connected to an external substrate (not shown), and are provided to receive an operation instruction for the first semiconductor element 21 and the second semiconductor element 22.

[0037] In addition, the semiconductor device 101 includes a plurality of fifth wires 53, and the plurality of fifth wires 53 are arranged to connect between the first semiconductor element 21 and the control integrated circuit 52, between the second semiconductor element 22 and the control integrated circuit 52, and between the control terminal 54 and the control integrated circuit 52. The plurality of fifth wires 53 are provided, for example, to send a control signal for instructing conduction or cutoff in the switching operation from the control integrated circuit 52 to the first semiconductor element 21 and the second semiconductor element 22, or are provided for the control integrated circuit 52 to receive an operation instruction for the first semiconductor element 21 and the second semiconductor element 22 from the outside. The fifth wire 53 is, for example, a bonding wire made of a gold wire.

[0038] In addition, the semiconductor device 101 is as Figure 2includes an insulating sheet 60 as shown. The insulating sheet 60 is arranged such that the upper surface of the insulating sheet 60 faces the lower surfaces of the first chip pad 11 and the second chip pad 12, that is, the surfaces of the first chip pad 11 and the second chip pad 12 opposite to the mounting surfaces of the first semiconductor element 21 and the second semiconductor element 22.

[0039] The insulating sheet 60 is made of a material having insulation and good heat conductivity. For example, an epoxy resin including any one of BN, SiO2, Si3N4, Al2O3, and AlN as a filler is used.

[0040] The semiconductor device 101 encapsulates each structure with a packaging resin 70 having a quadrilateral shape when viewed from above. Specifically, the packaging resin 70 encapsulates the first chip pad 11, the second chip pad 12, the third chip pad 51, the first semiconductor element 21, the second semiconductor element 22, the control integrated circuit 52, the first wire 31, the second wire 32, the third wire 33, the fourth wire 34, the fifth wire 53, a part of the first main terminal 41, a part of the second main terminal 42, a part of the output terminal 43, a part of the control terminal 54, and a part of the insulating sheet 60. That is, a part of the first main terminal 41, a part of the second main terminal 42, a part of the output terminal 43, a part of the control terminal 54, and at least a part of the lower surface of the insulating sheet 60 are exposed to the outside of the packaging resin 70.

[0041] According to the above structure, the heat generated by the first semiconductor element 21 and the second semiconductor element 22 is released to the outside of the semiconductor device 101 through the first chip pad 11 or the second chip pad 12 and the insulating sheet 60 with which they are in contact.

[0042] In addition, the semiconductor device 101 may also include a heat sink (not shown). The heat sink is arranged on the lower surface of the insulating sheet 60. By further providing the heat sink, the heat dissipation performance of the heat generated by the first semiconductor element 21 and the second semiconductor element can be improved.

[0043] As described above, the semiconductor device 101 has a structure in which three first semiconductor elements 21, three second semiconductor elements 22, and three control integrated circuits 52 for controlling the first semiconductor element 21 and the second semiconductor element 22 are installed in one package. The semiconductor device 101 has a three-phase inverter circuit composed of three first semiconductor elements 21 and three second semiconductor elements 22 and a drive circuit composed of three control integrated circuits 52. Here, the circuit structure of the semiconductor device 101 will be described.

[0044] The three-phase inverter circuit included in the semiconductor device 101 is a circuit that converts DC power into three-phase AC power and outputs it through the switching operations of the first semiconductor element 21 and the second semiconductor element 22. The three-phase inverter circuit is configured such that the first semiconductor element 21 on the high-potential side and the second semiconductor element 22 on the low-potential side are electrically connected between a first main terminal 41 connected to an external substrate (not shown) on the high-potential side and a second main terminal 42 connected to an external substrate (not shown) on the low-potential side, and the connection node connecting the AC power output sides of both is the output terminal 43. That is, in order to form the three-phase inverter circuit, the first semiconductor element 21 on the high-potential side and the second semiconductor element 22 on the low-potential side need to be electrically connected. In addition, the three first semiconductor elements 21 need to be electrically connected in parallel. Similarly, the three second semiconductor elements 22 need to be electrically connected in parallel.

[0045] As described above, three first semiconductor elements 21 and three second semiconductor elements 22 are respectively provided corresponding to the three phases. That is, one first semiconductor element 21 and one second semiconductor element 22 are provided for each phase, and three first semiconductor elements 21 and three second semiconductor elements 22 are provided in the three phases. Three output terminals 43 are provided corresponding to each of the three phases.

[0046] The drive circuit included in the semiconductor device 101 is a circuit that controls the switching operations of the first semiconductor element 21 and the second semiconductor element 22. The drive circuit is configured such that one control integrated circuit 52 controls the switching operations of the group of the first semiconductor element 21 and the second semiconductor element 22 that constitute one phase of the three phases. That is, one control integrated circuit 52 is provided for each phase, and three control integrated circuits 52 are provided in the three phases.

[0047] In this way, the semiconductor device 101 controls the switching operations of the three first semiconductor elements 21 and the three second semiconductor elements 22 through the three-phase inverter circuit and the drive circuit, converts DC power into three-phase AC power, and outputs it.

[0048] In addition, an example in which the semiconductor device 101 includes three first semiconductor elements 21 and three second semiconductor elements 22 each has been described. However, the semiconductor device 101 may also include more than three first semiconductor elements 21 and second semiconductor elements 22 each. The semiconductor device 101 only needs to include at least three first semiconductor elements 21 and second semiconductor elements 22 each. For example, it may also be configured to include six first semiconductor elements 21 and six second semiconductor elements 22 each to form a three-phase voltage type three-level inverter circuit. Depending on the number of the first semiconductor elements 21 and the second semiconductor elements 22, it may also include more than three first chip pads 11 and second chip pads 12 each.

[0049] <Manufacturing method of Embodiment 1> Next, a manufacturing method of the semiconductor device 101 according to Embodiment 1 of the present disclosure will be described. In addition, in the present embodiment, since processes other than the process of forming the three first chip pads 11 in the manufacturing process of the semiconductor device 101 can be appropriately implemented by using known techniques, again, only the process of forming the three first chip pads 11 will be described.

[0050] The three first chip pads 11 are formed by blanking a copper plate having conductivity and good thermal conductivity. The three first chip pads are formed, for example, by blanking the copper plate into a predetermined shape using a die.

[0051] <Function and effect of Embodiment 1> Next, the existing semiconductor device is compared with the semiconductor device 101 of the present disclosure, and the functions and effects of the semiconductor device 101 according to Embodiment 1 of the present disclosure will be described.

[0052] In an existing semiconductor device, for example, in the device of Patent Document 1, three groups of IGBTs and freewheeling diodes on the high-potential side are mounted on one chip pad portion. Therefore, in the device of Patent Document 1, it is a structure in which semiconductor elements on the high-potential side and semiconductor elements on the low-potential side that need to be electrically connected to each other to form a three-phase inverter circuit are arranged at separate positions. In order to connect the semiconductor elements on the high-potential side and the semiconductor elements on the low-potential side, the terminals extending from the chip pads on which the semiconductor elements on the low-potential side are mounted are formed in a shape having one or more bent portions. Therefore, in the device of Patent Document 1, it is impossible to increase the area of the chip pad portion by an amount equivalent to the space for arranging the bent portions of the terminals with respect to the overall area of the device, and it is impossible to improve the heat dissipation performance of the semiconductor elements by increasing the area of the chip pad portion.

[0053] The semiconductor device 101 according to Embodiment 1 of the present disclosure includes at least three first chip pads 11, at least three first semiconductor elements 21 respectively mounted on the first chip pads 11, first wire materials 31 respectively electrically connecting the first semiconductor elements 21, at least three second chip pads 12 alternately arranged with the first chip pads 11, at least three second semiconductor elements 22 respectively mounted on the second chip pads 12, and second wire materials 32 respectively electrically connecting the second semiconductor elements 22.

[0054] In the semiconductor device 101 according to Embodiment 1 of the present disclosure, the first chip pad 11 on which the first semiconductor element 21 corresponding to the high-potential-side semiconductor element is mounted is separated into three, and is alternately arranged with the second chip pad 12 on which the second semiconductor element 22 corresponding to the low-potential-side semiconductor element is mounted, so that the first semiconductor element 21 and the second semiconductor element 22 that need to be electrically connected to each other can be arranged adjacent to each other. By arranging the first semiconductor element 21 and the second semiconductor element 22 adjacent to each other, it is no longer necessary to bend and arrange the output terminal 43 corresponding to the terminal extending from the second chip pad in the direction approaching the first semiconductor element 21. That is, the first semiconductor element 21 and the second semiconductor element 22 can be electrically connected without bending the output terminal 43. Therefore, in the semiconductor device 101 according to Embodiment 1 of the present disclosure, since the output terminal 43 can be arranged without bending, the areas of the first chip pad 11 and the second chip pad 12 can be enlarged by an amount equivalent to the space for arranging the bent terminals in the conventional device compared with the prior art with respect to the area of the semiconductor device 101.

[0055] The heat generated by the first semiconductor element 21 and the second semiconductor element 22 is released to the outside of the semiconductor device 101 via the first chip pad 11 and the second chip pad 12. Therefore, in the semiconductor device 101 according to Embodiment 1 of the present disclosure, the areas of the first chip pad 11 and the second chip pad 12 can be further enlarged compared with the prior art, and thus the heat dissipation performance of the semiconductor device 101 can be improved compared with the prior art. In addition, in the semiconductor device 101 according to Embodiment 1 of the present disclosure, since the heat dissipation performance of the semiconductor device 101 is improved, the energization current of the semiconductor device 101 can be increased compared with the prior art.

[0056] Embodiment 2 In Embodiment 1 of the present disclosure, a semiconductor device 101 including a first main terminal 41, a second main terminal 42, and an output terminal 43 provided so as to protrude from a first side surface of a package resin 70 was described. Here, the first side surface of the package resin 70 includes a first side 71, and the first side 71 is a side that extends in the direction in which the first chip pads 11 and the second chip pads 12 are alternately arranged among the sides of the package resin 70 when viewed from above. In Embodiment 2 of the present disclosure, a semiconductor device 102 including an output terminal 43, a first main terminal 241, and a second main terminal 242 was described. The output terminal 43 is provided so as to protrude from the first side surface of the package resin 70, the first main terminal 241 is provided so as to protrude from the second side surface of the package resin 70, and the second terminal 242 is provided so as to protrude from the third side surface of the package resin 70. The second side surface of the package resin 70 includes a second side 72, and the second side 72 is a side on one end side among the sides of the package resin 70 when viewed from above in the direction in which the first chip pads 11 and the second chip pads 12 are alternately arranged. The third side surface of the package resin 70 includes a third side 73, and the third side 73 is a side on the other end side among the sides of the package resin 70 when viewed from above in the direction in which the first chip pads 11 and the second chip pads 12 are alternately arranged. In addition, in Embodiment 2, the same reference numerals are used for the same components as those in Embodiment 1 of the present disclosure, and the description of the same or corresponding parts is omitted. Hereinafter, with reference to the drawings, the semiconductor device 102 of Embodiment 2 will be described.

[0057] <Structure of Embodiment 2> Use Figure 3 、 Figure 4 And Figure 5 to describe the structure of the semiconductor device 102 of Embodiment 2 of the present disclosure. Figure 3 is a top view showing the semiconductor device 102. Figure 4 Is Figure 3 a cross-sectional view taken along line A-A of Figure 5 Is Figure 3 a cross-sectional view taken along line B-B of Figure 3 、 Figure 4 And Figure 5 In order to show the internal structure of the package resin 70, the representation of the package resin 70 is omitted. In addition, in Figure 3 、 Figure 4 And Figure 5 the outline of the package resin 70 when it exists is shown by a dashed line.

[0058] As Figure 3 、 Figure 4 And Figure 5As shown, the semiconductor device 102 includes an output terminal 43, a first main terminal 241, and a second main terminal 242. The output terminal 43 is provided so as to protrude from a first side surface of the encapsulation resin 70. The first main terminal 241 is provided so as to protrude from a second side surface of the encapsulation resin 70. The second main terminal 242 is provided so as to protrude from a third side surface of the encapsulation resin 70. The first side surface of the encapsulation resin 70 includes a first side 71, and the first side 71 is a side among the sides of the encapsulation resin 70 when viewed from above in the direction in which the first chip pad 11 and the second chip pad 12 are alternately arranged. The second side surface of the encapsulation resin 70 includes a second side 72, and the second side 72 is a side at one end side among the sides of the encapsulation resin 70 when viewed from above in the direction in which the first chip pad 11 and the second chip pad 12 are alternately arranged. The third side surface of the encapsulation resin 70 includes a third side 73, and the third side 73 is a side at the other end side among the sides of the encapsulation resin 70 when viewed from above in the direction in which the first chip pad 11 and the second chip pad 12 are alternately arranged.

[0059] As described above, by providing each terminal so as to protrude from a different side surface of the encapsulation resin 70, the first main terminal 241, the second main terminal 242, and the output terminal 43 are respectively arranged separately from other terminals.

[0060] In addition, not only are each terminal provided so as to protrude from different side surfaces of the encapsulation resin 70, but further, the area of the portion of each terminal protruding from the encapsulation resin 70 can be enlarged. Specifically, as Figure 3 、 Figure 4 and Figure 5 shown, each terminal can be provided so as to protrude from a different side surface of the encapsulation resin 70, and further, the width of the portion of each terminal protruding from the encapsulation resin 70 in the direction orthogonal to the protruding direction can be increased when viewed from above. Use Figure 3 、 Figure 4 and Figure 5 to describe the structure in which the width of the portion of each terminal protruding from the encapsulation resin 70 is increased.

[0061] As Figure 3 、 Figure 4 and Figure 5As shown, since the first main terminal 241, the second main terminal 242, and the output terminal 43 are arranged to protrude from different sides of the encapsulation resin 70 respectively, it is possible to increase the width of the portion of each terminal protruding from the encapsulation resin 70 in the direction orthogonal to the protruding direction when viewed from above. Specifically, in the direction in which the first chip pad 11 and the second chip pad 12 are alternately arranged, the width of the portion of the output terminal 43 protruding from the encapsulation resin 70 is larger than the width of the second chip pad 12. In addition, in the direction orthogonal to the direction in which the first chip pad 11 and the second chip pad 12 are alternately arranged, the width of the portion of the first main terminal 241 protruding from the encapsulation resin 70 is larger than the width of the first chip pad 11. In the direction orthogonal to the direction in which the first chip pad 11 and the second chip pad 12 are alternately arranged, the width of the portion of the second main terminal 242 protruding from the encapsulation resin 70 is larger than the width of the second chip pad 12.

[0062] As described above, regarding each terminal, by increasing the width of the portion of the terminal protruding from the encapsulation resin 70 in the direction orthogonal to the direction of protruding from the side of the encapsulation resin 70 when viewed from above, the area of each terminal is enlarged.

[0063] In addition, in Figure 3 an example is shown in which the shape of the portions of the first main terminal 241, the second main terminal 242, and the output terminal 43 protruding from the encapsulation resin 70 is a quadrilateral when viewed from above, but it is not limited thereto. The portions of the first main terminal 241, the second main terminal 242, and the output terminal 43 protruding from the encapsulation resin 70 may be, for example, a polygon or a plate-like member with a rounded corner shape.

[0064] <Manufacturing method of Embodiment 2> Since the manufacturing method of the semiconductor device 102 of Embodiment 2 of the present disclosure is the same as the manufacturing method of the semiconductor device 101 of Embodiment 1, the description thereof is omitted.

[0065] <Function and effect of Embodiment 2> Next, the functions and effects of the semiconductor device 102 of Embodiment 2 of the present disclosure will be described.

[0066] The semiconductor device 102 according to Embodiment 2 of the present disclosure includes an output terminal 43, a first main terminal 241, and a second main terminal 242. The output terminal 43 is provided so as to protrude from the first side surface of the encapsulation resin 70. The first main terminal 241 is provided so as to protrude from the second side surface of the encapsulation resin 70. The second main terminal 242 is provided so as to protrude from the third side surface of the encapsulation resin 70. The first side surface of the encapsulation resin 70 includes a first side 71. The first side 71 is a side of the encapsulation resin 70 having a quadrilateral shape in a plan view and is a side in the direction in which the first chip pad 11 and the second chip pad 12 are alternately arranged. The second side surface of the encapsulation resin 70 includes a second side 72. The second side 72 is a side at one end side in the direction in which the first chip pad 11 and the second chip pad 12 are alternately arranged among the sides of the encapsulation resin 70 in a plan view. The third side surface of the encapsulation resin 70 includes a third side 73. The third side 73 is a side at the other end side in the direction in which the first chip pad 11 and the second chip pad 12 are alternately arranged among the sides of the encapsulation resin 70 in a plan view.

[0067] In the semiconductor device 102 according to Embodiment 2 of the present disclosure, since the first main terminal 241, the second main terminal 242, and the output terminal 43 are provided so as to protrude from different side surfaces of the encapsulation resin 70, that is, the second side surface, the third side surface, and the first side surface, respectively, the first main terminal 241, the second main terminal 242, and the output terminal 43 are arranged to be separated from other terminals, and the creepage distance between the terminals can be reliably ensured.

[0068] In addition, in the semiconductor device 102 according to Embodiment 2 of the present disclosure, in the direction in which the first chip pad 11 and the second chip pad 12 are alternately arranged, the width of the portion of the output terminal 43 protruding from the encapsulation resin 70 is larger than the width of the second chip pad 12. In the direction orthogonal to the direction in which the first chip pad 11 and the second chip pad 12 are alternately arranged, the width of the portion of the first main terminal 241 protruding from the encapsulation resin 70 is larger than the width of the first chip pad 11. In the direction orthogonal to the direction in which the first chip pad 11 and the second chip pad 12 are alternately arranged, the width of the portion of the second main terminal 242 protruding from the encapsulation resin 70 is larger than the width of the second chip pad 12.

[0069] Thus, the semiconductor device 102 according to Embodiment 2 of the present disclosure can further increase the areas of the first main terminal 241, the second main terminal 242, and the output terminal 43 with respect to the area of the semiconductor device 102 while reliably ensuring the creepage distance between the terminals. The heat generated by the first semiconductor element 21 and the second semiconductor element 22 is released to the outside of the semiconductor device 102 via the first main terminal 241, the second main terminal 242, and the output terminal 43. Therefore, the semiconductor device 102 according to Embodiment 2 of the present disclosure can further improve the heat dissipation performance of the semiconductor device 102 by increasing the areas of the first main terminal 241, the second main terminal 242, and the output terminal 43. In addition, since the heat dissipation performance of the semiconductor device 102 is improved, the semiconductor device 102 according to Embodiment 2 of the present disclosure can further increase the energization current of the semiconductor device 102.

[0070] Embodiment 3 In Embodiment 2 of the present disclosure, the semiconductor device 102 including the output terminal 43 provided so as to protrude from the first side surface of the encapsulation resin 70, the first main terminal 241 provided so as to protrude from the second side surface of the encapsulation resin 70, and the second main terminal 242 provided so as to protrude from the third side surface of the encapsulation resin 70 has been described. In Embodiment 3 of the present disclosure, the semiconductor device 103 in which at least a part of the portions protruding from the encapsulation resin 70 is formed in a comb shape for the first main terminal 341, the second main terminal 342, and the output terminal 343 will be described. In addition, in Embodiment 3, the same reference numerals are used for the same components as those in Embodiment 1 and Embodiment 2 of the present disclosure, and the description of the same or corresponding parts is omitted. Hereinafter, with reference to the drawings, the semiconductor device 103 of Embodiment 3 will be described.

[0071] <Structure of Embodiment 3> Use Figure 6 To describe the structure of the semiconductor device 103 according to Embodiment 3 of the present disclosure. Figure 6 is a top view showing the semiconductor device 103. In addition, in Figure 6 , in order to show the structure inside the encapsulation resin 70, the representation of the encapsulation resin 70 is omitted. In addition, in Figure 6 , the outline when the encapsulation resin 70 is present is shown by a dashed line.

[0072] As Figure 6 shown, the semiconductor device 103 includes a first main terminal 341, a second main terminal 342, and an output terminal 343 in which at least a part of the portions protruding from the encapsulation resin 70 is formed in a comb shape. For example, as Figure 6As shown, the portions of the first main terminal 341, the second main terminal 342, and the output terminal 343 that protrude from the encapsulation resin 70 are polygons including one side whose shape is formed like a comb tooth when viewed from above. That is, the portions of the first main terminal 341, the second main terminal 342, and the output terminal 343 that protrude from the encapsulation resin 70 are quadrilaterals in shape when viewed from above before being formed like a comb tooth, and are formed by making one side of a plate-like member whose shape is a quadrilateral when viewed from above into a comb tooth shape.

[0073] In addition, for the first main terminal 341, the second main terminal 342, and the output terminal 343, it is sufficient that a part of the portion protruding from the encapsulation resin 70 is formed like a comb tooth. Regarding the first main terminal 341, the second main terminal 342, and the output terminal 343, it is not limited to making the entire one side of the plate-like member whose shape is a quadrilateral when viewed from above of the portion protruding from the encapsulation resin 70 into a comb tooth shape, and a part of one side can also be formed like a comb tooth. In addition, regarding the first main terminal 341, the second main terminal 342, and the output terminal 343, two or more sides of the plate-like member whose shape is a quadrilateral when viewed from above of the portion protruding from the encapsulation resin 70 can also be formed like a comb tooth. In addition, regarding the first main terminal 341, the second main terminal 342, and the output terminal 343, the shape when viewed from above of the portion protruding from the encapsulation resin 70 before being formed like a comb tooth may not be a quadrilateral, and a part of a polygon or a plate-like member having a rounded shape protruding from the encapsulation resin 70 can be formed like a comb tooth.

[0074] In addition, Figure 6 In [ ], similar to Embodiment 2, examples are shown in which the first main terminal 341, the second main terminal 342, and the output terminal 343, in which a part protruding from the encapsulation resin 70 is formed like a comb tooth, protrude from the second side surface, the third side surface, and the first side surface of the encapsulation resin 70, respectively. However, it is not limited to this, and for example, similar to Embodiment 1, the first main terminal 341, the second main terminal 342, and the output terminal 343, in which a part protruding from the encapsulation resin 70 is formed like a comb tooth, can be provided to protrude from the first side surface.

[0075] As described above, since a part of the portion of each terminal protruding from the encapsulation resin 70 is formed like a comb tooth, the contact area of each terminal with an external substrate (not shown) or external air is enlarged.

[0076] <Manufacturing Method of Embodiment 3> Next, a method for manufacturing the semiconductor device 103 according to Embodiment 3 of the present disclosure will be described. In addition, in the present embodiment, since the manufacturing processes of the semiconductor device 103 other than the processes of forming the first main terminal 341, the second main terminal 342, and the output terminal 343 can be implemented by appropriately applying known techniques, only the processes of forming the first main terminal 341, the second main terminal 342, and the output terminal 343 will be described here.

[0077] The first main terminal 341, the second main terminal 342, and the output terminal 343 are formed by punching a copper plate having conductivity and good thermal conductivity. The first main terminal 341, the second main terminal 342, and the output terminal 343 are formed, for example, by punching the copper plate into a specified shape using a die. Here, the specified shape is, for example, a polygonal shape including a comb-shaped side.

[0078] <Effects of Embodiment 3> Next, the functions and effects of the semiconductor device 103 according to Embodiment 3 of the present disclosure will be described.

[0079] The semiconductor device 103 according to Embodiment 3 of the present disclosure includes the first main terminal 341, the second main terminal 342, and the output terminal 343, in which a part of the portion protruding from the encapsulation resin 70 is formed in a comb shape.

[0080] According to the semiconductor device 103 of Embodiment 3 of the present disclosure, since at least a part of the portion of the first main terminal 341, the second main terminal 342, and the output terminal 343 protruding from the encapsulation resin 70 is formed in a comb shape, compared with Embodiment 1 and Embodiment 2, the areas of the first main terminal 341, the second main terminal 342, and the output terminal 343 in contact with an external substrate or external air (not shown) can be further enlarged. The heat generated by the first semiconductor element 21 and the second semiconductor element 22 is transferred to the external substrate or external air (not shown) via the first main terminal 341, the second main terminal 342, and the output terminal 343, and thus released to the outside of the semiconductor device 103. Therefore, according to the semiconductor device 103 of Embodiment 3 of the present disclosure, by providing the first main terminal 341, the second main terminal 342, and the output terminal 343 in which at least a part of the portion protruding from the encapsulation resin 70 is formed in a comb shape, the heat dissipation performance of the semiconductor device 103 can be further improved. In addition, according to the semiconductor device 103 of Embodiment 3 of the present disclosure, since the heat dissipation performance of the semiconductor device 103 is improved, the energization current of the semiconductor device 103 can be further increased.

[0081] Embodiment 4 In Embodiment 1 of the present disclosure, the semiconductor device 101 including the first wire 31, the second wire 32, and the third wire 33 was described. In Embodiment 4 of the present disclosure, the semiconductor device 104 in which the number of wires through which current flows frequently among the first wire 31, the second wire 32, and the third wire 33 is set to be multiple is described.

[0082] <Structure of Embodiment 4> Use Figure 7 To describe the structure of the semiconductor device 104 according to Embodiment 4 of the present disclosure. Figure 7 It is a top view showing the semiconductor device 104. In addition, in Figure 7 In order to show the structure inside the encapsulation resin 70, the representation of the encapsulation resin 70 is omitted. In addition, in Figure 7 In, the outline when the encapsulation resin 70 is present is shown by a dashed line.

[0083] As Figure 7 As shown, in the semiconductor device 104, the number of wires of the first wire 31a, which is arranged to connect between two first chip pads 11 on one end side in the direction where the first chip pads 11 and the second chip pads 12 are alternately arranged, is multiple, and the number of wires of the second wire 32a, which is arranged to connect between two second semiconductor elements 22 on the other end side in the direction where the first chip pads 11 and the second chip pads 12 are alternately arranged, is multiple, and the number of wires of the third wire 33 is multiple.

[0084] Compared with the first wire 31b arranged to connect between two first chip pads 11 on the other end side in the direction where the first chip pads 11 and the second chip pads 12 are alternately arranged and the second wire 23b arranged to connect between two second semiconductor elements 22 on one end side in the direction where the first chip pads 11 and the second chip pads 12 are alternately arranged, the first wire 31a, the second wire 32a, and the third wire 33 are wires through which current flows more frequently. Therefore, by increasing the number of the first wire 31a, the second wire 32a, and the third wire 33, the density of the current flowing in one wire can be reduced, thereby reducing the load caused by the current.

[0085] <Manufacturing Method of Embodiment 4> Since the manufacturing method of the semiconductor device 104 according to Embodiment 4 of the present disclosure is the same as the manufacturing method of the semiconductor device 101 according to Embodiment 1, the description is omitted.

[0086] <Function and Effect of Embodiment 4> Next, the functions and effects of the semiconductor device 104 according to Embodiment 4 of the present disclosure will be described.

[0087] In the semiconductor device 104 according to Embodiment 4 of the present disclosure, the number of wire elements of the first wire 31a provided to connect between two first chip pads 11 on one end side in the direction in which the first chip pads 11 and the second chip pads 12 are alternately arranged is multiple. The number of wire elements of the second wire 32a provided to connect between two second semiconductor elements 22 on the other end side in the direction in which the first chip pads 11 and the second chip pads 12 are alternately arranged in the second wire 32 included in the semiconductor device 104 is multiple. The number of wire elements of the third wire 33 included in the semiconductor device 104 is multiple.

[0088] According to the semiconductor device 104 of Embodiment 4 of the present disclosure, it is possible to reduce the current density flowing through the first wire 31a, the second wire 32a, and the third wire 33, which are wires through which current flows with a relatively high frequency, and it is possible to reduce the load caused by the current flowing through each wire. Therefore, according to the semiconductor device 104 of Embodiment 4 of the present disclosure, since the load caused by the current flowing through each wire is reduced, it is possible to suppress the deterioration of the wires and improve the power cycle life of the semiconductor device 104.

[0089] Embodiment 5 In Embodiment 4 of the present disclosure, the semiconductor device 104 in which the number of the first wire 31a, the second wire 32a, and the third wire 33, which are wires through which current flows with a relatively high frequency, is multiple was described. In Embodiment 5 of the present disclosure, the semiconductor device 105 in which the wire diameters of the first wire 31a, the second wire 32a, and the third wire 33 are thickened will be described.

[0090] <Structure of Embodiment 5> Use Figure 8 The structure of the semiconductor device 105 according to Embodiment 5 of the present disclosure will be described. Figure 8 is a top view showing the semiconductor device 105. In addition, in Figure 8 , in order to show the structure inside the encapsulation resin 70, the representation of the encapsulation resin 70 is omitted. Further, in Figure 8 , the outline when the encapsulation resin 70 is present is shown by a dashed line.

[0091] As Figure 8As shown, in the semiconductor device 105, compared with the first wire 31b connected between two first chip pads 11 on the other end side in the direction where the first chip pads 11 and the second chip pads 12 are alternately arranged, and the second wire 32b connected between two second semiconductor elements 22 on one end side in the direction where the first chip pads 11 and the second chip pads 12 are alternately arranged, the wire diameter of the first wire 31a connected between two first chip pads 11 on one end side in the direction where the first chip pads 11 and the second chip pads 12 are alternately arranged in the first wire 31, the second wire 32a arranged to connect two second semiconductor elements 22 on the other end side in the direction where the first chip pads 11 and the second chip pads 12 are alternately arranged in the second wire 32, and the third wire is thicker.

[0092] Also as described in Embodiment 4, compared with the first wire 31b and the second wire 32b, the first wire 31a, the second wire 32a, and the third wire 33 are wires through which current flows more frequently. Therefore, by thickening the wire diameters of the first wire 31a, the second wire 32a, and the third wire 33, the density of the current flowing in the wire can be reduced, thereby reducing the load caused by the current.

[0093] <Manufacturing method of Embodiment 5> Since the manufacturing method of the semiconductor device 105 according to Embodiment 5 of the present disclosure is the same as the manufacturing method of the semiconductor device 101 according to Embodiment 1, the description is omitted.

[0094] <Function and effect of Embodiment 5> Next, the functions and effects of the semiconductor device 105 according to Embodiment 5 of the present disclosure will be described.

[0095] Compared with the first wire 31b connected between two first chip pads 11 on the other end side in the direction where the first chip pads 11 and the second chip pads 12 are alternately arranged in the first wire 31 included in the semiconductor device 105 according to Embodiment 5 of the present disclosure, and the second wire 32b connected between two second semiconductor elements 22 on one end side in the direction where the first chip pads 11 and the second chip pads 12 are alternately arranged in the second wire 32 included in the semiconductor device 105, the wire diameter of the first wire 31a connected between two first chip pads 11 on one end side in the direction where the first chip pads 11 and the second chip pads 12 are alternately arranged, the second wire 32a arranged to connect two second semiconductor elements 22 on the other end side in the direction where the first chip pads 11 and the second chip pads 12 are alternately arranged, and the third wire is thicker.

[0096] For the semiconductor device 105 according to Embodiment 5 of the present disclosure, it is possible to reduce the current density flowing through the first wire 31a, the second wire 32a, and the third wire 33, which are wires with a relatively high frequency of current flow, and reduce the load caused by the current flowing through each wire. Therefore, for the semiconductor device 105 according to Embodiment 5 of the present disclosure, since the load caused by the current flowing through each wire is reduced, it is possible to suppress the deterioration of the wire and improve the power cycle life of the semiconductor device 105.

[0097] As described above, the present disclosure has been described based on each embodiment, but the present disclosure is not limited to each embodiment. In addition, as needed, appropriate combination, deformation, or omission of various embodiments are also included in the technical idea scope of the present disclosure. Symbol Explanation

[0098] 11 First chip pad; 12 Second chip pad; 21 First semiconductor element; 22 Second semiconductor element; 31 First wire; 32 Second wire; 33 Third wire; 34 Fourth wire; 41 First main terminal; 42 Second main terminal; 43 Output terminal; 51 Third chip pad; 52 Control integrated circuit; 53 Fifth wire; 54 Control terminal; 60 Insulating sheet; 70 Encapsulation resin.

Claims

1. A semiconductor device, comprising: At least three first chip pads; At least three first semiconductor elements, with at least three of the first semiconductor elements respectively mounted on the first chip pads; A first wire, which electrically connects the first semiconductor elements respectively; At least three second chip pads, with at least three of the second chip pads arranged alternately with the first chip pads; At least three second semiconductor elements, with at least three of the second semiconductor elements respectively mounted on the second chip pads; and A second wire, which electrically connects the second semiconductor elements respectively.

2. The semiconductor device according to claim 1, wherein It further includes: A first main terminal, which extends from the first chip pad on one end side in the direction where the first chip pads and the second chip pads are arranged alternately among the first chip pads; A second main terminal, which is arranged on the other end side in the direction where the first chip pads and the second chip pads are arranged alternately; At least three output terminals, with at least three of the output terminals extending from at least three of the second chip pads; And A packaging resin, which packages the first chip pads, the second chip pads, the first semiconductor elements, the second semiconductor elements, the first wire, the second wire, a part of the first main terminal, a part of the second main terminal, and a part of the output terminals.

3. The semiconductor device according to claim 2, wherein The shape of the packaging resin when viewed from above is a quadrilateral, The first main terminal, the second main terminal, and the output terminals are arranged to protrude from a first side surface of the packaging resin. The first side surface of the packaging resin includes a first side, and the first side is the side among the sides of the packaging resin when viewed from above that extends in the direction where the first chip pads and the second chip pads are arranged alternately.

4. The semiconductor device according to claim 2, wherein The shape of the packaging resin when viewed from above is a quadrilateral, The output terminals are arranged to protrude from a first side surface of the packaging resin. The first side surface of the packaging resin includes a first side, and the first side is the side among the sides of the packaging resin when viewed from above that extends in the direction where the first chip pads and the second chip pads are arranged alternately, The first main terminal is arranged to protrude from a second side surface of the packaging resin. The second side surface of the packaging resin includes a second side, and the second side is the side among the sides of the packaging resin when viewed from above that is on the one end side in the direction where the first chip pads and the second chip pads are arranged alternately, The second main terminal is arranged to protrude from a third side surface of the packaging resin. The third side surface of the packaging resin includes a third side, and the third side is the side among the sides of the packaging resin when viewed from above that is on the other end side in the direction where the first chip pads and the second chip pads are arranged alternately.

5. The semiconductor device according to claim 4, wherein In the direction in which the first chip pad and the second chip pad are alternately arranged, the width of the portion of the output terminal protruding from the encapsulation resin is greater than the width of the second chip pad. In the direction in which the first chip pad and the second chip pad are alternately arranged, the width of the portion of the first main terminal protruding from the encapsulation resin is greater than the width of the first chip pad. In the direction orthogonal to the direction in which the first chip pad and the second chip pad are alternately arranged, the width of the portion of the second main terminal protruding from the encapsulation resin is greater than the width of the second chip pad.

6. The semiconductor device according to any one of claims 2 to 5, characterized in that At least a part of the portions of the first main terminal, the second main terminal, and the output terminal protruding from the encapsulation resin is formed in a comb shape.

7. The semiconductor device according to any one of claims 2 to 5, characterized in that The semiconductor device further includes a third wire, and the third wire electrically connects the second main terminal and the second semiconductor element. The first wire is provided in such a manner as to connect between two of the first chip pads adjacent to each other with the second chip pad interposed therebetween. The second wire is provided in such a manner as to connect between two of the second semiconductor elements respectively mounted on two of the second chip pads adjacent to each other with the first chip pad interposed therebetween. The third wire is provided in such a manner as to connect between the second semiconductor element of the second chip pad disposed on the other end side in the direction in which the first chip pad and the second chip pad are alternately arranged and the second main terminal.

8. The semiconductor device according to claim 7, characterized in that The number of wires of the first wire provided in such a manner as to connect between two of the first chip pads on the one end side in the direction in which the first chip pad and the second chip pad are alternately arranged, the second wire provided in such a manner as to connect between two of the second semiconductor elements on the other end side in the direction in which the first chip pad and the second chip pad are alternately arranged, and the third wire is plural.

9. The semiconductor device according to claim 7, characterized in that Compared with the first wire provided in such a manner as to connect between two of the first chip pads on the other end side and the second wire provided in such a manner as to connect between two of the second semiconductor elements on the one end side, the wire diameters of the first wire provided in such a manner as to connect between two of the first chip pads on the one end side in the direction in which the first chip pad and the second chip pad are alternately arranged, the second wire provided in such a manner as to connect between two of the second semiconductor elements on the other end side in the direction in which the first chip pad and the second chip pad are alternately arranged, and the third wire are thicker.

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