QFN packaging structure and manufacturing method thereof

Abstract

The invention discloses a QFN packaging structure and a manufacturing method thereof, the manufacturing method is characterized in that a second pin is arranged on a second side and / or a fourth side, the second pin comprises a boss and an extension part located on the boss and connected with the boss, the boss is located on the second side and / or the fourth side, and the extension part is located on the second side and / or the fourth side; the extension part extends from the side where the boss is located to the direction of a second chip mounted on the second base island, and the second pin is used as an adapter pin when the second chip mounted on the front face of the second base island is electrically connected with a first chip mounted on the front face of the first base island and / or a first pin on the first side. The second bonding pad on the front surface of the second chip is electrically connected with the front surface of the extension part of the corresponding second pin through a first bonding wire, and the front surface of the extension part of the second pin is electrically connected with the corresponding first bonding pad and / or the corresponding first pin on the front surface of the first chip through a second bonding wire. According to the invention, the risk of wire collapse caused by overlong bonding wires can be prevented.

Description

Technical Field

[0001] This application relates to the field of packaging technology, and particularly to a QFN packaging structure and a manufacturing method thereof. Background Art

[0002] QFN (Quad Flat No-lead, quad flat no-pin package) packaging occupies a large proportion in the packaging market due to its excellent heat dissipation, high packaging efficiency, and extremely low impedance and self-inductance. QFN packaging has the advantages of mature technology, low cost, and good thermoelectric performance. With the accelerating trend of semiconductor devices towards functionalization and miniaturization, the development demand for QFN packaging will also expand accordingly.

[0003] Existing QFN packaging has evolved from single-base islands to double-base islands to meet the voltage requirements between different chips. However, in the existing QFN packaging with a double-base island structure, due to the large distance between the two base islands (especially for high-voltage chips, in order to prevent the influence of high voltage on the chips, the distance requirement between the two base islands will be even greater), when the chips mounted on one base island are electrically connected to the chips on the other base island through bonding wires or are electrically connected to the pins through bonding wires across the other base island, it is required that the length of the bonding wires is relatively long, thus there is a high risk of bonding wire collapse. Summary of the Invention

[0004] The purpose of this application is to provide a QFN packaging structure and a manufacturing method thereof, which can prevent the collapse of bonding wires or reduce the risk of bonding wire collapse while meeting the voltage distance requirements. To achieve the above purpose, on the one hand, an embodiment of this application provides a QFN packaging structure, including: A first side, a second side, a third side, and a fourth side, where the first side and the third side are oppositely arranged, and the second side and the fourth side are oppositely arranged; A plurality of discrete first pins located on the first side and arranged in sequence along the extension direction of the first side; A second base island located on the third side; A first base island located between the second base island and the first pins and close to the first pins; A first chip and a second chip, the back surface of the first chip is mounted on the front surface of the first base island, the front surface of the first chip has a plurality of discrete first pads, the back surface of the second chip is mounted on the front surface of the second base island, and the front surface of the second chip has a plurality of discrete second pads; At least one second pin located on the second side and / or the fourth side, the second pin including a boss and an extension portion connected to and located on the boss, the boss being located on the second side and / or the fourth side, the extension portion extending from the side where the boss is located towards the second chip mounted on the second base island, and the shortest straight-line distance between the back edge of the boss and the back edge of the second base island being greater than or equal to a preset value, and the shortest straight-line distance between the back edge of the first base island and the back edge of the second base island being greater than or equal to the preset value, the preset value meeting the voltage distance requirement between the first chip and the second chip; A first wire bonding wire electrically connecting a part of the second pads on the second chip to the extension portion of the second pin, a second wire bonding wire electrically connecting the second pin to a part of the first pads and / or a part of the first pins on the first side of the first chip, and a third wire bonding wire electrically connecting a part of the first pads and a part of the first pins on the first chip.

[0005] In some embodiments, it further includes: a plastic encapsulation layer covering the first base island, the second base island, the first pins, the second pins, the first chip, the second chip, the first wire bonding wire, the second wire bonding wire, and the third wire bonding wire, the back surface of the plastic encapsulation layer exposing the back surfaces of the first base island, the second base island, the back surfaces of the first pins, and the back surface of the boss of the second pin.

[0006] In some embodiments, the preset value is greater than or equal to 3 mm.

[0007] In some embodiments, there are two discrete second pins on the second side or the fourth side, both the first wire bonding wire and the second wire bonding wire have multiple strands, a part of the first wire bonding wires electrically connect a part of the second pads on the second chip to the extension portion of one of the second pins, and a part of the second wire bonding wires electrically connect this second pin to a part of the first pads on the first chip; another part of the first wire bonding wires electrically connect another part of the second pads on the second chip to the extension portion of the other second pin, and another part of the second wire bonding wires electrically connect this second pin to a part of the first pins on the first side.

[0008] In some embodiments, both the second side and the fourth side each have at least one second pin. The first bonding wire and the second bonding wire each have multiple strands. A part of the first bonding wires electrically connect a part of the second pads on the second chip to an extension of the second pins on the fourth side, and a part of the second bonding wires electrically connect the second pins on the fourth side to a part of the first pads and / or the first pins on the first chip; Another part of the first bonding wires electrically connect another part of the second pads on the second chip to an extension of the second pins on the second side, and another part of the second bonding wires electrically connect the second pins on the second side to a part of the first pads on the first chip and / or the first pins on the first side.

[0009] In some embodiments, it further includes: a third chip, a fourth bonding wire, and a fifth bonding wire. The back surface of the third chip is mounted on the front surface of the second base island on the side of the second chip away from the fourth side. The front surface of the third chip has several discrete third pads; both the second side and the fourth side each have at least one second pin; A part of the second pads on the second chip are electrically connected to an extension of the second pins on the fourth side through the first bonding wires, and the second pins on the fourth side are electrically connected to a part of the first pads and / or part of the first pins on the first chip through the second bonding wires; A part of the third pads on the third chip are electrically connected to an extension of the second pins on the second side through the fourth bonding wires, and the second pins on the second side are electrically connected to a part of the first pads and / or part of the first pins on the first side through the fifth bonding wires.

[0010] In some embodiments, the total thickness of the boss and the extension in the second pins is equal to the thickness of the first pins.

[0011] In some embodiments, the boss is located at a position on the second side and / or the fourth side close to the first side.

[0012] On the other hand, an embodiment of the present application further provides a manufacturing method for a QFN package structure, including: A lead frame is provided. The lead frame includes a plurality of frame unit regions and connecting ribs connecting adjacent frame unit regions. Each of the frame unit regions includes a first side, a second side, a third side, and a fourth side. The first side and the third side are oppositely arranged, and the second side and the fourth side are oppositely arranged. A plurality of discrete first pins are located on the first side and arranged in sequence along the extending direction of the first side. A second base island is located on the third side. A first base island is located between the second base island and the first pins and close to the first pins. At least one second pin is located on the second side and / or the fourth side. The second pin includes a boss and an extension portion connected to the boss on the boss. The boss is located on the second side or the fourth side. The extension portion extends from the second side or the fourth side where the boss is located towards the direction where the second chip is mounted on the second base island. And the linear distance between the back edge of the boss and the back edge of the second base island is greater than or equal to a preset value, and the preset value meets the voltage distance requirement between the first chip and the second chip. A plurality of first chips and a plurality of second chips are provided. The front surface of the first chip has a plurality of discrete first pads, and the front surface of the second chip has a plurality of discrete second pads. The back surface of the first chip is mounted on the front surface of the first base island in the corresponding frame unit region, and the back surface of the second chip is mounted on the front surface of the second base island in the corresponding frame unit region. A first bonding wire is formed to electrically connect some of the second pads on the second chip to the extension portion of the second pin. A second bonding wire is formed to electrically connect the second pin to some of the first pads on the first chip and / or some of the first pins on the first side. A third bonding wire is formed to electrically connect some of the first pads and some of the first pins on the first chip.

[0013] In some embodiments, it further includes: forming a plastic encapsulation layer covering the first base island, the second base island, the first pins, the second pins, the first bonding wire, the second bonding wire, and the third bonding wire. The back surface of the plastic encapsulation layer exposes the back surfaces of the first base island, the second base island, the back surfaces of the first pins, and the back surface of the boss of the second pin. The connecting ribs are cut to form a plurality of discrete packaging structures.

[0014] In some embodiments, it further includes: providing a third chip, the front surface of which has a number of discrete third pads; mounting the back surface of the third chip on the front surface of a second base island on a side of the second chip away from the fourth side; both the second side and the fourth side each have at least one second pin; a part of the second pads on the second chip is electrically connected to an extension of the second pin on the fourth side through the first bonding wire, and the second pin on the fourth side is electrically connected to a part of the first pads and / or a part of the first pins on the first chip through a second bonding wire; forming a fourth bonding wire that electrically connects a part of the third pads on the third chip to an extension of the second pin on the second side, and forming a fifth bonding wire that electrically connects the second pin on the second side to a part of the first pads on the first chip and / or a part of the first pins on the first side.

[0015] Advantages of the present application: The QFN package structure and its manufacturing method of the present application, by providing second pins with a specific structure at a specific position (the second side and / or the fourth side) (the second pin includes a boss and an extension connected to the boss, the boss is located on the second side or the fourth side, and the extension extends from the second side or the fourth side where the boss is located towards the direction where the second chip is mounted on the second base island), using the second pin as a transfer pin when electrically connecting the second chip mounted on the front surface of the second base island to the first chip mounted on the front surface of the first base island and / or the first pins on the first side. Specifically, the second pads on the front surface of the second chip are electrically connected to the front surface of the corresponding extension of the second pin through the first bonding wire, and the front surface of the extension of the second pin is electrically connected to the corresponding first pads and / or the corresponding first pins on the front surface of the first chip through the second bonding wire, thereby preventing the risk of wire collapse caused by too long bonding wires when the second chip is directly electrically connected to the first chip and / or the first pins. At the same time, the linear distance between the back edge of the boss and the back edge of the second base island, and the linear distance between the back edge of the first base island and the back edge of the second base island both meet the voltage distance requirements between the first chip and the second chip, especially the voltage distance requirements under high voltages. Description of the drawings Figure 1 is a top view structural schematic diagram of the QFN package structure in some embodiments of the present application; Figure 2 is along Figure 1 the cutting line AA1 in Figure 3 is along Figure 1 the cutting line AA2 in Figure 4 is along Figure 1The schematic cross-sectional structure diagram is obtained in the direction of the cutting line A1A2; Figures 5 - 7 is Figures 2 - 3 The schematic structure diagram after encapsulating the plastic sealing layer on the basis of; Figure 8 This is the top view structure diagram of the QFN package structure in some other embodiments of the present application; Figure 9 This is the top view structure diagram of the QFN package structure in some other embodiments of the present application. Detailed implementation manners

[0016] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0017] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without conflict, those skilled in the art can combine the different embodiments or examples described in this specification and the features of the different embodiments or examples.

[0018] One aspect of the embodiments of the present application provides a QFN package structure. Figure 1 This is the top view structure diagram of the QFN package structure in some embodiments of the present application; Figure 2 is along Figure 1 The schematic cross-sectional structure diagram is obtained in the direction of the cutting line AA1 in; Figure 3 is along Figure 1 The schematic cross-sectional structure diagram is obtained in the direction of the cutting line AA2 in; Figure 4 is along Figure 1 The schematic cross-sectional structure diagram is obtained in the direction of the cutting line A1A2 in; Figures 5 - 7 is Figures 2 - 3 The schematic structure diagram after encapsulating the plastic sealing layer on the basis of.

[0019] Refer to Figure 1 and in combination with reference to Figures 2 - 4 The QFN package structure includes: a first side 11, a second side 12, a third side 13 and a fourth side 14, wherein the first side 11 and the third side 13 are oppositely arranged, and the second side 12 and the fourth side 14 are oppositely arranged; a plurality of discrete first pins 103 located on the first side 11 and arranged in sequence along the extending direction of the first side 11; a second base island 102 located on the third side 13; a first base island 101 located between the second base island 102 and the first pins 103 and close to the first pins 103; a first chip 201 and a second chip 202, wherein the back surface of the first chip 201 is mounted on the front surface of the first base island 101, the front surface of the first chip 201 has a plurality of discrete first pads 204, the back surface of the second chip 202 is mounted on the front surface of the second base island 102, and the front surface of the second chip 202 has a plurality of discrete second pads 205; at least one second pin 104 located on the second side 12 and / or the fourth side 14, the second pin 104 includes a boss 105 and an extension portion 106 connected to the boss 105 and located on the boss 105, the boss 105 is located on the second side 12 and / or the fourth side 14, the extension portion 106 extends from the side where the boss 105 is located towards the second chip 202 mounted on the second base island 102, and the shortest straight-line distance D (reference Figure 4 ) between the back edge of the boss 105 and the back edge of the second base island 102 is greater than or equal to a preset value, and the shortest straight-line distance between the back edge of the first base island and the back edge of the second base island is greater than or equal to the preset value, and the preset value meets the voltage distance requirement between the first chip 201 and the second chip 202; a first bonding wire 107 for electrically connecting some of the second pads 205 on the second chip 202 to the extension portion 106 of the second pin 104, a second bonding wire 108 for electrically connecting the second pin 104 to some of the first pads 204 on the first chip 201 and / or some of the first pins 103 on the first side 11, and a third bonding wire 109 for electrically connecting some of the first pads 204 and some of the first pins 103 on the first chip 201.

[0020] In some embodiments, the bottom surface of the packaging structure is square, specifically, it can be a square or a rectangle, and the first side 11, the second side 12, the third side 13 and the fourth side 14 can correspond to the four sides of the square, wherein the first side 11 and the second side 12 are two opposite and parallel sides of the square, and the third side 13 and the fourth side 14 are the other two opposite and parallel sides of the square.

[0021] The second base island 102 is located on one side of the first base island 101, and the second base island 102 is located on the third side 13. The first base island 101 is located between the second base island 102 and the first pin 103 and is close to the first pin 103. Both the first base island 101 and the second base island 102 include opposite front and back surfaces. The front surfaces of the first base island 101 and the second base island 102 are used for mounting and supporting chips, and the back surfaces of the first base island 101 and the second base island 102 can be used for heat dissipation of the QFN package structure.

[0022] In some embodiments, the first chip 201 is mounted on the front surface of the first base island 101, and the second chip 202 can be mounted on the front surface of the second base island 202. In some embodiments, the third chip 203 can also be mounted on the front surface of the second base island 202. The first chip 201, the second chip 202, and the third chip 203 all include opposite front and back surfaces. The front surface of the first chip 201 has a plurality of discrete first pads 204. The back surface of the first chip 201 is mounted on the front surface of the first base island 101. In a specific example, the back surface of the first chip 201 is mounted on the front surface of the first base island 101 through an adhesive 210 (reference Figure 2 or Figure 3 ). The front surface of the second chip 202 has a plurality of discrete second pads 205. The back surface of the second chip 202 is mounted on the front surface of the second base island 102. In a specific example, the back surface of the second chip 202 is mounted on the front surface of the second base island 102 through an adhesive 211 (reference Figure 3 ) mounted on the front surface of the second base island 102.

[0023] There is a gap 110 between the first base island 101 and the second base island 102, and the shortest straight-line distance between the back edge of the first base island 101 and the back edge of the second base island 102 is greater than or equal to the preset value, and the preset value meets the voltage distance requirement between the first chip 201 and the second chip 202 (the voltage distance requirement is: at a certain voltage (including a high voltage, the high voltage is greater than 20V), to prevent electrical short circuit and creepage between the first chip 201 and the second chip 202, and ensure the safety and reliability of the chip, the minimum value of the straight-line distance between the back edge of the first base island 101 and the back edge of the second base island 102), so that the distance between the first base island 101 and the second base island 102 meets the voltage distance requirement between the first chip 201 mounted on the first base island 101 and the second chip 202 mounted on the second base island 102, and prevent the performance of the first chip 201 and the second chip 202 from being affected by the relatively close distance between the first base island 101 and the second base island 102 (for example, when the first chip 201 and the second chip 202 are high-voltage devices, there is a voltage distance requirement for the first chip 201 and the second chip 202 at a high voltage (the high voltage is greater than 20V), that is, there is a minimum distance requirement for the exposed back entity part of the first base island 102 and the exposed back entity part of the second base island 102 in the QFN package structure. If the shortest straight-line distance between the back edge of the first base island 101 and the back edge of the second base island 102 is less than the minimum distance, the high voltage will affect the first chip 201 and the second chip 202 (for example, electrical short circuit and / or creepage phenomena will occur, reducing safety and reliability), affecting the performance of the first chip 201 and the second chip 202). In some embodiments, the preset value is greater than or equal to 3mm, and specifically can be 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 5.1mm, 5.2mm, 5.3mm, 5.4 mm or 5.5mm.

[0024] In some embodiments, referring to Figures 3 - 4 , the back edges of the first base island 101, the second base island 102 and the first pin 103 may have a stepped structure (it should be noted that the stepped structure of the back edge of the first pin 103 is located at the back edge of the first pin 103 close to the first side 13, Figures 3 - 4 not shown in), so as to increase the contact area between the first base island 101, the second base island 102 and the first pin 103 and the plastic encapsulation layer covering the QFN package structure, thereby increasing the adhesion force and preventing delamination of the plastic encapsulation layer.

[0025] The plurality of first pins 103 are discrete from each other. The plurality of discrete first pins 103 are located on the first side 11 and are arranged in sequence along the extending direction of the first side 11. Each of the first pins 103 includes an opposite front surface and back surface. The front surfaces of some of the first pins 103 are electrically connected to corresponding first pads 204 on the front surface of the first chip 201 through third bonding wires 109. The front surfaces of some of the first pins 103 are electrically connected to the front surfaces of the extending portions 106 of the corresponding second pins 104 through some of the second bonding wires 108. The back surface of the first pin 103 serves as a terminal when the QFN package structure is connected to other substrates or devices. The second pin 104 serves as a transfer pin when the second chip 202 (and the third chip 203) is electrically connected to the first chip 201 and / or the first pin 103, preventing the risk of wire collapse caused by too long bonding wires when the second chip 202 (and the third chip 203) is directly electrically connected to the first chip 201 and / or the first pin 103. Specifically, the second pads 205 on the front surface of the second chip 202 are electrically connected to the front surfaces of the extending portions 106 of the corresponding second pins 104 through first bonding wires 107. The front surfaces of the extending portions 106 of the second pins 104 are electrically connected to the corresponding first pads 204 on the front surface of the first chip 201 and / or the corresponding first pins 103 through second bonding wires 108. The third pads 206 on the front surface of the third chip 203 are electrically connected to the front surfaces of the extending portions 106 of the corresponding second pins 104 through fourth bonding wires 120. The front surfaces of the extending portions 106 of the second pins 104 are electrically connected to the corresponding first pads 204 on the front surface of the first chip 201 and / or the corresponding first pins 103 through fifth bonding wires 121.

[0026] In some embodiments, there are a plurality of semi-etched grooves 117 in the front surface of the first base island 101. The depth of the grooves 117 is less than the thickness of the first base island 101. There are a plurality of semi-etched grooves 116 in the front surface of the second base island 102. The depth of the grooves 116 is less than the thickness of the second base island 102. The shapes of the grooves 116 and the grooves 117 can be "X" shaped. Through the grooves 117 and the grooves 116, the contact area between the formed encapsulation layer and the first base island 101 and the second base island 102 can be increased, thereby increasing the adhesion between the encapsulation layer and the first base island 101 and the second base island 102 and preventing delamination.

[0027] The second pins 104 are disposed on the second side 12 and / or the fourth side 14. Specifically, in some embodiments, the second pins 104 are only disposed on the second side 12. In another embodiment, the second pins 104 are only disposed on the fourth side 14. In another embodiment, the second pins 104 can be disposed on both the second side 12 and the fourth side 14.

[0028] The second pin 104 includes a boss 105 and an extension 106 connected to the boss 105 and located on the boss 105. The boss 105 is located on the second side 12 and / or the fourth side 14. The extension 106 extends from the side where the boss 105 is located towards the second chip 202 mounted on the second base island 102. And the shortest straight-line distance D (reference Figure 4 )between the back edge of the boss 105 and the back edge of the second base island 102 is greater than or equal to a preset value. The preset value meets the voltage distance requirement between the first chip 201 and the second chip 202 (the voltage distance requirement is: at a certain voltage (including a high voltage, the high voltage is greater than 20V), to prevent electrical short-circuit and creepage phenomena between the first chip 201 and the second chip 202, and to ensure the safety and reliability of the chips, the minimum value of the straight-line distance between the back edge of the boss 105 and the back edge of the second base island 102). In some embodiments, the preset value is greater than or equal to 3mm, and specifically can be 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 5.1mm, 5.2mm, 5.3mm, 5.4 mm or 5.5mm. In this application, by setting the second pin 104 with a specific structure at a specific position (the second side 12 and / or the fourth side 14), the second pin 104 is used as a transfer pin when the second chip 202 (and the third chip 203) is electrically connected to the first chip 201 and / or the first pin 103. Specifically, the second pad 205 on the front of the second chip 202 is electrically connected to the front of the corresponding extension 106 of the second pin 104 through the first bonding wire 107. The front of the extension 106 of the second pin 104 is electrically connected to the corresponding first pad 204 on the front of the first chip 201 and / or the corresponding first pin 103 through the second bonding wire 108. The third pad 206 on the front of the third chip 203 is electrically connected to the front of the corresponding extension 106 of the second pin 104 through the fourth bonding wire 120. The front of the extension 106 of the second pin 104 is electrically connected to the corresponding first pad 204 on the front of the first chip 201 and / or the corresponding first pin 103 through the fifth bonding wire 121, thereby preventing the risk of wire collapse caused by too long bonding wires when the second chip 202 (and the third chip 203) is directly electrically connected to the first chip 201 and / or the first pin 103. At the same time, the shortest straight-line distance between the back edge of the boss 105 and the back edge of the second base island 102, and the shortest straight-line distance between the back edge of the first base island 101 and the back edge of the second base island 102 both meet the voltage distance requirement between the first chip 201 and the second chip 202, especially the voltage distance requirement under high voltage.

[0029] In some embodiments, continue to refer to Figure 2, the total thickness of the boss 105 and the extension 106 in the second pin 104 is equal to the thickness of the first pin 103. In some embodiments, continuing to refer to Figure 1 , the boss 105 is located on the second side 12 or on the fourth side 14 near the first side 11, so that the shortest straight-line distance between the back edge of the boss 105 and the back edge of the second base island 102 can more easily meet the voltage distance requirement, especially the voltage distance requirement under high voltage.

[0030] In some embodiments, continuing to refer to Figure 1, the first chip 201 is surface-mounted on the front of the first base island 101, the second chip 202 and the third chip 203 are surface-mounted on the front of the second base island 102, and the back of the third chip 203 is surface-mounted on the front of the second base island 102 on the side of the second chip 202 away from the fourth side 14; both the second side 12 and the fourth side 14 have at least one second pin 104, for example, both the second side 12 and the fourth side 14 have one second pin 104 or two or more second pins 104, and there is a gap 113 between adjacent second pins 104, and the gap 113 communicates with the gap 110; a part of the second pads 205 on the second chip 202 is electrically connected to the extension 106 of the second pin 104 on the fourth side 14 through the first bonding wire 107, and the second pin 104 on the fourth side 14 is electrically connected to a part of the first pads 204 and / or a part of the first pins 103 on the first chip 201 through the second bonding wire 108. In a specific example, when the fourth side 14 has two second pins 104, both the first bonding wire 107 and the second bonding wire 108 have multiple strands. A part of the first bonding wire 107 electrically connects a part of the second pads 205 on the second chip 202 to the extension 106 of the second pin 104 on the fourth side 14, and a part of the second bonding wire 108 electrically connects the second pin 104 on the fourth side 14 to a part of the first pads 204 and / or the first pins 103 on the first chip 201; another part of the first bonding wire 107 electrically connects another part of the second pads 205 on the second chip 202 to the extension 106 of the second pin 104 on the second side 12, and another part of the second bonding wire 108 electrically connects the second pin 104 on the second side 12 to a part of the first pads 204 and / or the first pins 103 on the first side 11 of the first chip 201. A part of the third pads 206 on the third chip 203 is electrically connected to the extension 106 of the second pin 104 on the second side 12 through the fourth bonding wire 120, and the second pin 104 on the second side 12 is electrically connected to a part of the first pads 204 and / or a part of the first pins 103 on the first side 11 of the first chip 201 through the fifth bonding wire 121.In a specific example, when the second side 12 has two second pins 104, the third bonding wires 120 and the fifth bonding wires 121 are multiple. A part of the third pads 206 on the third chip 203 are electrically connected to an extension 106 of one of the second pins 104 on the second side 12 through a part of the fourth bonding wires 120, and this second pin 104 is electrically connected to a part of the first pads 204 on the first chip 201 and / or a part of the first pins 103 on the first side 11 through a part of the fifth bonding wires 121; Another part of the third pads 206 on the third chip 203 are electrically connected to an extension 106 of the other second pin 104 on the second side 12 through another part of the fourth bonding wires 120, and this second pin 104 is electrically connected to another part of the first pads 204 on the first chip 201 and / or another part of the first pins 103 on the first side 11 through another part of the fifth bonding wires 121.

[0031] In other embodiments, referring to Figure 8 , only the second chip 202 is mounted on the front surface of the second base island 102. Both the second side 12 and the fourth side 14 have at least one second pin 104. For example, two second pins are provided on both the second side 12 and the fourth side 14. The first bonding wires 107 and the second bonding wires 108 are multiple. A part of the first bonding wires 107 electrically connect a part of the second pads 205 on the second chip 202 to an extension 106 of the second pin 104 on the fourth side 14. A part of the second bonding wires 108 electrically connect the second pin 104 on the fourth side 14 to a part of the first pads 204 on the first chip 201 and / or the first pins 103; Another part of the first bonding wires 107 electrically connect another part of the second pads 205 on the second chip 202 to an extension 106 of the second pin 104 on the second side 12. Another part of the second bonding wires 108 electrically connect the second pin 104 on the second side 12 to a part of the first pads 204 on the first chip 201 and / or the first pins 103 on the first side 11.

[0032] In other embodiments, referring to Figure 9 , only the second chip 202 is mounted on the front surface of the second base island 102. There are two discrete second pins 104 on the second side 12 or the fourth side 14 ( Figure 9Taking, as an example, the two discrete second pins 104 on the fourth side 14, there are multiple first bonding wires 107 and second bonding wires 108. A part of the first bonding wires 107 electrically connect a part of the second pads 205 on the second chip 202 to an extension 106 of one of the second pins 104, and a part of the second bonding wires 108 electrically connect the second pin 104 to a part of the first pads 204 on the first chip 201; Another part of the first bonding wires 107 electrically connect another part of the second pads 205 on the second chip 202 to an extension 106 of another second pin 104, and another part of the second bonding wires 108 electrically connect the second pin 104 to the first pin 103 on a part of the first side 11.

[0033] In some embodiments, referring to Figures 5 - 7 , Figures 5 - 7 is Figures 2 - 3 a schematic structural diagram after encapsulating the plastic encapsulation layer on the basis of, further including: a plastic encapsulation layer 118 covering the first base island 101, the second base island 102, the first pin 103, the second pin 104, the first chip 201, the second chip 202, the first bonding wire 107, the second bonding wire 108 and the third bonding wire 109. The back surface of the plastic encapsulation layer 118 exposes the back surfaces of the first base island 101, the second base island 102, the back surface of the first pin 103 and the back surface of the boss 105 of the second pin 104. The side surfaces of the plastic encapsulation layer 118 expose the corresponding side surfaces of the first pin 103 and the second pin 104. In some embodiments, the plastic encapsulation layer 118 may include a first plastic encapsulation layer filled between the first base island 101, the second base island 102, the first pin 103, and the second pin 104; and a second plastic encapsulation layer located on the first plastic encapsulation layer covering the first chip 201, the second chip 202, the first bonding wire 107, the second bonding wire 108 and the third bonding wire 109. The first plastic encapsulation layer is formed before mounting the first chip 201 and the second chip 202. In some embodiments, the material of the plastic encapsulation layer 118 may include epoxy resin containing fillers, polyimide resin, benzocyclobutene resin or polybenzoxazole resin; or may also include polybutylene terephthalate containing fillers, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol. In some embodiments, the filler may include inorganic filler or organic filler.

[0034] Another aspect of the embodiments of the present application further provides a manufacturing method of a QFN package structure, referring to Figure 1 and in combination with reference to Figures 2 - 3 , including: A lead frame is provided. The lead frame includes a plurality of frame unit regions and connecting ribs connecting adjacent frame unit regions. Each of the frame unit regions includes a first side 11, a second side 12, a third side 13, and a fourth side 14. The first side 11 and the third side 13 are disposed opposite to each other, and the second side 12 and the fourth side 14 are disposed opposite to each other. A plurality of discrete first pins 103 are located on the first side 11 and arranged in sequence along the extending direction of the first side 11. A second base island 102 is located on the third side 13. A first base island 101 is located between the second base island 102 and the first pins 103 and close to the first pins 103. At least one second pin 104 is located on the second side 12 and / or the fourth side 14. The second pin 104 includes a boss 105 and an extension 106 connected to the boss 105 on the boss 105. The boss 105 is located on the second side 12 or the fourth side 14. The extension 106 extends from the second side 12 or the fourth side 14 where the boss 105 is located towards the direction where the second chip 202 is mounted on the second base island 102. And the linear distance between the back edge of the boss 105 and the back edge of the second base island 102 is greater than or equal to a preset value, and the preset value meets the voltage distance requirement between the first chip 201 and the second chip 202. A plurality of first chips 201 and a plurality of second chips 202 are provided. The front surface of the first chip 201 has a plurality of discrete first pads 204, and the front surface of the second chip 202 has a plurality of discrete second pads 205. The back surface of the first chip 201 is mounted on the front surface of the first base island 101 in the corresponding frame unit region, and the back surface of the second chip 202 is mounted on the front surface of the second base island 102 in the corresponding frame unit region. A first bonding wire 107 is formed to electrically connect some of the second pads 205 on the second chip 202 to the extension 106 of the second pin 104. A second bonding wire 108 is formed to electrically connect the second pin 104 to some of the first pads 204 on the first chip 201 and / or some of the first pins 103 on the first side 11. A third bonding wire 109 is formed to electrically connect some of the first pads 204 and some of the first pins 103 on the first chip 201.

[0035] In one embodiment, referring to Figures 5 - 7 , it further includes: forming a plastic encapsulation layer 118 covering the first base island 101, the second base island 102, the first pins 103, the second pins 104, the first bonding wire 107, the second bonding wire 108, and the third bonding wire 109. The back surface of the plastic encapsulation layer 118 exposes the back surfaces of the first base island 101, the second base island 102, the first pins 103, and the back surface of the boss 105 of the second pin 104. The connecting ribs are removed to form a plurality of discrete packaging structures.

[0036] In one embodiment, with continued reference to Figure 1 , it further includes: providing a third chip 203, the front surface of the third chip 203 having a plurality of discrete third pads 206; mounting the back surface of the third chip 203 on the front surface of a second base island 102 of the second chip 202 away from the fourth side 14; both the second side 12 and the fourth side 14 having at least one second pin 104; a part of the second pads 205 on the second chip 202 being electrically connected to an extension 106 of the second pin 104 on the fourth side 14 through the first bonding wire 107, the second pin 104 on the fourth side 14 being electrically connected to a part of the first pads 204 and / or a part of the first pins 103 on the first chip 201 through a second bonding wire 108; forming a fourth bonding wire 120 that electrically connects a part of the third pads 206 on the third chip 203 to the extension 106 of the second pin 104 on the second side 12, and forming a fifth bonding wire 121 that electrically connects the second pin 104 on the second side 12 to a part of the first pads 204 on the first chip 201 and / or a part of the first pins 103 on the first side 11.

[0037] Although this application has been disclosed above with preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by using the methods and technical contents disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes, and decorations made to the above embodiments based on the technical essence of this application without departing from the technical solutions of this application all fall within the protection scope of the technical solutions of this application.

Claims

1. A QFN package structure, characterized in that, Comprising: A first side, a second side, a third side, and a fourth side, wherein the first side and the third side are oppositely arranged, and the second side and the fourth side are oppositely arranged; A plurality of discrete first pins located on the first side and arranged in sequence along the extending direction of the first side; A second base island located on the third side; A first base island located between the second base island and the first pins and close to the first pins; A first chip and a second chip, wherein the back surface of the first chip is mounted on the front surface of the first base island, and the front surface of the first chip has a plurality of discrete first pads; the back surface of the second chip is mounted on the front surface of the second base island, and the front surface of the second chip has a plurality of discrete second pads; At least one second pin located on the second side and / or the fourth side, the second pin including a boss and an extension portion connected to the boss on the boss, the boss being located on the second side and / or the fourth side, the extension portion extending from the side where the boss is located towards the second chip mounted on the second base island, and the shortest straight-line distance between the back edge of the boss and the back edge of the second base island being greater than or equal to a preset value, and the shortest straight-line distance between the back edge of the first base island and the back edge of the second base island being greater than or equal to the preset value, the preset value meeting the voltage distance requirement between the first chip and the second chip.

2. The QFN package structure according to claim 1, wherein The preset value is greater than or equal to 3 mm.

3. The QFN package structure according to claim 1 or 2, characterized in that, Further comprising: A first bonding wire electrically connecting some of the second pads on the second chip to the extension portion of the second pin, a second bonding wire electrically connecting the second pin to some of the first pads on the first chip and / or some of the first pins on the first side, and a third bonding wire electrically connecting some of the first pads and some of the first pins on the first chip.

4. The QFN package structure according to claim 3, wherein Further comprising: A plastic encapsulation layer covering the first base island, the second base island, the first pins, the second pins, the first chip, the second chip, the first bonding wire, the second bonding wire, and the third bonding wire, and the back surface of the plastic encapsulation layer exposes the back surfaces of the first base island, the second base island, the back surfaces of the first pins, and the back surface of the boss of the second pin.

5. The QFN package structure according to claim 3, wherein There are two discrete second pins on the second side or the fourth side, both the first bonding wire and the second bonding wire have multiple strands, a part of the first bonding wire electrically connects some of the second pads on the second chip to the extension portion of one of the second pins, and a part of the second bonding wire electrically connects this second pin to some of the first pads on the first chip; another part of the first bonding wire electrically connects some of the other second pads on the second chip to the extension portion of the other second pin, and another part of the second bonding wire electrically connects this second pin to some of the first pins on the first side.

6. The QFN package structure according to claim 3, wherein, Both the second side and the fourth side each have at least one second pin. Both the first bonding wire and the second bonding wire have multiple strands. A part of the first bonding wires electrically connect a part of the second pads on the second chip to the extension of the second pins on the fourth side, and a part of the second bonding wires electrically connect the second pins on the fourth side to a part of the first pads and / or the first pins on the first chip; Another part of the first bonding wires electrically connect another part of the second pads on the second chip to the extension of the second pins on the second side, and another part of the second bonding wires electrically connect the second pins on the second side to a part of the first pads on the first chip and / or the first pins on the first side.

7. The QFN package structure according to claim 3 further includes: A third chip, a fourth bonding wire, and a fifth bonding wire. The back surface of the third chip is mounted on the front surface of the second base island on the side of the second chip away from the fourth side. The front surface of the third chip has several discrete third pads; Both the second side and the fourth side each have at least one second pin; A part of the second pads on the second chip are electrically connected to the extension of the second pins on the fourth side through the first bonding wires, and the second pins on the fourth side are electrically connected to a part of the first pads and / or a part of the first pins on the first chip through the second bonding wires; A part of the third pads on the third chip are electrically connected to the extension of the second pins on the second side through the fourth bonding wires, and the second pins on the second side are electrically connected to a part of the first pads and / or a part of the first pins on the first side through the fifth bonding wires.

8. The QFN package structure according to claim 1, wherein The total thickness of the boss and the extension in the second pin is equal to the thickness of the first pin.

9. The QFN package structure according to claim 1, wherein The boss is located at a position on the second side and / or the fourth side close to the first side.

10. A manufacturing method of a QFN package structure, characterized in that, Including: Providing a lead frame, the lead frame includes several frame unit areas and connecting ribs connecting adjacent frame unit areas. Each frame unit area includes a first side, a second side, a third side, and a fourth side. The first side and the third side are oppositely arranged, and the second side and the fourth side are oppositely arranged; Several discrete first pins located on the first side and arranged in sequence along the extension direction of the first side; A second base island located on the third side; A first base island located between the second base island and the first pins and close to the first pins; At least one second pin located on the second side and / or the fourth side. The second pin includes a boss and an extension connected to the boss on the boss. The boss is located on the second side and / or the fourth side. The extension extends from the side where the boss is located towards the direction where the second chip is mounted on the second base island, and the shortest straight-line distance between the back edge of the boss and the back edge of the second base island is greater than or equal to a preset value, and the preset value meets the voltage distance requirement between the first chip and the second chip; Provide a plurality of first chips and a plurality of second chips. The front surface of the first chip has a plurality of discrete first pads, and the front surface of the second chip has a plurality of discrete second pads. Mount the back surface of the first chip on the front surface of the first base island in the corresponding frame unit area, and mount the back surface of the second chip on the front surface of the second base island in the corresponding frame unit area; Form a first bonding wire that electrically connects some of the second pads on the second chip to the extension of the second pin, form a second bonding wire that electrically connects the second pin to some of the first pads on the first chip and / or some of the first pins on the first side, and form a third bonding wire that electrically connects some of the first pads and some of the first pins on the first chip.

11. The manufacturing method of the QFN package structure according to claim 10, characterized in that, Further include: Form a plastic encapsulation layer that covers the first base island, the second base island, the first pin, the second pin, the first bonding wire, the second bonding wire, and the third bonding wire. The back surface of the plastic encapsulation layer exposes the back surfaces of the first base island, the second base island, the back surface of the first pin, and the back surface of the boss of the second pin; Cut the connecting ribs to form a plurality of discrete packaging structures.

12. The manufacturing method of the QFN package structure according to claim 11, wherein, Further include: Provide a third chip. The front surface of the third chip has a plurality of discrete third pads; Mount the back surface of the third chip on the front surface of the second base island on the side of the second chip away from the fourth side; Both the second side and the fourth side have at least one second pin; Some of the second pads on the second chip are electrically connected to the extension of the second pin on the fourth side through the first bonding wire, and the second pin on the fourth side is electrically connected to some of the first pads on the first chip and / or some of the first pins through the second bonding wire; Form a fourth bonding wire that electrically connects some of the third pads on the third chip to the extension of the second pin on the second side, and form a fifth bonding wire that electrically connects the second pin on the second side to some of the first pads on the first chip and / or some of the first pins on the first side.

Images