Semiconductor element structure with mixed joint structure with air gap and preparation method of semiconductor element structure

Abstract

The invention provides a semiconductor element structure and a preparation method thereof. The semiconductor device structure includes a first substrate, a second substrate, and a hybrid bonding structure. The second substrate is bonded to the first substrate through the hybrid bonding structure. The hybrid bonding structure includes a dielectric structure and a conductive structure. The dielectric structure defines an air gap therein.

Description

[0001] Cross-reference

[0002] This application claims the priority of U.S. Patent Application No. 18 / 421,049 (i.e., the priority date is "January 24, 2024"), the content of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a method for fabricating a semiconductor device structure. In particular, it relates to a semiconductor layer including a hybrid bonding structure having an air gap. Background Art

[0004] With the rapid development of the electronics industry, the development of integrated circuits (ICs) has reached high performance and miniaturization. Technological advancements in IC materials and design have produced several generations of ICs, each generation having smaller and more complex circuits than the previous one.

[0005] A dynamic random access memory (DRAM) device is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Typically, a DRAM is arranged in a square array with one capacitor and one transistor per cell. A vertical transistor has been developed for 4F 2 DRAM cells, where F represents the minimum feature width or critical dimension (CD) of lithography. However, recently, as the word line pitch has been continuously reduced, DRAM manufacturers are facing a huge challenge of reducing the memory cell area.

[0006] The above description of "prior art" only provides background art and does not admit that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above "prior art" should not be taken as any part of the present disclosure. Summary of the Invention

[0007] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first substrate, a second substrate, and a hybrid bonding structure. The second substrate is bonded to the first substrate through the hybrid bonding structure. The hybrid bonding structure includes a dielectric structure and a conductive structure. The dielectric structure defines an air gap.

[0008] Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first substrate, a passivation layer, a wire, a dielectric structure, a first conductive layer, a second conductive layer, and an air gap. The passivation layer is disposed above the first substrate. The wire is disposed within the passivation layer. The dielectric structure is disposed above the passivation layer. The first conductive layer is electrically connected to the wire. The second conductive layer is disposed above the first conductive layer and is electrically connected to the wire through the first conductive layer. The air gap is disposed within the dielectric structure. The air gap laterally overlaps with the first conductive layer.

[0009] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device structure. The manufacturing method includes providing a first substrate; forming a first dielectric layer above the first substrate, wherein the first dielectric layer defines a first opening and a second opening; forming a first conductive layer within the first opening; providing a second substrate, wherein a second dielectric layer is formed on the second substrate, a second conductive layer penetrates the second dielectric layer, and the second dielectric layer defines a third opening; and bonding the first dielectric layer to the second dielectric layer, and bonding the first conductive layer and the second conductive layer to define a hybrid bonding structure having an air gap formed by the second opening and the third opening.

[0010] These embodiments of the present disclosure provide a semiconductor device structure and a method for manufacturing the same. The semiconductor device structure may include a first substrate and a second substrate bonded to the first substrate through a hybrid bonding technique. In this embodiment, the hybrid bonding structure includes an air gap, so that the parasitic capacitance between adjacent conductive structures within the hybrid bonding structure can be reduced.

[0011] The technical features and advantages of the present disclosure have been outlined rather broadly above, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art to which the present disclosure pertains should understand that the concepts and specific embodiments disclosed below can be readily utilized as a basis for modifying or designing other structures or processes to achieve the same purposes as the present disclosure. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent constructs do not depart from the spirit and scope of the present disclosure as defined by the claims. Description of the Drawings

[0012] A more complete understanding of the present disclosure can be obtained by reference to the detailed description and the claims. The present disclosure should also be understood as being associated with the element numbers of the drawings, and the element numbers of the drawings represent similar elements throughout the description.

[0013] Figure 1 is a cross-sectional schematic diagram illustrating the semiconductor device structure of some embodiments of the present disclosure.

[0014] Figure 2 is a cross-sectional schematic diagram, illustrating the semiconductor element structure of some embodiments of the present disclosure.

[0015] Figure 3 is a cross-sectional schematic diagram, illustrating the semiconductor element structure of some embodiments of the present disclosure.

[0016] Figure 4 is a cross-sectional schematic diagram, illustrating one or more stages of an example of the method for preparing the semiconductor element structure of some embodiments of the present disclosure.

[0017] Figure 5 is a cross-sectional schematic diagram, illustrating one or more stages of an example of the method for preparing the semiconductor element structure of some embodiments of the present disclosure.

[0018] Figure 6 is a cross-sectional schematic diagram, illustrating one or more stages of an example of the method for preparing the semiconductor element structure of some embodiments of the present disclosure.

[0019] Figure 7 is a cross-sectional schematic diagram, illustrating one or more stages of an example of the method for preparing the semiconductor element structure of some embodiments of the present disclosure.

[0020] Figure 8 is a cross-sectional schematic diagram, illustrating one or more stages of an example of the method for preparing the semiconductor element structure of some embodiments of the present disclosure.

[0021] Figure 9 is a cross-sectional schematic diagram, illustrating one or more stages of an example of the method for preparing the semiconductor element structure of some embodiments of the present disclosure.

[0022] Figure 10 is a cross-sectional schematic diagram, illustrating one or more stages of an example of the method for preparing the semiconductor element structure of some embodiments of the present disclosure.

[0023] Figure 11 is a cross-sectional schematic diagram, illustrating one or more stages of an example of the method for preparing the semiconductor element structure of some embodiments of the present disclosure.

[0024] Figure 12 is a cross-sectional schematic diagram, illustrating one or more stages of an example of the method for preparing the semiconductor element structure of some embodiments of the present disclosure.

[0025] Figure 13 is a cross-sectional schematic diagram, illustrating one or more stages of an example of the method for preparing the semiconductor element structure of some embodiments of the present disclosure.

[0026] Figure 14is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0027] Figure 15 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0028] Figure 16 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0029] Figure 17 is a flow schematic diagram illustrating a method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0030] Description of reference numerals:

[0031] 100a: Semiconductor device structure

[0032] 100b: Semiconductor device structure

[0033] 100c: Semiconductor device structure

[0034] 102: First substrate

[0035] 104: Interlayer dielectric

[0036] 106: Conductive wire

[0037] 108: Conductive via

[0038] 110: Interlayer dielectric

[0039] 112: Conductive wire

[0040] 114: Passivation layer

[0041] 120: Hybrid bonding structure

[0042] 120': Hybrid bonding structure

[0043] 122: First dielectric layer

[0044] 122s1: Surface

[0045] 124: Second dielectric layer

[0046] 124s1: Surface

[0047] 126: Conductive layer

[0048] 126': Conductive layer

[0049] 126s1: Surface

[0050] 126's1: Surface

[0051] 128: Conductive layer

[0052] 128': Conductive layer

[0053] 128s1: Surface

[0054] 130: Conductive layer

[0055] 130': Conductive layer

[0056] 130s1: Surface

[0057] 132: Conductive layer

[0058] 132': Conductive layer

[0059] 132s1: Surface

[0060] 134: Air gap

[0061] 134': Air gap

[0062] 134a: First terminal part

[0063] 134b: Neck

[0064] 134c: Second terminal part

[0065] 140: Second substrate

[0066] 150a: Photosensitive layer

[0067] 150b: Photosensitive layer

[0068] 150s1: Surface

[0069] 160a: Sacrificial layer

[0070] 160b: Sacrificial layer

[0071] 160c: Sacrificial layer

[0072] 160s1: Surface

[0073] 162: Dielectric layer

[0074] 162o: Opening

[0075] 164: Opening

[0076] 166: Opening

[0077] 168: Conductive material

[0078] 170: First opening

[0079] 172: Second opening

[0080] 200: Preparation method

[0081] 202: Step

[0082] 204: Step

[0083] 206: Step

[0084] 208: Step

[0085] 210: Step

[0086] 212: Step

[0087] 214: Step

[0088] 216: Step

[0089] 218: Step

[0090] L1: Length

[0091] L2: Length

[0092] L3: Length

[0093] P1: Pitch (etching technology)

[0094] P2: Pitch (etching technology)

[0095] P3: Pitch (etching technology)

[0096] T1: Dimension

[0097] T2: Thickness

[0098] W1: Length

[0099] W2: Length

[0100] W3: Length

[0101] X: Axis

[0102] Y: Axis Detailed implementation manners

[0103] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, when it is described that the first component is formed on the second component, it may include an embodiment where the first and second components are in direct contact, or it may include an embodiment where additional components are formed between the first and second components so that the first and second components are not in direct contact. Additionally, the embodiments of the present disclosure may repeat reference numerals and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between various embodiments and / or the configurations discussed.

[0104] It should be understood that when an element is referred to as being “connected to” or “coupled to” another element, the initial element can be directly connected to or coupled to the other element, or there may be other intermediate elements.

[0105] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer or section discussed below may be referred to as the second element, component, region, layer or section.

[0106] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0107] It should be understood that in the description of the present disclosure, the term “about” modifies the quantity of the ingredients, compositions or reactants of the present disclosure, and means, for example, the quantity variations that may occur through typical measurements for preparing concentrates or solutions and liquid handling procedures. Moreover, variations may result from inadvertent errors in the measurement procedures, differences in the manufacture, source or purity of the ingredients used to make the compositions or implement the methods, etc. In one aspect, the term “about” means within 10% of the reported value. In another aspect, the term “about” means within 5% of the reported value. Further, in yet another aspect, the term “about” means within 10, 9, 8, 7, 6, 5, 4, 3, 2 or 1% of the reported value.

[0108] Figure 1 is a cross-sectional schematic diagram illustrating the semiconductor element structure 100a of some embodiments of the present disclosure.

[0109] In some embodiments, the semiconductor element structure 100a may include a first substrate 102, a hybrid bonding structure 120, and a second substrate 140. In some embodiments, the first substrate 102 may be bonded or attached to the second substrate 140 through the hybrid bonding structure 120.

[0110] The first substrate 102 may include a semiconductor carrier (or wafer) and integrated circuit (IC) elements formed within and / or on the semiconductor carrier. The semiconductor carrier may include a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor carrier may include an elemental semiconductor containing silicon or germanium in single crystal form, polycrystalline form, or amorphous form; a compound semiconductor material including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material, or a combination thereof. In some embodiments, the alloy semiconductor substrate may include a SiGe alloy having a graded Ge profile, where the Si and Ge compositions change from one ratio at one location to another ratio at another location with respect to the position of the profile. In another embodiment, the SiGe alloy is formed over a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the semiconductor carrier may have a multi-layer structure, or the semiconductor carrier may include a multi-layer compound semiconductor structure. It should be understood that some doping regions, isolation structures, and / or other features may be formed within the semiconductor carrier.

[0111] In some embodiments, the IC elements may include active elements such as transistors and / or passive elements such as resistors, capacitors, inductors, or combinations thereof. By way of example, the IC elements may include memories (e.g., DRAM), application specific ICs (ASICs), memory integrated circuits, radio frequency integrated circuits (RFICs), central processing units (CPUs), microprocessor units (MPUs), graphics processing units (GPUs), microcontroller units (MCUs), field programmable gate arrays (FPGAs), power management ICs (PMICs), or other types of ICs.

[0112] In some embodiments, the semiconductor element structure 100a may include an interlayer dielectric 104. The interlayer dielectric 104 may be disposed on the first substrate 102. The interlayer dielectric 104 may include a multi-layer structure. For example, the interlayer dielectric 104 may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material (k < 4), or other suitable materials. In some embodiments, the interlayer dielectric 104 may also be referred to as an interlayer dielectric (ILD).

[0113] In some embodiments, the semiconductor element structure 100a may include a wire 106. The wire 106 may be disposed on the first substrate 102. The wire 106 may be electrically connected to an IC element within the first substrate 102. The wire 106 may be embedded within the interlayer dielectric 104. The interlayer dielectric 104 may include copper (Cu), tungsten (W), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, titanium nitride (TiN), analogs, and / or combinations thereof. In some embodiments, the interlayer dielectric 104 may also be referred to as an "M(N)" layer, where N is equal to a positive integer, such as 1, 2, etc.

[0114] In some embodiments, the semiconductor element structure 100a may include a conductive via 108. The conductive via 108 may be disposed on the wire 106 and electrically connected to the wire 106. The conductive via 108 may be embedded within the interlayer dielectric 104. The conductive via 108 may include copper, tungsten, aluminum, tantalum, molybdenum, tantalum nitride, titanium, titanium nitride, analogs, and / or combinations thereof.

[0115] In some embodiments, the semiconductor element structure 100a may include an interlayer dielectric 110. In some embodiments, the interlayer dielectric 110 may be disposed on the interlayer dielectric 104. The interlayer dielectric 110 may include a multi-layer structure. For example, the interlayer dielectric 110 may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, borophosphosilicate glass, low-k dielectric material, or other suitable materials.

[0116] In some embodiments, the semiconductor element structure 100a may include a wire 112. The wire 112 may be disposed on the conductive via 108 and electrically connected to the conductive via 108. The wire 112 may be embedded within the interlayer dielectric 110. For example, the wire 112 may include copper, tungsten, aluminum, tantalum, molybdenum, tantalum nitride, titanium, titanium nitride, analogs, and / or combinations thereof. In some embodiments, the wire 112 may also be referred to as an "M(N + 1)" layer. For example, the wire 106 is the M1 layer and the wire 112 is the M2 layer.

[0117] In some embodiments, the semiconductor element structure 100a may include a passivation layer 114. In some embodiments, an interlayer dielectric 110 may be disposed on the passivation layer 114. For example, the passivation layer 114 may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, borophosphosilicate glass, a low-k dielectric material, or other suitable materials. In some embodiments, the passivation layer 114 may be omitted.

[0118] In some embodiments, a hybrid bonding structure 120 may be disposed on the passivation layer 114. In some embodiments, the hybrid bonding structure 120 may include a bonding interface formed by a hybrid bonding technique, which involves at least two materials to be bonded. In some embodiments, the hybrid bonding structure 120 may include a first dielectric layer 122, a second dielectric layer 124, a conductive layer 126, a conductive layer 128, a conductive layer 130, a conductive layer 132, and an air gap 134.

[0119] In some embodiments, the first dielectric layer 122 may be disposed on the passivation layer 114. For example, in some embodiments, the first dielectric layer 122 may include silicon carbonitride, silicon carbide, silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, the material of the first dielectric layer 122 may be different from that of the passivation layer 114. For example, the first dielectric layer 122 may include or be made of silicon carbonitride, and the passivation layer 114 may include or be made of silicon oxide. In some embodiments, the material of the first dielectric layer 122 may be different from that of the passivation layer 114. In embodiments where the passivation layer 114 is not formed, the first dielectric layer 122 may be in direct contact with the interlayer dielectric 110.

[0120] In some embodiments, the second dielectric layer 124 may be disposed on the first dielectric layer 122. In some embodiments, the second dielectric layer 124 may be bonded to the first dielectric layer 122. In some embodiments, there is no interface or an indistinct interface between the first dielectric layer 122 and the second dielectric layer 124. For example, in some embodiments, the second dielectric layer 124 may include silicon carbonitride, silicon carbide, silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, the material of the second dielectric layer 124 may be the same as or similar to that of the first dielectric layer 122. In some embodiments, the first dielectric layer 122 and the second dielectric layer 124 may be collectively referred to as a dielectric structure.

[0121] In some embodiments, the conductive layer 126 may be disposed on the passivation layer 114. In some embodiments, the conductive layer 126 may penetrate the first dielectric layer 122. In some embodiments, the conductive layer 126 may penetrate the passivation layer 114. In some embodiments, the conductive layer 126 may penetrate the interlayer dielectric 110. In some embodiments, the conductive layer 126 may be electrically connected to the wire 112. For example, in some embodiments, the first dielectric layer 122 may include copper, tungsten, aluminum, tantalum, molybdenum, tantalum nitride, titanium, titanium nitride, the like, and / or combinations thereof.

[0122] In some embodiments, the conductive layer 128 may be disposed on the passivation layer 114. In some embodiments, the conductive layer 128 may penetrate the first dielectric layer 122. In some embodiments, the conductive layer 128 may penetrate the passivation layer 114. In some embodiments, the conductive layer 128 may penetrate the interlayer dielectric 110. In some embodiments, the conductive layer 128 may be electrically connected to the wire 112. For example, in some embodiments, the conductive layer 128 may include copper, tungsten, aluminum, tantalum, molybdenum, tantalum nitride, titanium, titanium nitride, the like, and / or combinations thereof. The conductive layer 128 may be located on a plane that is the same as a plane of the conductive layer 126 relative to the first substrate 102. In some embodiments, the conductive layer 126 and the conductive layer 128 may have different sizes. The conductive layer 126 may have a length (or width or diameter) L1 in the X direction. The conductive layer 126 may have a length (or width or diameter) L2 in the Y direction. The conductive layer 128 may have the length L1 in the X direction. The conductive layer 128 may have a length (or width or diameter) L3 in the Y direction. In some embodiments, the length L1 may be greater than the length L2. In some embodiments, the length L1 may be greater than the length L3. In some embodiments, the length L3 may be greater than the length L2.

[0123] In some embodiments, the conductive layer 130 may be disposed on the conductive layer 126. In some embodiments, the conductive layer 130 may penetrate the second dielectric layer 124. In some embodiments, the conductive layer 130 may be electrically connected to the conductive layer 126. For example, in some embodiments, the first dielectric layer 122 may include copper, tungsten, aluminum, tantalum, molybdenum, tantalum nitride, titanium, titanium nitride, the like, and / or combinations thereof.

[0124] In some embodiments, the conductive layer 132 may be disposed on the conductive layer 128. In some embodiments, the conductive layer 132 may penetrate the second dielectric layer 124. In some embodiments, the conductive layer 132 may be electrically connected to the conductive layer 128. For example, in some embodiments, the conductive layer 132 may include copper, tungsten, aluminum, tantalum, molybdenum, tantalum nitride, titanium, titanium nitride, the like, and / or combinations thereof.

[0125] In some embodiments, conductive layer 126 and conductive layer 130 may be collectively referred to as a first conductive structure, and each of conductive layer 126 and conductive layer 130 may be regarded as a part of the first conductive structure. In some embodiments, conductive layer 128 and conductive layer 132 may be collectively referred to as a second conductive structure, and each of conductive layer 128 and conductive layer 132 may be regarded as a part of the second conductive structure.

[0126] In some embodiments, air gap 134 may be embedded within first dielectric layer 122 and second dielectric layer 124. In some embodiments, air gap 134 may be defined by second substrate 140, first dielectric layer 122, second dielectric layer 124, and passivation layer 114. In some embodiments, air gap 134 may be spaced apart from conductive layers 126, 128, 130, and 132. In some embodiments, air gap 134 may be configured to reduce the parasitic capacitance between adjacent conductive structures. The first conductive structure (e.g., conductive layer 126 and conductive layer 130) may define a pitch Pi1. The second conductive structure (e.g., conductive layer 128 and conductive layer 132) may define a pitch Pi2. Air gap 134 may define a pitch Pi3. In some embodiments, pitch Pi3 may be less than pitch Pi1. In some embodiments, pitch Pi3 may be less than pitch Pi2.

[0127] In some embodiments, second substrate 140 may be disposed on hybrid bonding structure 120. Second substrate 140 may include a semiconductor carrier (or wafer) and IC elements formed within and / or on the semiconductor carrier. The semiconductor carrier may include a bulk semiconductor, a semiconductor-on-insulator substrate, or the like. The semiconductor carrier may include an elemental semiconductor, containing silicon or germanium in single crystal form, polycrystalline form, or amorphous form; a compound semiconductor material, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP, any other suitable material, or a combination thereof. In some embodiments, the alloy semiconductor substrate may include a SiGe alloy having a graded Ge profile, wherein the Si and Ge components change from one ratio at one location to another ratio at another location with respect to the location of the profile. In another embodiment, the SiGe alloy is formed over a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the semiconductor carrier may have a multi-layer structure, or the semiconductor carrier may include a multi-layer compound semiconductor structure. It should be understood that some doping regions, isolation structures, and / or other features may be formed within the semiconductor carrier.

[0128] In some embodiments, the IC component may include active components such as transistors and / or passive components such as resistors, capacitors, inductors, or combinations thereof. For example, the IC component may include a memory (e.g., DRAM), an application specific IC (ASIC), a memory integrated circuit, a radio frequency integrated circuit (RFIC), a central processing unit (CPU), a microprocessor unit (MPU), a graphics processing unit (GPU), a microcontroller unit (MCU), a field programmable gate array (FPGA), a power management IC (PMIC), or other types of ICs.

[0129] The second substrate 140 may further include an electrical interconnection (not shown) between the IC component and the hybrid bonding structure 120.

[0130] Figure 2 is a cross-sectional schematic diagram illustrating a semiconductor component structure 100b according to some embodiments of the present disclosure.

[0131] The semiconductor component structure 100b may include a hybrid bonding structure 120'. In some embodiments, the first dielectric layer 122 and the second dielectric layer 124 are misaligned.

[0132] The first dielectric layer 122 may have a surface 122s1 (or a side surface). The second dielectric layer 124 may have a surface 124s1 (or a side surface). In some embodiments, the surface 122s1 of the first dielectric layer 122 may be misaligned or non-coplanar with the surface 124s1 of the second dielectric layer 124.

[0133] In some embodiments, the conductive layer 126 and the conductive layer 130 are misaligned. The conductive layer 126 may have a surface 126s1 (or a side surface). The conductive layer 130 may have a surface 130s1 (or a side surface). In some embodiments, the surface 126s1 of the conductive layer 126 may be misaligned or non-coplanar with the surface 130s1 of the conductive layer 130. In some embodiments, the conductive layer 128 and the conductive layer 132 are misaligned. The conductive layer 128 may have a surface 128s1 (or a side surface). The conductive layer 132 may have a surface 132s1 (or a side surface). In some embodiments, the surface 128s1 of the conductive layer 128 may be misaligned or non-coplanar with the surface 132s1 of the conductive layer 132.

[0134] The hybrid bonding structure 120' may include an air gap 134' defined by misaligned dielectric structures. In some embodiments, the air gap 134' may include a first terminal portion 134a, a neck portion 134b, and a second terminal portion 134c. The first terminal portion 134a may be adjacent to the first substrate 102. The second terminal portion 134c may be adjacent to the second substrate 140. The neck portion 134b may be located between the first terminal portion 134a and the second terminal portion 134c. The neck portion 134b may be in communication with the first terminal portion 134a. The neck portion 134b may be in communication with the second terminal portion 134c. In some embodiments, the first terminal portion 134a may be misaligned with the second terminal portion 134c. The first terminal portion 134a may have a length (or width or diameter) W1. The neck portion 134b may have a length (or width or diameter) W2. The second terminal portion 134c may have a length (or width or diameter) W3. In some embodiments, the length W1 may be greater than the length W2. In some embodiments, the length W3 may be greater than the length W2. In some embodiments, the length W1 may be substantially equal to the length W3.

[0135] Figure 3 is a cross-sectional schematic diagram illustrating a semiconductor element structure 100c of some embodiments of the present disclosure. The semiconductor element structure 100c may be similar to the semiconductor element structure 100a, and the differences therebetween are described as follows.

[0136] The semiconductor element structure 100c may include conductive layers 126', 128', 130', and 132'. In some embodiments, the conductive layer 126' may continuously taper towards the first substrate 102. The conductive layer 126' may have a surface 126's1. The surface 126's1 may continuously extend and contact the first dielectric layer 122, the passivation layer 114, and the interlayer dielectric 110. In some embodiments, the conductive layer 128' may continuously taper towards the first substrate 102. In some embodiments, the conductive layer 130' may continuously taper towards the second substrate 140. In some embodiments, the conductive layer 132' may continuously taper towards the second substrate 140.

[0137] Figures 4 to 16 is a cross-sectional schematic diagram illustrating different stages of an example of a method for manufacturing a semiconductor element structure of some embodiments of the present disclosure.

[0138] Please refer to Figure 4 , a first substrate 102 may be provided. The wire 106 may be formed on the first substrate 102. The manufacturing techniques for the wire 106 may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or other suitable processes.

[0139] The interlayer dielectric 104 can be formed on the first substrate 102 and cover the wire 106. The fabrication techniques for the interlayer dielectric 104 can include chemical vapor deposition, physical vapor deposition, atomic layer deposition, low-pressure chemical vapor deposition, or other suitable processes.

[0140] The conductive vias 108 and the wires 112 can be formed on the wire 106. In some embodiments, an etching technique can be performed to define a plurality of openings in the interlayer dielectric 104. A conductive material can be formed to fill the openings of the interlayer dielectric 104 and cover the interlayer dielectric 104. The fabrication techniques for the conductive material can include physical vapor deposition, chemical vapor deposition, atomic layer deposition, low-pressure chemical vapor deposition, or other suitable processes. A patterning technique can be performed to pattern the conductive material, thereby generating the conductive vias 108 and the wires 112. The patterning technique can include a lithography technique and an etching technique.

[0141] The interlayer dielectric 110 can be formed on the interlayer dielectric 104 and cover the wires 112. The fabrication techniques for the interlayer dielectric 110 can include chemical vapor deposition, physical vapor deposition, atomic layer deposition, low-pressure chemical vapor deposition, or other suitable processes.

[0142] In some embodiments, the passivation layer 114 can be formed on the interlayer dielectric 110. The fabrication techniques for the passivation layer 114 can include chemical vapor deposition, physical vapor deposition, atomic layer deposition, low-pressure chemical vapor deposition, or other suitable processes.

[0143] Please refer to Figure 5 , a photosensitive layer 150a can be formed on the passivation layer 114. The photosensitive layer 150a can include a positive photoresist or a negative photoresist.

[0144] Please refer to Figure 6 , an etching technique P1 can be performed to remove a portion of the photosensitive layer 150a, thereby defining a photosensitive layer 150b. In some embodiments, the etching technique P1 can include a dry etching technique. In some embodiments, an oxygen plasma can be used to remove a portion of the photosensitive layer 150a. The size (e.g., width or surface area) of the photosensitive layer 150b can be smaller than the size of the photosensitive layer 150a.

[0145] Please refer to Figure 7, a sacrificial layer 160a may be formed on the passivation layer 114. The sacrificial layer 160a may cover the photosensitive layer 150a. In some embodiments, the sacrificial layer 160a may include silicon nitride, silicon oxynitride, silicon oxide, hafnium oxide, aluminum oxide, titanium oxide, or other suitable materials. In some embodiments, the material of the sacrificial layer 160a may be different from the material of the passivation layer 114. In some embodiments, the material of the sacrificial layer 160a may be different from the material of the interlayer dielectric 110. For example, the sacrificial layer 160a may include a nitride, while the passivation layer 114 may include an oxide. Fabrication techniques for the sacrificial layer 160a may include chemical vapor deposition, physical vapor deposition, atomic layer deposition, low-pressure chemical vapor deposition, or other suitable processes.

[0146] Please refer to Figure 8 , an etching technique P2 may be performed. In some embodiments, a portion of the sacrificial layer 160a may be removed, thereby defining a sacrificial layer 160b. In some embodiments, the sacrificial layer 160b may be disposed on a surface 150s1 of the photosensitive layer 150b. In some embodiments, the sacrificial layer 160b may be configured to define the location or site of an air gap to be formed subsequently. The size T1 of the sacrificial layer 160b may determine the size of an air gap. The size T1 of the sacrificial layer 160b may determine the sizes of the conductive layers to be formed subsequently.

[0147] Please refer to Figure 9 , the photosensitive layer 150b may be removed, thereby defining an opening 162o (or aperture) that exposes the passivation layer 114.

[0148] Please refer to Figure 10 , a dielectric layer 162 may be formed. The dielectric layer 162 may be formed on a surface 160s1 (or side surface) of the sacrificial layer 160b. As a result, openings 164 and 166 (or apertures) are defined and the passivation layer 114 is exposed. The openings 164 and 166 may have different sizes (e.g., length, width, diameter, or surface area). In some embodiments, the thickness T2 of the dielectric layer 162 may be configured to determine the size of the conductive layer (or conductive structure) to be formed subsequently. Fabrication techniques for the dielectric layer 162 may include chemical vapor deposition, physical vapor deposition, atomic layer deposition, low-pressure chemical vapor deposition, or other suitable processes. In some embodiments, the material of the dielectric layer 162 may be different from the material of the sacrificial layer 160b. In some embodiments, the material of the dielectric layer 162 may be different from the material of the passivation layer 114. In some embodiments, the dielectric layer 162 may include silicon carbonitride, silicon carbide, silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.

[0149] Please refer to Figure 11, an etching technique P3 can be performed. A part of the sacrificial layer 160b can be removed, thereby defining a sacrificial layer 160c with a thickness less than that of the dielectric layer 162. A part of the passivation layer 114 exposed through the openings 164 and 166 is removed. A part of the interlayer dielectric 110 exposed through the openings 164 and 166 is removed. The wire 112 can be exposed.

[0150] Please refer to Figure 12 , a polishing technique (e.g., chemical mechanical polishing (CMP)) can be performed to remove a part of the dielectric layer 162, thereby defining a first dielectric layer 122. A conductive material 168 can be formed to fill the openings 164 and 166. The conductive material 168 can cover the first dielectric layer 122 and the sacrificial layer 160c. The manufacturing techniques of the conductive material 168 can include physical vapor deposition, chemical vapor deposition, atomic layer deposition, low-pressure chemical vapor deposition, or other suitable processes.

[0151] Please refer to Figure 13 , a polishing technique (e.g., chemical mechanical polishing (CMP)) can be performed to remove a part of the conductive material 168, thereby defining conductive layers 126 and 128 with different sizes. The first dielectric layer 122 and the sacrificial layer 160c can be exposed.

[0152] Please refer to Figure 14 , the sacrificial layer 160c can be removed, thereby defining a first opening 170 (or first aperture) surrounded by the first dielectric layer 122.

[0153] Please refer to Figure 15 , a second substrate 140 can be provided. A second dielectric layer 124 can be formed on the second substrate 140. Conductive layers 130 and 132 with different sizes can be formed on the second substrate 140. A second opening 172 (or second aperture) can be surrounded by the second dielectric layer 124.

[0154] Please refer to Figure 16 , a hybrid bonding technique can be performed to bond the first substrate 102 and the second substrate 140. The first dielectric layer 122 can be bonded to the second dielectric layer 124. The conductive layer 126 can be bonded to the conductive layer 130. The conductive layer 128 can be bonded to the conductive layer 132. The first opening 170 and the second opening 172 can jointly define an air gap 134. As a result, a semiconductor element structure (e.g., the semiconductor element structure as shown in Figure 1 ) can be produced.

[0155] Figure 17 is a process schematic diagram, illustrating a method 200 for preparing a semiconductor element structure according to some embodiments of the present disclosure.

[0156] Preparation method 200 starts at step 202, where a first substrate is provided.

[0157] Preparation method 200 proceeds to step 204, where a passivation layer is formed on the first substrate. Figure 4 Illustrate the stages corresponding to steps 202 and 204.

[0158] Preparation method 200 proceeds to step 206, where a patterned photosensitive layer is formed on the passivation layer. Figure 5 Illustrate the stage corresponding to step 206.

[0159] Preparation method 200 proceeds to step 208, where a sacrificial layer is formed on the sidewalls of the patterned photosensitive layer. In some embodiments, the patterned photosensitive layer may also be etched. In some embodiments, the sacrificial layer may be formed on the upper surface and the sidewalls of the patterned photosensitive layer. In some embodiments, a portion of the sacrificial layer may be removed by an etching technique such that the sacrificial layer remains on the sidewalls of the patterned photosensitive layer. Figures 5 to 8 Illustrate the stage corresponding to step 208.

[0160] Preparation method 200 proceeds to step 210, where the patterned photosensitive layer is removed. Figure 9 Illustrate the stage corresponding to step 210.

[0161] Preparation method 200 proceeds to step 212, where a first dielectric layer is formed on the sidewalls of the sacrificial layer. Figure 10 Illustrate the stage corresponding to step 212.

[0162] Preparation method 200 proceeds to step 214, where a first conductive layer is formed in a plurality of openings surrounded by the first dielectric layer. Figures 11 to 13 Illustrate the stage corresponding to step 214. In some embodiments, a portion of the sacrificial layer may be removed. In some embodiments, the first dielectric layer may be polished such that the first dielectric layer is flush with the sacrificial layer. In some embodiments, a conductive material is deposited to cover the upper surfaces of the sacrificial layer and the first dielectric layer. In some embodiments, a polishing technique may be performed to planarize the conductive material such that the upper surface of the conductive layer is flush with the upper surfaces of the sacrificial layer and the first dielectric layer.

[0163] Preparation method 200 proceeds to step 216, where the sacrificial layer is removed to define a first opening. Figure 14 Illustrate the stage corresponding to step 216.

[0164] Fabrication method 200 continues with step 218, where the second substrate is bonded to the first substrate. A second dielectric layer is formed on the second substrate. A second conductive layer is formed on the second substrate. The second opening is defined and surrounded by the second dielectric layer. A hybrid bonding technique can be performed to bond the first substrate and the second substrate. An air gap can be formed to align the first opening and the second opening. Figure 15 and Figure 16 Illustrates the stage corresponding to step 218.

[0165] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first substrate, a second substrate, and a hybrid bonding structure. The second substrate is bonded to the first substrate through the hybrid bonding structure. The hybrid bonding structure includes a dielectric structure and a conductive structure. The dielectric structure defines an air gap.

[0166] Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first substrate, a passivation layer, a wire, a dielectric structure, a first conductive layer, a second conductive layer, and an air gap. The passivation layer is disposed above the first substrate. The wire is disposed within the passivation layer. The dielectric structure is disposed above the passivation layer. The first conductive layer is electrically connected to the wire. The second conductive layer is disposed above the first conductive layer and is electrically connected to the wire through the first conductive layer. The air gap is disposed within the dielectric structure. The air gap laterally overlaps with the first conductive layer.

[0167] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device structure. The fabrication method includes providing a first substrate; forming a first dielectric layer above the first substrate, where the first dielectric layer defines a first opening and a second opening; forming a first conductive layer within the first opening; providing a second substrate, where a second dielectric layer is formed on the second substrate, a second conductive layer penetrates the second dielectric layer, and the second dielectric layer defines a third opening; and bonding the first dielectric layer to the second dielectric layer, and bonding the first conductive layer and the second conductive layer to define a hybrid bonding structure having an air gap formed by the second opening and the third opening.

[0168] The embodiments of the present disclosure provide a semiconductor device structure and a method for fabricating the same. The semiconductor device structure may include a first substrate and a second substrate bonded to the first substrate through a hybrid bonding technique. In this embodiment, the hybrid bonding structure includes an air gap, such that the parasitic capacitance between adjacent conductive structures within the hybrid bonding structure can be reduced.

[0169] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced by other processes or combinations thereof.

[0170] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same function or achieve substantially the same result as the corresponding embodiments described herein can be used in accordance with the present disclosure. Accordingly, these processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor device structure, comprising: A first substrate; And A second substrate, attached to the first substrate through a hybrid bonding structure, wherein the hybrid bonding structure includes: A dielectric structure; and A conductive structure; Wherein, the dielectric structure defines an air gap.

2. The semiconductor device structure according to claim 1, wherein the air gap is spaced apart from the conductive structure by the dielectric structure.

3. The semiconductor device structure according to claim 1, wherein the conductive structure includes a first conductive layer and a second conductive layer bonded to the first conductive layer.

4. The semiconductor device structure according to claim 3, further comprising a passivation layer disposed between the hybrid bonding structure and the first substrate, wherein the first conductive layer penetrates through the passivation layer.

5. The semiconductor device structure according to claim 4, wherein the first conductive layer continuously tapers towards the first substrate.

6. The semiconductor device structure according to claim 5, wherein the second conductive layer tapers towards the second substrate.

7. The semiconductor device structure according to claim 4, wherein a material of the passivation layer is different from a material of the dielectric structure.

8. The semiconductor device structure according to claim 1, wherein the air gap includes a first terminal portion and a neck connected to the first terminal portion, and a pore diameter of the first terminal portion is different from a pore diameter of the neck.

9. The semiconductor device structure according to claim 8, wherein the air gap further includes a second terminal portion connected to the neck.

10. The semiconductor device structure according to claim 9, wherein the first terminal portion and the second terminal portion are partially misaligned.

11. The semiconductor device structure according to claim 1, wherein the conductive structure includes a first section and a second section, the first section has a first size, and the second section has a second size different from the first size.

12. The semiconductor device structure according to claim 1, wherein the first substrate includes a memory element.

13. A method for manufacturing a semiconductor device structure, comprising: Providing a first substrate; Forming a first dielectric layer over the first substrate, wherein the first dielectric layer defines a first opening and a second opening; Forming a first conductive layer in the first opening; Providing a second substrate, wherein a second dielectric layer is formed on the second substrate, a second conductive layer penetrates through the second dielectric layer, and the second dielectric layer defines a third opening; And Bonding the first dielectric layer to the second dielectric layer, and bonding the first conductive layer and the second conductive layer to define a hybrid bonding structure having an air gap formed by the second opening and the third opening.

14. The manufacturing method according to claim 13, further comprising: Before forming the first dielectric layer, forming a passivation layer over the first substrate; Forming a photosensitive material on the passivation layer; Forming a sacrificial layer on a sidewall of the photosensitive material; And Forming the first dielectric layer on a sidewall of the sacrificial layer to define the first opening.

15. The manufacturing method according to claim 14, further comprising removing the sacrificial layer to define the second opening.

16. The manufacturing method according to claim 15 further includes determining a thickness of the sacrificial layer to define a first size and a second size of the first conductive layer, wherein the first size is different from the second size.

17. The manufacturing method according to claim 14 further includes patterning the passivation layer such that the first opening penetrates the passivation layer.

18. The manufacturing method according to claim 14, wherein a material of the passivation layer is different from a material of the first dielectric layer.

Images