Interconnection intermediary component, chip packaging system and electronic equipment

Abstract

The embodiment of the invention discloses an interconnection intermediary component, a chip packaging system and electronic equipment. The interconnection intermediary component comprises a local interconnection component and a carrier layer, and the local interconnection component is embedded on the carrier layer; the first through hole in the carrier layer is arranged between the first surface and the second surface of the carrier layer in a penetrating manner, and the second through hole in the carrier layer is arranged between the groove bottom of the first groove and the second surface of the carrier layer in a penetrating manner; a first interface and a second interface which are connected with the core particles are arranged on the additional layer on the first surface side of the carrier layer, and a third interface and a fourth interface which are connected with the PCB are arranged on the additional layer on the second surface side of the carrier layer; the first interface is electrically connected with the third interface through the first through hole, the second interface is electrically connected with the fourth interface through the local interconnection component and the second through hole, and the local interconnection component is electrically connected with the plurality of second interfaces. Through the arrangement, the installability, the reliability and the supptability of the system are effectively improved while the high-density layout requirement is met.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of chip packaging, and in particular, to an interconnection interposer component, a chip packaging system, and an electronic device. Background Art

[0002] With the increasing difficulty of transistor process miniaturization and the continuous improvement of high-performance requirements for chips, the industry has begun to explore solutions in the packaging field. In a traditional chip board-level system, dies are packaged on a substrate to form a chip package body, which is then installed on a PCB (Printed Circuit Board). Among them, the FCBGA (Flip chip BGA) technology has been widely used due to its advantages such as high integration, high performance, and low power consumption.

[0003] To meet the requirements of high-density layout, in a typical FCBGA packaging architecture, an RDL (Re-distributed layer)-based silicon interposer is arranged between the die and the substrate to enable small-pitch placement of the die, effectively improving the bandwidth performance. With the integration of more chips, the size of the FCBGA has become larger and larger, resulting in development bottlenecks in terms of installability, reliability, and supplyability. Summary of the Invention

[0004] The embodiments of the present application provide an interconnection interposer component, a chip packaging system, and an electronic device, which can effectively improve the installability, reliability, and supplyability of the system while meeting the requirements of high-density layout.

[0005] In a first aspect of the embodiments of the present application, an interconnection interposer component is provided. The interconnection interposer component includes a local interconnection component and a carrier layer. The carrier layer includes a first surface and a second surface. A first groove is formed on the first surface of the carrier layer, and the local interconnection component is embedded in the first groove. The carrier layer has a first through hole and a second through hole. The first through hole penetrates between the first surface and the second surface of the carrier layer, and the second through hole penetrates between the bottom of the first groove and the second surface of the carrier layer. Reinforcement layers are respectively covered on both sides of the carrier layer, that is, a first reinforcement layer is covered on the first surface side of the carrier layer, and a second reinforcement layer is provided on the second surface side of the carrier layer. The reinforcement layer on the first surface side of the carrier layer has a first interface and a second interface for connecting with a die, and the reinforcement layer on the second surface side of the carrier layer has a third interface and a fourth interface for connecting with a printed circuit board. The first interface is electrically connected to the third interface through the first through hole, the second interface is electrically connected to the fourth interface through the local interconnection component and the second through hole, and the local interconnection component is electrically connected to a plurality of second interfaces.

[0006] The local interconnection component based on the interconnection intermediary component can achieve high-density connection for on-board packaging between dies. Moreover, the single product size is relatively small, which can effectively reduce the risk of deformation and has high reliability. At the same time, it can reduce the difficulty of the assembly process, has good mountability, and effectively improves the manufacturing yield of the product.

[0007] In addition, the interconnection intermediary component is formed based on a carrier layer and can be configured according to the number of dies to be interconnected. Thus, the single size of the interconnection intermediary component can be reasonably controlled; in practical applications, it is not affected by the difficulty of realizing large-size substrates and has good supplyability. In addition, the interconnection intermediary component with a relatively small single size has good assembly processability while having a small actual board occupation size, which is convenient for setting more devices and can further improve the supplyability.

[0008] In practical applications, the carrier layer can be made of a rigid inorganic material. As the layout carrier of the local interconnection component, it can make the interconnection intermediary component have high flatness. Based on the good flatness of the single body, it can further reduce the difficulty of the assembly process and improve the mountability.

[0009] Exemplarily, the rigid inorganic material can be a glass material, which can ensure the mechanical stability of the interconnection intermediary component and effectively avoid the influence of excessive carrier deformation on the interconnection reliability. At the same time, the dielectric constant of the glass material is relatively low, and the loss and parasitic effects can be effectively controlled, ensuring the integrity of the transmitted signal while achieving high-density connection.

[0010] Based on the first aspect, the embodiment of the present application also provides a first implementation manner of the first aspect: The first through hole and the second through hole on the carrier layer are TGVs (Through glass vias). In this way, each blind hole located on the first build-up layer can be connected to the blind hole located on the second build-up layer through the through hole on the carrier layer, realizing the electrical connection between the die and the PCB. Based on the good TGV hole layout density and hole filling ability, it can also improve the heat transfer ability and current flow ability from one side to the other side of the interconnection intermediary component, providing a technical guarantee for ensuring the performance of the high-density layout chips.

[0011] Based on the first aspect, or the first implementation manner of the first aspect, the embodiment of the present application also provides a second implementation manner of the first aspect: The build-up layer is made of an organic material. That is to say, the build-up layers on both sides of the carrier layer are made of an organic material, and the local interconnection component for the high-density layout of dies is manufactured by using a rigid inorganic carrier and an organic build-up layer system.

[0012] Exemplarily, the build-up layer can be made of ABF (Ajinomoto Build-up Film), which can ensure the hole forming shape and dimensional accuracy of the blind vias on the build-up layer, facilitating the formation of reliable electrical connections.

[0013] In practical applications, the build-up layer can also be made of other organic materials such as PP (Prepreg).

[0014] Based on the first implementation manner of the first aspect, the embodiments of the present application further provide a second implementation manner of the first aspect: the first interface, the second interface, the third interface, and the fourth interface are respectively interface pads formed on the build-up layer on the corresponding side. That is, the first interface pad and the second interface pad for connecting with the die are formed on the first build-up layer. Among them, the first interface pad is electrically connected to the first through hole, and the second interface pad is electrically connected to the top pins of the local interconnection component; the third interface pad and the fourth interface pad for connecting with the PCB are formed on the second build-up layer, the third interface pad is electrically connected to the first through hole, and the fourth interface pad is electrically connected to the second through hole. With such a setting, as the interfaces connecting the die and the PCB, each interface pad can be directly used to achieve the corresponding electrical connection, featuring simple structure and good processability.

[0015] Based on the second implementation manner of the first aspect, the embodiments of the present application further provide a third implementation manner of the first aspect: solder mask layers are respectively covered on the build-up layers on both sides of the carrier layer; a first external bump and a second external bump are formed on the solder mask layer on one side of the carrier layer, and the first external bump and the second external bump are respectively electrically connected to the first interface and the second interface on the corresponding side; a third external bump and a fourth external bump are formed on the solder mask layer on the other side of the carrier layer, and the third external bump and the fourth external bump are respectively electrically connected to the third interface and the fourth interface on the corresponding side. In this way, external bumps are formed by laminating on the interface pads, and the die and the PCB are connected through the corresponding external bumps. It has good assembly processability.

[0016] Based on the third implementation manner of the first aspect, the embodiments of the present application further provide a fourth implementation manner of the first aspect: the second external bump is a Ni / Sn Pillar structure. For example but not limited to, it can be Ni / Sn Pillars with a pitch of 50um. In this way, corresponding to the high-density interconnection line layer on the side of the local interconnection component 2, a high-density bump layout can be formed, and reliable electrical connection and good heat dissipation performance can be provided.

[0017] Based on the first aspect, or the first implementation manner of the first aspect, or the second implementation manner of the first aspect, or the third implementation manner of the first aspect, or the fourth implementation manner of the first aspect, or the fifth implementation manner of the first aspect, the embodiments of the present application further provide a sixth implementation manner of the first aspect: The interconnection intermediate component further includes a passive device. Accordingly, a second groove is formed on the first surface of the carrier layer, and the passive device is embedded in the second groove; a fifth interface for connecting to the die is further provided on the build-up layer on the first surface side of the carrier layer, and the fifth interface is electrically connected to the top pin of the passive device. In actual use, the passive device can be buried on the first surface side of the carrier layer according to actual needs, and the electrical performance can be further improved without increasing the board area occupied by the interconnection intermediate component.

[0018] Exemplarily, the passive device can be a device such as a capacitor, a resistor or an inductor.

[0019] In actual application, a fifth external bump can also be formed on the solder mask layer on one side of the carrier layer, and the fifth external bump is electrically connected to the fifth interface. In this way, it can be connected to the die side through the corresponding external bump, and the assembly processability is good.

[0020] In other actual applications, the first external bump, the third external bump, the fourth external bump and the fifth external bump are all external convex structures formed by using the Small Outline Package (SOP) process. For example but not limited to, an external convex structure with a pitch of 130um to 150um has good processability.

[0021] Based on the first aspect, or the first implementation manner of the first aspect, or the second implementation manner of the first aspect, or the third implementation manner of the first aspect, or the fourth implementation manner of the first aspect, or the fifth implementation manner of the first aspect, the embodiments of the present application further provide a sixth implementation manner of the first aspect: The local interconnection component includes a dielectric layer and a high-density interconnection line layer stacked, and the dielectric layer is made of an organic material. Exemplarily, the dielectric layer of the local interconnection component 2 can be made of PI (polyimide), PP (polypropylene) or ABF (Ajinomoto Build-up Film).

[0022] In the second aspect of the embodiments of the present application, a chip packaging system is provided. The chip packaging system includes a PCB, a plurality of die chips, and the interconnection intermediary component as described above. The interconnection intermediary component is disposed on the surface of the PCB and is connected to the PCB through a third interface and a fourth interface; at least two die chips are coupled to the PCB through the interconnection intermediary component and are connected to the interconnection intermediary component through a first interface and a second interface, and adjacent two die chips are electrically connected through a local interconnection component on the interconnection intermediary component. In this way, high-density short-distance electrical connections between die chips and between die chips and the PCB can be achieved through the interconnection intermediary component. For example, but not limited to, it can be used to achieve power supply, communication (data signals and control signals) transmission, etc. At the same time, based on the interconnection intermediary component with good reliability, mountability, and supplyability, the design requirements on the PCB side can be reduced, and the design cost and process implementation cost of the board-level packaging system can be reasonably controlled.

[0023] In practical applications, the number of interconnection intermediary components provided can be determined according to the actual system function requirements, and the interconnection intermediary components can be arranged at intervals.

[0024] Exemplarily, the substrate of the PCB can be a BT board, a ceramic board, a glass board, or a metal board.

[0025] Based on the second aspect, the embodiments of the present application also provide a first implementation manner of the second aspect: at least one die chip is electrically connected to a passive device on the interconnection intermediary component through a fifth interface. With such a setting, while meeting the trend requirements of high-density layout, good electrical performance is taken into account.

[0026] Based on the second aspect, or the first implementation manner of the second aspect, the embodiments of the present application also provide a second implementation manner of the second aspect: the solder joints between the interconnection intermediary component and the PCB are coated with underfill to effectively improve the welding reliability.

[0027] Exemplarily, after performing a flux cleaning operation, an underfill process can be used to protect the solder joints between the interconnection intermediary component and the PCB, and then the die chips are assembled.

[0028] Based on the second aspect, or the first implementation manner of the second aspect, or the second implementation manner of the second aspect, the embodiments of the present application also provide a third implementation manner of the second aspect: the chip packaging system further includes other functional devices disposed on the PCB. In practical applications, the other functional devices disposed on the PCB can include at least one of a power supply module, a connector, and a capacitor.

[0029] Exemplarily, for the power supply module, the die and the interposer are located on one side surface of the PCB, and the power supply module is located on the other side surface of the PCB, on the surface of the PCB opposite to the die. Thus, a board-level architecture with vertical power supply having lower power supply loss and higher integration is formed. Exemplarily, the power supply module can also be located on the same side surface of the PCB as the die and the interposer, forming a board-level architecture with horizontal power supply.

[0030] Exemplarily, for the connector, the connector can be located on the same side surface as the die and the interposer, the link length can be reasonably controlled, and the link loss between the connector and the die can be reduced.

[0031] In the second aspect of the embodiments of the present application, an electronic device is provided. The electronic device includes a main board and the chip packaging system as described above, and the chip packaging system is disposed on the main board. Exemplarily, the chip packaging system can be functional components such as a CPU (Central Processing Unit), a GPU (Graphic Processing Unit), an ASIC (Application Specific Integrated Circuit), an SOC (System on Chip), etc. configured in the electronic device.

[0032] In practical applications, the electronic device can be a server, a computer, or a high-performance computing cluster. Additionally, the electronic device can also be a switch, a router, an indoor baseband processing unit, or an edge device, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of the architecture of a chip board-level system provided by the embodiments of the present application;

[0034] Figure 2 It is a schematic diagram of an interposer provided by the embodiments of the present application;

[0035] Figure 3 It is a schematic diagram of the assembly process of a chip board-level system provided by the embodiments of the present application;

[0036] Figure 4 It is a schematic diagram of another interposer provided by the embodiments of the present application;

[0037] Figure 5 It is a schematic diagram of another architecture of a chip board-level system provided by the embodiments of the present application;

[0038] Figure 6 It is a schematic diagram of the structure of an electronic device provided by the embodiments of the present application. Specific Embodiments

[0039] The embodiment of the present application provides a realization scheme for a chip packaging structure with locally high density, which effectively takes into account the requirements of high-density layout while improving installability, reliability, and supplyability.

[0040] In scenarios of high-density layout and high integration, flip chips are applied in medium- and high-performance products. Taking a typical FCBGA packaging architecture as an example, the line width capability of the substrate is usually about 15um. To improve the layout density of the architecture, a silicon interposer is arranged between the die and the substrate. The line width capability of the RDL formed on the silicon wafer can reach 1um, which is much smaller than the line width formed on the resin substrate, enabling the die to be placed with a small pitch. The FCBGA package is installed on the PCB board to form a chip board-level system that can meet the established functions. With the improvement of product performance, the number of die integrated on the FCBGA packaging architecture increases accordingly, resulting in an increase in the size of the FCBGA, and development bottlenecks have emerged in terms of installability, reliability, and supplyability.

[0041] Based on this, the embodiment of the present application provides an interconnection intermediary component, including a local interconnection component and a carrier layer. The local interconnection component includes a dielectric layer and a high-density interconnection line layer arranged in a stacked manner. The carrier layer includes a first surface and a second surface. A first groove is formed on the first surface of the carrier layer, and the local interconnection component is embedded in the first groove. The carrier layer has a first through hole and a second through hole. Among them, the first through hole penetrates between the first surface and the second surface of the carrier layer, and the second through hole penetrates between the bottom of the first groove and the second surface of the carrier layer. A first build-up layer is covered on the first surface side of the carrier layer. The first build-up layer has a first interface and a second interface for connecting with the die. The first interface is electrically connected to the first through hole, the second interface is electrically connected to the local interconnection component, and the local interconnection component is electrically connected to a plurality of second interfaces. A second build-up layer is provided on the second surface side of the carrier layer, and a third interface and a fourth interface for connecting with the PCB are formed on the second build-up layer. The third interface is electrically connected to the first through hole, and the fourth interface is electrically connected to the second through hole.

[0042] With such a setting, based on this interconnection intermediary component, high-density connection of die-to-board packaging can be realized. Using the carrier layer as the layout carrier of the local interconnection component, the single body size is relatively small, which can effectively reduce the risk of deformation and has high reliability. Compared with the FCBGA packaging architecture, the embodiment of the present application uses the interconnection intermediary component as the connection layer, and simplifies from interposer→substrate→PCB to interposer (interconnection intermediary component)→PCB. Different process dies can be directly installed on the PCB, effectively avoiding the installation difficulty caused by the warping of large-size FCBGA, having good installability, and effectively improving the product manufacturing yield.

[0043] In addition, the interconnect intermediary component formed based on the carrier layer can be constructed according to the number of dies to be interconnected, whereby the monomer size can be reasonably controlled. In practical applications, it is not affected by the difficulty of realizing a large-size substrate and has good supplyability. In addition, the interconnect intermediary component with a relatively small monomer size has good processability and can further improve the supplyability.

[0044] To better understand the technical solution and technical effect of the present application, without loss of generality, the vertical power supply board-level architecture will be used as an application example of the interconnect intermediary component below, and specific embodiments will be described in detail with reference to the accompanying drawings. Please refer to Figure 1 , which is a schematic diagram of the architecture of a chip board-level system provided by an embodiment of the present application.

[0045] As Figure 1 shown, on the PCB 20 of the chip board-level system 100, there are provided an interconnect intermediary component 10, a power supply module 40, and a connector 50. Multiple dies 30 achieve high-density short-distance electrical connections between dies 30 and between die 30 and the PCB 20 through the interconnect intermediary component 10. For example, but not limited to, it can be respectively used to achieve power supply, communication (data signals and control signals) transmission, etc. In this embodiment, the die 30 is located on one side surface of the PCB 20, and the power supply module 40 is located on the other side surface of the PCB 20, forming a board-level architecture with vertical power supply having lower power supply loss and higher integration. In other possible implementation solutions, the power supply module 40 can also be located on the same side surface of the PCB 20 as the die 30, forming a board-level architecture with horizontal power supply.

[0046] In specific implementation, the chip board-level system architecture can be implemented by the mSAP (Modified Semi-Additive Process) process or the SAP (Semi-Additive Process) process. The embodiments of the present application do not make limitations.

[0047] Exemplarily, in this embodiment, an interconnect intermediary component 10 is provided on one side surface of the PCB 20. The die 30 can be coupled to the PCB 20 through the interconnect intermediary component 10 and achieve electrical connection with the PCB 20. At the same time, electrical connection between two adjacent dies 30 is achieved based on the interconnect intermediary component 10. For example, but not limited to, it is used for high-performance data transmission between dies.

[0048] It should be understood that in other possible implementation solutions, the number of interconnected intermediate components 10 can be determined according to the actual system function requirements. For example, a plurality of interconnected intermediate components (not shown in the figure) can be provided, such as but not limited to two or three interconnected intermediate components. For the case of arranging a plurality of interconnected intermediate components on one side surface of the PCB 20, the interconnected intermediate components can be arranged at intervals. In a specific implementation, regardless of the number of interconnected intermediate components 10 on the PCB 20, the connection manner between the interconnected intermediate component 10, the PCB, and the chiplet 30 is the same. Therefore, the following takes the case where one interconnected intermediate component 10 is provided on the PCB as an example for description.

[0049] For multiple chiplets in the upper board assembly, some chiplets can be electrically connected based on the interconnected intermediate component, and the other part of the chiplets can be directly electrically connected to the PCB 20 (not shown in the figure). For the chiplets that are electrically connected based on the interconnected intermediate component, in one implementation manner, each chiplet can be connected to other chiplets based on the local interconnect component 2 on the interconnected intermediate component 10; in another implementation manner, some chiplets can also be connected to other chiplets based on the local interconnect component 2 on the interconnected intermediate component 10. That is to say, among the chiplets that are electrically connected based on the interconnected intermediate component, at least two chiplets 30 are electrically connected through the local interconnect component 2, which can be specifically determined according to the overall product design, and the embodiments of the present application do not make any limitations.

[0050] Among them, the connector 50, the interconnected intermediate component 10, and the multiple chiplets 30 are located on the same side surface of the PCB 20 and are used to connect to other external devices (not shown in the figure). The connector 50 and the chiplet 30 are located on the same side surface, so that the link length can be reasonably controlled, and the link loss between the connector and the chiplet can be reduced. For the connector 50 installed on the PCB 20, its structural form and the set number can be configured according to the function of the board-level system to achieve the electrical connection between the external device and the side of the PCB 20, and it only needs to meet the requirements of electrical interaction.

[0051] In addition, as an optional configuration structure, the connector 50 can also be located on the other side surface of the PCB 20 that is opposite to the interconnected intermediate component 10 and the chiplet 30, rather than being limited to being located on the same side surface of the PCB 20 as the interconnected intermediate component 10 and the chiplet 30. The embodiments of the present application do not make any limitations.

[0052] Again Figure 1 As shown, in addition to the power supply module 40 and the connector 50, other functional devices can also be provided on the PCB 20 of the chip board-level system 100. Optionally, other board-level functional devices can also be provided on the PCB 20, such as Figure 1As shown, for this vertical power supply board-level architecture, a Super Voltage Divider Module (SVDM) 60 is provided on the other side surface of the PCB 20. Based on the switching technology of the SVDM, the input voltage can be increased to a higher voltage output through a voltage multiplier circuit. At the same time, a Multi-layer Ceramic Capacitor (MLCC) 70 is also provided on the other side surface of the PCB 20 to improve the power supply performance.

[0053] In other possible implementation manners, in addition to the SVDM, other active devices can also be integrally provided on the PCB 20, such as, but not limited to, a voltage regulator for ensuring the stability of the output voltage, a current sensor for monitoring the current of the power supply output, a voltage sensor for monitoring the voltage of the power supply output, etc.; in addition to capacitors, other passive devices can also be integrally provided on the PCB 20, such as, but not limited to, devices such as resistors or inductors.

[0054] It should be understood that for other functional devices on the PCB 20, they can be configured according to the board-level system functions in the actual application scenarios. The embodiments of the present application do not make any limitations.

[0055] It should be noted that for this chip board-level system architecture, each die 30 can be of the same type of die or different types of dies to achieve different functional configurations. In a specific implementation, at least part of the multiple dies 30 are memory dies, which can be determined according to the overall design requirements of the specific application scenario for realizing data reading and writing operations; such as, but not limited to, integrated circuit components such as CPUs, GPUs, ASICs, and SOCs. The embodiments of the present application do not make any limitations.

[0056] In this implementation scheme, the interconnection intermediary component 10 for realizing high-density short-distance connection between die and die and between die and PCB, its carrier layer 1 is made of a rigid inorganic material to provide stable mechanical properties. Here, the "rigid inorganic material" refers to an inorganic material with high hardness, good rigidity, and high chemical stability, such as, but not limited to, a glass substrate. In other possible implementation manners, the carrier layer 1 can also be made of other rigid inorganic materials as the carrier substrate of the local interconnection device. The embodiments of the present application do not make any limitations.

[0057] Please refer to Figure 2 , which is a schematic diagram of an interconnection intermediary component provided by an embodiment of the present application.

[0058] In this embodiment, the carrier layer 1 of the interconnection intermediary component 10 is made of glass material, which can ensure the mechanical stability of the interconnection intermediary component 10 and avoid the influence of excessive carrier deformation on the interconnection reliability. At the same time, the dielectric constant of the glass material is relatively low, and the loss and parasitic effects can be effectively controlled, ensuring the integrity of the transmitted signal while achieving high-density connection.

[0059] A local interconnection component 2 is embedded on the carrier layer 1. The local interconnection component 2 includes a dielectric layer and a high-density interconnection line layer arranged in a stacked manner. Its structure can be a structure of a mixture of dielectric and redistribution layer, that is, a high-density interconnection line layer is constructed through the redistribution layer. For example but not limited to, the local interconnection component 2 can be a structure formed by alternately stacking a layer of dielectric and a layer of metal (such as copper). Through the local interconnection component 2, electrical connection between two adjacent dielets 30 can be achieved, or electrical connection between two adjacent dielets 30 in a group of dielets can be achieved.

[0060] At the same time, a passive device 6 is also embedded on the carrier layer 1. For example but not limited to, the passive device 6 can be a capacitor, resistor, inductor or other devices, which can improve the electrical performance without increasing the board area occupied by the interconnection intermediary component 10 on the PCB. In other possible implementation manners, according to the chip performance requirements, the passive device 6 can be a selectable configuration device, that is, the passive device may not be configured on the carrier layer 1.

[0061] Specifically, the carrier layer 1 includes a first surface and a second surface. A first groove 11 and a second groove 14 are formed on the first surface of the carrier layer 1, which are respectively used for burying the local interconnection component 2 and the passive device 6. Among them, the local interconnection component 2 is embedded in the first groove 11, and the passive device 6 is embedded in the second groove 14. It can be understood that the "embedding" here includes the situation where the device is completely built into the corresponding embedding groove, and also includes the situation where a small part of the device is exposed outside the corresponding embedding groove.

[0062] In this embodiment, the local interconnection component 2 can be a double-sided connection structure. Figure 2 Taking the placement direction of the shown interconnection intermediary component 10 as the reference direction, the pins for electrically connecting to the dielet 30 are located at the top of the local interconnection component 2, and the pins for electrically connecting to the PCB 20 are located at the bottom of the local interconnection component 2. For the local interconnection component 2 arranged on the carrier layer 1, the interconnection intermediary component 10 provided in this embodiment realizes external electrical connection through the buildup 3.

[0063] In a specific implementation, the build-up layer 3 can be made of organic materials, such as but not limited to ABF, which can ensure the hole shape and dimensional accuracy of the blind holes on the build-up layer, so as to form a reliable electrical connection. Overall, the local interconnection component 2 is manufactured using a rigid inorganic carrier and an organic build-up layer system to form an interconnection intermediate component 10.

[0064] In other specific implementations, the build-up layer 3 may also be made of other organic materials such as PP.

[0065] For example Figure 2 As shown, the build-up layer 3 covered by the first side of the carrier layer 1 is the first build-up layer, and the build-up layer 3 covered by the second side of the carrier layer 1 is the second build-up layer. The build-up layer 3 material is provided with blind holes for external connection, and the surface of the build-up layer 3 provides interface pads for connecting the core particles with the local interconnection components 2 and the PCB. At the same time, the interconnection intermediate component 10 realizes the upper and lower interconnection through the through holes set on the carrier layer 1. In a specific implementation, each TGV through hole that is interconnected with each other can be formed by metallization based on the glass through hole TGV; combined with Figure 1 As shown, in other words, each blind hole on the first build-up layer is directly or indirectly connected to the blind hole on the second build-up layer through the through hole on the carrier layer 1, so as to realize the electrical connection between the core particle and the PCB. In this way, based on the good TGV hole density and hole filling ability, the heat transfer and flow capacity in the Z direction (the direction perpendicular to the carrier layer) can also be improved.

[0066] Specifically, the through holes on the carrier layer 1 include a first through hole 12 and a second through hole 13, wherein the first through hole 12 is arranged between the first surface and the second surface of the carrier layer 1, so that the blind hole on the first build-up layer can directly pass through the through hole on the carrier layer 1 to achieve connection with the blind hole on the second build-up layer, and the through hole on the carrier layer 1 is connected to the first build-up layer. Figure 1 As shown, the core particle 30 is interconnected with the PCB 20 side through the first through hole 12; wherein, the second through hole 13 is set between the bottom of the first groove 11 and the second surface of the carrier layer 1, based on the electrical connection between the bottom pin of the local interconnection component 2 embedded in the first groove 11 and the second through hole 13, the blind hole on the first build-up layer can be indirectly connected to the blind hole on the second build-up layer through the through hole on the carrier layer 1, combined with Figure 1 As shown, the chip 30 is interconnected with the PCB 20 side through the local interconnection component 2 and the second through hole 13.

[0067] Accordingly, a first interface pad 31, a second interface pad 32, and a fifth interface pad 37 for connecting to the die 30 are formed on the first build-up layer. Among them, the first interface pad 31 is electrically connected to the first through-hole 12, the second interface pad 32 is electrically connected to the top pins of the local interconnect component 2, and the fifth interface pad 37 is electrically connected to the top pins of the passive device 6; a third interface pad 33 and a fourth interface pad 34 for connecting to the PCB are formed on the second build-up layer. The third interface pad 33 is electrically connected to the first through-hole 12, and the fourth interface pad 34 is electrically connected to the second through-hole 13. As an interface connecting the die 30 and the PCB 20, each interface pad can be directly used to achieve the corresponding electrical connection, or an external bump can be formed on the interface pad to connect to the die 30 and the PCB 20 through the corresponding external bump.

[0068] For another example Figure 2 As shown, solder mask (green oil layer) 4 is respectively coated on the build-up layers 3 on both sides of the interposer 10, and external bumps 5 are formed on the solder mask 4. Among them, on the side of the local interconnect component 2 of the interposer 10, the external bump 5 can include a first external bump 51 and a second external bump 52. The first external bump 51 is sequentially connected to the first through-hole 12 through the first interface pad 31 and the blind hole 36 on the build-up layer. Each second external bump 52 is sequentially connected to the top pins of the corresponding local interconnect component 2 through the second interface pad 32 and the via hole 35 on the build-up layer. Among them, on the other side of the interposer 10, the external bump 5 can include a third external bump 53 and a fourth external bump 54. The third external bump 53 is sequentially connected to the first through-hole 12 through the third interface pad 33 and the corresponding blind hole 36, and the fourth external bump 54 is sequentially connected to the second through-hole 13 through the fourth interface pad 34 and the corresponding blind hole 36.

[0069] For the passive device 6 embedded in the second groove 14, on the side of the local interconnect component 2 of the interposer 10, the external bump 5 can further include a fifth external bump 44, and the fifth external bump 44 is sequentially connected to the pins of the passive device 6 through the fifth interface pad 37 and the corresponding blind hole 36.

[0070] In a specific implementation, each external bump 5 can be implemented using the same process or different processes according to needs. For example but not limited to, the first external bump 51, the third external bump 53, the fourth external bump 54, and the fifth external bump 55 can be external convex structures formed based on the Small Outline Package (SOP) process; the second external bump 52 can be a nickel-tin column structure, which can correspond to the high-density interconnect line layer on the side of the local interconnect component 2 to form a high-density bump layout. Thus, reliable electrical connection and good heat dissipation performance can be provided.

[0071] In other possible implementation manners, the number of the externally-connected bumps 5 provided and the forming process can be determined according to the overall design of the product, and the embodiments of the present application do not make any limitations. Among them, for each local interconnection component 2, the number of the second externally-connected bumps 52 provided can be determined according to the top pin layout of the local interconnection component 2. As Figure 2 shown, each local interconnection component 2 is interconnected with two adjacent dies 30. In other possible implementation manners, each local interconnection component 2 can be interconnected with more than two other dies 30. In other words, multiple dies 30 can be electrically connected through one local interconnection component 2.

[0072] Based on the structural feature that the local interconnection component 2 is embedded in the carrier layer 1, to determine the thickness of the build-up layer 3, it is only necessary to meet the forming conditions of the second interface pads 32 corresponding to the local interconnection component 2. In this way, by reasonably controlling the thickness of the build-up layer 3, a stacked via can be arranged thereon to achieve the corresponding electrical connection, which has better processability.

[0073] In possible implementation solutions, the structural forms and the board surface layout forms of the first interface pads 31 and the second interface pads 32 can be determined according to the external interface forms of the local interconnection component 2 and the die. Similarly, the structural forms and the board surface layout forms of the third interface pads 33 and the fourth interface pads 34 can also be determined according to the interface form on the PCB side. The embodiments of the present application do not make any limitations.

[0074] For the local interconnection component 2, its dielectric layer can be made of an organic material. In a specific implementation, the dielectric layer of the local interconnection component 2 can be made of PI, PP or ABF.

[0075] For the PCB 20, its substrate can be a BT (Bismaleimide Triazine, BT resin) board. Of course, in other possible implementation solutions, the PCB 20 can be a circuit board of an inorganic system, and the substrate of the PCB 20 can be a ceramic board, a glass board, a metal board, etc. The embodiments of the present application do not make any limitations.

[0076] The following briefly describes Figure 3 the assembly process of the chip board-level system shown in Figure 1 .

[0077] Step S301: Prepare the glass substrate incoming material of the carrier layer 1.

[0078] Step S302: Open TGV holes. TGV holes are opened at the positions of the formed through holes (the first through hole 12 and the second through hole 13) of the glass substrate. The specific hole-forming process can be determined according to the overall design requirements of the product, such as, but not limited to, sandblasting method, photosensitive glass method or laser-induced etching method, etc.

[0079] Step S303, TGV metal patterning. Based on the TGV process, electroplating is used to fill the holes, and corresponding interface pads are formed on both side surfaces of the carrier layer 1. For example, but not limited to, the process of plugging holes with copper paste and double-sided printing and sintering of copper paste are adopted to form a current-carrying structure with good heat transfer and current-carrying capabilities.

[0080] Step S304, opening blind vias and local polishing. The first groove 11 and the second groove 14 are opened on the carrier layer 1. In a specific implementation, UV Laser (ultraviolet laser), CO2 laser (carbon dioxide laser) or other mechanical processing techniques can be used to open the grooves, and local polishing is performed to form an embedded cavity.

[0081] Step S305, embedding the local interconnection component 2 and the passive device 6. Here, the bottom pins of the local interconnection component 2 are connected to the second through-hole 13 at the bottom of the first groove 11. In a specific implementation, the passive device 6 can be a capacitor or an inductor.

[0082] Step S306, filling the blind vias and pressing to add layers. The gaps between the local interconnection component 2 and the first groove 11, and between the passive device 6 and the second groove 14 are filled and pressed, and at the same time, after hot pressing and leveling on both sides of the carrier layer 1, the additional layer 3 is formed. In a specific implementation, the filling material and the additional layer material can be ABF.

[0083] In other possible implementation manners, the material used to fill the gap can be the same as or different from the additional layer material.

[0084] Step S307, filling the vias with patterns and forming external bumps to fabricate the interconnection intermediate component 10.

[0085] First, blind vias are opened on the additional layer 3 and a pad structure is formed. For example, but not limited to, the surface of the pad can be processed by the ENIG (Electroless Nickel / Immersion Gold) process, and specific selection can be made according to actual process conditions. This is not limited in the embodiments of the present application.

[0086] At the same time, an outer solder mask layer 4 is formed outside the additional layers 3 on both sides, and the surface of the outer layer metal is processed to form interface pads. For the second external bump 52 connected to the top pins of the local interconnection component 2, it can be a Ni / Sn Pillar with a pitch of 50um, taking into account good electrical connection and heat dissipation performance; among them, for the first external bump 51, the third external bump 53, the fourth external bump 54 and the fifth external bump 55 on both sides of the interconnection intermediate component 10, they can be external convex structures with a pitch of 130um - 150um formed based on the small epitaxial packaging process, which has good processability.

[0087] In specific implementation, the processes of opening holes, electroplating, and surface pads can be implemented using existing technologies, and the embodiments of this application do not make any limitations.

[0088] Based on the interconnecting intermediate component 10 obtained from steps 301 to 307, the interconnecting intermediate component 10 can be first assembled on the PCB 20, and then the devices can be assembled.

[0089] Step S308, PCB assembly and underfill. The interconnecting intermediate component 10 is placed on the PCB 20, and the third external bumps 53 and the fourth external bumps 54 on the interconnecting intermediate component 10 are soldered to the interface pads on the surface layer of the PCB 20 to meet the system requirements. At the same time, the underfill process can be used to protect the solder joints between the interconnecting intermediate component 10 and the PCB 20. Specifically, the liquid underfill material is injected or sprayed on the periphery of the interconnecting intermediate component 10, and penetrates between the interconnecting intermediate component 10 and the PCB 20 using the principle of capillary flow, and is heated and cured, which can effectively improve the soldering reliability.

[0090] In other possible implementation solutions, the above liquid underfill can also be replaced by NCF (Non-Conductive Adhesive Film), which can also achieve the function of reliably fixing the interconnecting intermediate component 10.

[0091] Step S309, device assembly, to fabricate the chip board-level system 100 that realizes vertical power supply. In specific implementation, according to the functional configuration requirements of the system, the die 30 can be selectively connected to the first external bumps 51 and the second external bumps 52 on the top of the interconnecting intermediate component 10, and the electrical connection with the PCB 20 is realized through the interconnecting intermediate component 10.

[0092] Among them, the connector 50 and the interconnecting intermediate component 10 are located on the same side surface of the PCB 20, and the power supply module 40, the super voltage divider module 60, and the chip multi-layer ceramic capacitor 70 are located on the other side surface of the PCB 20.

[0093] In other possible implementation manners, based on the interconnecting intermediate component 10 obtained from steps 301 to 307, the die can be first assembled on the interconnecting intermediate component 10, then the interconnecting intermediate component 10 integrated with the die can be assembled on the PCB 20, and finally the assembly of other devices on the board can be completed. The embodiments of this application do not make any limitations.

[0094] The interconnected intermediate component described in the foregoing embodiments has passive devices embedded in its carrier layer to improve electrical performance. In other specific implementations, the carrier layer of the interconnected intermediate component may also be embedded only with local interconnection components 2 for die-on-board assembly. Please refer to Figure 4 and Figure 5 , where Figure 4 is a schematic diagram of another interconnected intermediate component provided by an embodiment of the present application, Figure 5 is a schematic architecture diagram of another chip-board level system provided by an embodiment of the present application, and this system architecture is constructed based on the interconnected intermediate component shown in Figure 4 . To clearly show the differences and connections between this implementation and the embodiments described in Figure 1 and Figure 2 , the components and structures with the same functions are denoted by the same reference numerals in the figure.

[0095] Compared with the interconnected intermediate component described in Figure 2 , the difference of this implementation is that only local interconnection components 2 are embedded in the interconnected intermediate component 10. As shown in Figure 4 , on the first surface of the carrier layer 1, a plurality of first grooves 11 for embedding and arranging the local interconnection components 2 are provided. As shown in combination with Figure 5 , based on the plurality of local interconnection components 2 embedded in the carrier layer 1, the short-distance interconnection between dies 30 is realized by making full use of the area size of the carrier layer 1.

[0096] It should be noted that the number of local interconnection components 2 provided on the carrier layer 1 can be determined according to the overall product design, and the embodiments of the present application do not make any limitations.

[0097] In addition to the foregoing chip packaging system, this embodiment also provides an electronic device. Please refer to Figure 5 , which is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

[0098] As shown in Figure 5 , the electronic device 1000 includes a housing 300 and a main board 200 disposed inside the housing 300. A chip-board level system 100 as described in the foregoing embodiments is disposed on the main board 200. Here, the chip-board level system 100 may be a functional component such as a CPU, a GPU, an ASIC, or an SOC.

[0099] In a specific implementation, the electronic device may be a server, a computer, or a high-performance computing cluster. For example, it may be a high-power, high-integration, and ultra-large-scale data center server; in addition, the electronic device may also be a switch, a router, an indoor baseband processing unit, or an edge device, etc., and the embodiments of the present application do not make any limitations.

[0100] It should be understood that other functions of the electronic device do not constitute the core inventive points of this application, and those skilled in the art can implement them according to the prior art, so they will not be elaborated herein.

[0101] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. An interconnected intermediate component, characterized in that, It comprises a local interconnection component and a carrier layer, wherein the carrier layer comprises a first surface and a second surface, a first groove is formed on the first surface of the carrier layer, and the local interconnection component is embedded in the first groove; The carrier layer has a first through hole and a second through hole, the first through hole is arranged between the first surface and the second surface of the carrier layer, and the second through hole is arranged between the bottom of the first groove and the second surface of the carrier layer; The build-up layer on the first side of the carrier layer has a first interface and a second interface for connecting to the core particle, and the build-up layer on the second side of the carrier layer has a third interface and a fourth interface for connecting to the printed circuit board; The first interface is electrically connected to the third interface through the first through-hole, the second interface is electrically connected to the fourth interface through the local interconnection component and the second through-hole, and the local interconnection component is electrically connected to a plurality of the second interfaces.

2. The interconnected intermediary component according to claim 1, characterized in that, The carrier layer is made of rigid inorganic material.

3. The interconnected intermediary component according to claim 2, characterized in that, The rigid inorganic material is a glass material.

4. The interconnected intermediary component according to claim 3, characterized in that, The first through hole and the second through hole on the carrier layer are glass through holes.

5. The interconnected intermediary component according to any one of claims 1 to 4, characterized in that, The build-up layer is made of organic material.

6. The interconnected intermediary component according to claim 5, characterized in that, The added layer is made of ajinomoto laminated film.

7. The interconnected intermediary component according to any one of claims 1 to 6, characterized in that, The first interface, the second interface, the third interface and the fourth interface are respectively formed as interface pads on the build-up layer on the side.

8. The interconnected intermediary component according to claim 7, characterized in that, The build-up layers on both sides of the carrier layer are respectively covered with solder resist layers; a first external bump and a second external bump are formed on the solder resist layer on one side of the carrier layer, and the first external bump and the second external bump are respectively electrically connected to the first interface and the second interface on their side; a third external bump and a fourth external bump are formed on the solder resist layer on the other side of the carrier layer, and the third external bump and the fourth external bump are respectively electrically connected to the third interface and the fourth interface on their side.

9. The interconnected intermediary component according to claim 8, wherein The second external bump is a nickel-tin column structure.

10. The interconnected intermediary component according to claim 8 or 9, characterized in that, It also includes a passive component, the first surface of the carrier layer is further provided with a second groove, and the passive component is embedded in the second groove; The build-up layer on the first surface side of the carrier layer also has a fifth interface for connecting to the core particle, and the fifth interface is electrically connected to the passive device.

11. The interconnected intermediate component according to claim 10, wherein, A fifth external bump is also formed on the solder resist layer located on one side of the carrier layer, and the fifth external bump is electrically connected to the fifth interface.

12. The interconnected intermediary component according to claim 11, wherein The first external bump, the third external bump, the fourth external bump and the fifth external bump are all external bump structures formed by adopting a small epitaxial packaging process.

13. The interconnected intermediary component according to any one of claims 1 to 12, characterized in that, The local interconnection component comprises a dielectric layer and a high-density interconnection line layer which are stacked, and the dielectric layer is made of organic material.

14. A chip packaging system, characterized in that, The chip packaging system includes a printed circuit board, a plurality of dies, and the interconnecting intermediary component according to any one of claims 1 to 13. The interconnecting intermediary component is disposed on the surface of the printed circuit board and is connected to the printed circuit board through a third interface and a fourth interface; at least two of the dies are coupled to the printed circuit board through the interconnecting intermediary component and are connected to the interconnecting intermediary component through a first interface and a second interface, and adjacent two of the dies are electrically connected through a local interconnect component on the interconnecting intermediary component.

15. The chip packaging system according to claim 14, wherein, At least one of the dies is electrically connected to a passive device on the interconnecting intermediary component through a fifth interface.

16. The chip packaging system according to claim 14 or 15, characterized in that, The solder joints between the interconnecting intermediary component and the printed circuit board are coated with underfill.

17. The chip packaging system according to any one of claims 14 to 16, characterized in that, A plurality of the interconnecting intermediary components are provided, and the plurality of interconnecting intermediary components are arranged at intervals on the surface of the printed circuit board.

18. The chip packaging system according to any one of claims 14 to 17, characterized in that, The substrate of the printed circuit board is a resin board, a ceramic board, a glass board, or a metal board.

19. The chip packaging system according to any one of claims 14 to 18, characterized in that, The chip packaging system further includes other functional devices disposed on the printed circuit board.

20. The chip packaging system according to claim 19, wherein The other functional devices include at least one of a power supply module, a connector, and a capacitor.

21. The chip packaging system according to claim 19 or 20, characterized in that, The other functional devices and the interconnecting intermediary component are located on the same side surface of the printed circuit board, or the other functional devices are located on the surface of the printed circuit board on the opposite side of the interconnecting intermediary component.

22. An electronic device, characterized in that, It includes a main board and the chip packaging system according to any one of claims 14 to 21, and the chip packaging system is disposed on the main board.

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