Semiconductor device

Abstract

The present disclosure provides a semiconductor device capable of achieving optimization of switching characteristics and high power density. A semiconductor device (100) is provided with a plurality of semiconductor chips (1, 2, 3) mounted on an insulating substrate (10), and a case (20) that houses the semiconductor chips (1, 2, 3). The housing (20) has a gate terminal (21), a source sensing terminal (22), a source terminal (23), and a drain terminal (24). The height of the gate terminal (21) and the height of the source sensing terminal (22) are different from each other, and the height of the source terminal (23) is lower than the height of the gate terminal (21) and the height of the source sensing terminal (22).

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. Background Art

[0002] For the purpose of facilitating wire bonding in the manufacture of semiconductor devices and miniaturizing semiconductor devices, a technique has been proposed in which height differences are provided in the respective heights of a plurality of terminals (bus bars, leads, pads, etc.) provided on a semiconductor device (for example, Patent Documents 1 and 2 below). In addition, the "height" of the terminal here refers to the height of the mounting position of the terminal, not the thickness of the terminal. Prior Art Documents Patent Documents

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2012-89548 Patent Document 2: Japanese Patent Application Laid-Open No. 6-181279 Summary of the Invention Technical Problem to be Solved by the Invention

[0004] In Patent Document 1, a structure in which height differences are provided in the heights of two main terminals (source terminal and drain terminal) is proposed, but signal terminals (gate terminal, source sense terminal, etc.) are not considered, and there is room for improvement in switching characteristics.

[0005] In Patent Document 2, the height of the signal terminal is also considered, with the main terminals arranged in the upper stage and the signal terminals arranged in the lower stage. However, in this configuration, the main lead wire connected to the main terminal becomes longer, and there is a concern that heat generation due to the main lead wire becomes larger. In order to achieve high power density of the semiconductor device, it is necessary to shorten the main lead wire.

[0006] The present disclosure has been completed to solve the above problems, and an object thereof is to provide a semiconductor device capable of optimizing switching characteristics and achieving high power density. Technical Means for Solving the Technical Problem

[0007] The semiconductor device according to the present disclosure includes: an insulating substrate; a drain pattern and a gate pattern formed on the upper surface of the insulating substrate; a plurality of semiconductor chips having a drain electrode joined to the drain pattern on the lower surface and a source electrode and a gate electrode on the upper surface; and a housing that houses the plurality of semiconductor chips and has a gate terminal, a source sensing terminal, a source terminal, and a drain terminal. The drain terminal is connected to the drain pattern via a first wire, the source terminal is connected to the source electrodes of the plurality of semiconductor chips via a second wire, the gate terminal is connected to the gate pattern via a third wire, the gate pattern is connected to the gate electrodes of the plurality of semiconductor chips via a fourth wire, the source sensing terminal is connected to the source electrode of any one of the plurality of semiconductor chips via a fifth wire. The height of the gate terminal is different from the height of the source sensing terminal, and the height of the source terminal is lower than the height of the gate terminal and the height of the source sensing terminal. Advantages of the Invention

[0008] According to the present disclosure, it is possible to optimize the switching characteristics and increase the power density of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a top view of the semiconductor device according to Embodiment 1. Figure 2 is a cross-sectional view of the semiconductor device according to Embodiment 1. Figure 3 is a cross-sectional view of the semiconductor device according to Embodiment 2. Figure 4 is a cross-sectional view of the semiconductor device according to Embodiment 3. Figure 5 is a cross-sectional view of the semiconductor device according to Embodiment 4. DETAILED DESCRIPTION

[0010] <Embodiment 1> Figure 1 and Figure 2 are diagrams showing the structure of the semiconductor device 100 according to Embodiment 1, respectively showing a top view and a cross-sectional view of the semiconductor device 100.

[0011] The semiconductor device 100 includes a plurality of semiconductor chips mounted on an insulating substrate 10. The insulating substrate 10 is formed of, for example, ceramics. In the present embodiment, an example is shown in which the first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3 are mounted as a plurality of semiconductor chips on the insulating substrate 10. The first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3 are, for example, switching elements for power control such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or IGBT (Insulated Gate Bipolar Transistor). In addition, in Figure 2 the first semiconductor chip 1 is representatively shown.

[0012] The first semiconductor chip 1 has a source electrode 1s and a gate electrode 1g on its upper surface, and a drain electrode 1d on its lower surface. The second semiconductor chip 2 has a source electrode 2s and a gate electrode 2g on its upper surface, and a drain electrode 2d on its lower surface. The third semiconductor chip 3 has a source electrode 3s and a gate electrode 3g on its upper surface, and a drain electrode 3d on its lower surface.

[0013] On the upper surface of the insulating substrate 10, a drain pattern 11 and a gate pattern 12 made of, for example, copper are formed. The drain electrode 1d of the first semiconductor chip 1, the drain electrode 2d of the second semiconductor chip 2, and the drain electrode 3d of the third semiconductor chip 3 are respectively joined to the drain pattern 11 by a joining material 41 such as solder.

[0014] In addition, on the lower surface of the insulating substrate 10, a metal pattern 13 made of, for example, copper is formed. The metal pattern 13 is joined to a copper bottom plate 15 by a joining material 42 such as solder.

[0015] A housing 20 is joined to the peripheral portion of the bottom plate 15. The housing 20 houses the insulating substrate 10 and the first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3 mounted thereon. On the housing 20, a gate terminal 21 and a source sense terminal 22 as signal terminals, and a source terminal 23 and a drain terminal 24 as main terminals through which a large current flows are provided. These terminals are terminals embedded and molded in the housing 20. By using embedded electrodes instead of external plug electrodes, it is possible to help reduce the assembly process.

[0016] The gate terminal 21, the source sensing terminal 22, and the source terminal 23 are arranged along the same side of the housing 20. The gate terminal 21 and the source sensing terminal 22 are arranged outside the source terminal 23. The height of the gate terminal 21 is different from the height of the source sensing terminal 22. The height of the source terminal 23 is lower than that of the gate terminal 21 and the source sensing terminal 22. In addition, the gate pattern 12 on the insulating substrate 10 is arranged between the drain pattern 11 and the source terminal 23.

[0017] The drain terminal 24 is connected to the drain pattern 11 via the first wire 31. The source terminal 23 is connected to the source electrodes 1s of the first semiconductor chip 1, the source electrodes 2s of the second semiconductor chip 2, and the source electrodes 3s of the third semiconductor chip 3 via the second wire 32.

[0018] The gate terminal 21 is connected to the gate pattern 12 via the third wire 33. The gate terminal 12 is connected to the gate electrodes 1g of the first semiconductor chip 1, the gate electrodes 2g of the second semiconductor chip 2, and the gate electrodes 3g of the third semiconductor chip 3 via the fourth wire 34.

[0019] The source sensing terminal 22 is connected to any one of the source electrodes 1s of the first semiconductor chip 1, the source electrodes 2s of the second semiconductor chip 2, and the source electrodes 3s of the third semiconductor chip 3 via the fifth wire 35.

[0020] The sealing material 25 is filled in the housing 20, and the opening of the housing 20 is covered by the cover 26.

[0021] According to the semiconductor device 100 according to Embodiment 1, since the heights of the gate terminal 21 and the source sensing terminal 22 as signal terminals are different from each other, the degree of freedom of wire bonding becomes higher, and a complex circuit structure can be achieved while maintaining component commonality, and the optimization of switching characteristics can be achieved. In addition, since the source terminal 23 is arranged at the lowermost stage, the second wire 32, which is the main wire for flowing a large current, can be shortened, heat generation can be suppressed, and high power density of the semiconductor device 100 can be facilitated.

[0022] In addition, in Embodiment 1, the height of the source sensing terminal 22 is made higher than the height of the gate terminal 21. That is, the heights from high to low are the source sensing terminal 22, the gate terminal 21, and the source terminal 23 in sequence. Thereby, by dividing the reference potential of source sensing, positive feedback and negative feedback during the switching operation can be appropriately controlled.

[0023] In addition, in Embodiment 1, as Figure 1As shown in the figure, when viewed from above, the third wire 33 connected to the gate terminal 21 and the fifth wire 35 connected to the source sensing terminal 22 are parallel to each other. The first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3, which are switching elements, are easily affected by the source impedance and easily disrupt the current balance between the chips. However, the fifth wire 35 connected to the source sensing terminal 22 does not cross the third wire 33 connected to the gate terminal 21. Thus, the source sensing reference potential can be optimized, and an improvement in the current balance can be expected.

[0024] Assume that the first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3 are formed of a wide bandgap semiconductor such as silicon carbide (SiC) and are driven at high speed. When the first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3 are driven at high speed, the deviation of the source impedance has a greater impact on the switching. Therefore, it is particularly effective to make the third wire 33 parallel to the fifth wire 35 when the first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3 are formed of a wide bandgap semiconductor.

[0025] <Embodiment 2> Figure 3 is a top view showing the structure of the semiconductor device 100 according to Embodiment 2. The cross-sectional view of the semiconductor device 100 is the same as that of Figure 2 the same.

[0026] In the semiconductor device 100 according to Embodiment 2, when viewed from above, the fifth wire 35 connected to the source sensing terminal 22 crosses both the second wire 32 connected to the source terminal 23 and the third wire 33 connected to the gate terminal 21. Thus, a complex circuit structure can be realized in a space-saving manner.

[0027] However, as described above, when the third wire 33 crosses the fifth wire 35, it should be noted that the first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3, which are switching elements, are easily affected by the source impedance.

[0028] <Embodiment 3> Figure 4 is a cross-sectional view showing the structure of the semiconductor device 100 according to Embodiment 3. The top view of the semiconductor device 100 is the same as that of Figure 1 or Figure 3 the same.

[0029] In the semiconductor device 100 according to Embodiment 3, the distance D from the side surface of the housing 20 to the source sensing terminal 22 and the gate terminal 21 is 3.0 mm or more. Thus, the reliability of the semiconductor device 100 and the strength during the assembly of the semiconductor device 100 are improved.

[0030] <Embodiment 4> Figure 5 This is a cross-sectional view showing the structure of the semiconductor device 100 according to Embodiment 4. The top view of this semiconductor device 100 is the same as Figure 1 or Figure 3 the same.

[0031] In the semiconductor device 100 according to Embodiment 4, the interval C between the third wire 33 connected to the gate terminal 21 and the fifth wire 35 connected to the source sense terminal 22 is 3.0 mm or more.

[0032] For example, when a customer who has purchased a product with the semiconductor device 100 sets up the semiconductor device 100 and performs wiring, there is a possibility that the source sense terminal 22 is miswired as a drain sense terminal. However, by ensuring that the interval C between the third wire 33 and the fifth wire 35 is 3.0 mm or more, it is possible to prevent discharge between the drain and gate or between the drain and source, and it is possible to prevent the occurrence of discharge breakdown. Assuming that the insulation withstand amount of air is 1 kV per 1 mm, a design can be obtained in which discharge breakdown does not occur even when a voltage of 3 kV or more is applied between the drain and gate or between the drain and source.

[0033] In addition, the respective embodiments can be freely combined, or appropriately deformed or omitted.

[0034] <Supplementary Note> Hereinafter, the respective aspects of the present disclosure are summarized and described as supplementary notes.

[0035] (Supplementary Note 1) A semiconductor device, comprising: an insulating substrate; a drain pattern and a gate pattern formed on the upper surface of the insulating substrate; a plurality of semiconductor chips having a drain electrode joined to the drain pattern on the lower surface and a source electrode and a gate electrode on the upper surface; and a housing that houses the plurality of semiconductor chips and has a gate terminal, a source sense terminal, a source terminal, and a drain terminal, the drain terminal is connected to the drain pattern via a first wire, the source terminal is connected to the source electrodes of the plurality of semiconductor chips via a second wire, the gate terminal is connected to the gate pattern via a third wire, the gate pattern is connected to the gate electrodes of the plurality of semiconductor chips via a fourth wire, the source sense terminal is connected to the source electrode of any one of the plurality of semiconductor chips via a fifth wire, The height of the gate terminal is different from the height of the source sense terminal, The height of the source terminal is lower than the height of the gate terminal and the height of the source sense terminal.

[0036] (Supplementary Note 2) The semiconductor device as described in Supplementary Note 1, The height of the source sense terminal is higher than the height of the gate terminal.

[0037] (Supplementary Note 3) The semiconductor device as described in Supplementary Note 1 or 2, When viewed from above, the third wire and the fifth wire are parallel.

[0038] (Supplementary Note 4) The semiconductor device as described in Supplementary Note 3, A plurality of the semiconductor chips are formed of a wide bandgap semiconductor.

[0039] (Supplementary Note 5) The semiconductor device as described in Supplementary Note 1 or 2, When viewed from above, the fifth wire intersects both the second wire and the third wire.

[0040] (Supplementary Note 6) The semiconductor device as described in any one of Supplementary Notes 1 to 5, The distance from the side surface of the housing to the source sense terminal and the gate terminal is 3.0 mm or more.

[0041] (Supplementary Note 7) The semiconductor device as described in any one of Supplementary Notes 1 to 6, The interval between the third wire and the fifth wire is 3.0 mm or more. Reference Numeral Explanation

[0042] 100 Semiconductor device 1 First semiconductor chip 2 Second semiconductor chip 3 Third semiconductor chip 1s, 2s, 3s Source electrodes 1d, 2d, 3d Drain electrodes 1g, 2g, 3g Gate electrodes 10 Insulating substrate 11 Drain pattern 12 Gate pattern 13 Metal pattern 15 Bottom plate 20 Housing 21 Gate terminal 22 Source sense terminal 23 Source terminal 24 Drain terminal 25 Sealing material 26 Cover 31 First Conductor 32 Second Conductor 33 Third Conductor 34 Fourth Conductor 35 Fifth Conductor 41, 42 Bonding Material

Claims

1. A semiconductor device, characterized in that, Comprising: An insulating substrate; A drain pattern and a gate pattern formed on the upper surface of the insulating substrate; A plurality of semiconductor chips having a drain electrode joined to the drain pattern on the lower surface and a source electrode and a gate electrode on the upper surface; And A housing that houses the plurality of semiconductor chips and has a gate terminal, a source sense terminal, a source terminal, and a drain terminal, The drain terminal is connected to the drain pattern via a first wire, The source terminal is connected to the source electrodes of the plurality of semiconductor chips via a second wire, The gate terminal is connected to the gate pattern via a third wire, The gate pattern is connected to the gate electrodes of the plurality of semiconductor chips via a fourth wire, The source sense terminal is connected to the source electrode of any one of the plurality of semiconductor chips via a fifth wire, The height of the gate terminal is different from the height of the source sense terminal, The height of the source terminal is lower than the height of the gate terminal and the height of the source sense terminal.

2. The semiconductor device according to claim 1, wherein The height of the source sense terminal is higher than the height of the gate terminal.

3. The semiconductor device according to claim 1 or 2, wherein When viewed from above, the third wire and the fifth wire are parallel.

4. The semiconductor device according to claim 3, wherein The plurality of semiconductor chips are formed of a wide bandgap semiconductor.

5. The semiconductor device according to claim 1 or 2, wherein When viewed from above, the fifth wire intersects both the second wire and the third wire.

6. The semiconductor device according to any one of claims 1 to 5, wherein The distance from the side surface of the housing to the source sense terminal and the gate terminal is 3.0 mm or more.

7. The semiconductor device according to any one of claims 1 to 6, wherein The interval between the third wire and the fifth wire is 3.0 mm or more.

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