Low-offset operational amplifier based on cyclic folded cascode structure and application of low-offset operational amplifier

Abstract

The invention discloses a low-offset operational amplifier based on a cyclic folded cascode structure and application of the low-offset operational amplifier, and belongs to the technical field of operational amplifiers. The low-offset operational amplifier based on the cyclically-folded cascade structure comprises a cyclically-folded cascade structure operational amplifier and an auxiliary operational amplifier which are connected with each other, wherein the negative input end voltage value of the auxiliary operational amplifier is set as the clamping value of the output voltage Vout of the cyclically-folded cascade structure operational amplifier. According to the low-offset operational amplifier, the auxiliary operational amplifier is added, so that the problem of direct-current offset caused by the operational amplifier under the condition of output voltage clamping is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of operational amplifiers, and more particularly to a low-offset operational amplifier based on a cyclic folded cascode structure and its applications. Background Art

[0002] With the rapid development of microelectronics technology, electronic devices are increasingly trending towards miniaturization and high-integration design. Operational amplifiers are widely used in signal processing, filtering, and data acquisition systems, and their performance directly affects the accuracy and stability of the entire electronic device. Traditional operational amplifiers are often limited by input offset voltage in high-precision applications, which can cause the output signal to shift, thereby affecting the overall performance of the system.

[0003] For example, in a sensor readout circuit, the input offset of the operational amplifier can cause system detection errors, thereby reducing the accuracy of the measured signal. Therefore, the demand for reducing the offset of operational amplifiers in design is increasing.

[0004] In traditional differential input-single-ended output operational amplifiers (such as folded cascode operational amplifiers), the output stage usually converts the differential signal into a single-ended signal through a self-biased point generated by a current mirror structure. When the output signal needs to perform a voltage clamping operation (a typical application is the reset stage of a current integrator), since the mirror flip point voltage of the cascode current mirror is determined by the DC bias point of the operational amplifier itself, while the output clamping voltage is determined by the requirements of the external circuit, the existing architecture is prone to mismatch between the mirror flip point voltage and the output clamping voltage, resulting in imbalance of the left and right currents, and further causing system offset at the output end of the differential input-single-ended operational amplifier. Due to the inability of traditional static bias compensation techniques to track voltage changes in real time, the above system offset problem is particularly prominent in dynamic operating scenarios (such as periodic reset or fast transient response). In addition, in low supply voltage and high gain application scenarios, conventional offset calibration techniques (such as chopper modulation or auto-zeroing) are often difficult to apply due to the additional introduction of noise or dynamic errors, and complex compensation circuits will significantly increase power consumption and area, not meeting the design requirements of miniaturization and low power consumption.

[0005] Therefore, how to provide an innovative solution to achieve offset suppression without significantly increasing circuit complexity is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention provides a low-offset operational amplifier based on a cyclic folded cascode structure and its applications, which are used to solve at least some of the technical problems in the background art.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] The present invention first discloses a low-offset operational amplifier based on a cyclic folded cascode structure, which includes a cyclic folded cascode structure operational amplifier and an auxiliary operational amplifier connected to each other. Among them, the voltage value of the negative input terminal of the auxiliary operational amplifier is set to the clamping value of the output voltage V out of the cyclic folded cascode structure operational amplifier.

[0009] Preferably, it further includes a differential-mode loop stability compensation unit composed of a compensation resistor and a compensation capacitor connected in series; one end of the differential-mode loop stability compensation unit is connected to the output terminal of the auxiliary operational amplifier; the other end of the differential-mode loop stability compensation unit is connected to the positive input terminal of the auxiliary operational amplifier.

[0010] Preferably, in the cyclic folded cascode structure operational amplifier and the auxiliary operational amplifier connected to each other,

[0011] the cyclic folded cascode structure operational amplifier includes PMOS transistors MP5, MP6, MP7, MP8, and NMOS transistors MN7, MN8. The MP5 and MP6 are connected to each other through their respective bases; the MP7 and MP8 are connected to each other through their respective bases; the MN7 and MN8 are connected to each other through their respective bases; the sources of the MP5 and MP6 are both connected to one end of the power supply. The drain of the MP5 is connected to the source of the MP7, the drain of the MP7 is connected to the drain of the MN7, the drain of the MP6 is connected to the source of the MP8, and the drain of the MP8 is connected to the drain of the MN8;

[0012] The output terminal of the auxiliary operational amplifier is connected to the base connection line of the MP5 and MP6. The positive input terminal of the auxiliary operational amplifier is connected to the drain connection line of the MP7 and MN7. The negative input terminal of the auxiliary operational amplifier is set to the clamping value of the output voltage V out of the cyclic folded cascode structure operational amplifier.

[0013] Preferably, the cyclic folded cascode structure operational amplifier further includes PMOS transistors MP0, MP1, MP2, MP3, MP4, and NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6;

[0014] Among them, the source of the MP0 is connected to one end of the power supply, and the base of the MP0 is set to the bias voltage V bias of the cyclic folded cascode structure operational amplifier;

[0015] MP1, MP2, MP3, and MP4 form the input PMOS transistors of the cyclic folded cascode structure operational amplifier, which are used to provide input transconductance for the cyclic folded cascode structure operational amplifier. The base of the MP1 is set to the differential-mode voltage Vip , the base of MP4 is set to the differential-mode voltage V in ;

[0016] MN1 and MN2, MN3 and MN4, MN5 and MN6 form three groups of current mirrors for boosting the input transconductance through circulating current; the drain of MN3 is connected to the drain of MP1 and also to the source of MN7; the drain of MN6 is connected to the drain of MP4 and also to the source of MN8.

[0017] Preferably, the auxiliary operational amplifier includes auxiliary PMOS transistors MAP1, MAP2, MAP3, MAP4 and auxiliary NMOS transistor MAN1;

[0018] Among them, MAP1 and MAP2 are connected to each other through their respective bases; the sources of MAP1 and MAP2 are both connected to one end of the power supply; MAP3 and MAP4 are connected to each other through their respective drains: the drain of MAP1 is connected to the source of MAP3; the drain of MAP2 is connected to the source of MAP4; the base of MAP3 serves as the positive input terminal of the auxiliary operational amplifier, and the base of MAP4 serves as the negative input terminal of the auxiliary operational amplifier; the connection line between the drain of MAP2 and the source of MAP4 leads out the output terminal of the auxiliary operational amplifier;

[0019] The drain of MAN1 is connected to the connection line of the drains of MAP3 and MAP4; the source of MAN1 is connected to the other end of the power supply.

[0020] The present invention also discloses a current integrator applying a low-offset operational amplifier based on a cyclic folded cascode structure, including any low-offset operational amplifier based on a cyclic folded cascode structure disclosed in the present invention, a switching device, an integrating capacitor, a current source and a parasitic capacitor;

[0021] Among them, the switching device and the integrating capacitor are connected in parallel, one end of the parallel component formed by the switching device and the integrating capacitor is connected to the output terminal of the low-offset operational amplifier based on a cyclic folded cascode structure, and the other end of the parallel component formed by the switching device and the integrating capacitor is connected to the positive input terminal of the low-offset operational amplifier based on a cyclic folded cascode structure; the positive input terminal of the low-offset operational amplifier based on a cyclic folded cascode structure is simultaneously connected to the current source; one end of the parasitic capacitor is connected to the current source, and the other end of the parasitic capacitor is grounded.

[0022] It can be seen from the above technical solutions that, compared with the prior art, the present invention discloses a low-offset operational amplifier based on a cyclic folded cascode structure and its application, having the following beneficial effects:

[0023] In the output signal path of the operational amplifier with a cyclic folded cascode structure, the present invention performs voltage clamping on the output symmetry point, thereby greatly reducing the offset of the operational amplifier. Since the power consumption required by the added auxiliary operational amplifier is very low, and at the same time, the differential-mode loop stability compensation unit can ensure the loop stability of the system; therefore, the low-offset operational amplifier disclosed by the present invention has obvious advantages in the application scenario of high-precision and low-power analog-to-digital conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0025] Figure 1 It is a schematic diagram of the overall structure of the low-offset operational amplifier provided by the embodiment of the present invention.

[0026] Figure 2 It is a schematic diagram of the internal structure of the auxiliary operational amplifier in the low-offset operational amplifier provided by the embodiment of the present invention.

[0027] Figure 3 It is a schematic diagram of the current integrator structure applying the low-offset operational amplifier provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0029] The embodiment of the present invention first discloses a low-offset operational amplifier based on a cyclic folded cascode structure. By introducing an auxiliary operational amplifier to match the bias voltage of the current mirror flip point and the output clamping voltage, the offset of the operational amplifier is eliminated in this case, and the system performance is improved.

[0030] An embodiment of the present invention discloses a low-offset operational amplifier based on a loop-folded cascode structure, which includes a loop-folded cascode operational amplifier, an auxiliary operational amplifier, and a differential-mode loop stability compensation unit. In the embodiment, the loop-folded cascode operational amplifier can be regarded as composed of an input-stage operational amplifier and an output-stage operational amplifier, and the auxiliary operational amplifier is connected to the output-stage operational amplifier.

[0031] As Figure 1 shown, in the overall low-offset operational amplifier proposed in the embodiment, PMOS transistors MP0-MP8 and NMOS transistors MN1-MN8 jointly form a loop-folded cascode operational amplifier (main operational amplifier) OP1. Among them, as Figure 1 shown in the left half, PMOS transistors MP0-MP4 and NMOS transistors MN1-MN6 form an input-stage operational amplifier. In the input-stage operational amplifier, MP0 is used to implement the current bias of the input stage; MP1-MP4 are input PMOS transistors, providing transconductance; MN1-MN6 are current mirrors, realizing the utilization of loop current to improve the transconductance of the input stage.

[0032] As Figure 1 shown by the circuit described by the black lines in the right part, PMOS transistors MP5, MP6, MP7, MP8, and NMOS transistors MN7, MN8 constitute an output-stage operational amplifier. In the output-stage operational amplifier, MP5 and MP6 are also current mirror structures, providing current bias for the folded cascode stage; MP7, MP8, MN7, and MN8 are folded cascode transistors, used to improve the DC gain of the operational amplifier.

[0033] The first resistor R1 and the first capacitor C1 form a stability compensation circuit for the differential-mode loop.

[0034] As Figure 1 shown by the blue lines in the right part, the output terminal of the auxiliary operational amplifier OP2 is connected to the base connection line of MP5 and MP6, the positive input terminal of the auxiliary operational amplifier OP2 is connected to the drain connection line of MP7 and MN7, and the negative input terminal of the auxiliary operational amplifier OP2 is set to the clamping value of the output voltage V out of the two-stage folded cascode operational amplifier.

[0035] In this embodiment, when the operational amplifier is used as a current integrator, the output voltage Vout is fixed. Without adding an auxiliary operational amplifier, point A and point B are short - circuited. Since the voltage at point B is determined by the current in this branch, VA is not equal to Vout. This causes the VDS voltages of MP7 and MP8 to be unequal, and due to the second - order effects of MOS transistors, the two - path currents are mismatched, thus causing system offset. The key point of this design is to add an auxiliary operational amplifier to make VA = VAid, where VAid is the clamped value of the output voltage Vout. At this time, the VDS voltages of MP7 and MP8 are equal, so the offset caused by current mismatch can be eliminated. In the proposed structure, since the introduction of the auxiliary operational amplifier changes the zero - poles of the main operational amplifier, C1 and R1 are added for zero - pole compensation to ensure the loop stability of the system.

[0036] As Figure 2 shown, in a specific embodiment, the internal structure of the auxiliary operational amplifier OP2 consists of PMOS transistors MAP1 - MAP4 and NMOS transistor MAN1. Among them, MAP3 and MAP4 are the input stage, and MAP1 and MAP2 are the current - mirror loads; MAN1 provides the current bias for the auxiliary operational amplifier. After adding this auxiliary operational amplifier, the voltages at point A and Vout can be matched through VAid, thus eliminating the DC offset of the operational amplifier. Zero - pole compensation is carried out through R1 and C1 to ensure the stability of the loop.

[0037] Figure 3 is a schematic diagram of the possible application - scenario connection of the low - offset operational amplifier proposed by the present invention. In this application, the low - offset operational amplifier serves as a continuous - time current - type integrator. Where C para is the parasitic capacitance at the input end, C int is the integration capacitance, then the output voltage V out is determined by the following formula: V out = V REF + I in ·ΔT / C int . After adding the auxiliary operational amplifier, in order to match the voltage at point A with the voltage of V out , the input voltage V id of the auxiliary operational amplifier is set to . At this time, the VDS voltages of MP7 and MP8 are approximately equal, and the DC offset caused by current mismatch can be eliminated to the greatest extent.

[0038] The present invention is mainly used in scenarios where the output voltage of the operational amplifier is clamped, such as current integrators, single - ended output Sigma - Delta ADCs, etc.

[0039] The present invention solves the problem of DC offset caused by the operational amplifier under the condition of output voltage clamping by adding an auxiliary operational amplifier, and ensures the stability of the system through zero-pole compensation with R and C. Compared with the main operational amplifier, the auxiliary operational amplifier consumes very low power. Therefore, this operational amplifier can achieve a good trade-off between power consumption and offset in the application scenario of output voltage clamping.

[0040] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section.

[0041] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A low-offset operational amplifier based on a loop-folded cascode structure, characterized in that, It includes a mutually connected loop-folded cascode operational amplifier and an auxiliary operational amplifier, wherein the voltage value of the negative input terminal of the auxiliary operational amplifier is set to the clamping value of the output voltage V out of the loop-folded cascode operational amplifier.

2. The low-offset operational amplifier based on a cyclic folded cascode structure according to claim 1, wherein It also includes a differential-mode loop stability compensation unit composed of a compensating resistor and a compensating capacitor connected in series; one end of the differential-mode loop stability compensation unit is connected to the output end of the auxiliary operational amplifier; the other end of the differential-mode loop stability compensation unit is connected to the positive input end of the auxiliary operational amplifier.

3. A low-offset operational amplifier based on a cyclic folded cascode structure according to claim 1, characterized in that In the interconnected cyclic folded cascode operational amplifier and auxiliary operational amplifier, the cyclic folded cascode operational amplifier includes PMOS transistors MP5, MP6, MP7, MP8, and NMOS transistors MN7, MN8. MP5 and MP6 are connected to each other through their respective bases; MP7 and MP8 are connected to each other through their respective bases; MN7 and MN8 are connected to each other through their respective bases; the sources of MP5 and MP6 are both connected to one end of the power supply. The drain of MP5 is connected to the source of MP7, the drain of MP7 is connected to the drain of MN7, the drain of MP6 is connected to the source of MP8, and the drain of MP8 is connected to the drain of MN8. The output terminal of the auxiliary operational amplifier is connected to the base connection lines of MP5 and MP6. The positive input terminal of the auxiliary operational amplifier is connected to the drain connection lines of MP7 and MN7. The negative input terminal of the auxiliary operational amplifier is set to the clamped value of the output voltage V of the folded cascode operational amplifier out of 4. A low-offset operational amplifier based on a cyclic folded cascode structure according to claim 3, characterized in that The cyclic folded cascode operational amplifier further includes PMOS transistors MP0, MP1, MP2, MP3, MP4, and NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6. Among them, the source of MP0 is connected to one end of the power supply, and the base of MP0 is set to the bias voltage V of the folded cascode operational amplifier bias ; MP1, MP2, MP3, and MP4 form the input PMOS transistors of the folded cascode operational amplifier in a loop, which are used to provide the input transconductance for the folded cascode operational amplifier in a loop; the base of the MP1 is set to the differential mode voltage V ip , and the base of the MP4 is set to the differential mode voltage V in ; MN1 and MN2, MN3 and MN4, MN5 and MN6 form three groups of current mirrors for enhancing the input transconductance through cyclic current. The drain of MN3 is connected to the drain of MP1 and is also connected to the source of MN7. The drain of MN6 is connected to the drain of MP4 and is also connected to the source of MN8.

5. A low-offset operational amplifier based on a cyclic folded cascode structure according to claim 1, characterized in that, The auxiliary operational amplifier includes auxiliary PMOS transistors MAP1, MAP2, MAP3, MAP4 and auxiliary NMOS transistor MAN1. Among them, MAP1 and MAP2 are connected to each other through their respective bases; the sources of MAP1 and MAP2 are both connected to one end of the power supply; MAP3 and MAP4 are connected to each other through their respective drains; the drain of MAP1 is connected to the source of MAP3; the drain of MAP2 is connected to the source of MAP4; the base of MAP3 serves as the positive input end of the auxiliary operational amplifier, and the base of MAP4 serves as the negative input end of the auxiliary operational amplifier; the connection line between the drain of MAP2 and the source of MAP4 leads out the output end of the auxiliary operational amplifier. The drain of MAN1 is connected to the connection line between the drains of MAP3 and MAP4; the source of MAN1 is connected to the other end of the power supply.

6. A current integrator using the low-offset operational amplifier based on the loop-folded cascode structure according to any one of claims 1-5, characterized in that It includes a low-offset operational amplifier based on a cyclic folded cascode structure, a switching device, an integrating capacitor, a current source, and parasitic capacitances. Among them, the switching device and the integrating capacitor are connected in parallel with each other. One end of the parallel component formed by the switching device and the integrating capacitor is connected to the output end of the low-offset operational amplifier based on the cyclic folded cascode structure, and the other end of the parallel component formed by the switching device and the integrating capacitor is connected to the positive input end of the low-offset operational amplifier based on the cyclic folded cascode structure; the positive input end of the low-offset operational amplifier based on the cyclic folded cascode structure is simultaneously connected to the current source; one end of the parasitic capacitor is connected to the current source, and the other end of the parasitic capacitor is grounded.

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