Ultra-wideband power amplification circuit and control method thereof

Abstract

The invention discloses an ultra-wideband power amplification circuit and a control method thereof, and the circuit comprises an input transmission line transformer circuit, an input LC passive matching circuit, a GaN power amplification transistor, an output LC passive matching circuit, an output transmission line transformer circuit, an L-R-C negative feedback stabilization circuit, a gate bias circuit and a drain bias circuit. The input transmission line transformer circuit is connected with the input LC passive matching circuit, the input LC passive matching circuit is connected with a grid electrode of the GaN power amplifier transistor, the L-R-C negative feedback stabilizing circuit is connected with the grid electrode and a drain electrode of the GaN power amplifier transistor, the grid electrode biasing circuit is connected with the grid electrode of the GaN power amplifier transistor, and the L-R-C negative feedback stabilizing circuit is connected with the grid electrode of the GaN power amplifier transistor. And the drain electrode biasing circuit is connected with the drain electrode of the GaN power amplifier transistor. According to the ultra-wide-band power amplification circuit and the control method thereof, power amplification in an ultra-wide frequency band range is realized by adopting a single-stage amplification circuit, the ultra-wide-band power amplification circuit has excellent frequency power characteristics, and the circuit complexity of communication equipment is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of electrical digital data processing, and particularly relates to an ultra-wideband power amplifier circuit and a control method thereof. Background Art

[0002] With the development of wireless technology, the communication mode has gradually transitioned from narrowband communication to ultra-wideband communication. To meet the requirements of miniaturization and lightweight of communication devices, the ultra-wideband circuit design technology has gradually become a research hotspot in the industry. As a key circuit in the radio frequency transmission link, the power amplifier circuit realizes the amplification of the transmitted signal power by converting the power supply power into the transmitted signal power, and further realizes the goal of long-distance wireless transmission communication. Traditional power amplifier circuits are mostly narrowband circuits. To meet the requirements of ultra-wideband communication, a multi-stage power amplifier circuit splicing method is usually adopted to achieve ultra-wideband coverage. However, this method has problems such as a relatively large device volume, a complex circuit structure, a relatively high cost, and a relatively low circuit reliability index due to the use of many devices. Summary of the Invention

[0003] The present invention proposes an ultra-wideband power amplifier circuit and a control method thereof to solve the problems of the existing ultra-wideband power amplifier circuit, such as a relatively large device volume, a complex circuit structure, a relatively high cost, and a relatively low circuit reliability index.

[0004] The present invention provides the following technical solutions:

[0005] In a first aspect, this specification provides an ultra-wideband power amplifier circuit, including an input transmission line transformer circuit 1, an input LC passive matching circuit 2, a GaN power amplifier transistor 3, an output LC passive matching circuit 4, an output transmission line transformer circuit 5, an L-R-C negative feedback stabilization circuit 6, a gate bias circuit 7, and a drain bias circuit 8. The input transmission line transformer circuit 1 is connected to the input LC passive matching circuit 2. The input LC passive matching circuit 2 is connected to the gate of the GaN power amplifier transistor 3. The L-R-C negative feedback stabilization circuit 6 is respectively connected to the gate and the drain of the GaN power amplifier transistor 3. The gate bias circuit 7 is connected to the gate of the GaN power amplifier transistor 3. The drain bias circuit 8 is connected to the drain of the GaN power amplifier transistor 3. The output LC passive matching circuit 4 is connected to the drain of the GaN power amplifier transistor 3. The output transmission line transformer circuit 5 is connected to the output LC passive matching circuit 4, wherein:

[0006] The input transmission line transformer circuit 1 is configured to receive a radio frequency input signal 9, perform impedance matching on the radio frequency input signal 9 to obtain a primary impedance matching signal 10, and send the primary impedance matching signal 10 to the input LC passive matching circuit 2;

[0007] The input LC passive matching circuit 2 is configured to receive the primary impedance matching signal 10, perform impedance matching on the primary impedance matching signal 10 to obtain a secondary impedance matching signal 11, and send the secondary impedance matching signal 11 to the gate of the GaN power amplifier transistor 3;

[0008] The gate bias circuit 7 is configured to filter the first power supply signal to obtain a filtered first power supply signal 18, and send the filtered first power supply signal 18 to the gate of the GaN power amplifier transistor 3;

[0009] The GaN power amplifier transistor 3 is configured to receive the secondary impedance matching signal 11, the filtered first power supply signal 18, and the feedback signal 16, process the secondary impedance matching signal 11 to obtain a first output signal 12 and a second output signal 15, send the first output signal 12 to the output LC passive matching circuit 4, and send the second output signal 15 to the L-R-C negative feedback stabilization circuit 6;

[0010] The L-R-C negative feedback stabilization circuit 6 is configured to receive the second output signal 15, process the second output signal 15 according to the preset circuit stability requirements for the ultra-wideband full-frequency range, obtain the feedback signal 16, and send the feedback signal 16 to the gate of the GaN power amplifier transistor 3;

[0011] The output LC passive matching circuit 4 is configured to receive the first output signal 12, perform impedance matching on the first output signal 12 to obtain a third output signal 13, and send the third output signal 13 to the output transmission line transformer circuit 5;

[0012] The output transmission line transformer circuit 5 is configured to receive the third output signal 13, perform impedance matching on the third output signal 13 to obtain a power amplifier circuit output signal 14;

[0013] The drain bias circuit 8 is configured to filter the second power supply signal to obtain a filtered second power supply signal 20, and send the filtered second power supply signal 20 to the drain of the GaN power amplifier transistor 3.

[0014] Optionally, the L-R-C negative feedback stabilization circuit 6 is composed of a low-loss RF capacitor, an AlN resistor, and a low-ESR RF inductor connected in series in sequence. The low-loss RF capacitor is respectively connected to the drain of the GaN power amplifier transistor 3 and the AlN resistor. The AlN resistor is connected to the low-ESR RF inductor, and the low-ESR RF inductor is connected to the gate of the GaN power amplifier transistor 3.

[0015] Optionally, the loss tangent value of the low-loss RF capacitor is not greater than 10×10 -4 , the rated power consumption of the AlN resistor is 100 W, and the equivalent series resistance of the low-ESR RF inductor is less than 1 Ω.

[0016] Optionally, the ratio of the input impedance value to the output impedance value of the input transmission line transformer circuit 1 is 4:1, and the ratio of the input impedance value to the output impedance value of the output transmission line transformer circuit 5 is 4:1.

[0017] Optionally, a ferrite core is provided in the input transmission line transformer circuit 1 and the output transmission line transformer circuit 5, and the ferrite core is an MnZn ferrite core with a magnetic permeability of 4000.

[0018] Optionally, the gate bias circuit 7 and the drain bias circuit 8 are LC power filter circuits, the inductor in the gate bias circuit 7 is an RF inductor, and the inductor in the drain bias circuit 8 is a magnetic winding inductor.

[0019] Optionally, the distance between the inductor in the gate bias circuit 7 and the gate of the GaN power amplifier transistor 3 does not exceed 1 mm.

[0020] Optionally, the gate bias circuit 7 includes a first capacitor group. The capacitor with the smallest capacitance value in the first capacitor group is an RF capacitor. The distance between the capacitor with the smallest capacitance value in the first capacitor group and the inductor in the gate bias circuit 7 does not exceed 1 mm, and the capacitor with the largest capacitance value in the first capacitor group is an electrolytic capacitor.

[0021] Optionally, the drain bias circuit 8 includes a second capacitor group. The capacitor with the smallest capacitance value in the second capacitor group is an RF capacitor. The distance between the capacitor with the smallest capacitance value in the second capacitor group and the inductor in the drain bias circuit 8 does not exceed 1 mm, and the capacitor with the largest capacitance value in the second capacitor group is an electrolytic capacitor.

[0022] In a second aspect, the present invention provides a method for controlling an ultra-wideband power amplifier circuit, including:

[0023] The input transmission line transformer circuit 1 receives the RF input signal 9, performs impedance matching on the RF input signal 9 to obtain a primary impedance matching signal 10, and sends the primary impedance matching signal 10 to the input LC passive matching circuit 2;

[0024] The input LC passive matching circuit 2 receives the primary impedance matching signal 10, performs impedance matching on the primary impedance matching signal 10 to obtain a secondary impedance matching signal 11, and sends the secondary impedance matching signal 11 to the gate of the GaN power amplifier transistor 3;

[0025] The gate bias circuit 7 filters the first power supply signal to obtain the filtered first power supply signal 18, and sends the filtered first power supply signal 18 to the gate of the GaN power amplifier transistor 3;

[0026] The GaN power amplifier transistor 3 receives the secondary impedance matching signal 11, the filtered first power supply signal 18, and the feedback signal 16, processes the secondary impedance matching signal 11 to obtain a first output signal 12 and a second output signal 15, and sends the first output signal 12 to the output LC passive matching circuit 4 and the second output signal 15 to the L-R-C negative feedback stabilization circuit 6;

[0027] The L-R-C negative feedback stabilization circuit 6 receives the second output signal 15, processes the second output signal 15 according to the preset circuit stability requirements for the ultra-wideband full frequency band range, obtains the feedback signal 16, and sends the feedback signal 16 to the gate of the GaN power amplifier transistor 3;

[0028] The output LC passive matching circuit 4 receives the first output signal 12, performs impedance matching on the first output signal 12 to obtain a third output signal 13, and sends the third output signal 13 to the output transmission line transformer circuit 5;

[0029] The output transmission line transformer circuit 5 receives the third output signal 13, performs impedance matching on the third output signal 13 to obtain the power amplifier circuit output signal 14;

[0030] The drain bias circuit 8 filters the second power supply signal to obtain the filtered second power supply signal 20, and sends the filtered second power supply signal 20 to the drain of the GaN power amplifier transistor 3.

[0031] The ultra-wideband power amplifier circuit and its control method provided by the embodiments of the present invention use a single-stage amplifier circuit to achieve power amplification in an ultra-wide frequency band range, thereby effectively reducing the circuit complexity of communication equipment, and solving the problems of the existing ultra-wideband power amplifier circuit having a relatively large device volume, a complex circuit structure, a relatively high cost, and a relatively low circuit reliability index. Description of the Drawings

[0032] Figure 1 is a schematic block diagram of the ultra-wideband power amplifier circuit in the embodiments of the present invention;

[0033] Figure 2 is a schematic diagram of the ultra-wideband power amplifier circuit in the embodiments of the present invention;

[0034] Figure 3 is a schematic diagram of the ultra-wideband matching circuit in the embodiments of the present invention;

[0035] Figure 4 This is a schematic diagram of the series negative feedback broadband stable circuit in the embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of the broadband stability improvement effect in the embodiment of the present invention.

[0037] Other features and advantages of the present invention will be described in the following specification, and in part will be obvious from the specification, or will be understood by implementing the present invention. The objectives and other advantages of the present invention can be realized and obtained by the structures specifically pointed out in the written specification, claims, and drawings. Detailed Embodiments

[0038] To make the objectives, technical solutions, and advantages of this specification clearer, the technical solutions of this specification will be clearly and completely described below in conjunction with the specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all of them. Based on the embodiments in this specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this specification.

[0039] As described herein, the term "including" and its various variants can be understood as open-ended terms, meaning "including but not limited to", and the term "one embodiment" can be understood as "at least one embodiment".

[0040] The inventors found that existing ultra-wideband power amplifier circuits have problems such as a relatively large device volume, a complex circuit structure, a relatively high cost, and a relatively low circuit reliability index. In view of this, in the embodiments of the present invention, a single-stage amplifier circuit is used to achieve the power amplification target within an ultra-wide frequency band range and has excellent frequency-power characteristics, thereby effectively reducing the circuit complexity of communication devices, reducing the device volume, and improving the device reliability index.

[0041] Figure 1 and Figure 2 Schematically shows an ultra-wideband power amplifier circuit according to an embodiment of the present application, including an input transmission line transformer circuit 1, an input LC passive matching circuit 2, a GaN power amplifier transistor 3, an output LC passive matching circuit 4, an output transmission line transformer circuit 5, an L-R-C negative feedback stable circuit 6, a gate bias circuit 7, and a drain bias circuit 8.

[0042] Specifically, for the input transmission line transformer circuit, its input terminal is connected to the RF input signal, and the output terminal is connected to the input LC passive matching circuit. It uses the low-Q value characteristic of the transmission line transformer to achieve ultra-wideband impedance matching between the standard RF impedance value (e.g., 50 Ω) and the input intermediate impedance value within a frequency range of more than 10 octaves.

[0043] Specifically, for the input LC passive matching circuit, its input terminal is connected to the output of the input transmission line transformer circuit, and the output terminal is connected to the input gate terminal of the GaN power amplifier transistor. It uses the low-loss (insertion loss better than 1 dB) characteristic of the LC passive matching network to achieve impedance matching between the input intermediate impedance value and the low input impedance value of the GaN power amplifier transistor, and at the same time improves the output power flatness index of the entire power amplifier circuit.

[0044] Specifically, for the GaN power amplifier transistor, its input terminal is connected to the output of the input LC passive matching circuit, and the output terminal is connected to the output LC passive matching circuit. It uses the excellent broadband power amplification ability of the GaN power transistor to convert the power supply power into RF signal power, thereby achieving the goal of high output power.

[0045] Specifically, for the output LC passive matching circuit, its input terminal is connected to the drain output of the GaN power amplifier transistor, and the output terminal is connected to the input of the output transmission line transformer circuit. It uses the low-loss (insertion loss better than 1 dB) characteristic of the LC passive matching network to achieve impedance matching between the low output impedance value of the GaN power amplifier transistor and the output intermediate impedance value, and at the same time reduces the loss of the matching network to the output power.

[0046] Specifically, for the output transmission line transformer circuit, its input terminal is connected to the output of the output LC passive matching circuit, and the output terminal is the output of the entire power amplifier circuit. It uses the low-Q value characteristic of the transmission line transformer to achieve ultra-wideband impedance matching between the output intermediate impedance value and the standard RF impedance value (e.g., 50 Ω) within a frequency range of more than 10 octaves, thereby achieving maximum transmission of the output power.

[0047] Specifically, the L-R-C negative feedback stabilization circuit is composed of a low-loss (loss tangent value tanδ ≤ 10×10-4) RF capacitor, a high-power-resistant (rated power consumption of 100 W) AlN resistor, and an RF inductor (ESR < 1 Ω) connected in series in sequence. One end of the low-loss (loss tangent value tanδ ≤ 10×10-4) RF capacitor is connected to the output drain terminal of the GaN power amplifier transistor, and the other end is connected to the high-power-resistant (rated power consumption of 100 W) AlN resistor. The other end of the high-power-resistant (rated power consumption of 100 W) AlN resistor is connected to the RF inductor, and the other end of the RF inductor is connected to the input gate terminal of the GaN power amplifier transistor. It uses the negative feedback characteristic to achieve absolute stability of the power amplifier circuit within an ultra-wide frequency range.

[0048] Specifically, the input terminal of the gate bias circuit is connected to the power supply, and the output terminal is connected to the input gate terminal of the GaN power amplifier transistor. The low-pass characteristic of the LC network is utilized to complete the filtering of the gate power supply of the GaN power amplifier transistor, and at the same time, the radio frequency isolation function of the power supply branch is realized.

[0049] Specifically, the input terminal of the drain bias circuit is connected to the power supply, and the output terminal is connected to the output drain terminal of the GaN power amplifier transistor. It is used for filtering the drain power supply of the GaN power amplifier transistor, and realizes the radio frequency isolation function of the power supply branch while providing the overcurrent capacity of large current.

[0050] Specifically, both the gate bias circuit and the drain bias circuit adopt LC power supply filter circuits. For the choke inductance L of the gate bias circuit, an inductor with low ESR (ESR < 5Ω) is used, and for the drain bias circuit, a large current magnetic winding inductor is used to provide large overcurrent capacity.

[0051] In specific implementation, the radio frequency input signal RFIN9 is connected to the input terminal of the input transmission line transformer circuit 1. After impedance matching, the output signal 10 is used as the input of the input LC passive matching circuit 2. After secondary impedance matching, the output signal 11 is used as the input of the GaN power amplifier transistor 3. After the GaN power amplifier transistor 3 completes the conversion of the power supply power to the radio frequency output signal power, it is output in two paths, namely the output signal 12 and the output signal 15. Among them, the output signal 12 is used as the input of the output LC passive matching circuit 4. After impedance matching, the output signal 13 is obtained. The output signal 13 is impedance-matched by the output transmission line transformer circuit 5 to obtain the output signal RFOUT14 of the entire power amplifier circuit; the output signal 15 is used as a feedback signal to enter the L-R-C negative feedback stabilization circuit 6 to realize the circuit stability in the ultra-wideband full frequency band range and output the feedback signal 16 to the gate input of the GaN power amplifier transistor 3, thereby forming a negative feedback loop; the power supply 117 is connected to the gate bias circuit 7. After power supply filtering, the power supply signal 18 is output and connected to the gate of the GaN power amplifier transistor 3 to realize the gate power supply of the GaN power amplifier transistor 3; the power supply 219 is connected to the drain bias circuit 8. After power supply filtering, the power supply signal 20 is output and connected to the drain of the GaN power amplifier transistor 3 to realize the drain power supply of the GaN power amplifier transistor 3.

[0052] In one implementation manner, both the input transmission line transformer circuit 1 and the output transmission line transformer circuit 5 adopt an ultra-wideband 4:1, that is, the ratio of the input impedance value to the output impedance value is 4:1 (the same below) transmission line transformer structure. The length of the transmission line used in this structure is taken as λ / 8 corresponding to the highest frequency point in the working frequency band. Its function is to realize the impedance transformation from the standard impedance 50Ω to the intermediate real impedance 12.5Ω. At the same time, a high-permeability ferrite core such as an MnZn ferrite core with a permeability of 4000 is added to the 4:1 transmission line transformer to realize the low-frequency band expansion. For specific examples, see Figure 3 as shown.

[0053] In one embodiment, both the input LC passive matching circuit 2 and the output LC passive matching circuit 4 adopt the form of an "L-type" matching network. "L-type": When inductors and capacitors are connected in series from the input to the output first, and then capacitors and inductors are connected in parallel to ground afterwards, its shape looks like the letter "L" in the English alphabet from the perspective of the circuit structure, so it gets this name. The inductor L is a radio frequency inductor with low ESR (ESR < 1Ω) and high precision, and the inductance value accuracy is 5%. The capacitor C is a radio frequency capacitor with low insertion loss and high precision, and the capacitance value accuracy is ±0.1pF. Combining with the actual matching and debugging requirements, the 0Ω resistor is sometimes used to replace the inductor L.

[0054] In one embodiment, the L-R-C negative feedback stabilization circuit 6 is composed of a radio frequency wound inductor L (ESR < 1Ω), a high-precision resistor R with a resistance value accuracy of 1% and a high-power withstand rating power consumption of 100W AlN resistor, and a low insertion loss capacitor C connected in series. The main function of the capacitor C is to block direct current in the feedback loop and ensure that the static operating point of the entire circuit is not affected by the feedback branch. The resistor R is the main device to improve the working stability of the entire circuit. Its function is to offset the positive transmission negative resistance of the power amplifier circuit. Its value is usually in the range of 100Ω to 300Ω. Considering its application under high-power conditions, its power dissipation is usually large, and ordinary surface mount resistors cannot meet the requirements, so an AlN resistor with a high-power withstand rating power consumption of 100W is selected. The main function of the inductor L is to compensate the available gain of the circuit on the premise of improving stability. See the specific example in Figure 4 as shown, and the corresponding broadband stability improvement effect is shown in Figure 5 .

[0055] In one embodiment, both the gate bias circuit 7 and the drain bias circuit 8 adopt LC power supply filter circuits. The LC power supply filter circuit is a low-pass filter circuit, which realizes the functions of filtering the power supply and isolating radio frequency signals. The inductor L in the gate bias circuit 7 is a radio frequency inductor (ESR < 5Ω) and is placed as close as possible (the spacing does not exceed 1mm) to the gate input of the GaN power amplifier transistor 3. The inductor L in the drain bias circuit 8 is a large-current magnetic winding inductor to provide a large over-current capacity. For the capacitors on the filter circuit, they are combined according to the rule of increasing by an order of magnitude from low capacitance value to high capacitance value, such as a combined capacitor group of 10pF - 100pF - 10nF - 100nF - 10uF - 47uF. Among them, the small capacitance value capacitors are radio frequency capacitors with low RSR and are placed as close as possible (the spacing does not exceed 1mm) to the inductor L, and the large capacitance value capacitors are electrolytic capacitors and are placed as close as possible (the spacing does not exceed 2mm) to the input power supply.

[0056] In one embodiment, the input transmission line transformer circuit, the output transmission line transformer circuit, the input LC passive matching circuit, and the output LC passive matching circuit all adopt a "composite structure matching circuit" composed of a transmission line transformer and an LC impedance matching network to achieve the impedance matching goal within a frequency range of more than 10 octaves. Among them, the transmission line transformer is used to achieve impedance matching from a standard RF impedance (such as 50Ω) to a certain real impedance value close to the input / output impedance of the GaN power amplifier transistor (such as 12.5Ω or 5.56Ω), and the LC impedance matching network then completes the impedance matching goal within an ultra-wide frequency band from this real impedance value to the input / output complex impedance of the GaN power amplifier transistor.

[0057] The above embodiment constructs an ultra-wideband power amplifier circuit, which adopts a series negative feedback method of RF wound inductors, high-precision and high-power-resistant AlN resistors, and low insertion-loss capacitors, as well as a "composite structure matching circuit" composed of a transmission line transformer and an LC impedance matching network, so as to achieve the impedance matching goal within an ultra-wide frequency band, ensure that the entire power amplifier circuit has excellent frequency-power characteristics within an ultra-wide frequency band, further improve the stability of the ultra-wideband power amplifier circuit, enable it to meet the requirements of ultra-wideband communication systems, and solve the problems of the existing ultra-wideband power amplifier circuit, such as large equipment volume, complex circuit structure, high cost, and low circuit reliability index.

[0058] Embodiment 2

[0059] The embodiment of the present invention provides a method for controlling an ultra-wideband power amplifier circuit. This method is executed by a processor and includes the following steps:

[0060] Step 1: The input transmission line transformer circuit 1 receives the RF input signal 9, performs impedance matching on the RF input signal 9 to obtain a primary impedance-matched signal 10, and sends the primary impedance-matched signal 10 to the input LC passive matching circuit 2.

[0061] Step 2: The input LC passive matching circuit 2 receives the primary impedance-matched signal 10, performs impedance matching on the primary impedance-matched signal 10 to obtain a secondary impedance-matched signal 11, and sends the secondary impedance-matched signal 11 to the gate of the GaN power amplifier transistor 3.

[0062] Step 3: The gate bias circuit 7 filters the first power supply signal to obtain a filtered first power supply signal 18, and sends the filtered first power supply signal 18 to the gate of the GaN power amplifier transistor 3.

[0063] Step 4: The GaN power amplifier transistor 3 receives the secondary impedance matching signal 11, the filtered first power supply signal 18, and the feedback signal 16, processes the secondary impedance matching signal 11 to obtain a first output signal 12 and a second output signal 15, sends the first output signal 12 to the output LC passive matching circuit 4, and sends the second output signal 15 to the L-R-C negative feedback stabilization circuit 6.

[0064] Step 5: The L-R-C negative feedback stabilization circuit 6 receives the second output signal 15, processes the second output signal 15 according to the preset circuit stability requirements for the ultra-wideband full-frequency range, obtains the feedback signal 16, and sends the feedback signal 16 to the gate of the GaN power amplifier transistor 3.

[0065] Step 6: The output LC passive matching circuit 4 receives the first output signal 12, performs impedance matching on the first output signal 12 to obtain a third output signal 13, and sends the third output signal 13 to the output transmission line transformer circuit 5.

[0066] Step 7: The output transmission line transformer circuit 5 receives the third output signal 13, performs impedance matching on the third output signal 13 to obtain the power amplifier circuit output signal 14.

[0067] Step 8: The drain bias circuit 8 filters the second power supply signal to obtain the filtered second power supply signal 20, and sends the filtered second power supply signal 20 to the drain of the GaN power amplifier transistor 3.

[0068] In summary, in the embodiment of the present invention, the ultra-wideband power amplifier circuit uses a single-stage amplifier circuit to achieve power amplification in the ultra-wide frequency band range and has excellent frequency-power characteristics. From the circuit implementation solution, it overcomes the defects of complex structure, large volume, and high cost of the power amplifier circuit in the traditional ultra-wideband communication system. At the same time, it improves the reliability index of the whole ultra-wideband communication system, effectively reduces the circuit complexity of the communication equipment, and reduces the equipment volume.

[0069] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0070] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A ultra-wideband power amplification circuit, characterized in that It includes an input transmission line transformer circuit (1), an input LC passive matching circuit (2), a GaN power amplifier transistor (3), an output LC passive matching circuit (4), an output transmission line transformer circuit (5), an L-R-C negative feedback stabilization circuit (6), a gate bias circuit (7) and a drain bias circuit (8). The input transmission line transformer circuit (1) is connected to the input LC passive matching circuit (2). The input LC passive matching circuit (2) is connected to the gate of the GaN power amplifier transistor (3). The L-R-C negative feedback stabilization circuit (6) is respectively connected to the gate and the drain of the GaN power amplifier transistor (3). The gate bias circuit (7) is connected to the gate of the GaN power amplifier transistor (3). The drain bias circuit (8) is connected to the drain of the GaN power amplifier transistor (3). The output LC passive matching circuit (4) is connected to the drain of the GaN power amplifier transistor (3). The output transmission line transformer circuit (5) is connected to the output LC passive matching circuit (4), where: The input transmission line transformer circuit (1) is configured to receive a radio frequency input signal (9), perform impedance matching on the radio frequency input signal (9) to obtain a primary impedance matching signal (10), and send the primary impedance matching signal (10) to the input LC passive matching circuit (2); The input LC passive matching circuit (2) is configured to receive the primary impedance matching signal (10), perform impedance matching on the primary impedance matching signal (10) to obtain a secondary impedance matching signal (11), and send the secondary impedance matching signal (11) to the gate of the GaN power amplifier transistor (3); The gate bias circuit (7) is configured to filter the first power supply signal to obtain a filtered first power supply signal (18), and send the filtered first power supply signal (18) to the gate of the GaN power amplifier transistor (3); The GaN power amplifier transistor (3) is configured to receive the secondary impedance matching signal (11), the filtered first power supply signal (18) and a feedback signal (16), process the secondary impedance matching signal (11) to obtain a first output signal (12) and a second output signal (15), send the first output signal (12) to the output LC passive matching circuit (4), and send the second output signal (15) to the L-R-C negative feedback stabilization circuit (6); The L-R-C negative feedback stabilization circuit (6) is configured to receive the second output signal (15), process the second output signal (15) according to the preset circuit stability requirements for the ultra-wideband full frequency band range to obtain the feedback signal (16), and send the feedback signal (16) to the gate of the GaN power amplifier transistor (3); The output LC passive matching circuit (4) is configured to receive the first output signal (12), perform impedance matching on the first output signal (12) to obtain a third output signal (13), and send the third output signal (13) to the output transmission line transformer circuit (5). The output transmission line transformer circuit (5) is configured to receive the third output signal (13), perform impedance matching on the third output signal (13) to obtain a power amplifier circuit output signal (14). The drain bias circuit (8) is configured to filter the second power supply signal to obtain a filtered second power supply signal (20), and send the filtered second power supply signal (20) to the drain of the GaN power amplifier transistor (3).

2. The circuit according to claim 1, wherein The L-R-C negative feedback stabilization circuit (6) is composed of a low-loss RF capacitor, an AlN resistor, and a low-ESR RF inductor connected in series in sequence. The low-loss RF capacitor is respectively connected to the drain of the GaN power amplifier transistor (3) and the AlN resistor. The AlN resistor is connected to the low-ESR RF inductor, and the low-ESR RF inductor is connected to the gate of the GaN power amplifier transistor (3).

3. The circuit according to claim 1, wherein The loss tangent value of the low-loss RF capacitor is not greater than 10×10 -4 , the rated power consumption of the AlN resistor is 100 W, and the equivalent series resistance of the low-ESR RF inductor is less than 1 Ω.

4. The circuit according to claim 1, wherein The ratio of the input impedance value to the output impedance value of the input transmission line transformer circuit (1) is 4:1, and the ratio of the input impedance value to the output impedance value of the output transmission line transformer circuit (5) is 4:

1.

5. The circuit according to claim 1, wherein Ferrite cores are provided in the input transmission line transformer circuit (1) and the output transmission line transformer circuit (5), and the ferrite cores are MnZn ferrite cores with a magnetic permeability of 4000.

6. The circuit according to claim 1, wherein The gate bias circuit (7) and the drain bias circuit (8) are LC power supply filter circuits. The inductor in the gate bias circuit (7) is an RF inductor, and the inductor in the drain bias circuit (8) is a magnetic winding inductor.

7. The circuit according to claim 1, wherein The distance between the inductor in the gate bias circuit (7) and the gate of the GaN power amplifier transistor (3) does not exceed 1 mm.

8. The circuit according to claim 1, wherein The gate bias circuit (7) includes a first capacitor bank. The capacitor with the smallest capacitance value in the first capacitor bank is an RF capacitor. The distance between the capacitor with the smallest capacitance value in the first capacitor bank and the inductor in the gate bias circuit (7) does not exceed 1 mm, and the capacitor with the largest capacitance value in the first capacitor bank is an electrolytic capacitor.

9. The circuit according to claim 1, wherein The drain bias circuit (8) includes a second capacitor bank. The capacitor with the smallest capacitance value in the second capacitor bank is a radio frequency capacitor. The distance between the capacitor with the smallest capacitance value in the second capacitor bank and the inductor in the drain bias circuit (8) does not exceed 1 mm. The capacitor with the largest capacitance value in the second capacitor bank is an electrolytic capacitor.

10. A method for controlling the ultra-wideband power amplifier circuit according to any one of claims 1-9, characterized in that, Comprising: The input transmission line transformer circuit (1) receives a radio frequency input signal (9), performs impedance matching on the radio frequency input signal (9) to obtain a primary impedance matching signal (10), and sends the primary impedance matching signal (10) to the input LC passive matching circuit (2). The input LC passive matching circuit (2) receives the primary impedance matching signal (10), performs impedance matching on the primary impedance matching signal (10) to obtain a secondary impedance matching signal (11), and sends the secondary impedance matching signal (11) to the gate of the GaN power amplifier transistor (3). The gate bias circuit (7) filters the first power supply signal to obtain a filtered first power supply signal (18), and sends the filtered first power supply signal (18) to the gate of the GaN power amplifier transistor (3). The GaN power amplifier transistor (3) receives the secondary impedance matching signal (11), the filtered first power supply signal (18), and the feedback signal (16), processes the secondary impedance matching signal (11) to obtain a first output signal (12) and a second output signal (15), sends the first output signal (12) to the output LC passive matching circuit (4), and sends the second output signal (15) to the L-R-C negative feedback stabilization circuit (6). The L-R-C negative feedback stabilization circuit (6) receives the second output signal (15), processes the second output signal (15) according to the preset circuit stability requirements for the ultra-wideband full frequency range, obtains the feedback signal (16), and sends the feedback signal (16) to the gate of the GaN power amplifier transistor (3). The output LC passive matching circuit (4) receives the first output signal (12), performs impedance matching on the first output signal (12) to obtain a third output signal (13), and sends the third output signal (13) to the output transmission line transformer circuit (5). The output transmission line transformer circuit (5) receives the third output signal (13), performs impedance matching on the third output signal (13) to obtain a power amplifier circuit output signal (14). The drain bias circuit (8) filters the second power supply signal to obtain a filtered second power supply signal (20), and sends the filtered second power supply signal (20) to the drain of the GaN power amplifier transistor (3).

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