Frequency modulation matching circuit and electronic equipment

Abstract

The invention discloses a frequency modulation matching circuit and electronic equipment, and relates to the technical field of radio frequency power supplies. Wherein the output end of the system-on-chip circuit is connected with the input end of the digital frequency synthesis circuit; the output end of the digital frequency synthesis circuit is connected with the input end of the signal processing circuit; the output end of the signal processing circuit is connected with the input end of the impedance matching circuit; the first output end of the impedance matching circuit is connected with a load; the input end of the sampling circuit is connected with the second output end of the impedance matching circuit, and the output end of the sampling circuit is connected with the input end of the system-on-chip circuit. Therefore, the load is monitored in real time, the parameters of the impedance matching circuit are dynamically adjusted, the energy transmission efficiency is improved, the digital frequency synthesis technology is adopted, microsecond-level frequency switching can be achieved, the high-frequency frequency modulation requirement is met, high-frequency resolution is provided, and the precision and stability of radio-frequency signals are ensured.

Description

Technical Field

[0001] The present application relates to the technical field of radio frequency power supplies, and particularly to a frequency modulation matching circuit and an electronic device. Background Art

[0002] During the ion processing in a System on Chip (SOC), the load changes with the operation of the SOC, resulting in fluctuations in the impedance of the plasma. However, the frequency of the fixed-frequency radio frequency power supply in the SOC is fixed, so it is difficult to adapt to the change of the load and maintain the stability of the plasma, which leads to the extinction of the plasma and further generates interference; and because the frequency of the signal is fixed, the electric field distribution generated by the signal will be relatively single, and unevenness occurs in the processing area.

[0003] In view of the above technology, it is an urgent problem for those skilled in the art to seek a frequency modulation matching circuit. Summary of the Invention

[0004] The purpose of the present application is to provide a frequency modulation matching circuit and an electronic device, which can solve the problem that the fixed-frequency radio frequency signal in the prior art is difficult to adapt to the change of the load, resulting in a relatively single electric field distribution generated by the signal and unevenness in the processing area.

[0005] To solve the above technical problems, on the one hand, the present application provides a frequency modulation matching circuit, including: a system-on-chip circuit, a digital frequency synthesis circuit, a signal processing circuit, an impedance matching circuit, and a sampling circuit;

[0006] Wherein, the output end of the system-on-chip circuit is connected to the input end of the digital frequency synthesis circuit, and is used to send a generation signal representing a preset frequency to the digital frequency synthesis circuit;

[0007] The output end of the digital frequency synthesis circuit is connected to the input end of the signal processing circuit, and is used to generate a radio frequency signal with a preset frequency according to the generation signal;

[0008] The output end of the signal processing circuit is connected to the input end of the impedance matching circuit, and is used to amplify and filter the radio frequency signal;

[0009] The first output end of the impedance matching circuit is connected to the load, and is used to determine the circuit parameters matching the load according to the processed radio frequency signal;

[0010] The input end of the sampling circuit is connected to the second output end of the impedance matching circuit, and the output end of the sampling circuit is connected to the input end of the system-on-chip circuit. The sampling circuit is used to send the parameters corresponding to the current impedance matching circuit to the system-on-chip circuit, so that the system-on-chip circuit can generate a generation signal representing different frequencies according to the parameters.

[0011] Preferably, the system-on-chip circuit includes: a drive control circuit and an algorithm processing circuit;

[0012] Among them, the first end of the drive control circuit is connected to the input end of the digital frequency synthesis circuit as the output end of the system-on-chip circuit; the second end of the drive control circuit is connected to the output end of the sampling circuit as the input end of the system-on-chip circuit;

[0013] The third end and the fourth end of the drive control circuit are connected to the first end and the second end of the algorithm processing circuit through the AXI bus protocol;

[0014] The third end of the algorithm processing circuit is connected to the memory module; the fourth end of the algorithm processing circuit is connected to the host computer.

[0015] Preferably, the digital frequency synthesis circuit includes: a reference clock, a phase-locked loop, an accumulation controller, a memory, and a conversion filter circuit;

[0016] Among them, the output end of the reference clock is connected to the input end of the phase-locked loop;

[0017] The output end of the phase-locked loop is connected to the first input end of the accumulation controller and the first input end of the memory;

[0018] The second input end of the accumulation controller is connected to the output end of the system-on-chip circuit as the input end of the digital frequency synthesis circuit;

[0019] The output end of the accumulation controller is connected to the second input end of the memory;

[0020] The output end of the memory is connected to the input end of the conversion filter circuit;

[0021] The output end of the conversion filter circuit is connected to the input end of the signal processing circuit as the output end of the digital frequency synthesis circuit.

[0022] Preferably, the conversion filter circuit includes: a digital-to-analog converter and a first low-pass filter;

[0023] Among them, the input end of the digital-to-analog converter is connected to the output end of the memory as the input end of the conversion filter circuit;

[0024] The output end of the digital-to-analog converter is connected to the input end of the first low-pass filter;

[0025] The output end of the first low-pass filter is connected to the input end of the signal processing circuit as the output end of the conversion filter circuit.

[0026] Preferably, the signal processing circuit includes: a variable gain amplifier, a power amplifier, and a second low-pass filter;

[0027] Among them, the input end of the variable gain amplifier is connected to the output end of the digital frequency synthesis circuit as the input end of the signal processing circuit;

[0028] The output end of the variable gain amplifier is connected to the input end of the power amplifier;

[0029] The output end of the power amplifier is connected to the input end of the second low-pass filter;

[0030] The output end of the second low-pass filter is connected to the input end of the impedance matching circuit as the output end of the signal processing circuit;

[0031] The connection end of the variable gain amplifier is connected to the first connection end of the system-on-chip circuit;

[0032] The connection end of the power amplifier is connected to the second connection end of the system-on-chip circuit.

[0033] Preferably, the impedance matching circuit includes: a first capacitor, a second capacitor, and a first inductor;

[0034] Among them, the first end of the first capacitor is connected to the first end of the second capacitor, and they are jointly used as the input end of the impedance matching circuit and connected to the output end of the signal processing circuit;

[0035] The second end of the first capacitor and the second end of the second capacitor are jointly used as the second output end of the impedance matching circuit and connected to the input end of the sampling circuit;

[0036] The third end of the first capacitor is connected to the first end of the first inductor;

[0037] The second end of the first inductor is used as the first output end of the impedance matching circuit and connected to the load;

[0038] The third end of the second capacitor is grounded.

[0039] Preferably, the first capacitor and the second capacitor are variable capacitors.

[0040] Preferably, it further includes: an equivalent resistor;

[0041] Among them, the first end of the equivalent resistor is connected to the output end of the digital frequency synthesis circuit;

[0042] The second end of the equivalent resistor is connected to the input end of the signal processing circuit.

[0043] Preferably, the sampling circuit is a radio frequency agile transceiver.

[0044] On the other hand, the present application also provides an electronic device, including the above-mentioned frequency modulation matching circuit.

[0045] A frequency modulation matching circuit provided by the present application includes: a system-on-chip circuit, a digital frequency synthesis circuit, a signal processing circuit, an impedance matching circuit, and a sampling circuit; wherein, the output end of the system-on-chip circuit is connected to the input end of the digital frequency synthesis circuit and is used to send a generation signal representing a preset frequency to the digital frequency synthesis circuit; the output end of the digital frequency synthesis circuit is connected to the input end of the signal processing circuit and is used to generate a radio frequency signal with a preset frequency according to the generation signal; the output end of the signal processing circuit is connected to the input end of the impedance matching circuit and is used to perform amplification and filtering processing on the radio frequency signal; the first output end of the impedance matching circuit is connected to a load and is used to determine circuit parameters matching the load according to the processed radio frequency signal; the input end of the sampling circuit is connected to the second output end of the impedance matching circuit, and the output end of the sampling circuit is connected to the input end of the system-on-chip circuit and is used to send the parameters corresponding to the current impedance matching circuit to the system-on-chip circuit, so that the system-on-chip circuit generates a generation signal representing different frequencies according to the parameters. It can be seen that the present application monitors the load in real time and dynamically adjusts the parameters of the impedance matching circuit to improve the energy transmission efficiency. Moreover, the present application adopts the technology of digital frequency synthesis, can achieve microsecond-level frequency switching, meet the high-frequency frequency modulation requirements, and provides high frequency resolution to ensure the accuracy and stability of the radio frequency signal. Description of the Drawings

[0046] In order to more clearly illustrate the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0047] Figure 1 It is a module diagram of a frequency modulation matching circuit provided by the present application;

[0048] Figure 2 It is a general module diagram of a frequency modulation matching circuit provided by the present application;

[0049] Figure 3 It is a circuit diagram of the digital frequency synthesis circuit provided by the embodiments of the present application;

[0050] Figure 4 It is a circuit diagram of the signal processing circuit provided by the embodiments of the present application;

[0051] Figure 5 It is a flowchart of the method corresponding to the frequency modulation matching circuit provided by the embodiments of the present application. Detailed Embodiments

[0052] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0053] The core of the present application is to provide a frequency modulation matching circuit and an electronic device.

[0054] In order to enable those skilled in the art to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0055] Figure 1 A module diagram of a frequency modulation matching circuit provided by the present application is shown in Figure 1 As shown, it includes: a system-on-chip circuit 1, a digital frequency synthesis circuit 2, a signal processing circuit 3, an impedance matching circuit 4, and a sampling circuit 5. In addition, it further includes: a load ZL. The connection relationship of its circuit is: the output end of the system-on-chip circuit 1 is connected to the input end of the digital frequency synthesis circuit 2; the output end of the digital frequency synthesis circuit 2 is connected to the input end of the signal processing circuit 3; the output end of the signal processing circuit 3 is connected to the input end of the impedance matching circuit 4; the first output end of the impedance matching circuit 4 is connected to the load ZL; the input end of the sampling circuit 5 is connected to the second output end of the impedance matching circuit 4, and the output end of the sampling circuit 5 is connected to the input end of the system-on-chip circuit 1.

[0056] In a specific embodiment, according to the connection relationship of the above circuit, it can be known that it forms a loop. The system-on-chip circuit 1 first sends a generation signal representing a preset frequency to the digital frequency synthesis circuit 2; and the digital frequency synthesis circuit 2 generates a radio frequency signal with a preset frequency according to the generation signal; after the radio frequency signal enters the signal processing circuit 3, the signal processing circuit 3 performs amplification and filtering processing on the radio frequency signal; and the impedance matching circuit 4 will adjust the parameters of its own resistors, capacitors, inductors, etc. according to the processed radio frequency signal to achieve the purpose of matching with the load (obtaining the impedance of the load and then performing matching); after the matching, the sampling circuit will collect the corresponding parameters of the current impedance matching circuit 4 again, which may be the circuit parameters after matching or the normal parameters, and then send them to the system-on-chip circuit 1, and the system-on-chip circuit 1 generates a generation signal representing different frequencies again according to the parameters, and repeats the above process again to achieve the purpose of continuous adjustment, so as to ensure that for any value of the load, its impedance matching circuit 4 can achieve the purpose of matching.

[0057] In this design, according to the system-on-chip circuit 1, digital frequency synthesis circuit 2, signal processing circuit 3, impedance matching circuit 4, and sampling circuit 5, the working process of a frequency modulation matching circuit can be determined as follows:

[0058] 1. Design the system-on-chip circuit 1, digital frequency synthesis circuit 2, signal processing circuit 3, impedance matching circuit 4, and sampling circuit 5.

[0059] 2. Initialize the system-on-chip circuit 1 and set the initial frequency and matching parameters.

[0060] 3. The digital frequency synthesis circuit 2 generates a radio frequency signal, and the signal processing circuit 3 amplifies the signal and transmits it to the load ZL.

[0061] 4. Monitor the impedance of the load ZL in real time and feedback the data to the system-on-chip circuit 1.

[0062] 5. The system-on-chip circuit 1 calculates the optimal frequency and matching parameters, and adjusts the output of the digital frequency synthesis circuit 2 and the parameters of the impedance matching circuit 4.

[0063] 6. Repeat steps 4 - 5 until the system reaches a stable state.

[0064] A frequency modulation matching circuit provided in this application includes: a system-on-chip circuit, a digital frequency synthesis circuit, a signal processing circuit, an impedance matching circuit, and a sampling circuit; wherein, the output end of the system-on-chip circuit is connected to the input end of the digital frequency synthesis circuit and is used to send a generation signal representing a preset frequency to the digital frequency synthesis circuit; the output end of the digital frequency synthesis circuit is connected to the input end of the signal processing circuit and is used to generate a radio frequency signal with a preset frequency according to the generation signal; the output end of the signal processing circuit is connected to the input end of the impedance matching circuit and is used to perform amplification and filtering processing on the radio frequency signal; the first output end of the impedance matching circuit is connected to the load and is used to determine the circuit parameters matching the load according to the processed radio frequency signal; the input end of the sampling circuit is connected to the second output end of the impedance matching circuit, and the output end of the sampling circuit is connected to the input end of the system-on-chip circuit and is used to send the parameters corresponding to the current impedance matching circuit to the system-on-chip circuit, so that the system-on-chip circuit generates a generation signal representing different frequencies according to the parameters. Thus, it can be seen that this application monitors the load in real time and dynamically adjusts the parameters of the impedance matching circuit to improve the energy transmission efficiency. Moreover, this application adopts the technology of digital frequency synthesis, which can achieve microsecond-level frequency switching, meet the high-frequency frequency modulation requirements, and provide high frequency resolution to ensure the accuracy and stability of the radio frequency signal.

[0065] In a specific embodiment, such as Figure 2As shown, the system-on-chip circuit 1 includes: a drive control circuit 11 and an algorithm processing circuit 12. The connection relationship is as follows: the first end of the drive control circuit 11 serves as the output end of the system-on-chip circuit 1 and is connected to the input end of the digital frequency synthesis circuit 2; the second end of the drive control circuit 11 serves as the input end of the system-on-chip circuit 1 and is connected to the output end of the sampling circuit 5; the third end and the fourth end (PL end) of the drive control circuit 11 are connected to the first end and the second end of the algorithm processing circuit 12 through the AXI bus protocol; the third end of the algorithm processing circuit 12 is connected to the memory module DDR4 (Double DataRate); the fourth end (PS end) of the algorithm processing circuit 12 is connected to the host computer (PC).

[0066] And Figure 2 In the circuit shown, the impedance matching circuit 4 includes: a first capacitor C1, a second capacitor C2, and a first inductor L1. The connection relationship is as follows: the first end of the first capacitor C1 is connected to the first end of the second capacitor C2, and they jointly serve as the input end of the impedance matching circuit 4 and are connected to the output end of the signal processing circuit 3; the second end of the first capacitor C1 and the second end of the second capacitor C2 jointly serve as the second output end of the impedance matching circuit 4 and are connected to the input end of the sampling circuit 5; the third end of the first capacitor C1 is connected to the first end of the first inductor L1; the second end of the first inductor L2 serves as the first output end of the impedance matching circuit 4 and is connected to the load ZL; the third end of the second capacitor C2 is grounded. In addition, the load ZL is also grounded.

[0067] And Figure 2 In the circuit shown, an equivalent resistance ZS is further included between the digital frequency synthesis circuit and the signal processing circuit.

[0068] In a specific embodiment, for the system-on-chip circuit 1, the drive control circuit 11 uses the logic processing fourth end (PL end) of the FPGA (Field-Programmable Gate Array) to drive the digital frequency synthesis circuit to generate a radio frequency signal, and the signal processing circuit 3 performs operations such as amplification, filtering, and noise reduction, outputs the processed radio frequency signal (RF signal), and drives the sampling circuit 5 to collect the parameters in the impedance matching circuit 4 in real time; among them, the fourth end (PS end, Processing System) of the algorithm processing circuit 12, as an important part of the algorithm processing circuit 12, undertakes key functions such as system management, algorithm processing, and communication control. The specific cooperation workflow between the PS end and the PL end includes but is not limited to:

[0069] 1. The PS end initializes the system and configures the digital frequency synthesis circuit 2 and the impedance matching circuit 4 of the PL end.

[0070] 2. The PL side generates RF signals and acquires the impedance data corresponding to the load, and transmits the data to the PS side through the AXI bus.

[0071] 3. The PS side runs the matching algorithm, calculates the optimal frequency and matching parameters, and sends the results to the PL side for execution.

[0072] 4. The PS side monitors the system status in real time, processes external instructions, and stores the operation data.

[0073] 5. When the impedance of the load changes, the PS side dynamically adjusts the algorithm parameters to ensure that the system is always in the optimal working state.

[0074] 6. The PS side supports a human-machine interface (such as a touch screen, keyboard, and display). Users can set parameters such as the frequency and power of the RF signal through the interface; and provide a configuration file management function. Users can save and load different working mode configurations to facilitate quick switching of application scenarios.

[0075] For the impedance matching circuit 4, it is necessary to first determine the impedance of the load ZL in order to achieve the matching between the impedance matching circuit 4 and the load ZL.

[0076] The steps to determine the impedance of the load ZL are as follows:

[0077] 1. Signal injection: Inject an RF signal with a known frequency and amplitude into the load ZL. The RF signal can be generated by the digital frequency synthesis circuit 2 and transmitted to the load ZL after being amplified and filtered by the signal processing circuit 3.

[0078] 2. Signal acquisition: Use voltage and current sensors to acquire the voltage and current signals on the load ZL. Among them, the voltage sensor measures the voltage across the load, and the current sensor measures the current passing through the load.

[0079] 3. Signal processing: Convert the acquired analog signal into a digital signal through an ADC (analog-to-digital converter), and filter and calibrate the digital signal to eliminate noise and errors.

[0080] 4. Calculation method: The calculation of the impedance of the load ZL is based on Ohm's law and the complex impedance formula:

[0081] Ohm's law:

[0082] The calculation formula for the impedance Z of the load ZL is:

[0083] ;

[0084] where V is the voltage across the load ZL and I is the current passing through the load ZL.

[0085] Complex impedance:

[0086] The impedance Z can be expressed in complex form as:

[0087] ;

[0088] where R is the resistance (real part) and X is the reactance (imaginary part).

[0089] By measuring the phase difference between the voltage and the current, the reactance X can be calculated as:

[0090] ;

[0091] where θ is the phase difference between the voltage and the current.

[0092] The impedance matching circuit 4 is matched with the load ZL in the following ways:

[0093] 1. The calculation of the optimal frequency and matching parameters is usually based on the impedance matching theory. Common methods include:

[0094] The first method: conjugate matching method:

[0095] The goal is to make the impedance Z of the load ZL conjugate-matched with the impedance of the equivalent resistance ZS, that is: ;

[0096] ;

[0097] where is the conjugate complex number of the load impedance.

[0098] By adjusting the frequency and the component values of the matching network, the impedance of the equivalent resistance ZS is made to be conjugate-matched with the impedance Z of the load ZL. is conjugate-matched with the impedance Z of the load ZL.

[0099] The second method: Smith chart method: Use the Smith chart tool to calculate the component values of the matching network by a graphical method. According to the position of the load impedance, find the matching path on the Smith chart and determine the values of the inductor L1, the first capacitor C1, and the second capacitor C2.

[0100] 2. Optimization algorithm: Use numerical optimization algorithms (such as the gradient descent method, genetic algorithm) to calculate the optimal frequency and matching parameters. The goal is to minimize the reflection coefficient or maximize the transmission efficiency.

[0101] 3. Parameter adjustment: Frequency adjustment, send the calculated optimal frequency parameter to the system-on-chip circuit 1 to adjust the frequency of the RF signal; matching network adjustment, adjust the component values of the impedance matching network (such as the first inductor L1, the first capacitor C1, and the second capacitor C2) through the digital control interface SPI.

[0102] Among them, it should be noted that the embodiments provided in this application are only one implementable way, but are not limited to only this implementable way, and can be set by oneself according to the needs of users.

[0103] Among them, it should also be noted that in order to reduce the operation of disassembling and replacing components, the first capacitor C1 and the second capacitor C2 in this application are variable capacitors; and the sampling circuit 5 is a radio frequency agile transceiver.

[0104] This application defines the specific structures of the system-on-chip circuit and the impedance matching circuit. Under this structure, the system-on-chip circuit integrates multiple functional modules, simplifying the system design; the impedance matching circuit can achieve load matching and improve the energy transmission efficiency.

[0105] Based on the above embodiments, as Figure 3 shown, its digital frequency synthesis circuit 2 includes: a reference clock 21, a phase-locked loop 22, an accumulation controller 23, a memory 24, a digital-to-analog converter 25, and a first low-pass filter 26. The connection relationship of its circuit is: the output end of the reference clock 21 is connected to the input end of the phase-locked loop 22; the output end of the phase-locked loop 22 is connected to the first input end of the accumulation controller 23 and the first input end of the memory 24; the second input end of the accumulation controller 23 is used as the input end of the digital frequency synthesis circuit 2 and is connected to the output end of the system-on-chip circuit 1; the output end of the accumulation controller 23 is connected to the second input end of the memory 24; the output end of the memory 24 is connected to the input end of the digital-to-analog converter 25; the output end of the digital-to-analog converter 25 is connected to the input end of the first low-pass filter 26; the output end of the first low-pass filter 26 is used as the output end of the digital frequency synthesis circuit 2 and is connected to the input end of the signal processing circuit 3.

[0106] As Figure 4 shown, its signal processing circuit 3 includes: a variable gain amplifier 31, a power amplifier 32, and a second low-pass filter 33. The connection relationship is: the input end of the variable gain amplifier 31 is used as the input end of the signal processing circuit 3 and is connected to the output end of the digital frequency synthesis circuit 2; the output end of the variable gain amplifier 31 is connected to the input end of the power amplifier 32; the output end of the power amplifier 32 is connected to the input end of the second low-pass filter 33; the output end of the second low-pass filter 33 is used as the output end of the signal processing circuit 3 and is connected to the input end of the impedance matching circuit 4; the connection end of the variable gain amplifier 31 is connected to the first connection end of the system-on-chip circuit 1; the connection end of the power amplifier 32 is connected to the second connection end of the system-on-chip circuit 1.

[0107] Among them, it should be noted that the main function of the digital frequency synthesis circuit 2 is to generate a corresponding radio frequency signal according to the generated signal, while the signal processing circuit 3 processes the radio frequency signal such as amplification and filtering. Therefore, the structure provided in this application is only one implementable way, but not limited to only this implementation way, and can be set by itself according to the needs of users.

[0108] In summary, the process of this application is as Figure 5 shown, including the following processes:

[0109] S10: Start.

[0110] S11: Circuit initialization.

[0111] S12: Determine whether the system-on-chip circuit and the PC side are successfully configured.

[0112] S13: Generate a radio frequency signal through the digital frequency synthesis circuit.

[0113] S14: Determine whether a radio frequency signal is generated.

[0114] S15: If so, perform an impedance test on the load.

[0115] S16: If not, adjust the frequency of the radio frequency signal and rematch, and enter step S11.

[0116] S17: The system-on-chip circuit performs algorithm processing.

[0117] S18: Determine whether the parameters corresponding to the impedance matching circuit are optimal values.

[0118] S19: If so, determine that the system is stable and enter step S14; if not, enter step S16.

[0119] S20: Perform monitoring and protection.

[0120] S21: Determine whether an abnormality occurs.

[0121] S22: If so, end; if not, return to step S19.

[0122] Since steps S10 - S22 are the summary of the above embodiments, they will not be elaborated in this application.

[0123] Thus, it can be seen that the frequency modulation matching circuit provided in this application has the following advantages:

[0124] 1. Fast frequency modulation: Based on the technologies of the system-on-chip circuit and the digital frequency synthesis circuit, microsecond-level frequency switching is achieved to meet the high-frequency frequency modulation requirements.

[0125] 2. High-efficiency matching: Monitor the impedance of the load in real time and dynamically adjust the matching parameters to improve the energy transfer efficiency.

[0126] 3. Integrated design: The system-on-chip circuit integrates multiple functional modules to simplify the system design.

[0127] 4. High precision: The technology of the digital frequency synthesis circuit provides high frequency resolution to ensure the accuracy and stability of the radio frequency signal.

[0128] On the other hand, the present application also provides an electronic device, including the above frequency modulation matching circuit, and having the same beneficial effects.

[0129] Since the embodiment of the electronic device provided by the present application is the same as the embodiment of the above frequency modulation matching circuit, the present application will not be described in detail here.

[0130] The above has introduced in detail a frequency modulation matching circuit and an electronic device provided by the present application. Each embodiment in the specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same and similar parts among the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple. For the relevant parts, refer to the description in the method part. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present application, several improvements and modifications can still be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0131] The above has introduced in detail a frequency modulation matching circuit and an electronic device provided by the present application. Each embodiment in the specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same and similar parts among the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple. For the relevant parts, refer to the description in the method part. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present application, several improvements and modifications can still be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0132] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

Claims

1. A frequency modulation matching circuit, characterized in that, Including: System-on-chip circuit, digital frequency synthesis circuit, signal processing circuit, impedance matching circuit, and sampling circuit; Wherein, the output end of the system-on-chip circuit is connected to the input end of the digital frequency synthesis circuit, and is used to send a generation signal representing a preset frequency to the digital frequency synthesis circuit; The output end of the digital frequency synthesis circuit is connected to the input end of the signal processing circuit, and is used to generate a radio frequency signal with the preset frequency according to the generation signal; The output end of the signal processing circuit is connected to the input end of the impedance matching circuit, and is used to perform amplification and filtering processing on the radio frequency signal; The first output end of the impedance matching circuit is connected to a load, and is used to determine circuit parameters matching the load according to the processed radio frequency signal; The input end of the sampling circuit is connected to the second output end of the impedance matching circuit, and the output end of the sampling circuit is connected to the input end of the system-on-chip circuit, and is used to send the parameters corresponding to the current impedance matching circuit to the system-on-chip circuit, so that the system-on-chip circuit generates the generation signal representing different frequencies according to the parameters.

2. The frequency modulation matching circuit according to claim 1, characterized in that, The system-on-chip circuit includes: a drive control circuit and an algorithm processing circuit; Wherein, the first end of the drive control circuit is used as the output end of the system-on-chip circuit and is connected to the input end of the digital frequency synthesis circuit; the second end of the drive control circuit is used as the input end of the system-on-chip circuit and is connected to the output end of the sampling circuit; The third end and the fourth end of the drive control circuit are connected to the first end and the second end of the algorithm processing circuit through the AXI bus protocol; The third end of the algorithm processing circuit is connected to a memory module; the fourth end of the algorithm processing circuit is connected to a host computer.

3. The frequency modulation matching circuit according to claim 1, characterized in that The digital frequency synthesis circuit includes: a reference clock, a phase-locked loop, an accumulation controller, a memory, and a conversion and filtering circuit; Wherein, the output end of the reference clock is connected to the input end of the phase-locked loop; The output end of the phase-locked loop is connected to the first input end of the accumulation controller and the first input end of the memory; The second input end of the accumulation controller is used as the input end of the digital frequency synthesis circuit and is connected to the output end of the system-on-chip circuit; The output end of the accumulation controller is connected to the second input end of the memory; The output end of the memory is connected to the input end of the conversion and filtering circuit; The output end of the conversion and filtering circuit is used as the output end of the digital frequency synthesis circuit and is connected to the input end of the signal processing circuit.

4. The frequency modulation matching circuit according to claim 3, characterized in that The conversion and filtering circuit includes: a digital-to-analog converter and a first low-pass filter; Wherein, the input end of the digital-to-analog converter is used as the input end of the conversion and filtering circuit and is connected to the output end of the memory; The output end of the digital-to-analog converter is connected to the input end of the first low-pass filter; The output end of the first low-pass filter is used as the output end of the conversion and filtering circuit and is connected to the input end of the signal processing circuit.

5. The frequency modulation matching circuit according to claim 1, wherein The signal processing circuit includes: a variable gain amplifier, a power amplifier, and a second low-pass filter; Among them, the input end of the variable gain amplifier serves as the input end of the signal processing circuit and is connected to the output end of the digital frequency synthesis circuit; The output end of the variable gain amplifier is connected to the input end of the power amplifier; The output end of the power amplifier is connected to the input end of the second low-pass filter; The output end of the second low-pass filter serves as the output end of the signal processing circuit and is connected to the input end of the impedance matching circuit; The connection end of the variable gain amplifier is connected to the first connection end of the system-on-chip circuit; The connection end of the power amplifier is connected to the second connection end of the system-on-chip circuit.

6. The frequency modulation matching circuit according to claim 1, wherein The impedance matching circuit includes: a first capacitor, a second capacitor and a first inductor; Among them, the first end of the first capacitor is connected to the first end of the second capacitor, and they jointly serve as the input end of the impedance matching circuit and are connected to the output end of the signal processing circuit; The second end of the first capacitor and the second end of the second capacitor jointly serve as the second output end of the impedance matching circuit and are connected to the input end of the sampling circuit; The third end of the first capacitor is connected to the first end of the first inductor; The second end of the first inductor serves as the first output end of the impedance matching circuit and is connected to the load; The third end of the second capacitor is grounded.

7. The frequency modulation matching circuit according to claim 6, characterized in that The first capacitor and the second capacitor are variable capacitors.

8. The frequency modulation matching circuit according to claim 1, characterized in that It further includes: An equivalent resistor; Among them, the first end of the equivalent resistor is connected to the output end of the digital frequency synthesis circuit; The second end of the equivalent resistor is connected to the input end of the signal processing circuit.

9. The frequency modulation matching circuit according to any one of claims 1-8, characterized in that, The sampling circuit is a radio frequency agile transceiver.

10. An electronic device, characterized in that, It includes the frequency modulation matching circuit according to any one of claims 1-9.

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