High-voltage pulse source generator with controllable amplitude and frequency and large-depth ground penetrating radar device

Abstract

The application provides a high-voltage pulse source generator with controllable amplitude frequency and a large-depth ground penetrating radar device, relates to the technical field of electronic circuits, and comprises an edge trigger signal circuit, a pulse generation adjusting circuit, a comparison adjusting circuit, an MCU control circuit, a high-voltage generation adjusting circuit, a high-voltage MOS drive circuit, a MOS tube high-side power supply circuit and a wireless communication circuit, wherein the edge trigger signal circuit is connected with the pulse generation adjusting circuit; the pulse generation adjusting circuit is connected with the comparison adjusting circuit and the MCU control circuit respectively, the comparison adjusting circuit is connected with the MCU control circuit and the high-voltage MOS drive circuit respectively; the MCU control circuit is connected with the high-voltage generation adjusting circuit and the wireless communication circuit respectively; the high-voltage MOS drive circuit is connected with the high-voltage generation adjusting circuit and the MOS tube high-side power supply circuit respectively, and is used for adjusting positive pulse signals and negative pulse signals. The application is helpful to improve the control precision of the high-voltage pulse source generator.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, in particular to a high-voltage pulse source generator with controllable amplitude and frequency and a large-depth ground penetrating radar device. BACKGROUND

[0002] A high-voltage pulse power supply is a power supply device that stores energy at a low speed and releases it at a high speed. It outputs high-voltage pulses of a certain width, amplitude, and frequency through the opening and closing of various forms of switches. Currently, high-voltage pulse power supplies are mainly used in basic research fields such as gas discharge, dielectric aging, and pulsed jet mechanism, as well as industrial application fields such as material surface modification, wastewater / gas treatment, and sterilization. In experimental research, the pulse width, frequency, amplitude, and other parameters need to be changed to analyze the influence of different power supply parameters on different discharge forms. In industrial applications, the pulse width, frequency, amplitude, and other parameters need to be changed to deal with different processing objects.

[0003] A Chinese patent with publication number CN114400989A discloses a pulse generation circuit, a pulse generation device, and a control method thereof. The pulse generation circuit includes a high-voltage DC power supply, at least one magnetic drive loop circuit, and a Marx main circuit connected in parallel with the high-voltage DC power supply. The output end of the half-bridge control circuit in the magnetic drive loop circuit and at least one gate drive circuit group transmit control signals using the magnetic induction law through high-voltage wires. The gate drive circuit group is provided with a first output end and a second output end. The first output end is connected with a main switch in the Marx main circuit, and the second output end is connected with a tail switch in the Marx main circuit. However, the above-mentioned scheme relies on the magnetic induction method to transmit control signals through high-voltage wires, which is easily affected by electromagnetic interference, signal attenuation, and time delay. Moreover, although the positive and negative pulses have the same pulse width, they have limitations in precise synchronization and amplitude consistency, leading to a decrease in control precision. Therefore, it is necessary to provide a high-voltage pulse source generator with controllable amplitude and frequency and a large-depth ground penetrating radar device to improve the control precision of the high-voltage pulse source generator. SUMMARY

[0004] Therefore, the present application provides a high-voltage pulse source generator with controllable amplitude and frequency and a large-depth ground penetrating radar device. By comparing and adjusting the relative delay of positive and negative pulse signals in the comparison adjustment circuit, the accurate relative delay between the positive and negative pulse signals is ensured. At the same time, the MOS drive circuit adjusts the positive and negative pulse signals, thereby improving the control precision of the high-voltage pulse source generator.

[0005] The present application provides a high-voltage pulse source generator with controllable amplitude and frequency, which includes an edge trigger signal circuit, a pulse generation adjustment circuit, a comparison adjustment circuit, an MCU control circuit, a high-voltage generation adjustment circuit, a high-voltage MOS drive circuit, a MOS tube high-side power supply circuit, and a wireless communication circuit.

[0006] The edge trigger signal circuit is connected with the pulse generation adjustment circuit;

[0007] The pulse generation adjustment circuit is connected with the comparison adjustment circuit and the MCU control circuit respectively, and is used for receiving the external synchronization trigger edge signal sent by the edge trigger signal circuit, and generating a positive and negative pulse signal with an electrically adjustable pulse width;

[0008] The comparison adjustment circuit is connected with the MCU control circuit and the high-voltage MOS drive circuit respectively, and is used for adjusting the positive and negative pulse signals output by the pulse generation adjustment circuit according to the positive and negative pulse signals generated by the pulse generation adjustment circuit and a reference voltage, so as to obtain the positive and negative pulse signals with a relative delay;

[0009] The MCU control circuit is connected with the high-voltage generation adjustment circuit and the wireless communication circuit respectively, and the high-voltage generation adjustment circuit outputs a direct current voltage with an adjustable amplitude in response to the instruction of the MCU control circuit, and provides a direct current bias for the high-voltage MOS drive circuit;

[0010] The high-voltage MOS drive circuit is connected with the high-voltage generation adjustment circuit and the MOS tube high-side power supply circuit respectively, and is used for adjusting the positive and negative pulse signals, so as to generate two high-voltage pulse signals with the same pulse width and amplitude and opposite polarities.

[0011] On the basis of the above technical scheme, preferably, the edge trigger signal circuit comprises a fiber receiver U3, a capacitor C16, a capacitor C20, a capacitor C23, a comparator U52.1, a resistor R4, a resistor R8 and a resistor R23, one end of the capacitor C23 is connected with the first end of the fiber receiver U3, the other end of the capacitor C23 and the reverse input end of the comparator U52.1 are connected with one end of the resistor R23, the second end of the fiber receiver U3 is grounded, the third end of the fiber receiver U3 is connected with a voltage input end, the fourth end of the fiber receiver U3 is connected with the capacitor C16, the other end of the capacitor C16 and the positive input end of the comparator U52.1 are connected with one end of the resistor R4, the other end of the resistor R4 is connected with the output end of the comparator U52.1 and one end of the resistor R8 respectively, the common end of the resistor R8 and the resistor R23 is connected with one end of the capacitor C20 and the pulse generation adjustment circuit respectively, and the other end of the capacitor C20 is grounded.

[0012] On the basis of the above technical solutions, preferably, the pulse generation adjustment circuit comprises a multivibrator U60, a digital potentiometer U61, an oscillation resistor R130, an oscillation capacitor C132, and a resistor R131, a first pin of the multivibrator U60 is grounded, the external synchronization trigger edge signal is input by a second pin of the multivibrator U60, a third pin of the multivibrator U60 is connected with one end of the resistor R131, a fourth pin of the multivibrator U60 is grounded together with the other end of the resistor R131, a fifth pin of the multivibrator U60 is externally connected with a voltage input end, a sixth pin of the multivibrator U60 is connected with a common end of the oscillation resistor R130 and the oscillation capacitor C132, a seventh pin of the multivibrator U60 is connected with the other end of the oscillation capacitor C132, and the other end of the oscillation resistor R130 is connected with the digital potentiometer U61.

[0013] Further preferably, the comparison adjustment circuit comprises a DAC output chip U59, a comparator U51.1, and a comparator U55.1, a first pin of the DAC output chip U59 is externally connected with a voltage input end, a second pin of the DAC output chip U59 is connected with a reverse input end of the comparator U51.1, a third pin of the DAC output chip U59 is connected with a reverse input end of the comparator U55.1, a positive input end of the comparator U51.1 and the comparator U55.1 is connected with the pulse generation adjustment circuit, and an output end of the comparator U51.1 and the comparator U55.1 is connected with the high-voltage MOS drive circuit.

[0014] Further preferably, the high-voltage generation adjustment circuit comprises a resistor R74, a resistor R75, a resistor R78, a resistor R80, a resistor R83, a resistor R85, a resistor R86, a resistor R127, a resistor R128, a resistor R129, a capacitor C97, a capacitor C101, a capacitor C104, a capacitor C106, a capacitor C130, a PWM controller U32, an NMOS tube U56, a filter inductor L10, a rectifier diode D19, a diode D22, and a high-frequency transformer T5, wherein,

[0015] One end of the resistor R80 is grounded through the resistor R85, one end of the resistor R80 is connected with the MCU control circuit through the resistor R86, one end of the resistor R80 is also connected with the common end of the resistor R83, the capacitor C106 and the PWM controller U32, the other common end of the resistor R83 and the capacitor C106 is connected with the first pin of the PWM controller U32, the third pin of the PWM controller U32 is connected with the common end of the resistor R83 and the capacitor C101, the fourth pin of the PWM controller U32 is connected with the common end of the resistor R75 and the capacitor C104, the common end of the capacitor C104 and the resistor R74 is grounded, the common end of the resistor R75 and the resistor R74 is connected with the source of the NMOS tube U56, the other end of the capacitor C104 is grounded through the resistor R78, the other end of the resistor R75 is connected with the fifth pin of the PWM controller U32 to which a voltage input end is externally connected in common, the sixth pin of the PWM controller U32 and the common end of the filter inductor L10 are externally connected with a voltage input end, the seventh pin of the PWM controller U32 is connected with the gate of the NMOS tube U56, the eighth pin of the PWM controller U32 is grounded, the drain of the NMOS tube U56 is connected with the anode of the diode D22 and the second end of the high-frequency transformer T5 respectively, the cathode of the diode D22 is connected with the first common end of the resistor R127 and the capacitor C130, the second common end of the resistor R127 and the capacitor C130 is connected with the other end of the filter inductor L10 and the first end of the high-frequency transformer T5 respectively, the third end of the high-frequency transformer T5 is connected with the anode of the rectifier diode D19, the cathode of the rectifier diode D19, one end of the capacitor C97 and the resistor R128 are connected with the other end of the resistor R80, the capacitor C97 is grounded in common with the fourth end of the high-frequency transformer T5, the common end of the resistor R128 and the resistor R129 is connected with the MCU control circuit, the other end of the resistor R129 is grounded.

[0016] More preferably, the high-voltage MOS drive circuit comprises a first drive sub-circuit and a second drive sub-circuit, and the first drive sub-circuit and the second drive sub-circuit are connected with the comparison adjustment circuit, the high-voltage generation adjustment circuit and the MOS tube high-side power supply circuit.

[0017] Further preferably, the first driving sub-circuit comprises a plurality of inverters U8, a transformer T4, a gate driver U5, a gate driver U11, resistors R7, R12, R21, R35, R110, R111, a power resistor R25, capacitors C22, C25, C28, NMOS tubes Q3, Q5, voltage stabilizing diodes D6, D7 and D46, a first pin of the inverter U8 is connected with the comparison and adjustment circuit and one end of the capacitor C25 respectively, a second pin of the inverter U8 is connected with a first end of the transformer T4 through the capacitor C28, a second end of the transformer T4 is grounded, a third end of the transformer T4 is connected with a third pin of the gate driver U5, a fourth end of the transformer T4 is connected with a common end of the resistor R7 and the resistor R12, a first pin of the gate driver U5 is connected with the MOS high-side power supply circuit, a second pin of the gate driver U5, another end of the resistor R12, a source of the NMOS tube Q3, a positive electrode of the voltage stabilizing diode D46, one end of the power resistor R25 and a common end of the capacitor C22 and the resistor R110 are all connected with the MOS high-side power supply circuit, a fourth pin of the gate driver U5 is connected with a gate of the NMOS tube Q3, a fifth pin of the gate driver U5 is connected with another end of the resistor R7, a drain of the NMOS tube Q3 is connected with a negative electrode of the voltage stabilizing diode D46 and the high-voltage generation adjustment circuit respectively, a third pin of the inverter U8 is connected with a common end of the capacitor C25 and the resistor R21, another end of the resistor R21 is grounded, a fourth pin of the inverter U8 is connected with a sixth pin of the inverter U8, a fifth pin of the inverter U8 is externally connected with a power input end, a seventh pin of the inverter U8 is connected with a first pin of the gate driver U11 and one end of the resistor R35 through the voltage stabilizing diode D6 respectively, another end of the resistor R35 is connected with a third pin of the gate driver U11, a second pin of the gate driver U11 is connected with a gate of the NMOS tube Q5, a drain of the NMOS tube Q5 and a negative electrode of the voltage stabilizing diode D7 are both connected with another end of the power resistor R2, a source of the NMOS tube Q5 and a positive electrode of the voltage stabilizing diode D7 are commonly grounded, a common end of the resistor R110 and the resistor R111 is grounded, a common end of the capacitor C22 and the resistor R111 is taken as an output feeding point of the positive pulse signal.

[0018] Further preferably, the second driving sub-circuit comprises a plurality of inverters U52, a transformer T6, a gate driver U54, a gate driver U53, a resistor R120, a resistor R121, a resistor R124, a resistor R125, a resistor R126, a power resistor R22, a capacitor C127, a capacitor C128, a capacitor C129, an NMOS Q28, an NMOS Q29, a voltage stabilizing diode D44, a voltage stabilizing diode D8, and a resistor R123, a first pin of the plurality of inverters U52 is connected with the comparison adjusting circuit and one end of the capacitor C128 respectively, a second pin of the plurality of inverters U52 is connected with a first end of the transformer T6 through the capacitor C127, a second end of the transformer T6 is grounded, a third end of the transformer T6 is connected with a third pin of the gate driver U54, a fourth end of the transformer T6 is connected with a common end of the resistor R126 and the resistor R125, a first pin of the gate driver U54 is connected with the MOS high-side power supply circuit, a second pin of the gate driver U54, another end of the resistor R125, a source of the NMOS Q29, one end of the power resistor R22, and a common end of the resistor R123 are all connected with the MOS high-side power supply circuit, a fourth pin of the gate driver U54 is connected with a gate of the NMOS Q29, a fifth pin of the gate driver U54 is connected with another end of the resistor R126, a drain of the NMOS Q29 is connected with another end of the resistor R123 and the high-voltage generating adjusting circuit respectively, a third pin of the plurality of inverters U52 is connected with a common end of the capacitor C128 and the resistor R120, another end of the resistor R120 is grounded, a fourth pin of the plurality of inverters U52 is connected with a sixth pin of the plurality of inverters U52, a fifth pin of the plurality of inverters U52 is externally connected with a power input end, a seventh pin of the plurality of inverters U52 is connected with a first pin of the gate driver U53 and one end of the resistor R121 through the voltage stabilizing diode D44 respectively, another end of the resistor R121 is connected with a third pin of the gate driver U53, a second pin of the gate driver U53 is connected with a gate of the NMOS Q28, a drain of the NMOS Q28 and a negative electrode of the voltage stabilizing diode D8 are both connected with another end of the power resistor R22, a source of the NMOS Q28 and a positive electrode of the voltage stabilizing diode D8 are commonly grounded, one end of the resistor R124 is grounded, and a common end of the capacitor C129 and the resistor R124 is an output feeding point of the negative pulse signal.

[0019] The second aspect of the application provides a large-depth ground penetrating radar device, comprising a main shell, a plurality of groups of segmented antenna rods arranged on opposite sides of the main shell, and a high-voltage pulse source generator with controllable amplitude and frequency arranged in the main shell.

[0020] Further preferably, the segmented antenna rod comprises a plurality of hollow cylindrical antennas with a diameter of 5-20 mm, any two adjacent hollow cylindrical antennas are threadedly connected, and a long strip-shaped PCB is arranged in the hollow cylindrical antenna, and a patch diode, a resistor and a capacitor are arranged on the long strip-shaped PCB, and the diode is used to select the center frequency of the antenna.

[0021] The high-voltage pulse source generator with controllable amplitude and frequency and the large-depth ground penetrating radar device provided by the application have the following beneficial effects compared with the prior art:

[0022] Through the edge trigger signal circuit and the pulse generation adjustment circuit, the external synchronous trigger signal is captured and the positive and negative pulse signals with electrically adjustable pulse width are generated, so that the pulse signals can be accurately controlled in timing and width, and the relative delay of the positive and negative pulse signals is adjusted in the comparison adjustment circuit according to the reference voltage, so that the positive and negative pulse signals have accurate relative delay, thereby improving the overall accuracy and consistency of the pulse signals, the high-voltage generation adjustment circuit can output adjustable DC high voltage to provide flexible voltage adjustment capability for the generation of high-voltage pulses, so that the high-voltage pulse source generator can adapt to different detection depths and target characteristics, and the applicability and detection precision of the high-voltage pulse source generator are improved.

[0023] The use of multiple inverters and special gate drivers cooperates to accurately drive the NMOS tube, thereby ensuring the steepness of the high-voltage pulse edge and the stability of the pulse width and amplitude, improving the overall pulse output accuracy, and through the reasonable configuration of transformers, capacitors, resistors and other elements, effective isolation between signals and power supply is realized, the influence of external interference on the driving circuit is reduced, and the parameters of each part of the circuit are matched, the driving performance is improved, the series and parallel design of each device in the circuit makes the delay and response of the driving signal consistent, thereby realizing stable feeding of the positive pulse output signal and meeting the needs of high-speed switching and double-sided driving, with the help of MOS high-side power supply circuit and stabilizing diode and other elements, the circuit provides stable bias and DC voltage, not only ensuring the consistency of the output pulse, but also improving the anti-interference ability of the circuit to power fluctuations and electromagnetic interference. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only show some embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0025] Figure 1 A frame schematic diagram of a high-voltage pulse source generator with controllable amplitude and frequency provided by the present application;

[0026] Figure 2 A circuit diagram of an edge trigger signal circuit provided by the present application;

[0027] Figure 3 A circuit diagram of a pulse generation adjustment circuit provided by the present application;

[0028] Figure 4 A circuit diagram of a comparison adjustment circuit provided by the present application;

[0029] Figure 5 A circuit diagram of a high-voltage generation adjustment circuit provided by the present application;

[0030] Figure 6 A circuit diagram of a high-voltage MOS drive circuit provided by the present application;

[0031] Figure 7 A circuit diagram of a MOS tube high-side power supply circuit provided by the present application;

[0032] Figure 8 A principle schematic diagram of an antenna radiation pulse provided by the present application;

[0033] Figure 9 A structure schematic diagram of a large-depth ground penetrating radar device provided by the present application;

[0034] Figure 10 A structure schematic diagram of a hollow cylindrical antenna provided by the present application;

[0035] Figure 11 A structure schematic diagram of a host base provided by the present application;

[0036] Figure 12 An explosion schematic diagram of a handrail support provided by the present application.

[0037] Explanation of reference signs: 1, edge trigger signal circuit; 2, pulse generation adjustment circuit; 3, comparison adjustment circuit; 4, MCU control circuit; 5, high voltage generation adjustment circuit; 6, high voltage MOS drive circuit; 7, MOS tube high side power supply circuit; 8, wireless communication circuit; 9, main machine shell; 10, segmented antenna rod; 101, outer threaded copper piece; 102, male plug; 103, nut; 104, FPC flexible plate; 105, female plug; 106, inner threaded copper piece; 107, protective antenna shell; 11, main machine base; 111, antenna connecting piece; 112, nut; 113, main machine bottom cover plate; 114, rubber pad; 115, bullseye ball; 116, main machine base shell; 117, contact copper piece; 12, fixing block; 13, handrail support; 131, hand-held rod; 131a, locking connection male head; 132, ring screw; 133, vertical rod; 133a, locking connection female head; 134, cam screw; 135, stabilizing block; 136, screw; 137, bolt. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0039] Unless otherwise defined, the technical terms or scientific terms used in the present application should be understood as the usual meanings understood by those skilled in the art to which the present application belongs. The terms "first", "second", and similar terms used in the present application do not represent any order, number, or importance, but are only used to distinguish different components. Similarly, the terms "one" or "a" and similar terms do not represent a quantity limitation, but represent the existence of at least one. The terms "connected" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "up", "down", "left", "right", and the like are only used to represent relative positional relationships, and when the absolute position of the described object changes, the relative positional relationship also changes accordingly.

[0040] Reference Figure 1 The present application provides a high voltage pulse source generator with controllable amplitude and frequency, comprising an edge trigger signal circuit 1, a pulse generation adjustment circuit 2, a comparison adjustment circuit 3, an MCU control circuit 4, a high voltage generation adjustment circuit 5, a high voltage MOS drive circuit 6, a MOS tube high side power supply circuit 7, and a wireless communication circuit 8, wherein,

[0041] The edge trigger signal circuit 1 is connected with the pulse generation adjustment circuit 2, as shown in the figure. Figure 2 The edge trigger signal circuit 1 includes a fiber receiver U3, a capacitor C16, a capacitor C20, a capacitor C23, a comparator U52.1, a resistor R4, a resistor R8 and a resistor R23. The first end of the fiber receiver U3 is connected with one end of the capacitor C23. The other end of the capacitor C23 and the reverse input end of the comparator U52.1 are both connected with one end of the resistor R23. The second end of the fiber receiver U3 is grounded. The third end of the fiber receiver U3 is externally connected with a voltage input end. The fourth end of the fiber receiver U3 is connected with the capacitor C16. The other end of the capacitor C16 and the positive input end of the comparator U52.1 are both connected with one end of the resistor R4. The other end of the resistor R4 is respectively connected with the output end of the comparator U52.1 and one end of the resistor R8. The common end of the resistor R8 and the resistor R23 is respectively connected with one end of the capacitor C20 and the pulse generation adjustment circuit 2. The other end of the capacitor C20 is grounded.

[0042] Further, the edge trigger signal circuit 1 includes a fiber receiver and a high-speed comparator. The high-speed fiber receiver can be used with a 650nm plastic optical fiber to realize a high-performance optical fiber communication link and is used for receiving the synchronization trigger signal sent by the upper computer. The receiver internally has a pulse width calibration circuit which can ensure that the pulse width distortion is within 4ns. Meanwhile, the high-speed comparator U52.1 is designed as a hysteresis comparison circuit which has strong anti-interference ability. After the fiber receiver output signal is processed by the comparison circuit, a stable and reliable synchronization trigger signal is obtained.

[0043] The pulse generation adjustment circuit 2 is connected with the comparison adjustment circuit 3 and the MCU control circuit 4 respectively. The pulse generation adjustment circuit 2 is used for receiving the external synchronization trigger edge signal sent by the edge trigger signal circuit 1 and generating a positive and negative pulse signal with an electrically adjustable pulse width.

[0044] Further, the pulse generation adjustment circuit 2 includes a multivibrator U60, a digital potentiometer U61, an oscillation resistor R130, an oscillation capacitor C132 and a resistor R131. The first pin of the multivibrator U60 is grounded. The external synchronization trigger edge signal is input by the second pin of the multivibrator U60. The third pin of the multivibrator U60 is connected with one end of the resistor R131. The fourth pin of the multivibrator U60 is connected with the other end of the resistor R131 which is commonly grounded. The fifth pin of the multivibrator U60 is externally connected with a voltage input end. The sixth pin of the multivibrator U60 is connected with the common end of the oscillation resistor R130 and the oscillation capacitor C132. The seventh pin of the multivibrator U60 is connected with the other end of the oscillation capacitor C132. The other end of the oscillation resistor R130 is connected with the digital potentiometer U61.

[0045] In the embodiment, the multi-vibrator U60 receives the synchronous trigger signal, and outputs a pulse signal with a controllable pulse width. The pulse width Tw=1*(R130+Rw)*C132, where Rw is the resistance between the center tap of the digital potentiometer U61 and B, and the MCU controller drives the digital potentiometer U61 to adjust the resistance Rw through the SPI interface, so as to adjust the output pulse width. The minimum pulse width is Tw=R130*C132, and the adjustment accuracy depends on the minimum resolution of the digital potentiometer.

[0046] As shown in Figure 3 , the pulse generation adjustment circuit 2 includes a multi-vibrator U60, a digital potentiometer U61, an oscillation resistor R130, and an oscillation capacitor C132. The processed external synchronous trigger edge signal is directly connected to the input B channel of the second pin of the multi-vibrator U60, the first pin A channel of the multi-vibrator U60 is directly connected to the ground electrode, one end of the oscillation resistor R130 is connected to the center tap of the sixth pin of the digital potentiometer U61, the other end is connected to the oscillation capacitor C132 in series, and then connected to the fifteenth pin of U60. The other end of the capacitor C132 is connected to the fourteenth pin of U60; the seventh pin B tap of the digital potentiometer U61 is connected to VCC_5V, and the thirteenth pin Q of U60 is the pulse output pin after adjustment. The pulse width of the external synchronous trigger edge signal ranges from 100ns to 4us, and the amplitude ranges from 2.5V to 5.5V. The resistance value of the oscillation resistor R130 ranges from 500Ω to 2kΩ, the capacitance value of the oscillation capacitor C132 ranges from 500pF to 2000pF, the resistance value of the digital potentiometer U61 ranges from 1kΩ to 10kΩ, the resolution ranges from 256 steps (8 bits) to 1024 steps (10 bits), and the pulse width of the thirteenth pin of the multi-vibrator U60 ranges from 100ns to 20us, with an amplitude of 5V.

[0047] The comparison adjustment circuit 3 is connected to the MCU control circuit 4 and the high-voltage MOS drive circuit 6, respectively. The comparison adjustment circuit 3 is used to adjust the positive and negative pulse signals output by the pulse generation adjustment circuit 2 according to the positive and negative pulse signals generated by the pulse generation adjustment circuit 2 and the reference voltage, so as to obtain positive and negative pulse signals with relative delay.

[0048] Further, the comparison adjustment circuit 3 includes a DAC output chip U59, a comparator U51.1, and a comparator U55.1. The first pin of the DAC output chip U59 is externally connected to a voltage input end, the second pin of the DAC output chip U59 is connected to the inverse input end of the comparator U51.1, the third pin of the DAC output chip U59 is connected to the inverse input end of the comparator U55.1, the positive input ends of the comparator U51.1 and the comparator U55.1 are connected to the pulse generation adjustment circuit 2, and the output ends of the comparator U51.1 and the comparator U55.1 are connected to the high-voltage MOS drive circuit.

[0049] As shown in Figure 4 The comparison adjustment circuit 3 includes a multi-channel DAC output chip U59, a comparator U51.1, and a comparator U55.1, wherein the 7th pin of the multi-channel DAC output chip U59 outputs the B channel connected to the 2nd pin of the comparator U51.1 as the reverse input end, the 6th pin of the multi-channel DAC output chip U59 outputs the A channel connected to the 2nd pin of the comparators U51.1 and U55.1 as the reverse input end, the 3rd pins of the comparators U51.1 and U55 are connected to the pulse signal generated by the pulse generation adjustment circuit 2 as the same direction input end, and the first pin is the output. The comparators U51.1 and U55 are completely the same type, or are two outputs of the same comparator, the output edges of the comparators U51.1 and U55 have a relative delay, the delay range is 0-100 ns, the pulse amplitude and pulse width are the same, the multi-channel DAC output chip U59 has a resolution of not less than 4096 (12 bits). The DAC output chip U59 is a four-channel DAC chip, the four-channel DAC chip is I2C interface driven, connected to the I2C interface of the single-chip microcomputer, the pulse signals are respectively connected to the same direction input end of U51 and U55, and the A channel and the B channel of the four-channel DAC output are respectively connected to the reverse input end of U51 and U55 as the reference end. The single-chip microcomputer can control the relative delay of the pulse outputs of U51 and U55 by adjusting the voltage difference of the A channel and the B channel of the DAC output.

[0050] The MCU control circuit 4 is connected with the high-voltage generation adjustment circuit 5 and the wireless communication circuit 8, the high-voltage generation adjustment circuit 5 outputs a direct current voltage with adjustable amplitude in response to the instruction of the MCU control circuit 4, and provides a direct current bias for the high-voltage MOS drive circuit.

[0051] In the embodiment, the MCU uses the HuaDa HC32L36 series low-power single-chip microcomputer, but is not limited thereto. The MCU needs to meet at least one UART interface for external wireless communication, at least one I2C interface for battery capacity monitoring, temperature monitoring, and DAC chip driving, at least one SPI interface for digital potentiometer chip driving, at least one ADC interface for high-voltage source output voltage monitoring, and at least ten IOs for electrically controlled enabling drive of various modules. Other models of MCUs that meet the above requirements can also realize the high-voltage pulse source generator in the scheme.

[0052] Further, the high-voltage generation adjustment circuit 5 includes resistors R74, R75, R78, R80, R83, R85, R86, R127, R128, R129, capacitors C97, C101, C104, C106, C130, a PWM controller U32, an NMOS tube U56, a filter inductor L10, a rectifier diode D19, a diode D22, and a high-frequency transformer T5, wherein

[0053] One end of the resistor R80 is grounded through the resistor R85, one end of the resistor R80 is connected with the MCU control circuit 4 through the resistor R86, one end of the resistor R80 is also connected with the resistor R83, the capacitor C106 and the common terminal of the PWM controller U32, the other common terminal of the resistor R83 and the capacitor C106 is connected with the first pin of the PWM controller U32, the third pin of the PWM controller U32 is connected with the common terminal of the resistor R83 and the capacitor C101, the fourth pin of the PWM controller U32 is connected with the common terminal of the resistor R75 and the capacitor C104, the common terminal of the capacitor C104 and the resistor R74 is grounded, the common terminal of the resistor R75 and the resistor R74 is connected with the source of the NMOS tube U56, the other end of the capacitor C104 is grounded through the resistor R78, the other end of the resistor R75 is connected with the fifth pin of the PWM controller U32, and the voltage input terminal is externally connected with the fifth pin of the PWM controller U32 and the common terminal of the filter inductor L10, the sixth pin of the PWM controller U32 is connected with the gate of the NMOS tube U56, the eighth pin of the PWM controller U32 is grounded, the drain of the NMOS tube U56 is connected with the anode of the diode D22 and the second terminal of the high-frequency transformer T5, the cathode of the diode D22 is connected with the first common terminal of the resistor R127 and the capacitor C130, the second common terminal of the resistor R127 and the capacitor C130 is connected with the other end of the filter inductor L10 and the first terminal of the high-frequency transformer T5, the third terminal of the high-frequency transformer T5 is connected with the anode of the rectifier diode D19, the cathode of the rectifier diode D19, one end of the capacitor C97 and the resistor R128 are connected with the other end of the resistor R80, the capacitor C97 is grounded with the fourth terminal of the high-frequency transformer T5, the common terminal of the resistor R128 and the resistor R129 is connected with the MCU control circuit 4, and the other end of the resistor R129 is grounded.

[0054] As shown in Figure 5 The high-voltage generating and regulating circuit 5 includes a PWM control circuit, a transformer rectifier circuit, an RCD peak absorption circuit, a current feedback circuit and a voltage feedback circuit, wherein,

[0055] The PWM control circuit comprises a PWM controller U32, a resistor R75, a capacitor C104, a resistor R78 and an N-channel MOS tube U56, wherein one side of the resistor R75 is connected with a reference voltage output from the 8th pin of the PWM controller U32, the other side of the resistor R75 is connected with one side of the capacitor C104 in series and then connected to the 4th pin of the PWM controller U32, the other side of the capacitor C104 is connected with the resistor R78 in series and then connected to the ground, the 6th pin of the PWM controller U32 is connected with the gate of the MOS tube U56 as a pwm output pin, the resistance value of the resistor R75 ranges from 1kΩ to 10kΩ, the capacitance value of the capacitor C104 ranges from 500pF to 2000pF. The resistor R75 and the capacitor C104 are connected in series to the 4th pin of the PWM controller U32 to form an RC oscillation circuit, the 6th pin of the PWM controller U32 outputs a pwm signal with an amplitude of 12V and is connected with the gate of the N-channel MOS tube U56, and the pwm output frequency fo=1.72 / (R75*C104).

[0056] The transformer rectification circuit comprises a high-frequency transformer T5, a filter inductor L10, a rectification diode D19 and a filter capacitor C97, wherein the same-name end of the primary side of the transformer T5 is connected to DC 12V through the filter inductor L10, the non-same-name end of the transformer T5 is connected with the drain of the MOS tube U56, the non-same-name end of the secondary side of the transformer T5 is connected with the anode of the rectification diode D19, the cathode of the rectification diode D19 is connected with one side of the filter capacitor C97 as a high-voltage output point, the other side of the filter capacitor C97 is connected with the same-name end of the secondary side of the transformer T5 to the ground electrode, the working frequency range of the high-frequency transformer T5 is 20kHz-300kHz, the primary / secondary turn ratio range of the high-frequency transformer T5 is 1:20-1:50, and the high-frequency transformer T5 uses a sandwich winding method.

[0057] The RCD peak absorption circuit comprises a diode D22, a capacitor C130 and a resistor R127, the anode of the diode D22 is connected with the primary non-same-name end of the transformer T5, the capacitor C130 and the resistor R127 are connected in parallel, one end of the capacitor C130 and the resistor R127 is connected with the primary same-name end of the transformer T5, and the other end of the capacitor C130 and the resistor R127 is connected with the cathode of the diode D22. The RC value depends on the switching frequency of the MOS tube. Since all the energy absorbed by the peak is consumed in the form of heat on the R127, the R127 package needs to consider factors such as heat dissipation and power when selected.

[0058] The current feedback circuit comprises a sampling resistor R74, a filter capacitor C101 and a filter resistor R83, one side of the sampling resistor is connected with the source of the MOS tube U56, and the sampling voltage signal is filtered through the low-pass filter composed of the R83 and the C101 and then connected to the 3rd pin of the PWM controller U32 as a current sampling pin.

[0059] The voltage feedback circuit comprises a resistor R80, a resistor R85, a resistor R86, a resistor R83 and a capacitor C106, one side of the resistor R80 is connected to the high voltage output VCC_HV after the transformer rectification circuit, the other side is connected to the resistor R85 and the resistor R86 and then connected to the voltage feedback pin of the second pin of the PWM controller U32, the other side of the resistor R85 is connected to the ground, the other side of the resistor R86 is connected to the adjustment voltage signal generated by the MCU control circuit 4, the resistor R80, the resistor R85 and the resistor R86 and the feedback network composed of the PWM controller U32 satisfy the relationship (Vhv-2.5V) / R80+(Vadj-2.5V) / R86=2.5V / R85, Vhv is the amplitude voltage of the high voltage output VCC_HV, the range is (0~5000V), Vadj is the voltage adjustment signal HV_ADJUST, the amplitude range is (0~5V), the resistor R83 and the capacitor C106 are connected to the first pin and the second pin of the PWM controller U32 in parallel, and are used as the feedback channel of the internal error amplifier of the PWM controller U32.

[0060] The voltage output by the transformer rectification is divided by the resistor R80 and the resistor R85 and then sent to the feedback pin of the second pin of the PWM controller U32, and the DAC output voltage of the single-chip microcomputer is also connected to the feedback point through the resistor R86, so that the single-chip microcomputer can adjust the DAC output voltage, the duty cycle of the PWM controller U32 output pwm is adjusted, and the output voltage VCC_HV is electrically controlled and adjusted, the adjustment range of VCC_HV is (0V-5000V), the feedback network composed of R80, R85 and R86 satisfies the Kirchhoff KCL law; R83 is the feedback resistor of the internal error amplifier of the PWM controller U32, which determines the internal feedback coefficient of the PWM controller U32 and finally affects the high voltage output precision.

[0061] The high-voltage MOS drive circuit 6 is connected with the high-voltage generation adjustment circuit 5 and the MOS high-side power supply circuit 7, and is used for adjusting the positive pulse signal and the negative pulse signal to generate two high-voltage pulse signals with the same pulse width and opposite polarities.

[0062] In the embodiment, the high-voltage MOS drive circuit comprises a first drive sub-circuit and a second drive sub-circuit, and the first drive sub-circuit and the second drive sub-circuit are connected with the comparison adjustment circuit 3, the high-voltage generation adjustment circuit 5 and the MOS high-side power supply circuit 7.

[0063] The first driving sub-circuit comprises a plurality of inverters U8, a transformer T4, a gate driver U5, a gate driver U11, resistors R7, R12, R21, R35, R110, R111, a power resistor R25, capacitors C22, C25, C28, NMOS tubes Q3, Q5, voltage stabilizing diodes D6, D7 and D46, the first pin of the inverter U8 is connected with the comparison adjustment circuit 3 and one end of the capacitor C25, the second pin of the inverter U8 is connected with the first end of the transformer T4 through the capacitor C28, the second end of the transformer T4 is grounded, the third end of the transformer T4 is connected with the third pin of the gate driver U5, the fourth end of the transformer T4 is connected with the common end of the resistor R7 and the resistor R12, the first pin of the gate driver U5 is connected with the MOS high-side power supply circuit 7, the second pin of the gate driver U5, the other end of the resistor R12, the source of the NMOS tube Q3, the positive electrode of the voltage stabilizing diode D46, one end of the power resistor R25 and the common end of the capacitor C22 and the resistor R110 are all connected with the MOS high-side power supply circuit 7, the fourth pin of the gate driver U5 is connected with the gate of the NMOS tube Q3, the fifth pin of the gate driver U5 is connected with the other end of the resistor R7, the drain of the NMOS tube Q3 is connected with the negative electrode of the voltage stabilizing diode D46 and the high-voltage generation adjustment circuit 5 respectively, the third pin of the inverter U8 is connected with the common end of the capacitor C25 and the resistor R21, the other end of the resistor R21 is grounded, the fourth pin of the inverter U8 is connected with the sixth pin of the inverter U8, the fifth pin of the inverter U8 is externally connected with a power input end, the seventh pin of the inverter U8 is connected with the first pin of the gate driver U11 and one end of the resistor R35 through the voltage stabilizing diode D6, the other end of the resistor R35 is connected with the third pin of the gate driver U11, the second pin of the gate driver U11 is connected with the gate of the NMOS tube Q5, the drain of the NMOS tube Q5 and the negative electrode of the voltage stabilizing diode D7 are both connected with the other end of the power resistor R2, the source of the NMOS tube Q5 and the positive electrode of the voltage stabilizing diode D7 are commonly grounded, the common end of the resistor R110 and the resistor R111 is grounded, and the common end of the capacitor C22 and the resistor R111 is used as an output feeding point of the positive pulse signal.

[0064] The second driving sub-circuit comprises a plurality of inverters U52, a transformer T6, a gate driver U54, a gate driver U53, resistors R120, R121, R124, R125, R126, a power resistor R22, capacitors C127, C128, C129, NMOS tubes Q28, Q29, voltage stabilizing diodes D44, D8 and a resistor R123. The first pin of the inverter U52 is connected to the comparison adjustment circuit 3 and one end of the capacitor C128, respectively. The second pin of the inverter U52 is connected to the first end of the transformer T6 through the capacitor C127. The second end of the transformer T6 is grounded. The third end of the transformer T6 is connected to the third pin of the gate driver U54. The fourth end of the transformer T6 is connected to the common end of the resistors R126 and R125. The first pin of the gate driver U54 is connected to the MOS high-side power supply circuit 7. The second pin of the gate driver U54, the other end of the resistor R125, the source of the NMOS tube Q29, one end of the power resistor R22 and the common end of the resistor R123 are all connected to the MOS high-side power supply circuit 7. The fourth pin of the gate driver U54 is connected to the gate of the NMOS tube Q29. The fifth pin of the gate driver U54 is connected to the other end of the resistor R126. The drain of the NMOS tube Q29 is connected to the other end of the resistor R123 and the high-voltage generation adjustment circuit 5, respectively. The third pin of the inverter U52 is connected to the common end of the capacitor C128 and the resistor R120. The other end of the resistor R120 is grounded. The fourth pin of the inverter U52 is connected to the sixth pin of the inverter U52. The fifth pin of the inverter U52 is externally connected to the power input end. The seventh pin of the inverter U52 is connected to the first pin of the gate driver U53 and one end of the resistor R121 through the voltage stabilizing diode D44, respectively. The other end of the resistor R121 is connected to the third pin of the gate driver U53. The second pin of the gate driver U53 is connected to the gate of the NMOS tube Q28. The drain of the NMOS tube Q28 and the negative electrode of the voltage stabilizing diode D8 are both connected to the other end of the power resistor R22. The source of the NMOS tube Q28 and the positive electrode of the voltage stabilizing diode D8 are commonly grounded. One end of the resistor R124 is grounded. The common end of the capacitor C129 and the resistor R124 serves as the output feeding point of the negative pulse signal.

[0065] Please refer to Figure 6 Taking the first driving circuit as an example, the first driving circuit comprises a pulse signal inversion processing circuit, a high-side MOS tube driving circuit, a low-side MOS tube driving circuit and an output coupling circuit, wherein,

[0066] The pulse signal inverting processing circuit includes a multiplexer U8, a resistor R21 and a capacitor C25. The first channel input end of the first pin of the multiplexer U8 is connected to the first pulse input signal generated by the comparison adjusting circuit 3. The second pin of the multiplexer U8 is connected to the high-side drive signal coupling capacitor C28. One side of the capacitor C25 is connected to the first pin of the multiplexer U8, and the other side is connected to the fifth pin of the multiplexer U8 in series with the resistor R21, and the other side of the resistor R21 is grounded. The other channels of U8 are connected in a cascading manner, i.e., the sixth pin is connected to the thirteenth pin, the twelfth pin is connected to the eleventh pin, the tenth pin is connected to the ninth pin, and the eighth pin is the output after four cascades. The values of the capacitor C25 and the resistor R21 satisfy the time constant 100ns<(τ=C25*R21)<3us. The capacitor C25 and the capacitor C128 are of the same type and model. The resistor R21 and the resistor R120 are of the same type and model. The multiplexer U8 and the multiplexer U52 are of the same type and model.

[0067] The high-side MOS tube drive circuit includes a coupling capacitor C28, an isolation transformer T4, a gate driver U5, a resistor R7, a resistor R12 and an N-channel high-voltage MOS tube Q3. One side of the coupling capacitor C28 is connected to the first channel output of the second pin of the multiplexer U8, and the other side is connected to the non-identical end of the primary side of the isolation transformer T4. The same end of the primary side of the isolation transformer T4 is connected to the ground. The same end of the secondary side is connected to the third pin input of the gate driver U5. The fifth pin output of the gate driver U5 is connected to the non-identical end of the secondary side of the isolation transformer T4 after being divided by the resistors R7 and R12 in series. The fourth pin output of the gate driver U5 is connected to the gate of Q3. The first pin power supply positive end and the second pin power supply ground end of the gate driver U5 are connected to the isolation output power supply generated by the MOS tube high-side power supply circuit 7. The drain of Q3 is connected to the output voltage VCC_HV of the high-voltage generating adjusting circuit 5. The source is connected to the isolation output power supply ground end P1_H_GATE_VCOM generated by the MOS tube high-side power supply circuit 7. The working frequency range of the isolation transformer T4 is 0-500kHz. The primary / secondary turns ratio is 1:6. The inductance range of the primary side is 5uH-30uH. The capacitance value of the coupling capacitor C28 is 1nF-100nF. The values of the resistors R7 and R12 are the same. The isolation transformer T4 and the isolation transformer T5 are of the same type and model. The resistors R7, R12, R126 and R125 are of the same type and model.

[0068] The low-side MOS tube driving circuit includes a zener diode D6, a gate driver U11, a bias resistor R35, an N-channel MOS tube Q5, and a power resistor R25. The anode of the zener diode D6 is connected to the 8th pin of the multiplexer U8, the cathode is connected to the 3rd pin input of the gate driver U11, the 5th pin of the gate driver U11 is connected to one side of R35, the other side of R35 is connected to the anode of D6, the 1st pin and the 2nd pin of the gate driver U11 are respectively connected to a 22V DC voltage and a ground electrode, the 4th pin of the gate driver U11 is connected to the gate of Q5, the drain of Q5 is connected to the source of Q3 through the power resistor R25, the source of Q5 is grounded, the power resistors R25 and R22 have the same model parameters, the resistance value is in the range of 500Ω-1500Ω, the zener diodes D6 and D44 have the same model parameters, the voltage stabilization range is 1.6V-6V, the MOS tubes Q3, Q5, Q29, and Q28 have the same model parameters, and the gate drivers U5, U11, U54, and U53 have the same model parameters.

[0069] The positive pulse output coupling circuit includes a capacitor C22, a resistor R110, and a resistor R111. The left side of the coupling capacitor C22 is connected to one side of the resistor R110 and the source of Q3, respectively. The right side of C22 is connected to one side of the resistor R111 as a pulse output feed point, and the other sides of R110 and R111 are directly grounded. The negative pulse output coupling circuit includes C129, R123, and R124. One side of the coupling capacitor C129 is connected to the source of Q29 and one side of R123, the other side of R123 is connected to a high-voltage bias voltage VCC_HV, the other side of the coupling capacitor C129 is connected to the resistor R124 as a negative pulse output feed point, and the other side of R124 is grounded. The coupling capacitors C22 and C129 have a value in the range of 100nF-1000nF, and the resistors R110, R111, R123, and R124 have the same value.

[0070] Taking the first drive circuit as an example, due to the totem-pole topology, the high and low MOSFETs need to be switched on and off alternately. The control pulse signal is the single-ended pulse signal generated by the comparator adjustment circuit 3 in section 5 above. Therefore, a multi-channel inverter is used here. After processing the single-ended pulse signal by the inverter, two pulse drive signals are obtained, which control the high and low MOSFETs to switch on and off respectively. Due to the Miller effect of the MOSFETs, the two pulse drive signals must have a certain dead time, which is determined by the time constants of R21 and C25. The function of the Zener diode D6 is because the amplitude of the inverter output signal is 5V. The minimum drive voltage of the gate driver is 6V. Here, a Zener diode is used to provide a DC voltage bias through resistor R35, so that the inverter output signal can directly drive the gate driver. This method can also improve the drive speed. Zener diode D6 is selected as (1.6V-6V). Similarly, R7 and R12 are divided and connected to isolation transformer T4 to provide a basic DC voltage bias for the output of gate driver U5. The power resistor R25 is present for two purposes: one is to limit current, and the other is to quickly release the energy stored in the junction capacitance of the MOS transistor during high-speed switching, reducing the trailing phenomenon of the falling edge of the output pulse.

[0071] For the second drive circuit, the main implementation method is to utilize the fact that the voltage across capacitor C129 cannot change abruptly. Under normal conditions, the left side of C129 is pulled up to the high-voltage bias voltage VCC_HV by resistor R123, and the right side is pulled down to the ground electrode by R125. When the lower transistor Q28 is turned on, the left side of C129 is pulled down to ground, and at this time the output of the right side of C129 is -VCC_HV.

[0072] like Figure 7 The high-side power supply circuit 7 for the MOSFET shown includes an oscillation circuit, a power amplifier circuit, and a transformer-isolated voltage multiplier circuit. The oscillation circuit comprises a high-speed operational amplifier U2 and external resistors forming a feedback and frequency selection circuit. The circuit output oscillation frequency f = 1 / (2*pi*R103*C54). The power amplifier circuit includes a dual-channel integrated power amplifier U34. R97 and R6 form the first feedback circuit, R98 and R50 form the second feedback circuit, and C111 and C112 are the operational amplifier output coupling capacitors. The transformer-isolated voltage multiplier circuit includes a first transformer T1 and a second transformer T2. The dual power amplifier outputs are connected to the primary winding terminals of transformers T1 and T2 respectively via coupling capacitors C119 and C114. Diodes D1 and D35, along with capacitor C121, form the first voltage multiplier circuit, which is connected to the secondary side of transformer T1 via coupling capacitor C120. Similarly, diodes D8 and D38, along with capacitor C123, form the second voltage multiplier rectifier circuit, which is connected to the secondary side of transformer T2 via coupling capacitor C115. The amplified oscillation signal is then isolated by the transformer and rectified by the voltage multiplier circuit to obtain a DC voltage output with twice the amplitude, used for the high-side drive power supply of the MOSFET.

[0073] In the embodiment, the wireless communication circuit 8 is a WIFI module connected with the MCU through a serial port to realize wireless-to-serial communication, but it is not limited thereto. The wireless communication circuit 8 can also be Bluetooth or other wireless implementation forms.

[0074] In one example, the high-voltage pulse source generator includes a wireless communication circuit 8 for realizing a communication interface with the host computer; an MCU control circuit 4 for parameter modulation of the high-voltage pulse source generator, cooperating with the wireless communication circuit 8 to communicate with the host computer to realize parameter setting, state monitoring and other function interactions; an edge trigger signal circuit 1 for receiving a trigger signal from the host end to realize synchronization of the transmitter and receiver working states; a pulse generation circuit for receiving the edge trigger signal to generate two-way trigger signals with adjustable pulse width; a comparison adjustment circuit 3 for adjusting the relative delay of the positive and negative pulse trigger signals; a high-voltage generation adjustment circuit 5 for adjusting the high-voltage source output with adjustable amplitude; a MOS high-side power supply for high-side gate driver isolation power input to ensure reliable driving of the high-side MOS tube; and a MOS drive circuit driven by the adjusted pulse signal to generate positive and negative high-voltage pulse output signals.

[0075] In the embodiment, the working process of the high-voltage pulse source generator is as follows:

[0076] Step one: The edge signal trigger circuit receives and processes the synchronization trigger signal sent by the host computer in the fiber link to obtain a stable and reliable trigger signal;

[0077] Step two: The pulse generation adjustment circuit 2 generates a pulse signal with controllable pulse width according to the trigger signal;

[0078] Step three: The comparison adjustment circuit 3 generates two-way pulse signals with relative delay according to the pulse signal in step two, as shown in the attached Figure 8 , the delay time is T2-T1, and the amplitude and pulse width are completely the same;

[0079] Step four: The high-voltage generation adjustment circuit 5 generates a controllable high-voltage output (output range 0V-5000V), and the MOS high-side power supply circuit 7 generates an isolated output DC voltage (output range 22V-28V).

[0080] Step five: The two-way pulse signals generated in step three are used as input pulse drive signals for the positive and negative pulse drive circuits;

[0081] Step six: The positive and negative pulse drive circuits obtain high and low side alternating control gate control signals after processing the input pulse drive signals through inverters, the high side gate control signal is input to the gate drive after isolation transformer to drive the high side MOS tube to open and close, and the low side gate control signal is directly output to the low side gate drive to control the low side MOS tube to open and close;

[0082] Step seven: MOS tube driving output signal, after coupling through coupling capacitor, using the coupling capacitor cannot mutate respectively generated with opposite delay positive and negative pulse signal, its delay time is T2-T1;

[0083] Step eight: the positive and negative pulse generated in step seven, after coupling through antenna, can obtain pulse output with adjustable pulse width amplitude, as shown in Figure 8 .

[0084] The high-voltage pulse source generator mainly uses a high-voltage MOS tube as a core driving unit, adopts a totem pole topology structure to realize high-speed opening and closing driving, and adopts a flyback circuit topology for a direct-current high-voltage source of pulse output. The output voltage is adjusted by electrically controlling the feedback loop voltage, and positive and negative high-voltage pulse outputs are generated by using the characteristic that the voltage across the capacitor cannot be suddenly changed. The overall implementation manner is to electrically control the high-voltage output and the pulse signal width by the MCU control circuit 4, so as to generate a high-voltage pulse signal with controllable amplitude and pulse width.

[0085] The edge trigger signal circuit 1 and the pulse generation and adjustment circuit 2 realize the capture of an external synchronous trigger signal and the generation of a positive and negative pulse signal with electrically adjustable pulse width, so that the pulse signal can be accurately controlled in timing and width. In the comparison and adjustment circuit 3, the positive and negative pulse signals are adjusted according to the reference voltage to ensure that the positive and negative pulse signals have accurate relative delay, thereby improving the overall precision and consistency of the pulse signal. The high-voltage generation and adjustment circuit 5 can output a direct-current high-voltage with adjustable amplitude to provide flexible voltage adjustment capability for the generation of the high-voltage pulse, so that the high-voltage pulse source generator can adapt to different detection depths and target characteristics, and improve the applicability and detection precision of the high-voltage pulse source generator. At the same time, the MOS driving circuit generates two high-voltage pulse signals with the same pulse width amplitude and opposite polarity by adjusting the positive and negative pulse signals, so as to ensure the symmetry and consistency of the signals, thereby improving the control precision of the high-voltage pulse source generator.

[0086] As shown in Figure 9 , based on the above-mentioned high-voltage pulse source generator with controllable amplitude and frequency, the embodiment of the application discloses a large-depth ground penetrating radar device, which comprises a host shell 9, a plurality of groups of segmented antenna rods 10 arranged on opposite sides of the host shell 9, and a high-voltage pulse source generator arranged in the host shell 9. The segmented antenna rod 10 comprises a plurality of hollow cylindrical antennas with a diameter of 5-20 mm, and any two adjacent hollow cylindrical antennas are threadedly connected. The hollow cylindrical antenna is internally provided with a long strip-shaped PCB, and the long strip-shaped PCB is provided with a patch diode, a resistor and a capacitor. The diode is used to select the center frequency of the antenna.

[0087] In one example, the large depth ground penetrating radar device includes a main machine shell 9, a segmented antenna rod 10, a main machine base 11, a fixed block 12, and a handrail support 13. The main machine base 11 is designed to be fixedly installed with antenna connectors 111 on both sides. The main machine base 11 is symmetrically designed with 4 connection positions for each of the 8 segmented antenna rods 10, wherein the longitudinal distance between the first antenna and the second antenna is 70mm, the longitudinal distance between the first antenna and the third antenna is 250mm, and the longitudinal distance between the first antenna and the fourth antenna is 320mm.

[0088] The main machine base 11 is fixedly installed with a contact copper piece 117 on the upper side, as shown in Figure 10 The segmented antenna rod 10 is externally provided with a protective antenna shell 107. The segmented antenna rod 10 is fixedly provided with a male plug piece 102 on one side. The male plug piece 102 is inserted into an external threaded copper piece 101. The external threaded copper piece 101 is fixedly installed with a nut 112. The segmented antenna rod 10 is fixedly provided with a female plug piece 105 on one side. The female plug piece 105 is inserted into an internal threaded copper piece 106. The internal threaded copper piece 106 is fixedly installed with a nut 112. The external threaded copper piece 101 and the internal threaded copper piece 106 are connected and fixed using an FPC flexible board 104. The segmented antenna rod 10 includes the external threaded copper piece 101, the male plug piece 102, the internal threaded copper piece 106, and the female plug piece 105. The segmented antenna rod 10 extends into the interior of the main machine base 11. The internal threaded copper piece 106 is threadedly connected inside the antenna connector 111. The segmented antenna rod 10 is connected with a segmented antenna rod 10a. The segmented antenna rod 10 is provided with a threaded hole inside the external threaded copper piece 101 of the male plug. The threaded hole is threadedly connected with the internal threaded copper piece 106 of the female plug. The antenna assembly is formed.

[0089] As shown in Figure 11 The main machine base 11 includes the antenna connector 111, the nut 112, the main machine bottom cover plate 113, the rubber pad 114, the bullseye ball 115, the main machine base 11 shell, and the contact copper piece 117. The main machine base 11 shell provides a basic connection structure for the entire main machine base 11. The left and right sides are connected by the antenna connector 111 and the nut 112, which are connected by 8 pairs of connectors in a symmetrical manner, and are used to connect and fix the antenna rod structure described below. The main machine bottom cover plate 113 and the rubber pad 114 are used to support the pressure connection with the main machine shell 9. The contact copper piece 117 is used for reliable connection of the feed point between the high-voltage pulse source circuit board output pulse signal and the antenna structure.

[0090] As shown in Figure 12As shown, the upper part of the handrail support 13 is a hand rod 131, the two ends of the hand rod 131 are fixedly installed with a locking male connector 131a, the lower part of the handrail support 13 is a vertical rod 133, the upper end of the vertical rod 133 is fixedly installed with a locking female connector 133a, the locking male connector 131a is connected with a ring screw 136 through a circular hole slot, the lower end of the vertical rod 133 is fixedly connected with a stabilizing block 135, the lower end of the stabilizing block 135 is provided with a circular hole slot for fixedly connecting with a bolt 137, and the stabilizing block 135 is fixedly installed with a cam screw 134. The bottom of the vertical rod 133 includes the stabilizing block 135, four through holes are formed in the side surface of the stabilizing block 135, the sectional antenna rod 10 is inserted, and the cam screw 134 is pressed downward to be locked and fixed. The handrail support 13 includes the locking male connector 131a, the locking male connector 131a is inserted into the locking female connector 133a to be fixed, the ring screw 136 is threadedly connected to be locked, the lower end of the vertical rod 133 is inserted into the opening at the upper end of the stabilizing block 135, and the side edge is locked and fixed by using the bolt 137.

[0091] The above only describes the preferred embodiments of the present application and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A high-voltage pulse source generator with controllable amplitude and frequency, characterized in that, It includes an edge-triggered signal circuit (1), a pulse generation and adjustment circuit (2), a comparison and adjustment circuit (3), an MCU control circuit (4), a high-voltage generation and adjustment circuit (5), a high-voltage MOS drive circuit (6), a MOS transistor high-side power supply circuit (7), and a wireless communication circuit (8), among which, The edge trigger signal circuit (1) is connected to the pulse generation and adjustment circuit (2); The pulse generation adjustment circuit (2) is connected to the comparison adjustment circuit (3) and the MCU control circuit (4) respectively. The pulse generation adjustment circuit (2) is used to receive the external synchronous trigger edge signal sent by the edge trigger signal circuit (1) and generate positive and negative pulse signals with adjustable pulse width. The comparison adjustment circuit (3) is connected to the MCU control circuit (4) and the high voltage MOS drive circuit (6) respectively. The comparison adjustment circuit (3) is used to adjust the relative delay of the positive and negative pulse signals output by the pulse generation adjustment circuit (2) according to the positive and negative pulse signals generated by the pulse generation adjustment circuit (2) and the reference voltage, so as to obtain positive and negative pulse signals with relative delay. The MCU control circuit (4) is connected to the high voltage generation and adjustment circuit (5) and the wireless communication circuit (8) respectively. The high voltage generation and adjustment circuit (5) responds to the command of the MCU control circuit (4), outputs an adjustable DC voltage, and provides DC bias for the high voltage MOS drive circuit (6). The high-voltage MOS driving circuit (6) is connected to the high-voltage generation and adjustment circuit (5) and the high-side power supply circuit (7) of the MOS tube respectively. The high-voltage MOS driving circuit (6) is used to adjust the positive pulse signal and the negative pulse signal to generate two high-voltage pulse signals with the same pulse width amplitude and opposite polarity.

2. The high-voltage pulse source generator with controllable amplitude and frequency as described in claim 1, characterized in that, The edge-triggered signal circuit (1) includes an optical fiber receiver U3, capacitors C16, C20, and C23, a comparator U52.1, resistors R4, R8, and R23. The first end of the optical fiber receiver U3 is connected to one end of the capacitor C23. The other end of the capacitor C23 and the inverting input of the comparator U52.1 are both connected to one end of the resistor R23. The second end of the optical fiber receiver U3 is grounded. The third end of the optical fiber receiver U3 is connected to an external voltage input. The fourth end of the optical fiber receiver U3 is connected to the capacitor C16. The other end of the capacitor C16 and the positive input of the comparator U52.1 are both connected to one end of the resistor R4. The other end of the resistor R4 is connected to the output of the comparator U52.1 and one end of the resistor R8. The common end of the resistor R8 and the resistor R23 is connected to one end of the capacitor C20 and the pulse generation and adjustment circuit (2). The other end of the capacitor C20 is grounded.

3. The high-voltage pulse source generator with controllable amplitude and frequency as described in claim 1, characterized in that, The pulse generation and adjustment circuit (2) includes a multivibrator U60, a digital potentiometer U61, an oscillation resistor R130, an oscillation capacitor C132, and a resistor R131. The first pin of the multivibrator U60 is grounded, the external synchronous trigger edge signal is input through the second pin of the multivibrator U60, the third pin of the multivibrator U60 is connected to one end of the resistor R131, the fourth pin of the multivibrator U60 is grounded together with the other end of the resistor R131, the fifth pin of the multivibrator U60 is connected to an external voltage input terminal, the sixth pin of the multivibrator U60 is connected to the common terminal of the oscillation resistor R130 and the oscillation capacitor C132, the seventh pin of the multivibrator U60 is connected to the other end of the oscillation capacitor C132, and the other end of the oscillation resistor R130 is connected to the digital potentiometer U61.

4. The high-voltage pulse source generator with controllable amplitude and frequency as described in claim 1, characterized in that, The comparison adjustment circuit (3) includes a DAC output chip U59, a comparator U51.1 and a comparator U55.

1. The first pin of the DAC output chip U59 is connected to an external voltage input terminal. The second pin of the DAC output chip U59 is connected to the inverting input terminal of the comparator U51.

1. The third pin of the DAC output chip U59 is connected to the inverting input terminal of the comparator U55.

1. The positive input terminals of the comparators U51.1 and U55.1 are both connected to the pulse generation adjustment circuit (2). The output terminals of the comparators U51.1 and U55.1 are both connected to the high-voltage MOS drive circuit (6).

5. The high-voltage pulse source generator with controllable amplitude and frequency as described in claim 1, characterized in that, The high-voltage generation and regulation circuit (5) includes resistors R74, R75, R78, R80, R83, R85, R86, R127, R128, and R129; capacitors C97, C101, C104, C106, and C130; a PWM controller U32; an NMOS transistor U56; a filter inductor L10; a rectifier diode D19; a diode D22; and a high-frequency transformer T5. One end of resistor R80 is grounded through resistor R85, and the other end of resistor R80 is connected to the MCU control circuit (4) through resistor R86. One end of resistor R80 is also connected to the common terminal of resistor R83, capacitor C106, and PWM controller U32. The other common terminal of resistor R83 and capacitor C106 is connected to the first pin of PWM controller U32. The third pin of PWM controller U32 is connected to the common terminal of resistor R83 and capacitor C101. The fourth pin of PWM controller U32 is connected to the common terminal of resistor R75 and capacitor C104. The common terminal of capacitor C104 and resistor R74 is grounded. The common terminal of resistor R75 and resistor R74 is connected to the source of NMOS transistor U56. The other end of capacitor C104 is grounded through resistor R78. The other end of resistor R75 and the fifth pin of PWM controller U32 are connected to the external voltage input terminal. The sixth pin of PWM controller U32 and the... The common terminal of the filter inductor L10 is connected to the external voltage input terminal. The seventh pin of the PWM controller U32 is connected to the gate of the NMOS transistor U56, and the eighth pin of the PWM controller U32 is grounded. The drain of the NMOS transistor U56 is connected to the anode of the diode D22 and the second terminal of the high-frequency transformer T5. The cathode of the diode D22 is connected to the first common terminal of the resistor R127 and the capacitor C130. The second common terminals of the resistor R127 and the capacitor C130 are connected to the filter inductor L10. The other end of inductor L10 is connected to the first end of high-frequency transformer T5. The third end of high-frequency transformer T5 is connected to the positive terminal of rectifier diode D19. The negative terminal of rectifier diode D19, one end of capacitor C97, and the other end of resistor R128 and resistor R80 are connected. Capacitor C97 and the fourth end of high-frequency transformer T5 are grounded together. The common terminal of resistor R128 and resistor R129 is connected to the MCU control circuit (4). The other end of resistor R129 is grounded.

6. The high-voltage pulse source generator with controllable amplitude and frequency as described in claim 1, characterized in that, The high-voltage MOS drive circuit (6) includes a first drive sub-circuit and a second drive sub-circuit, both of which are connected to the comparison adjustment circuit (3), the high-voltage generation adjustment circuit (5), and the high-side power supply circuit (7) of the MOS transistor.

7. A high-voltage pulse source generator with controllable amplitude and frequency as described in claim 6, characterized in that, The first driving sub-circuit includes a multiplexer U8, a transformer T4, a gate driver U5, a gate driver U11, resistors R7, R12, R21, R35, R110, R111, a power resistor R25, capacitors C22, C25, and C28, NMOS transistors Q3 and Q5, Zener diodes D6, D7, and D46. The first pin of the multiplexer U8 is connected to the comparator adjustment circuit (3) and one end of the capacitor C25, respectively. The second pin of the multiplexer U8 is connected to the first end of the transformer T4 through the capacitor C28. The transformer T4 is connected to ground at its second end, and its third end is connected to the third pin of the gate driver U5. The fourth end of the transformer T4 is connected to the common terminal of resistors R7 and R12. The first pin of the gate driver U5 is connected to the high-side power supply circuit (7) of the MOS transistor. The second pin of the gate driver U5, the other end of resistor R12, the source of the NMOS transistor Q3, the anode of the Zener diode D46, one end of the power resistor R25, and the common terminal of capacitor C22 and resistor R110 are all connected to the high-side power supply circuit (7) of the MOS transistor. The fourth pin of the gate driver U5 is connected to the gate of the NMOS transistor Q3. The fifth pin of the gate driver U5 is connected to the other end of the resistor R7. The drain of the NMOS transistor Q3 is connected to the negative terminal of the Zener diode D46 and the high voltage generation and adjustment circuit (5). The third pin of the multiplexer U8 is connected to the common terminal of the capacitor C25 and the resistor R21. The other end of the resistor R21 is grounded. The fourth pin of the multiplexer U8 is connected to the sixth pin of the multiplexer U8. The fifth pin of the multiplexer U8 is connected to the external power input terminal. The seventh pin of the multiplexer U8 is connected to the Zener diode. Transistor D6 is connected to the first pin of the gate driver U11 and one end of the resistor R35. The other end of the resistor R35 is connected to the third pin of the gate driver U11. The second pin of the gate driver U11 is connected to the gate of the NMOS transistor Q5. The drain of the NMOS transistor Q5 and the cathode of the Zener diode D7 are both connected to the other end of the power resistor R2. The source of the NMOS transistor Q5 and the anode of the Zener diode D7 are grounded together. The common terminal of the resistors R110 and R111 is grounded. The common terminal of the capacitor C22 and the resistor R111 serves as the output feed point for the positive pulse signal.

8. A high-voltage pulse source generator with controllable amplitude and frequency as described in claim 6, characterized in that, The second driving sub-circuit includes a multiplexer U52, a transformer T6, a gate driver U54, a gate driver U53, resistors R120, R121, R124, R125, and R126, a power resistor R22, capacitors C127, C128, and C129, NMOS transistors Q28 and Q29, Zener diodes D44 and D8, and resistor R123. The first pin of the multiplexer U52 is connected to the comparator adjustment circuit (3) and one end of the capacitor C128, respectively. The second pin of the multiplexer U52 is connected to the transformer T6 through the capacitor C127. The first end of the transformer T6 is connected to the ground, the second end of the transformer T6 is grounded, the third end of the transformer T6 is connected to the third pin of the gate driver U54, the fourth end of the transformer T6 is connected to the common terminal of the resistor R126 and the resistor R125, the first pin of the gate driver U54 is connected to the high-side power supply circuit (7) of the MOS transistor, the second pin of the gate driver U54, the other end of the resistor R125, the source of the NMOS transistor Q29, one end of the power resistor R22, and the common terminal of the capacitor C129 and the resistor R123 are all connected to the high-side power supply circuit (7) of the MOS transistor, and the gate driver U54 is connected to the high-side power supply circuit (7). The fourth pin of the circuit 4 is connected to the gate of the NMOS transistor Q29. The fifth pin of the gate driver U54 is connected to the other end of the resistor R126. The drain of the NMOS transistor Q29 is connected to the other end of the resistor R123 and the high voltage generation and adjustment circuit (5). The third pin of the multiplexer U52 is connected to the common terminal of the capacitor C128 and the resistor R120. The other end of the resistor R120 is grounded. The fourth pin of the multiplexer U52 is connected to the sixth pin of the multiplexer U52. The fifth pin of the multiplexer U52 is connected to the external power input terminal. The seventh pin of the multiplexer U52 is connected to the power input terminal. The Zener diode D44 is connected to the first pin of the gate driver U53 and one end of the resistor R121. The other end of the resistor R121 is connected to the third pin of the gate driver U53. The second pin of the gate driver U53 is connected to the gate of the NMOS transistor Q28. The drain of the NMOS transistor Q28 and the cathode of the Zener diode D8 are both connected to the other end of the power resistor R22. The source of the NMOS transistor Q28 and the anode of the Zener diode D8 are both grounded. One end of the resistor R124 is grounded. The common terminal of the capacitor C129 and the resistor R124 serves as the output feed point for the negative pulse signal.

9. A deep-penetrating ground-penetrating radar device, characterized in that, It includes a main housing (9), a multi-section antenna rod (10) disposed on opposite sides of the main housing (9), and a high-voltage pulse source generator with controllable amplitude and frequency as described in any one of claims 1 to 8 disposed within the main housing (9).

10. A deep-penetrating ground-penetrating radar device as described in claim 9, characterized in that, The segmented antenna rod (10) includes multiple hollow cylindrical antennas with diameters of 5~20mm. Any two adjacent hollow cylindrical antennas are threaded together. The hollow cylindrical antenna has a long strip PCB inside. The long strip PCB has a surface-mount diode, a resistor, and a capacitor. The diode is used to select the center frequency of the antenna.

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