Adjustable Schmidt input circuit, memory chip and memory

Abstract

The invention discloses an adjustable Schmidt input circuit, a memory chip and a memory, through a control signal processing module, a signal input module and a signal enhancement module, the number of feedback paths can be adjusted according to a control signal and an inversion signal thereof, and burr filtering of an input signal and dynamic adjustment of high and low level thresholds are realized. The anti-interference capability of the circuit in a ground bounce noise environment is effectively improved, and the phenomenon that ground bounce noise interferes high and low level judgment of input and output signals is avoided. Compared with the traditional scheme, the memory chip provided by the invention not only can adapt to different working scenes and enhance the reliability of the input signal, but also ensures that the output signal has enough driving capability through the signal enhancement module, thereby meeting the requirements of subsequent chip processing, and remarkably improving the stability and applicability of the memory chip.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly to an adjustable Schmitt input circuit, a memory chip, and a memory. Background Art

[0002] With the increasingly wide application scenarios of integrated circuits, integrated circuits are inevitably affected by various noises during operation, including thermal noise, power supply noise, and parasitic noise, etc. Among them, parasitic noise is particularly significant in the application of memory chips and becomes one of the main difficulties in designing input and output parameters (such as input high-level threshold and input low-level threshold) of memory chips.

[0003] When a memory chip performs a read operation and outputs a signal externally, the memory chip usually adopts a multi-port parallel output mode. The simultaneous change of the output voltage of multi-port signals will generate a large output current. After this current passes through the parasitic resistors and inductors in the package and the PCB (Printed Circuit Board), it will cause the ground level inside the chip to change relative to the low level of the circuit board, thereby generating a voltage interference called ground bounce noise. The existence of this ground bounce noise may last for a certain period of time, seriously affecting the stability and reliability of the input and output signals of the memory chip.

[0004] In practical applications, when a memory chip performs a read operation or a write operation, the ground bounce noise will interfere with the judgment of the high and low levels of the input and output signals, and may cause situations such as incorrect signal recognition or misoperation. Summary of the Invention

[0005] The main objective of the present invention is to provide an adjustable Schmitt input circuit, a memory chip, and a memory, aiming to at least solve the technical problem that when a memory chip performs a read operation or a write operation, the ground bounce noise will interfere with the judgment of the high and low levels of the input and output signals in related technologies.

[0006] In the first aspect of the present invention, an adjustable Schmitt input circuit is provided, which includes a control signal processing module, a signal input module, and a signal enhancement module connected in sequence; the control signal processing module is used to receive a control signal and generate a corresponding inverted signal based on the control signal; the signal input module is used to receive an input signal, the control signal, and the inverted signal, and conduct a target number of feedback paths according to the inverted signal and the control signal; wherein, the feedback path is used to perform corresponding filtering processing on the input signal and output a first output signal; the signal enhancement module is used to perform signal enhancement processing on the first output signal and output a second output signal.

[0007] In a second aspect of the present invention, there is provided a memory chip, comprising a chip body and the adjustable Schmitt input circuit as described in the first aspect, and the adjustable Schmitt input circuit is integrated in the chip body.

[0008] In a third aspect of the present invention, there is provided a memory, comprising a memory body and the memory chip as described in the second aspect, and the memory chip is disposed in the memory body.

[0009] The adjustable Schmitt input circuit, memory chip and memory of the present invention can, through the control signal processing module, signal input module and signal enhancement module, adjust the number of feedback paths according to the control signal and its inverted signal, realize the glitch filtering of the input signal and the dynamic adjustment of the high and low level thresholds, effectively improve the anti-interference ability of the circuit in the ground bounce noise environment, and avoid the interference phenomenon that the ground bounce noise causes to the high and low level judgment of the input and output signals. Compared with the traditional scheme, the present invention can not only adapt to different working scenarios, enhance the reliability of the input signal, but also ensure that the output signal has sufficient driving ability through the signal enhancement module, so as to meet the requirements of subsequent chip processing, and significantly improve the stability and applicability of the memory chip. Description of the Drawings

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0011] Figure 1 It is a functional block diagram of the adjustable Schmitt input circuit provided by the embodiment of the present application;

[0012] Figure 2 It is a circuit connection diagram of the first inverting circuit in the embodiment of the present application;

[0013] Figure 3 It is a circuit connection diagram of the second inverting circuit in the embodiment of the present application;

[0014] Figure 4 It is a circuit connection diagram of the input signal processing module in the embodiment of the present application;

[0015] Figure 5 It is a circuit connection diagram of the signal enhancement module in the embodiment of the present application;

[0016] Figure 6 It is an overall circuit connection diagram of the adjustable Schmitt input circuit provided by the embodiment of the present application;

[0017] Figure 7 This is a comparison diagram of the output signal corresponding waveforms of the adjustable Schmitt input circuit provided by the embodiments of the present application and the input circuits of related technologies.

[0018] The realization, functional characteristics, and advantages of the present invention will be further described in conjunction with the embodiments with reference to the accompanying drawings. Specific embodiments

[0019] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0020] It should be noted that related terms such as "first", "second", etc. can be used to describe various components, but these terms do not limit the components. These terms are only used to distinguish one component from another. For example, without departing from the scope of the present invention, the first component can be called the second component, and the second component can similarly be called the first component. The term "and / or" refers to any combination of one or more of the related items and the described items.

[0021] In related technologies, the commonly adopted technical solutions usually reduce the driving ability of the input-output module to reduce the output current and thus reduce the influence of ground bounce noise. However, these technical solutions are not applicable in application scenarios that require large driving ability.

[0022] Therefore, in order to more effectively solve the technical problems such as ground bounce noise interfering with the high and low level judgment of input-output signals when a memory chip performs read or write operations in related technologies. Please refer to Figure 1 , the embodiments of the present application provide an adjustable Schmitt input circuit.

[0023] The adjustable Schmitt input circuit includes a control signal processing module 10, a signal input module 20, and a signal enhancement module 30 connected in sequence.

[0024] The control signal processing module 10 can be components such as an inverter, a logic circuit, etc., receive control signals (S0, S1), and perform inversion processing to generate inverted signals (S0N, S1N) corresponding to the control signals.

[0025] Specifically, the control signal generally refers to the original control signal provided externally to the circuit, which is used to specify the working state or feedback path of the circuit. For example, S0 may indicate turning on a certain set of feedback paths, while S1 may be used to control the conduction state of another set of paths. The inverted signal is the inverted signal generated by the control signal processing module 10. S0N is the logical inversion of S0, and S1N is the logical inversion of S1. If S0 is at a high level (logic 1), then S0N is at a low level (logic 0); similarly, if S1 is at a low level, then S1N is at a high level. The inverted signal provides more control logic options for the subsequent signal input module 20, enabling the feedback paths to achieve different combinations of conduction states based on the positive or inverted signals.

[0026] The signal input module 20 is the core signal processing unit in the embodiment of the present application. It is responsible for receiving various input signals (including the input signal DATA, control signal, and inverted signal), and selectively conducting a target number of feedback paths according to the logical states of the control signal and the inverted signal, thereby dynamically filtering the glitches or noise that may be doped in the input signal through the feedback paths and generating the first output signal DATA1.

[0027] It should be noted that the signal input module dynamically controls the conduction or closing of multiple feedback paths according to the combination of the control signal and the inverted signal. For example, conducting more feedback paths may enhance the low-frequency part of the signal, while closing some paths may improve the response to high-frequency signals. Generally, the larger the target number of the feedback paths selected by the signal input module 20, the stronger the corresponding glitch filtering processing ability or the stronger the input high and low level conversion value adjustment ability.

[0028] Among them, the feedback path is the key processing path in the signal input module 20. It is generally composed of components such as transistors and is used to perform specific filtering or adjustment on the input signal DATA to obtain the first output signal DATA1. It can be seen that the feedback path has a glitch filtering function. (Glitches are fast and short noise pulses in the input signal that may cause logical mis-triggering.) The feedback path can effectively suppress glitches and improve signal stability through the low-pass filtering function. And it has a level threshold adjustment function. By dynamically selecting the feedback path, the signal input module can adjust the high and low level thresholds (input high level threshold and input low level threshold) for the input signal DATA to adapt to different working environments (such as an environment with large ground bounce noise), that is, to ensure that the input high level threshold and input low level threshold can meet the index requirements specified in the chip manual in the ground bounce noise environment.

[0029] The signal enhancement module 30 can be a circuit composed of at least one inverting device, which can perform signal enhancement processing on the first output signal DATA1. Based on the fact that the first output signal DATA1 has undergone glitch filtering and level threshold adjustment, through further signal enhancement processing, a second output signal DATA_IN with a higher amplitude and stronger driving ability can be output, ensuring that the processed data signal has sufficient strength to be transmitted to the inside of the chip.

[0030] The adjustable Schmitt input circuit of the present invention can adjust the number of feedback paths according to the control signal and its inverted signal through the control signal processing module, the signal input module and the signal enhancement module, realizing glitch filtering of the input signal and dynamic adjustment of the high and low level thresholds, effectively improving the anti-interference ability of the circuit in the ground bounce noise environment. Compared with the traditional scheme, the present invention can not only adapt to different working scenarios and enhance the reliability of the input signal, but also ensure that the output signal has sufficient driving ability through the signal enhancement module, so as to meet the requirements of subsequent chip processing, significantly improving the stability and applicability of the memory chip.

[0031] In an alternative embodiment of this embodiment, the control signal includes a first control signal S0 and a second control signal S1, the inverted signals include a first inverted signal S0N and a second inverted signal S1N, and the control signal processing module includes a first inverting circuit (as Figure 2 shown) and a second inverting circuit (as Figure 3 shown).

[0032] Specifically, the first inverting circuit is used to invert the received first control signal S0 and output the corresponding first inverted signal S0N, the second inverting circuit is used to invert the received second control signal S1 and output the corresponding second inverted signal S1N, and the signal input module 20 is used to conduct the target number of feedback paths corresponding to the level combination according to the level combinations of the first inverted signal S0, the second inverted signal S1, the first control signal S0N and the second control signal S1N.

[0033] This embodiment mainly introduces multiple control signals (such as S0, S1, etc.), and the change of each signal can affect specific circuit behaviors or feedback paths. For example, the inverter circuits controlled by S0 and S1 generate different inverted signals (S0N, S1N), and these signals control the signal input module to turn on different numbers of feedback paths. This means that the control circuit can dynamically select and adjust the number of feedback paths according to different requirements, allowing for more precise adjustment of the processing method of the input signal. Moreover, through multiple control signals, the corresponding level combinations are increased, enabling more refined and targeted adjustment of the number of feedback paths, effectively filtering out noise or interference in different frequency bands. For example, some feedback paths may be mainly used to remove high-frequency noise, while other paths are used to enhance the stability of the signal.

[0034] Please refer to Figure 2 and Figure 3 , the first inverter circuit includes a first PMOS transistor PM12 and a first NMOS transistor NM12. The gates of the first PMOS transistor PM12 and the first NMOS transistor NM12 are both used to receive the first control signal S0. The source of the first PMOS transistor PM12 is used to receive the power supply voltage, the source of the first NMOS transistor NM12 is grounded, and the drains of the first PMOS transistor PM12 and the first NMOS transistor NM12 are both used to output the first inverted signal S0N. And, the second inverter circuit includes a second PMOS transistor PM13 and a second NMOS transistor NM13. The gates of the second PMOS transistor PM13 and the second NMOS transistor NM13 are both used to receive the second control signal S1. The source of the second PMOS transistor PM13 is used to receive the power supply voltage, the source of the second NMOS transistor NM13 is grounded, and the drains of the second PMOS transistor PM13 and the second NMOS transistor NM13 are both used to output the second inverted signal S1N.

[0035] Specifically, when the control signal is at a high level, the NMOS transistor is turned on and outputs a low level; when the control signal is at a low level, the PMOS transistor is turned on and outputs a high level. Through this reverse process, the two inverter circuits can output the first control signal S0, the second control signal S1, the first inverted signal S0N, and the second inverted signal S1N to the subsequent signal input module 20 in total. Based on these control signals, more control strategies are provided, and thus a more refined and higher target number matching feedback path is determined, so as to achieve glitch filtering of the input signal and dynamic adjustment of the high and low level thresholds, effectively improving the anti-interference ability of the circuit in the ground bounce noise environment and adapting to more working scenarios.

[0036] In an alternative embodiment of this embodiment, the input signal processing module includes a two-stage Schmitt trigger having a main signal path, a first-stage feedback path, and a second-stage feedback path.

[0037] In this two-stage Schmitt trigger, it mainly receives a first inverted signal S0N, a second inverted signal S1N, a first control signal S0, and a second control signal S1, and conducts the first-stage feedback path and / or the second-stage feedback path based on the corresponding level combination. The first-stage feedback path is used to perform first-stage feedback processing on the output signal and transmit it back to the main signal path, and the second-stage feedback path is used to perform second-stage feedback processing on the output signal and transmit it back to the main signal path.

[0038] Specifically, when the feedback path conducted by the two-stage Schmitt trigger is the first-stage feedback path or the second-stage feedback path (belonging to the conduction of the first-stage feedback path), the Schmitt trigger is in the first-stage filtering state at this time, and the corresponding first filtering ability is greater than the preset initial filtering setting range. When the feedback path conducted by the two-stage Schmitt trigger is the first-stage feedback path and the second-stage feedback path (belonging to the conduction of the second-stage feedback path), the Schmitt trigger is in the second-stage filtering state at this time, and the second filtering range of the two-stage Schmitt trigger for the input signal is greater than the first filtering range. That is, the two-stage Schmitt trigger can dynamically adjust the filtering ability of the input signal by dynamically selecting the first-stage feedback path and the second-stage feedback path, so that the Schmitt trigger can adapt to different working environments, especially in applications with poor noise environments or higher stability requirements, providing a more accurate and stable output.

[0039] It should be noted that when the feedback path in the two-stage Schmitt trigger is not conducted, it is in the primary filtering state (the filtering range is the initial filtering setting range). At this time, there is a minimum input high-level threshold and a maximum input low-level threshold and the two values are equal (i.e., VIH = VIL), and it has a small glitch filtering ability, that is, it can only filter glitches smaller than the high-low level conversion voltage. And when the two-stage Schmitt trigger is in the first-stage filtering state, there is a larger input high-level threshold and a smaller input low-level threshold and the two values are not equal (i.e., ΔV1 = VIH - VIL > 0), and it has a medium glitch filtering ability. And when the two-stage Schmitt trigger is in the second-stage filtering state, there is a maximum input high-level threshold and a minimum input low-level threshold and the two values are not equal (i.e., ΔV2 = VIH - VIL > ΔV1 > 0), and it has the strongest glitch filtering ability at the same time.

[0040] In addition, the range of the high-low level conversion voltage represents the range between the input high-level threshold and the input low-level threshold. The level change of the input signal needs to cross this range to trigger an output change. To further illustrate that the two-stage Schmitt trigger has an adjustable range of high-low level conversion voltages. Please refer to Table 1 below:

[0041] Table 1

[0042]

[0043] In Table 1, the filtering capabilities of the ordinary input unit and the ordinary Schmidt input unit in the related art are relatively weak. However, the adjustable Schmidt input circuit according to the embodiments of the present application has different gears (in different filtering states and with different filtering ranges), has a larger hysteresis window, can realize the filtering of glitches in the input signal and the dynamic adjustment of the high and low level thresholds, can provide a stronger glitch filtering ability, effectively improves the anti-interference ability of the circuit in the ground bounce noise environment, and can adapt to different working scenarios.

[0044] Please refer to Figure 4 , in the two-stage Schmidt trigger, the first-stage feedback path is provided with a first feedback PMOS transistor PM4, a second feedback PMOS transistor PM5, a first feedback NMOS transistor NM6, and a second feedback NMOS transistor NM7.

[0045] The corresponding electrical connection relationship is as follows: the drains of the first feedback PMOS transistor PM4 and the second feedback PMOS transistor PM5 are both electrically connected to the main signal path, the gates of the first feedback PMOS transistor PM4 and the second feedback PMOS transistor PM5 are both electrically connected to the output node of the main signal path, the source of the first feedback PMOS transistor PM4 is electrically connected to the drain of the first feedback NMOS transistor NM6, the source of the second feedback PMOS transistor PM5 is electrically connected to the drain of the second feedback NMOS transistor NM7, the gate of the first feedback NMOS transistor NM6 is used to receive the first control signal S0, the gate of the second feedback NMOS transistor NM7 is used to receive the second control signal S1, and the sources of the first feedback NMOS transistor NM6 and the second feedback NMOS transistor NM7 are both grounded.

[0046] In the two-stage Schmidt trigger, the first-stage feedback path passes through two feedback PMOS transistors (PM4 and PM5) and two feedback NMOS transistors (NM6 and NM7), and by combining the control of the conduction state of the first-stage feedback path by the second feedback NMOS transistor NM7 and the first feedback NMOS transistor NM6, the conversion voltage thresholds (VIH and VIL) of the input signal are affected. Through this feedback mechanism, the Schmidt trigger can dynamically adjust the filtering ability of the input signal, so as to provide different noise suppression and high and low level determination capabilities in different working states.

[0047] Please continue to refer to Figure 4 , the second-stage feedback path is provided with a third feedback PMOS transistor PM6, a fourth feedback PMOS transistor PM7, a third feedback NMOS transistor NM4, and a fourth feedback NMOS transistor NM5.

[0048] The corresponding electrical connection relationship is as follows: the sources of the third feedback NMOS transistor NM4 and the fourth feedback NMOS transistor NM5 are both electrically connected to the main signal path, the gates of the third feedback NMOS transistor NM4 and the fourth feedback NMOS transistor NM5 are both electrically connected to the output node of the main signal path, the drain of the third feedback NMOS transistor NM4 is electrically connected to the source of the third feedback PMOS transistor PM6, the drain of the fourth feedback NMOS transistor NM5 is electrically connected to the source of the fourth feedback PMOS transistor PM7, the gate of the third feedback PMOS transistor PM6 is used to receive the first inverted signal S0, the gate of the fourth feedback PMOS transistor PM7 is used to receive the second inverted signal S1, and the drains of the third feedback PMOS transistor PM6 and the fourth feedback PMOS transistor PM7 are both grounded.

[0049] In the two-stage Schmitt trigger, the second-stage feedback path includes two feedback PMOS transistors (PM6 and PM7) and two feedback NMOS transistors (NM4 and NM5). By combining the control of the conduction states of the third feedback PMOS transistor and the fourth feedback PMOS transistor on the second-stage feedback path, stronger signal stability and higher filtering ability can be provided, which is suitable for application scenarios that require high precision and strong anti-interference ability.

[0050] Please continue to refer to Figure 4 , the main signal path includes a level pull-up path and a level pull-down path. The specific devices and corresponding electrical connection relationships in the two paths are described below:

[0051] The level pull-up path includes a first pull-up PMOS transistor PM1, a second pull-up PMOS transistor PM2, and a third pull-up PMOS transistor PM3. The source of the first pull-up PMOS transistor PM1 is used to receive the voltage power supply VDD. The drain of the first pull-up PMOS transistor PM1 is simultaneously electrically connected to the source of the second pull-up PMOS transistor PM2 and the drain of the second feedback PMOS transistor PM5. The drain of the second pull-up PMOS transistor PM2 is simultaneously electrically connected to the source of the third pull-up PMOS transistor PM3 and the drain of the first feedback PMOS transistor PM4. The gates of the first pull-up PMOS transistor PM1, the second pull-up PMOS transistor PM2, and the third pull-up PMOS transistor PM3 are all used to receive the input signal DATA. The drain of the third pull-up PMOS transistor serves as the output node of the main signal path.

[0052] The level pull-down path includes a first pull-down NMOS transistor NM1, a second pull-down NMOS transistor NM2, and a third pull-down NMOS transistor NM3. The drain of the first pull-down NMOS transistor NM1 serves as the output node of the main signal path. The source of the first pull-down NMOS transistor NM1 is electrically connected to the drain of the second pull-down NMOS transistor NM2 and the source of the third feedback NMOS transistor NM4 at the same time. The source of the second pull-down NMOS transistor NM2 is electrically connected to the drain of the third pull-down NMOS transistor NM3 and the source of the fourth feedback NMOS transistor NM5 at the same time. The source of the third pull-down NMOS transistor NM3 is grounded. The gates of the first pull-down NMOS transistor NM1, the second pull-down NMOS transistor NM2, and the third pull-down NMOS transistor NM3 are all used to receive the input signal DATA. Among them, the level pull-up path is used to pull up the level of the input signal to a high level state, and the level pull-down path is used to pull down the level of the input signal to a low level state.

[0053] In this embodiment, through the cooperation of the pull-up PMOS and pull-down NMOS transistors in the level pull-up path and the level pull-down path, it is ensured that the input signal can be stably converted into a high level or a low level, jointly constituting the core part of the main signal path, so that the input signal can perform accurate high and low level determination in the Schmitt trigger.

[0054] It should be further noted that when the first inverted signal S0N, the second inverted signal S1N, the first control signal S0, and the second control signal S1 output by the control signal processing module 10 are transmitted to the input signal processing module 20, the first control signal S0 is used for the connection between the first internal node MID_p0 and GND in the first-stage feedback path in the Schmitt trigger, and the first inverted signal S0N is used for the connection between the first internal node MID_n0 and VDD in the second-stage feedback path in the Schmitt trigger; the second control signal S1 is used for the connection between the second internal node MID_p1 and GND in the first-stage feedback path in the Schmitt trigger, and the S1N signal is used for the connection between the second internal node MID_n1 and VDD in the second-stage feedback path in the Schmitt trigger. That is, S0 and S1 are used as control signals to regulate the conduction of the first-stage feedback path respectively, while S0N and S1N are used as inverted signals to regulate the conduction of the second-stage feedback path. The cooperation of these two levels of feedback paths helps the Schmitt trigger perform dynamic level conversion and glitch filtering according to the input signal.

[0055] Please refer to Figure 5, the signal enhancement module includes at least one inverter, and each inverter includes an inverting PMOS transistor and an inverting NMOS transistor respectively. In each inverter, the gates of the inverting PMOS transistor and the inverting NMOS transistor are both used to receive the first output signal, the drains of the inverting PMOS transistor and the inverting NMOS transistor are both used as the output terminals of the signal enhancement module, the source of the inverting PMOS transistor is used to receive the power supply voltage, and the source of the inverting NMOS transistor is grounded.

[0056] In an alternative embodiment, the signal enhancement module includes four inverters connected in sequence and gradually enhanced. The first inverter includes a first inverting PMOS transistor PM8 and a first inverting NMOS transistor NM8, the second inverter includes a second inverting PMOS transistor PM9 and a second inverting NMOS transistor NM9, the third inverter includes a third inverting PMOS transistor PM10 and a third inverting NMOS transistor NM10, and the fourth inverter includes a fourth inverting PMOS transistor PM11 and a fourth inverting NMOS transistor NM11 (for the specific electrical connection of the four inverters, reference can be made to Figure 5 , which will not be elaborated here in detail).

[0057] In the signal enhancement module, by setting a plurality of intermediate signal nodes (net1, net2, and net3), these nodes represent the signals that are processed by the current inverter and then transmitted to the next inverter. That is, the output of each inverter (net1, net2, net3) provides an input signal for the next inverter. After the signal is processed by the four inverters, the output is used as the enhanced second output signal. That is, in the signal enhancement module of this embodiment, the four inverters connected in series and gradually increasing in level invert and enhance the first output signal DATA1, and finally generate the second output signal DATA_IN (which is transmitted to the inside of the chip as a processed and driven enhanced data signal), so as to effectively provide a higher signal driving ability and ensure the stable transmission and processing of the signal in the subsequent circuit. At the same time, the operation of the inverter can not only invert the signal, but also enhance the signal quality and provide sufficient signal strength to meet the requirements of the subsequent circuit.

[0058] Please refer to Figure 6 and Figure 7 , the adjustable Schmitt input circuit of the embodiment of the present application is based on a Schmitt trigger (which can provide a feedback mechanism), and its corresponding circuit principle involves the positive and negative inversion and hysteresis effect of the input signal, specifically as follows:

[0059] In the input signal A region, a positive conversion is performed on the input. The front - end input signal is at a low level, the output is at a high level, and transistors NM1 - NM3 are all cut off. S0 - S1 inputs a high level, S0N - S1N outputs a low level, PM6 - PM7 are conducting. The voltage at point A is the source voltage of NM4, and the voltage at point B is the source voltage of NM5. VA = VDD - Vthnm4, VB = VDD - Vthnm5. As the input DATA_IN increases from 0 to VDD, before Vin is less than the threshold voltage Vthnm3 of NM3, VA and VB maintain their original voltages. When Vin is greater than the threshold voltage Vthnm3 of NM3, NM3 begins to conduct, and the voltage at point B begins to drop due to the conduction of NM3. As NM3 conducts and Vin continues to increase, NM2 also begins to conduct, and the voltage at point A begins to drop. Since the source voltage of NM1 is not 0, NM1 lags behind NM2 and NM3 in conduction, which is the source of hysteresis. When Vin increases to Vin - VA = Vthnm1, NM1 conducts, the output begins to drop, causing NM4 - NM5 to slowly turn off, further decreasing the voltages at points A and B. At the same time, as Vin increases, NM2 - NM3 conduct faster, the output drops faster, and NM4 - NM5 turn off faster, forming positive feedback. Finally, NM1 - NM3 are fully conducting.

[0060] In the input signal B region, a negative conversion is performed on the input. The front - end input signal is at a high level, the output is at a low level, and transistors PM1 - PM3 are all cut off. The control signals S0 - S1 input a high level, the inverted signals S0N - S1N output a low level, and transistors NM6 - NM7 are conducting. The voltage at point C is the source voltage of PM4, and the voltage at point D is the source voltage of PM5. VA = |Vthpm4|, VB = |Vthpm5|. As the input DATA_IN decreases from VDD to 0, before VDD - Vin is less than the threshold voltage |Vthpm1| of PM1, VA and VB maintain their original voltages. When VDD - Vin is greater than the threshold voltage |Vthpm3| of PM1, PM1 begins to conduct, and the voltage at point C begins to rise due to the conduction of PM1. As PM1 conducts and Vin continues to decrease, PM2 also begins to conduct, and the voltage at point D begins to rise. Since the source voltage of PM3 is not 0, PM3 lags behind PM1 and PM2 in conduction, which is the source of hysteresis. When Vin decreases to VD - Vin = |Vthpm3|, PM1 conducts, the output begins to rise, causing PM4 - PM5 to slowly turn off, further increasing the voltages at points C and D. At the same time, as Vin decreases, PM2 - PM3 conduct faster, the output rises faster, and PM4 - PM5 turn off faster, forming positive feedback. Finally, PM1 - PM3 are fully conducting.

[0061] The adjustable Schmitt input circuit according to the embodiment of the present application adopts two additional levels of Schmitt feedback loops, enabling the output curve to be adjusted and translated backward, and increasing the hysteresis interval to achieve the purpose of adjustable VIH and VIL. That is, it has the hysteresis effect and the positive feedback function. Hysteresis effect function: Through the positive feedback mechanism, the circuit can achieve stable conversion of the input signal, avoiding output errors caused by small fluctuations or noises in the signal. The size of the hysteresis window is determined by the threshold voltage difference of the input signal (the range of the high and low level conversion voltages). Positive feedback function: During the conversion process of the input signal, the positive feedback mechanism strengthens the change speed of the signal, enabling the signal to quickly stabilize at a definite high or low level.

[0062] It should be noted that the size of the hysteresis window (ΔV) refers to the difference between the input high level threshold (VIH) and the input low level threshold (VIL). This difference determines the tolerance range of the signal during the high and low level switching, ensuring the suppression effect of the system on noises and interferences.

[0063] The embodiment of the present application also provides a memory chip (such as an SRAM or MRAM chip), including a chip main body and the adjustable Schmitt input circuit as described in the above embodiment, and the adjustable Schmitt input circuit is integrated in the chip main body.

[0064] The embodiment of the present application also provides a memory, including a memory main body and the memory chip as described in the above embodiment, and the memory chip is arranged in the memory main body.

[0065] The adjustable Schmitt input circuit, memory chip and memory of the present invention can, through the control signal processing module, signal input module and signal enhancement module, adjust the number of feedback paths according to the control signal and its inverted signal, realize the glitch filtering of the input signal and the dynamic adjustment of the high and low level thresholds, effectively improving the anti-interference ability of the circuit in the ground bounce noise environment and avoiding the interference phenomenon that the ground bounce noise may cause to the high and low level judgment of the input and output signals. The present invention can process the input signal and delay the output signal backward by opening or closing the Schmitt control port, so that different input voltage values correspond to the output signal mutation, thereby realizing the adjustment of the input high and low levels and the input glitch filtering ability.

[0066] Compared with the traditional scheme, the present invention can not only adapt to different working scenarios and enhance the reliability of the input signal, but also ensure that the output signal has sufficient driving ability through the signal enhancement module, so as to meet the requirements of subsequent chip processing, significantly improving the stability and applicability of the memory chip. In addition, on the one hand, the present invention increases the adjustment ability of the input unit circuit, making the application scenario of the chip more flexible, and on the other hand, enhances the flexibility of the high and low level conversion values of the chip during the test stage, reducing the risk of the chip not meeting the index revision, and lowering the manufacturing cost of the chip.

[0067] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0068] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. An adjustable Schmitt input circuit, characterized in that, It includes a control signal processing module, a signal input module, and a signal enhancement module connected in sequence; The control signal processing module is used to receive a control signal and generate a corresponding inverted signal based on the control signal; The signal input module is used to receive an input signal, the control signal, and the inverted signal, and conduct a target number of feedback paths according to the inverted signal and the control signal; wherein, the feedback path is used to perform corresponding filtering processing on the input signal and output a first output signal; The signal enhancement module is used to perform signal enhancement processing on the first output signal and output a second output signal.

2. The adjustable Schmitt input circuit according to claim 1, characterized in that, The control signal includes a first control signal and a second control signal, the inverted signal includes a first inverted signal and a second inverted signal, and the control signal processing module includes a first inverter circuit and a second inverter circuit; The first inverter circuit is used to invert the received first control signal and output the corresponding first inverted signal; The second inverter circuit is used to invert the received second control signal and output the corresponding second inverted signal; The signal input module is used to conduct a target number of feedback paths corresponding to the level combination according to the level combination of the first inverted signal, the second inverted signal, the first control signal, and the second control signal.

3. The adjustable Schmitt input circuit according to claim 2, wherein The first inverter circuit includes a first PMOS transistor and a first NMOS transistor. The gates of the first PMOS transistor and the first NMOS transistor are both used to receive the first control signal. The source of the first PMOS transistor is used to receive the power supply voltage. The source of the first NMOS transistor is grounded. The drains of the first PMOS transistor and the first NMOS transistor are both used to output the first inverted signal; The second inverter circuit includes a second PMOS transistor and a second NMOS transistor. The gates of the second PMOS transistor and the second NMOS transistor are both used to receive the second control signal. The source of the second PMOS transistor is used to receive the power supply voltage. The source of the second NMOS transistor is grounded. The drains of the second PMOS transistor and the second NMOS transistor are both used to output the second inverted signal.

4. The adjustable Schmitt input circuit according to claim 2, characterized in that, The input signal processing module includes a two-stage Schmitt trigger having a main signal path, a first-stage feedback path, and a second-stage feedback path; The two-stage Schmitt trigger is used to receive the first inverted signal, the second inverted signal, the first control signal, and the second control signal, and conduct the first-stage feedback path and / or the second-stage feedback path based on the corresponding level combination; The first-stage feedback path is used to perform first-stage feedback processing on the output signal and transmit it back to the main signal path, and the second-stage feedback path is used to perform second-stage feedback processing on the output signal and transmit it back to the main signal path; Wherein, when the feedback path through which the two-stage Schmitt trigger conducts is the first-stage feedback path or the second-stage feedback path, the first filtering range of the two-stage Schmitt trigger for the input signal is greater than a preset initial filtering range; when the feedback path through which the two-stage Schmitt trigger conducts is the first-stage feedback path and the second-stage feedback path, the second filtering range of the two-stage Schmitt trigger for the input signal is greater than the first filtering range; the initial filtering range is the filtering range corresponding to the situation where the two-stage Schmitt trigger does not conduct the feedback path.

5. The adjustable Schmitt input circuit according to claim 4, wherein The first-stage feedback path is provided with a first feedback PMOS transistor, a second feedback PMOS transistor, a first feedback NMOS transistor, and a second feedback NMOS transistor; The drains of the first feedback PMOS transistor and the second feedback PMOS transistor are both electrically connected to the main signal path, the gates of the first feedback PMOS transistor and the second feedback PMOS transistor are both electrically connected to the output node of the main signal path, the source of the first feedback PMOS transistor is electrically connected to the drain of the first feedback NMOS transistor, the source of the second feedback PMOS transistor is electrically connected to the drain of the second feedback NMOS transistor, the gate of the first feedback NMOS transistor is used to receive the first control signal, the gate of the second feedback NMOS transistor is used to receive the second control signal, and the sources of the first feedback NMOS transistor and the second feedback NMOS transistor are both grounded; Wherein, the second feedback NMOS transistor and the first feedback NMOS transistor are used to control the conduction state of the first-stage feedback path.

6. The adjustable Schmitt input circuit according to claim 5, characterized in that The second-stage feedback path is provided with a third feedback PMOS transistor, a fourth feedback PMOS transistor, a third feedback NMOS transistor, and a fourth feedback NMOS transistor; The sources of the third feedback NMOS transistor and the fourth feedback NMOS transistor are both electrically connected to the main signal path, the gates of the third feedback NMOS transistor and the fourth feedback NMOS transistor are both electrically connected to the output node of the main signal path, the drain of the third feedback NMOS transistor is electrically connected to the source of the third feedback PMOS transistor, the drain of the fourth feedback NMOS transistor is electrically connected to the source of the fourth feedback PMOS transistor, the gate of the third feedback PMOS transistor is used to receive the first inverted signal, the gate of the fourth feedback PMOS transistor is used to receive the second inverted signal, and the drains of the third feedback PMOS transistor and the fourth feedback PMOS transistor are both grounded; Wherein, the third feedback PMOS transistor and the fourth feedback PMOS transistor are used to control the conduction state of the first-stage feedback path.

7. The adjustable Schmitt input circuit according to claim 6, characterized in that The main signal path includes a level pull-up path and a level pull-down path; The level pull-up path includes a first pull-up PMOS transistor, a second pull-up PMOS transistor, and a third pull-up PMOS transistor. The source of the first pull-up PMOS transistor is used to receive a voltage power supply. The drain of the first pull-up PMOS transistor is electrically connected to the source of the second pull-up PMOS transistor and the drain of the second feedback PMOS transistor at the same time. The drain of the second pull-up PMOS transistor is electrically connected to the source of the third pull-up PMOS transistor and the drain of the first feedback PMOS transistor at the same time. The gates of the first pull-up PMOS transistor, the second pull-up PMOS transistor, and the third pull-up PMOS transistor are all used to receive the input signal. The drain of the third pull-up PMOS transistor serves as the output node of the main signal path; The level pull-down path includes a first pull-down NMOS transistor, a second pull-down NMOS transistor, and a third pull-down NMOS transistor. The drain of the first pull-down NMOS transistor serves as the output node of the main signal path. The source of the first pull-down NMOS transistor is electrically connected to the drain of the second pull-down NMOS transistor and the source of the third feedback NMOS transistor at the same time. The source of the second pull-down NMOS transistor is electrically connected to the drain of the third pull-down NMOS transistor and the source of the fourth feedback NMOS transistor at the same time. The source of the third pull-down NMOS transistor is grounded. The gates of the first pull-down NMOS transistor, the second pull-down NMOS transistor, and the third pull-down NMOS transistor are all used to receive the input signal; Wherein, the level pull-up path is used to pull up the level of the input signal to a high level state, and the level pull-down path is used to pull down the level of the input signal to a low level state.

8. The adjustable Schmitt input circuit according to claim 4, characterized in that, The signal enhancement module includes at least one inverter, and each inverter includes an inverter PMOS transistor and an inverter NMOS transistor; The gates of the inverter PMOS transistor and the inverter NMOS transistor are both used to receive the first output signal. The drains of the inverter PMOS transistor and the inverter NMOS transistor both serve as the output terminals of the signal enhancement module. The source of the inverter PMOS transistor is used to receive a power supply voltage, and the source of the inverter NMOS transistor is grounded; Wherein, the inverter is used to perform level inversion and signal enhancement on the first output signal, and output the obtained second output signal.

9. A memory chip, characterized in that, It includes a chip body and the adjustable Schmitt input circuit according to any one of claims 1 to 8, and the adjustable Schmitt input circuit is integrated in the chip body.

10. A memory, characterized in that, It includes a memory body and the memory chip according to claim 9, and the memory chip is arranged in the memory body.

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