A driving circuit and driving method for composite dielectric grating photosensitive detector

Abstract

The present invention discloses a drive circuit for a composite dielectric grating photosensitive detector and a drive method thereof. The circuit includes a logic circuit, a level conversion circuit, and a core drive circuit. The logic circuit is used to perform basic logic operations on a digital input signal to generate an enable signal to control the operation of the level conversion circuit; the level conversion circuit is used to output a high / low level according to the enable signal to control the on and off of the transistor in the core drive circuit; and the core drive circuit ultimately outputs a positive / negative high voltage or low voltage according to the signal provided by the previous circuit. The circuit structure of the present invention can achieve precise and rapid transmission of a drive voltage, which can be used to switch the operating state of the composite dielectric grating photosensitive detector. The circuit structure is simple, has a small area, and is compatible with standard integrated circuit processes.

Description

Technical Field

[0001] The invention relates to a driving circuit and a driving method for a composite dielectric grating photosensitive detector, and belongs to the field of integrated circuits. Background Art

[0002] A composite dielectric grating photodetector is a photosensitive transistor with a structure similar to a floating-gate device. Its operating principle is based on the photoelectric effect. When a semiconductor substrate absorbs photons from sunlight, electrons in the valence band gain enough energy to transition to the conduction band, generating electron-hole pairs. These pairs then separate under the influence of an electric field, generating a photocurrent. It operates in three main states: reset, in which the transistor gate is connected to a negative high voltage, releasing any remaining electrons; exposure, in which the transistor gate is connected to a low voltage and senses the field of view, collecting photoelectrons; and readout, in which a positive high voltage is applied to the transistor gate to amplify and read the photoelectrons generated during the exposure phase. Compared to CIS (CMOS Image Sensor) sensors, which require multiple transistors in a single pixel to implement the basic reset-exposure-readout imaging process, composite dielectric grating photodetectors require only a single transistor, significantly reducing the pixel area and improving imaging resolution and integration.

[0003] In order to give full play to the above advantages of the composite dielectric grating photodetector, the high-voltage drive circuit that provides its operating voltage should be as simple as possible on the basis of being able to accurately transmit the required voltage to save area. The existing technology analyzes the two types of drives, MOSFET drive and IGBT drive, in the "Basic Principles of MOSFET and IGBT Gate Driver Circuits". Among them, the principle and structure of MOSFET drive are relatively simple. When voltage is applied between the gate and source of the MOSFET, a conductive channel is induced in the semiconductor material under the gate, allowing current to flow from the drain to the source. The switching state of the MOSFET is controlled by controlling the voltage of the gate. Therefore, the MOSFET drive is relatively simple. In low-frequency situations, it can be directly driven by a transistor. In high-frequency situations, transformers or dedicated chips are often used for driving. And because the gate input impedance of the MOSFET is very high, the loss of driving power is very small. However, the MOSFET drive has high requirements for the accuracy of the driving voltage. If the driving voltage is inaccurate, it may cause the on-resistance to increase or cause mis-conduction. In addition, the MOSFET drive circuit also needs to design resistors and inductors. Power devices increase the damping of the circuit through resistors to achieve current limiting and prevent parasitic oscillations, and match the impedance of the signal originating from the gate to ensure stable operation of the drive circuit; the energy is released or absorbed by the inductor for filtering, providing a stable power supply environment for the MOSFET drive circuit, and can also effectively prevent high-frequency interference signals from affecting normal switching operations; because power devices such as resistors or inductors are involved, the area is large and the advantage of small pixels of the composite dielectric grating photosensitive detector cannot be brought into play; the principle of IGBT driving is to control the on and off of the IGBT by controlling the voltage between the gate and the emitter, which can carry high voltage and large current and is suitable for high-power scenarios; however, the driving circuit is relatively complex, and a single circuit cannot meet the conditions that the composite dielectric grating photosensitive detector needs to transmit negative high voltage and positive high voltage in the reset and readout states respectively. It is necessary to design two driving circuits, positive voltage drive and negative voltage drive, respectively, according to the gate potential at shutdown; therefore, it will also cause excessive area power consumption.

[0004] Therefore, although the existing driving circuit structure can meet the requirements of different voltages required for the output of the composite dielectric grating photosensitive detector, due to the limitations of the circuit structure, it consumes a large amount of area power consumption and cannot give full play to the advantage of the small pixel area of ​​the composite dielectric grating photosensitive detector. Summary of the Invention

[0005] In response to the above defects in the prior art, the present invention provides a driving circuit and a driving method for a composite dielectric grating photosensitive detector. The circuit has a simple structure, does not contain large-area components, and can transmit all the voltages required for the operation of the composite dielectric grating photosensitive detector.

[0006] The first object of the present invention is to provide a driving circuit for a composite dielectric grating photosensitive detector, the driving circuit comprising a logic circuit, a level conversion circuit and a core driving circuit;

[0007] The logic circuit includes a number of AND gates, OR gates and inverters, which generate an enable signal to control the operation of the level conversion circuit by performing basic logic operations on the digital input signal;

[0008] The level conversion circuit includes a positive / negative high-voltage level conversion circuit and a low-voltage level conversion circuit, which controls the on / off of transistors in the core drive circuit according to the output of the logic circuit;

[0009] The core drive circuit includes 3 PMOS tubes and 2 NMOS tubes, which receive the signal output by the level conversion circuit and ultimately output positive / negative high voltage or low voltage.

[0010] Furthermore, the digital signal input to the logic circuit includes SWITCH <1> 、PULSE_TO_MUX、SWITCH <0> and SWITCH <2> ;

[0011] Furthermore, the positive high voltage level conversion circuit in the level conversion circuit includes 4 PMOS transistors and 4 NMOS transistors;

[0012] Furthermore, the negative high-voltage level conversion circuit in the level conversion circuit includes four PMOS transistors and four NMOS transistors;

[0013] Furthermore, the low-voltage level conversion circuit in the level conversion circuit includes two PMOS tubes and two NMOS tubes;

[0014] Furthermore, the core driving circuit includes a first P-type MOS transistor PM1, a second P-type MOS transistor PM2, a first N-type MOS transistor NM1, a second N-type MOS transistor NM2 and a third N-type MOS transistor NM3;

[0015] The first N-type MOS transistor NM1 is located in the low voltage LV transmission path; the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2 are located in the positive high voltage HVP transmission path; the second N-type MOS transistor NM2 and the third N-type MOS transistor NM3 are located in the negative high voltage HVN transmission path;

[0016] The source of the first N-type MOS transistor NM1, the source of the first P-type MOS transistor PM1, and the source input of the second N-type MOS transistor NM2 are LV, HVP, and HVN, respectively. The gate of the first N-type MOS transistor NM1 is connected to the output of the low-voltage level conversion circuit; the gate of the first P-type MOS transistor PM1 is connected to VHH, and the drain is connected to the source of the second P-type MOS transistor PM2; the gate of the second P-type MOS transistor PM2 is grounded; the source input of the second N-type MOS transistor NM2 is HVN, the gate is connected to the output VLL of the negative high-voltage level conversion circuit, and the drain is connected to the source of the third N-type MOS transistor NM3; the gate of the third N-type MOS transistor NM3 is grounded; the drains of the first N-type MOS transistor NM1, the second P-type MOS transistor PM2, and the third N-type MOS transistor NM3 are interconnected and output the final output VO of the core drive circuit.

[0017] A second object of the present invention is to provide a driving method for a composite dielectric grating photosensitive detector, the method comprising:

[0018] First, the logic circuit performs basic logical operations on the digital input signal to generate an enable signal that controls the operation of the level conversion circuit; then the level conversion circuit outputs a high / low level according to the enable signal to control the on and off of the transistor in the core drive circuit; after that, the core drive circuit finally outputs a positive / negative high voltage or low voltage according to the signal given by the level conversion circuit, and transmits it to the control gate end of the composite dielectric grating photosensitive detector, thereby controlling its working state.

[0019] Furthermore, the logic circuit is divided into three parts:

[0020] Digital Signal Switch <1> The enable signal of the positive high-voltage level conversion circuit is generated by an AND operation with PULSE_TO_MUX (referred to as the positive high-voltage enable signal). The enable signal of the positive high-voltage level conversion circuit is then reversed to generate the input signal of the positive high-voltage level conversion circuit (referred to as the positive high-voltage input signal).

[0021] The digital signal PULSE_TO_MUX is reversed and then connected to SWITCH <1> Do an AND operation and the generated signal is then combined with SWITCH <0> After an OR operation, an enable signal of the low-voltage level conversion circuit is generated (referred to as a low-voltage enable signal); the enable signal of the low-voltage level conversion circuit is further subjected to an inverse operation to generate an input signal of the low-voltage level conversion circuit (referred to as a low-voltage input signal);

[0022] Digital Signal Switch <2> is the enable signal of the negative high-voltage level conversion circuit (recorded as the negative high-voltage enable signal); the enable signal of the negative high-voltage level conversion circuit is further reversed to obtain the input signal of the negative high-voltage level conversion circuit (recorded as the negative high-voltage input signal).

[0023] Furthermore, the positive high-voltage input signal and the positive high-voltage enable signal in the level conversion circuit work together to switch the amplitude of the output voltage: when the positive high-voltage enable signal is high and the positive high-voltage input signal is low, the output voltage Vout is equal to the input voltage Vin (Vin is a positive high-voltage signal); when the positive high-voltage enable signal is low and the positive high-voltage input signal is high, the output voltage Vout is equal to the ground signal GND; the output signal of the positive high-voltage level conversion circuit is VHH.

[0024] Furthermore, the negative high-voltage input signal and the negative high-voltage enable signal in the negative high-voltage level conversion circuit of the level conversion circuit work together to switch the amplitude of the output voltage: when the negative high-voltage enable signal is high and the negative high-voltage input signal is low, the output voltage Vout of the negative high-voltage level conversion circuit is equal to the input voltage Vin (Vin is a negative high-voltage signal); when the negative high-voltage enable signal is low and the negative high-voltage input signal is high, the output voltage Vout of the negative high-voltage level conversion circuit is equal to the ground signal GND.

[0025] Furthermore, the low-voltage input signal in the level conversion circuit is the inverse signal of the low-voltage enable signal, and the two work together to switch the amplitude of the output voltage: when the low-voltage enable signal is high and the low-voltage input signal is low, the output voltage Vout is equal to the power supply signal VDD (VDD is a low-voltage signal); when the low-voltage enable signal is low and the low-voltage input signal is high, the output voltage Vout is equal to the ground signal GND; the output signal of the low-voltage level conversion circuit is EN_LV.

[0026] Furthermore, in the core driving circuit, the first N-type MOS transistor NM1 is located in the low voltage LV transmission path; the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2 are located in the positive high voltage HVP transmission path; the second N-type MOS transistor NM2 and the third N-type MOS transistor NM3 are located in the negative high voltage HVN transmission path.

[0027] When the first P-type MOS transistor PM1 and the second N-type MOS transistor NM2 are in the disconnected state and the first N-type MOS transistor NM1 is in the closed state, the low voltage LV transmission path is connected, and the output voltage VO=LV;

[0028] When the first N-type MOS transistor NM1 and the second N-type MOS transistor NM2 are in the open state, and the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2 are in the closed state, the positive high voltage HVP transmission path is connected, and the output voltage VO = HVP;

[0029] When the first N-type MOS transistor NM1 and the first P-type MOS transistor PM1 are in the open state, and the second N-type MOS transistor NM2 and the third N-type MOS transistor NM3 are in the closed state, the negative high voltage HVN transmission path is connected, and the output voltage VO=HVN.

[0030] The beneficial effects of the present invention are:

[0031] The present invention provides a driving circuit and a driving method for a composite dielectric grating photosensitive detector. The driving circuit includes a logic circuit, a level conversion circuit, and a core driving circuit. All modules are composed only of basic transistor devices, without large-area components such as resistors and inductors, and the overall area consumption is small. Compared with existing driving circuits, a single circuit can transmit positive / negative high voltages to meet the working voltage supply requirements of the composite dielectric grating photosensitive detector. In addition, the circuit provided by the present invention adopts a design compatible with standard integrated circuit processes, making it possible to apply the circuit structure in large-scale composite dielectric grating photosensitive detector arrays. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 This is a schematic diagram of the overall structure of a driving circuit structure for a composite dielectric grating photosensitive detector provided by the present invention;

[0034] Figure 2 This is a schematic diagram of the positive high-voltage level conversion circuit structure and signal waveform in a driving circuit for a composite dielectric grating photodetector provided by the present invention;

[0035] Figure 3 This is a schematic diagram of the structure of a negative high-voltage level conversion circuit and a schematic diagram of a signal waveform in a driving circuit for a composite dielectric grating photodetector provided by the present invention;

[0036] Figure 4 This is a schematic diagram of the structure of a low-voltage level conversion circuit and a schematic diagram of a signal waveform in a driving circuit for a composite dielectric grating photodetector provided by the present invention;

[0037] Figure 5 The present invention provides a truth value comparison table of input and output signals of a driving circuit for a composite dielectric grating photosensitive detector;

[0038] Figure 6The present invention provides a signal waveform diagram for a driving circuit of a composite dielectric grating photosensitive detector. DETAILED DESCRIPTION

[0039] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0040] Example 1

[0041] This embodiment provides a driving circuit for a composite dielectric grating photosensitive detector, such as Figure 1 As shown, the driving circuit includes a logic circuit, a level conversion circuit and a core driving circuit, and uses a total of 13 N-type transistors, 12 P-type transistors, 4 inverters, 2 AND gates and 1 OR gate;

[0042] The logic circuit includes 4 inverters, 2 AND gates and 1 OR gate, which generates an enable signal to control the operation of the level conversion circuit by performing basic logic operations on the digital input signal; the input of the logic circuit includes SWITCH <1> 、PULSE_TO_MUX、SWITCH <0> and SWITCH <2> ;

[0043] Digital Signal Switch <1> The enable signal of the positive high-voltage level conversion circuit is generated by an AND operation with PULSE_TO_MUX (referred to as the positive high-voltage enable signal). The enable signal of the positive high-voltage level conversion circuit is then reversed to generate the input signal of the positive high-voltage level conversion circuit (referred to as the positive high-voltage input signal).

[0044] The digital signal PULSE_TO_MUX is reversed and then connected to SWITCH <1> Do an AND operation and the generated signal is then combined with SWITCH <0> After an OR operation, an enable signal of the low-voltage level conversion circuit is generated (referred to as a low-voltage enable signal); the enable signal of the low-voltage level conversion circuit is further subjected to an inverse operation to generate an input signal of the low-voltage level conversion circuit (referred to as a low-voltage input signal);

[0045] Digital Signal Switch <2> is the enable signal of the negative high-voltage level conversion circuit (recorded as the negative high-voltage enable signal); the enable signal of the negative high-voltage level conversion circuit is further reversed to obtain the input signal of the negative high-voltage level conversion circuit (recorded as the negative high-voltage input signal).

[0046] The level conversion circuit includes a positive high-voltage level conversion circuit, a negative high-voltage level conversion circuit, and a low-voltage level conversion circuit, which controls the on and off of transistors in the core drive circuit according to the output results of the logic circuit;

[0047] The structure of the positive high voltage level conversion circuit is as follows Figure 2As shown, it includes a third P-type MOS transistor PM3, a fourth P-type MOS transistor PM4, a fifth P-type MOS transistor PM5, a sixth P-type MOS transistor PM6, a fourth N-type MOS transistor NM4, a fifth N-type MOS transistor NM5, a sixth N-type MOS transistor NM6 and a seventh N-type MOS transistor NM7;

[0048] The gate terminals of the sixth N-type MOS transistor NM6 and the seventh N-type MOS transistor NM7 are connected to the positive high-voltage enable signal and the positive high-voltage input signal respectively, the source terminals are connected to the ground signal GND, and the drain terminals are connected to the source terminals of the fourth N-type MOS transistor NM4 and the fifth N-type MOS transistor NM5 respectively; the drain terminals of the fourth N-type MOS transistor NM4 and the fifth N-type MOS transistor NM5 are connected to the drain terminals of the fifth P-type MOS transistor PM5 and the sixth P-type MOS transistor PM6 respectively; the source terminals of the fifth P-type MOS transistor PM5 and the sixth P-type MOS transistor PM6 are connected to the drain terminals of the third P-type MOS transistor PM3 and the fourth P-type MOS transistor PM4 respectively. The drain terminals of the fourth N-type MOS transistor NM4, the fifth N-type MOS transistor NM5, the fifth P-type MOS transistor PM5, and the sixth P-type MOS transistor PM6 are connected; the gate terminals of the third P-type MOS transistor PM3 and the fourth P-type MOS transistor PM4 are connected to the input voltage Vin; the gate terminal of the third P-type MOS transistor PM3 is connected to the source terminal of the sixth P-type MOS transistor PM6; the drain terminal of the third P-type MOS transistor PM3, the gate terminal of the fourth P-type MOS transistor PM4, and the source terminal of the fifth P-type MOS transistor PM5 are connected to form the output Vout of the positive high-voltage level conversion circuit;

[0049] The positive high-voltage enable signal and the positive high-voltage input signal are used to control the conduction states of the sixth N-type MOS transistor NM6 and the seventh N-type MOS transistor NM7, thereby controlling the states of the two branches, thereby adjusting the output Vout of the positive high-voltage level conversion circuit to the input voltage Vin or the ground signal GND.

[0050] The structure of the negative high voltage level conversion circuit is as follows Figure 3 As shown, the seventh P-type MOS transistor PM7, the eighth P-type MOS transistor PM8, the ninth P-type MOS transistor PM9, the tenth P-type MOS transistor PM10, the eighth N-type MOS transistor NM8, the ninth N-type MOS transistor NM9, the tenth N-type MOS transistor NM10 and the eleventh N-type MOS transistor NM11;

[0051] The source terminals of the seventh P-type MOS transistor PM7 and the eighth P-type MOS transistor PM8 are connected to the power supply VDD, the gate terminals are connected to the negative high-voltage input signal and the negative high-voltage enable signal respectively, and the drain terminals are connected to the source terminals of the ninth P-type MOS transistor PM9 and the tenth P-type MOS transistor PM10 respectively; the gate terminals of the ninth P-type MOS transistor PM9 and the tenth P-type MOS transistor PM10 are simultaneously connected to the ground signal GND, and the drain terminals are connected to the drain terminals of the eighth N-type MOS transistor NM8 and the ninth N-type MOS transistor NM9 respectively; the source terminals of the eighth N-type MOS transistor NM8 and the ninth N-type MOS transistor NM9 are respectively connected to the ground signal GND. The drain terminals of the tenth N-type MOS transistor NM10 and the eleventh N-type MOS transistor NM11 are connected to the input voltage Vin at the same time; the gate terminals of the eighth N-type MOS transistor NM8 and the eleventh N-type MOS transistor NM11 are connected to the drain terminal of the tenth P-type MOS transistor PM10 at the same time; the gate terminals of the ninth N-type MOS transistor NM9 and the tenth N-type MOS transistor NM10 and the drain terminal of the ninth P-type MOS transistor PM9 are connected to the output Vout of the negative high-voltage level conversion circuit at the same time;

[0052] The conduction states of the seventh P-type MOS transistor PM7 and the eighth P-type MOS transistor PM8 are controlled by the negative high-voltage input signal and the negative high-voltage enable signal, thereby controlling the states of the two branches, thereby adjusting the output Vout of the negative high-voltage level conversion circuit to the input voltage Vin or the ground signal GND.

[0053] The structure of the low voltage level conversion circuit is as follows Figure 4 As shown, it includes an eleventh P-type MOS transistor PM11, a twelfth P-type MOS transistor PM12, a twelfth N-type MOS transistor NM12 and a thirteenth N-type MOS transistor NM13;

[0054] The gate terminals of the twelfth N-type MOS transistor NM12 and the thirteenth N-type MOS transistor NM13 are connected to the low-voltage input signal and the low-voltage enable signal, respectively. The source terminals are also connected to the ground signal GND. The drain terminals are connected to the drain terminals of the eleventh P-type MOS transistor PM11 and the twelfth P-type MOS transistor PM12, respectively. The source terminals of the eleventh P-type MOS transistor PM11 and the twelfth P-type MOS transistor PM12 are connected to the power supply VDD. The gate terminal of the twelfth P-type MOS transistor PM12 is connected to the drain terminal of the twelfth N-type MOS transistor NM12. The gate terminal of the eleventh P-type MOS transistor PM11 and the drain terminal of the thirteenth N-type MOS transistor NM13 are connected to serve as the output Vout of the low-voltage level conversion circuit.

[0055] The conduction states of the twelfth N-type MOS transistor NM12 and the thirteenth N-type MOS transistor NM13 are controlled by the low-voltage input signal and the low-voltage enable signal, thereby controlling the states of the two branches, thereby adjusting the output Vout of the low-voltage level conversion circuit to the power supply VDD or the ground signal GND.

[0056] The core driving circuit includes a first P-type MOS transistor PM1, a second P-type MOS transistor PM2, a first N-type MOS transistor NM1, a second N-type MOS transistor NM2 and a third N-type MOS transistor NM3; it receives the signal output by the level conversion circuit and finally outputs positive / negative high voltage or low voltage.

[0057] The source inputs of the first N-type MOS transistor NM1, the source inputs of the first P-type MOS transistor PM1, and the source inputs of the second N-type MOS transistor NM2 are LV, HVP, and HVN, respectively. The gate of the first N-type MOS transistor NM1 is connected to the output EN_LV of the low-voltage level conversion circuit. The source input of the first P-type MOS transistor PM1 is HVP, the gate is connected to the output VHH of the positive high-voltage level conversion circuit, and the drain is connected to the source of the second P-type MOS transistor PM2. The gate of the second P-type MOS transistor PM2 is grounded. The source input of the second N-type MOS transistor NM2 is HVN, the gate is connected to the output VLL of the negative high-voltage level conversion circuit, and the drain is connected to the source of the third N-type MOS transistor NM3. The gate of the third N-type MOS transistor NM3 is grounded. The drains of the first N-type MOS transistor NM1, the second P-type MOS transistor PM2, and the third N-type MOS transistor NM3 are interconnected and output the final output VO of the core drive circuit.

[0058] Example 2

[0059] This embodiment provides a driving method for a composite dielectric grating photosensitive detector. The method is implemented based on the driving circuit provided in the first embodiment. The method specifically includes:

[0060] In logic circuits, digital signal SWITCH <1> The enable signal of the positive high voltage level conversion circuit is generated by an AND operation with PULSE_TO_MUX; the input signal of the positive high voltage level conversion circuit is the inverse signal of the enable signal of the positive high voltage level conversion circuit;

[0061] The digital signal PULSE_TO_MUX is reversed and then connected to SWITCH <1> Do an AND operation and the generated signal is then combined with SWITCH <0> An enable signal of the low-voltage level conversion circuit is generated through an OR operation; the input signal of the low-voltage level conversion circuit is an inverse signal of the enable signal of the low-voltage level conversion circuit;

[0062] Digital Signal Switch <2> is an enable signal of the negative high-voltage level conversion circuit, and the input signal of the negative high-voltage level conversion circuit is an inverse signal of the enable signal of the negative high-voltage level conversion circuit.

[0063] The waveforms of the enable signal and input signal of the positive high voltage level conversion circuit in the level conversion circuit are as follows: Figure 2As shown, when the positive high-voltage enable signal is high and the positive high-voltage input signal is low, the output voltage Vout of the positive high-voltage level conversion circuit is equal to the input voltage Vin (Vin is a positive high-voltage signal); when the high-voltage enable signal is low and the positive high-voltage input signal is high, the output voltage Vout is equal to the ground signal GND.

[0064] The waveforms of the enable signal and input signal of the negative high voltage level conversion circuit in the level conversion circuit are as follows: Figure 3 As shown, when the enable signal of the negative high-voltage level conversion circuit is at a high level and the input signal of the negative high-voltage level conversion circuit is at a low level, the output voltage Vout of the negative high-voltage level conversion circuit is equal to the input voltage Vin (Vin is a negative high-voltage signal); when the enable signal of the negative high-voltage level conversion circuit is at a low level and the input signal of the negative high-voltage level conversion circuit is at a high level, the output voltage Vout of the negative high-voltage level conversion circuit is equal to the ground signal GND;

[0065] The waveforms of the enable signal and input signal of the low voltage level conversion circuit in the level conversion circuit are as follows: Figure 4 As shown, when the enable signal of the low-voltage level conversion circuit is high and the input signal of the low-voltage level conversion circuit is low, the output voltage Vout of the low-voltage level conversion circuit is equal to the power supply signal VDD (VDD is a low-voltage signal); when the enable signal of the low-voltage level conversion circuit is low and the input signal of the low-voltage level conversion circuit is high, the output voltage Vout of the low-voltage level conversion circuit is equal to the ground signal GND.

[0066] In the core drive circuit: the first N-type MOS transistor NM1 in the core drive circuit is located in the low voltage LV transmission path; the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2 are located in the positive high voltage HVP transmission path; the second N-type MOS transistor NM2 and the third N-type MOS transistor NM3 are located in the negative high voltage HVN transmission path.

[0067] When the first P-type MOS transistor PM1 and the second N-type MOS transistor NM2 are in the disconnected state and the first N-type MOS transistor NM1 is in the closed state, the low voltage LV transmission path is connected, and the output voltage VO=LV;

[0068] When the first N-type MOS transistor NM1 and the second N-type MOS transistor NM2 are in the open state, and the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2 are in the closed state, the positive high voltage HVP transmission path is connected, and the output voltage VO = HVP;

[0069] When the first N-type MOS transistor NM1 and the first P-type MOS transistor PM1 are in the open state, and the second N-type MOS transistor NM2 and the third N-type MOS transistor NM3 are in the closed state, the negative high voltage HVN transmission path is connected, and the output voltage VO=HVN.

[0070] 4 input signals SWITCH of the overall circuit <0> 、SWITCH <1> 、SWITCH <2> The truth value comparison table of PULSE_TO_MUX and output signal VO is as follows Figure 5 As shown;

[0071] When SWITCH <0> 1. SWITCH <1> and SWITCH <2> 0 or SWITCH <1> 1. SWITCH <2> When PULSE_TO_MUX is 0, VO is the input low voltage LV;

[0072] When SWITCH <1> and PULSE_TO_MUX is 1, SWITCH <0> and SWITCH <2> When it is 0, VO is the input positive high voltage HVP;

[0073] When SWITCH <2> 1. SWITCH <0> and SWITCH <1> When VO is 0, VO is the input negative high voltage HVN.

[0074] When the circuit is applied to drive a composite dielectric grating photosensitive detector, it is necessary to first transmit a negative high voltage to reset it, then transmit a low voltage during the detector exposure period, and finally transmit a positive high voltage to read the detector signal. Combined with the working principle of the circuit, the corresponding working sequence is obtained as follows Figure 6 As shown;

[0075] First, let SWITCH <2> is 1, and the other signals are 0, transmitting a negative high-voltage signal HVN to VO and then to the gate end of the composite dielectric grating photosensitive detector, driving the composite dielectric grating photosensitive detector into a reset state and releasing the remaining electrons inside;

[0076] Then let SWITCH <0> When 1 is 1 and the other signals are 0, a low-voltage signal LV is transmitted to VO and then to the gate end of the composite dielectric grating photodetector, providing a bias voltage for the exposure stage, so that it can complete the collection of photoelectrons;

[0077] Finally, switch <1> When PULSE_TO_MUX is 1 and the other signals are 0, the positive high-voltage signal HVP is transmitted to VO and then to the gate end of the composite dielectric grating photosensitive detector for amplifying and reading the photoelectrons.

[0078] At this point, a complete imaging process has been completed.

[0079] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0080] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A driving circuit for a composite dielectric grating photosensitive detector, characterized in that: The circuit includes: a logic circuit, a level conversion circuit and a core driving circuit; The logic circuit is used to perform logic processing on the input digital signal; the level conversion circuit includes a positive high-voltage level conversion circuit, a negative high-voltage level conversion circuit, and a low-voltage level conversion circuit, and is used to output different level conversion signals; the core driving circuit controls the conduction state of different transmission paths according to the enable signal output by the level conversion circuit, thereby outputting positive / negative high voltage or low voltage; the transmission path of the core driving circuit includes a low-voltage LV transmission path, a positive high-voltage HVP transmission path, and a negative high-voltage HVN transmission path; The low voltage LV transmission path includes an N-type MOS transistor, and the gate of the N-type MOS transistor is connected to the output of the low voltage level conversion circuit; The positive high voltage HVP transmission path includes two P-type MOS transistors, wherein the drain of one P-type MOS transistor is connected to the source of the other P-type MOS transistor, the gate is connected to the output of the positive high voltage level conversion circuit, and the gate of the other P-type MOS transistor is grounded; The negative high voltage HVN transmission path includes two N-type MOS transistors, wherein the drain of one N-type MOS transistor is connected to the source of the other N-type MOS transistor, the gate is connected to the output of the negative high voltage level conversion circuit, and the gate of the other N-type MOS transistor is grounded; Outputs of the low voltage LV transmission path, the positive high voltage HVP transmission path, and the negative high voltage HVN transmission path are commonly connected to the output VO of the core driving circuit.

2. The circuit according to claim 1, characterized in that The digital signals input by the logic circuit include: SWITCH <1> 、PULSE_TO_MUX、SWITCH <0> and SWITCH <2> .

3. The circuit according to claim 2, characterized in that In the positive high voltage level conversion circuit: The enable signal of the positive high voltage level conversion circuit is provided by SWITCH <1> The input signal of the positive high-voltage level conversion circuit is the inverse signal of the enable signal after an AND operation with PULSE_TO_MUX; the output signal of the positive high-voltage level conversion circuit is VHH; The enable signal of the low voltage level conversion circuit is controlled by SWITCH <1> After a reverse operation with PULSE_TO_MUX, the result of the AND operation is combined with SWITCH <0> After one OR operation, the input signal of the low-voltage level conversion circuit is the inverse signal of the enable signal; the output signal of the low-voltage level conversion circuit is EN_LV; The enable signal of the negative high voltage level conversion circuit is SWITCH <2> , the input signal of the negative high voltage level conversion circuit is the inverse signal of the enable signal; the output signal of the negative high voltage level conversion circuit is VLL.

4. The circuit according to claim 3, characterized in that The logic circuit includes a plurality of inverters, AND gates and OR gates.

5. A driving method for a composite dielectric grating photosensitive detector, characterized in that: The method is implemented based on the circuit described in any one of claims 1 to 4.

6. The method according to claim 5, characterized in that The method comprises the following steps: a logic circuit performs a logic operation on an input digital signal to generate an enable signal for controlling the operation of a level conversion circuit; the level conversion circuit outputs a signal for controlling a core drive circuit according to the enable signal generated by the logic circuit; and the core drive circuit outputs a positive / negative high voltage or a low voltage under the control of the level conversion circuit.

7. The method according to claim 6, characterized in that In the level conversion circuit: When the enable signal of the positive high-voltage level conversion circuit is at a high level and the input signal of the positive high-voltage level conversion circuit is at a low level, the output voltage of the positive high-voltage level conversion circuit is the input positive high-voltage signal; when the enable signal of the positive high-voltage level conversion circuit is at a low level and the input signal of the positive high-voltage level conversion circuit is at a high level, the output voltage of the positive high-voltage level conversion circuit is a ground signal; When the enable signal of the negative high-voltage level conversion circuit is at a high level and the input signal of the negative high-voltage level conversion circuit is at a low level, the output voltage of the negative high-voltage level conversion circuit is a negative high-voltage signal; when the enable signal of the negative high-voltage level conversion circuit is at a low level and the input signal of the negative high-voltage level conversion circuit is at a high level, the output voltage of the negative high-voltage level conversion circuit is a ground signal; When the enable signal of the low-voltage level conversion circuit is at a high level and the input signal of the low-voltage level conversion circuit is at a low level, the output voltage of the low-voltage level conversion circuit is a low-voltage signal; when the enable signal of the low-voltage level conversion circuit is at a low level and the input signal of the low-voltage level conversion circuit is at a high level, the output voltage of the low-voltage level conversion circuit is a ground signal.

8. The method according to claim 7, characterized in that In the core driving circuit: When the P-type MOS transistor enabled by the positive high-voltage level conversion circuit in the positive high-voltage HVP transmission path and the N-type MOS transistor enabled by the negative high-voltage level conversion circuit in the negative high-voltage HVN transmission path are disconnected, and the N-type MOS transistor in the low-voltage LV transmission path is closed, the low-voltage LV transmission path is turned on, and the output voltage VO of the core drive circuit equals LV; When the N-type MOS transistor in the low voltage LV transmission path and the N-type MOS transistor enabled by the negative high voltage level conversion circuit in the negative high voltage HVN transmission path are disconnected, and the two P-type MOS transistors in the positive high voltage HVP transmission path are closed, the positive high voltage HVP transmission path is turned on, and the output voltage VO of the core drive circuit equals HVP; When the N-type MOS transistor in the low-voltage LV transmission path and the P-type MOS transistor enabled by the positive high-voltage level conversion circuit in the positive high-voltage HVP transmission path are disconnected, and the two N-type MOS transistors in the negative high-voltage HVN transmission path are closed, the negative high-voltage HVN transmission path is turned on, and the output voltage VO of the core drive circuit equals HVN.

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