Automatic frequency calibration circuit and phase-locked loop

Abstract

The present invention relates to the technical field of automatic frequency calibration, and discloses an automatic frequency calibration circuit and a phase-locked loop. The automatic frequency calibration circuit is constructed by constructing a frequency discriminator and an analog-to-digital converter, and using the signal comparison circuit and integration circuit in the frequency discriminator to compare the divided frequency signal. f div With reference clock signal f REF The frequency of the divided signal f div and reference clock signal f REF The signal currents are subtracted and converted into a voltage signal, which outputs a voltage signal proportional to the frequency difference between the two. This voltage signal is then converted via an analog-to-digital converter into a frequency control word for the VCO, which controls the VCO frequency up or down. Ultimately, after stabilization, the frequency divider output frequency is near the reference frequency. Compared to traditional methods, this invention significantly reduces the time required for automatic frequency band selection, thereby significantly reducing the stabilization time of the phase-locked loop frequency switching. This facilitates rapid frequency switching in electronic systems, particularly those requiring rapid scanning across a wide frequency range, such as detection systems.

Description

Technical Field

[0001] The present invention relates to the technical field of automatic frequency calibration, and in particular to an automatic frequency calibration circuit and a phase-locked loop. Background Art

[0002] Typical phase-locked loop principle is as follows Figure 1 As shown, its operation starts from the external input reference clock signal (f REF ), which is usually derived from a crystal oscillator, etc. The reference clock signal is used as one input signal of the frequency detector and the other input signal is derived from the output feedback signal of the N divider (f div The phase frequency detector compares the phase difference between the reference clock signal and the feedback signal and outputs a voltage pulse signal whose pulse width is proportional to the input phase difference. This is used to control the current source switch in the charge pump, so that the voltage pulse signal is converted into a current pulse signal of the same width. The current pulse is converted into a DC voltage V after passing through a low-pass filter. T , used to adjust the voltage controlled oscillator (VCO) output signal frequency ( f out ). In steady state, after the VCO output signal passes through the N divider, its frequency and phase are consistent with the reference clock signal, so a corresponding frequency-stable single-tone signal is obtained at the output end. The relationship between the output signal frequency and the reference clock signal frequency is: .

[0003] Typical VCO structure is as follows: Figure 2 As shown, its working principle is to use the resonant cavity composed of inductance and capacitance to generate a resonant signal, and the oscillation signal frequency is 1 / 2π(LC) 1 / 2 , the inductance L is Figure 2 The sum of L0 and L1 in the figure, capacitor C is the combined effect of C0, C1 and the capacitors in the capacitor array. Transistors M0 and M1 produce negative resistance to offset the parasitic resistance of inductors and capacitors. The tail current I B Provides bias current for the entire circuit. In order to obtain better output noise characteristics, the VCO input voltage V T To output frequency f out Gain K VCO It needs to be set as small as possible; then from the application perspective, it is hoped that the VCO output frequency range is as wide as possible to adapt to more application scenarios. To meet the above two application requirements, the frequency adjustment function of the VCO is achieved in two forms. One is the variable capacitor C0 and C1, whose capacitance is affected by the voltage V T Control, V T It is generated by filtering the output of the charge pump in the phase-locked loop. In order to obtain better noise characteristics, the adjustment range of C0 and C1 is often small; another way to adjust the frequency is to use a capacitor array controlled by a switch. Figure 2 As shown in N-1 Control each switch. When the switch is closed, the capacitor connected to it is connected to the oscillator circuit. On the contrary, when the capacitor connected to it is open, it will not affect the value of the resonant cavity capacitance. The comprehensive effect of adjusting the VCO output frequency is as follows: Figure 3 As shown, the overall output frequency range is f 0~ f 1, by frequency control word B0 to B N-1 It is divided into N segments, and the frequency range of each segment is determined by the voltage V T control.

[0004] Due to the above VCO output frequency control method, before each phase-locked loop starts working, it is necessary to select the appropriate frequency control word state B0~B N-1 , so that the desired output frequency f out In the frequency control word B0~B N-1 The frequency of the VCO can then be accurately locked to the selected frequency band through the phase-locked loop. f out The functional module that automatically selects the frequency band (and outputs the correct frequency control word) in a phase-locked loop (PLL) system is typically called an automatic frequency calibration (AFC) circuit. In current electronic systems, the frequency stabilization time of the output signal is highly demanding, preferably as short as possible. Reducing the time it takes for the AFC circuit to automatically and correctly select the frequency band has become a key technology in PLL applications.

[0005] The traditional automatic frequency band selection process is to try the frequency band selection control words B0~B N-1 N states, waiting for a long enough time t in each state s , then check whether the loop can be locked normally, t s It must be longer than the phase-locked loop's normal lock settling time, which is determined by the loop bandwidth. (For example, when the phase-locked loop bandwidth is 100 kHz, the time constant for its output frequency establishment is 1 / 2π*100k ≈ 1.5 μs. The settling time usually needs to be greater than or equal to 10 times the time constant, or 15 μs, to achieve sufficient output frequency accuracy.) Therefore, the total frequency band selection time will exceed N*15 μs. Summary of the Invention

[0006] The present invention provides an automatic frequency calibration circuit and a phase-locked loop, aiming to solve at least one of the above technical problems.

[0007] To achieve the above object, the present invention provides an automatic frequency calibration circuit, comprising:

[0008] A frequency discriminator having a frequency division signal input terminal, a reference clock signal input terminal and a voltage signal output terminal;

[0009] The frequency discriminator includes a signal comparison circuit and an integration circuit. The signal comparison circuit is configured to perform a signal current difference between the frequency-divided signal transmitted from the frequency-divided signal input terminal and the reference clock signal transmitted from the reference clock signal input terminal. The integration circuit is configured to convert the current difference into an output voltage and output it through the voltage signal output terminal.

[0010] The frequency-divided signal is configured as a first frequency-divided signal obtained by dividing the first frequency signal output by the voltage-controlled oscillator by an N-frequency divider;

[0011] an analog-to-digital converter having a voltage signal input terminal and a control signal output terminal;

[0012] The analog-to-digital converter receives the voltage signal output by the frequency discriminator through the voltage signal input terminal, converts the voltage signal into a digital signal and outputs it as a frequency control word through the control signal output terminal;

[0013] The frequency control word is configured to be transmitted to the voltage-controlled oscillator to control the voltage-controlled oscillator to generate a second frequency signal, driving the frequency of the second frequency-divided signal obtained after the second frequency signal is divided by the N divider to gradually approach the reference clock signal.

[0014] Optionally, the signal comparison circuit includes: a first comparison branch circuit and a second comparison branch circuit, wherein the first ends of the first comparison branch circuit and the second comparison branch circuit are configured to be connected to a common mode level, and the second ends of the first comparison branch circuit and the second comparison branch circuit are configured to be connected to an intermediate node;

[0015] The first comparison branch circuit and the second comparison branch circuit respectively include a series group of diodes connected in opposite directions and a coupling capacitor connected in parallel to the series group of diodes;

[0016] The intermediate node is configured to perform a signal current difference between the frequency-divided signal input through the coupling capacitor and the reference clock signal and output the current difference to the integration circuit.

[0017] Optionally, the first comparison branch circuit includes a first diode, a second diode and a first coupling capacitor, and the second comparison branch circuit includes a third diode, a fourth diode and a second coupling capacitor;

[0018] The anode of the first diode is connected to the middle node, the anode of the second diode is connected to the cathode of the first diode, the cathode of the second diode is connected to the common mode level, the first end of the first coupling capacitor is connected between the first diode and the second diode, and the second end of the first coupling capacitor is connected to the reference clock signal input terminal;

[0019] Among them, the positive electrode of the third diode is connected to the common mode level, the positive electrode of the fourth diode is connected to the negative electrode of the third diode, the negative electrode of the fourth diode is connected to the intermediate node, the first end of the second coupling capacitor is connected between the third diode and the fourth diode, and the second end of the second coupling capacitor is connected to the frequency division signal input end.

[0020] Optionally, the integration circuit includes an operational amplifier and an integration capacitor;

[0021] Wherein, the non-inverting input terminal of the operational amplifier is connected to the output terminal of the signal comparison circuit, and the inverting input terminal of the operational amplifier is connected to the common mode level;

[0022] The first end of the integrating capacitor is connected to the non-inverting input end of the operational amplifier, and the second end of the integrating capacitor is connected to the output end of the operational amplifier.

[0023] Optionally, the potential of the output terminal of the signal comparison circuit is clamped to a common mode level by an operational amplifier, and the current flowing through the integrating capacitor is a current difference value obtained by subtracting the signal current of the frequency-divided signal from the signal current of the reference clock signal;

[0024] The expression of the current difference is specifically:

[0025]

[0026]

[0027] Where, is the current flowing through the integrating capacitor, is the current value of the reference clock signal flowing into the middle node, is the current value of the reference clock signal flowing out of the middle node, The charge injected into the intermediate node by the reference clock signal for each reference cycle and the charge drawn from the intermediate node for each frequency-divided signal cycle, is the value of the coupling capacitor, is the swing of the reference clock signal and the divided frequency signal.

[0028] Optionally, the output voltage of the voltage signal output terminal of the integration circuit is related to the charge accumulation amount at both ends of the integration capacitor and is proportional to the current difference. The expression of the output voltage for the integral of time is specifically:

[0029] Where C0 is the capacitance of the integrating capacitor, is the output voltage that changes with time t.

[0030] Optionally, the frequency discriminator further includes a filter circuit disposed between the integration circuit and the voltage signal output terminal, the filter circuit including a filter resistor connected in series between the frequency discriminator and the analog-to-digital converter, and a filter capacitor connected in parallel between the filter resistor and the analog-to-digital converter. Optionally, the automatic frequency calibration circuit controls the voltage-controlled oscillator to generate a second frequency signal, driving the frequency of the second frequency-divided signal obtained after the second frequency signal is divided by the N-divider to gradually approach the reference clock signal, and the expression of the open-loop transfer function based on which is specifically:

[0031]

[0032] Where MVCO is the gain of the voltage-controlled oscillator output frequency after the voltage signal output by the frequency discriminator is converted into a frequency control word through the analog-to-digital converter. is the swing of the reference clock signal and the divided frequency signal, is the value of the coupling capacitor, C0 is the capacitance value of the integration capacitor, is the filter resistor, is the filter capacitor, and s is a complex frequency domain variable.

[0033] Optionally, in a process in which the automatic frequency calibration circuit controls the voltage-controlled oscillator to generate the second frequency signal, and drives the frequency of the second frequency-divided signal obtained after the second frequency signal is divided by the N-frequency divider to gradually approach the reference clock signal, an expression for the loop bandwidth is specifically:

[0034]

[0035] Where MVCO is the gain of the voltage-controlled oscillator output frequency after the voltage signal output by the frequency discriminator is converted into a frequency control word through the analog-to-digital converter. is the swing of the reference clock signal and the divided frequency signal, is the value of the coupling capacitor, and C0 is the capacitance value of the integrating capacitor.

[0036] In addition, in order to achieve the above-mentioned object, the present invention further provides a phase-locked loop, comprising: a voltage-controlled oscillator, an N-frequency divider, and the automatic frequency calibration circuit as described in any one of the above.

[0037] The beneficial effect of the present invention is that: an automatic frequency calibration circuit and a phase-locked loop are proposed, by constructing an automatic frequency calibration circuit including a frequency discriminator and an analog-to-digital converter, using the signal comparison circuit and the integration circuit in the frequency discriminator to compare the frequency-divided signal f div With reference clock signal f REF The frequency of the divided signal f div and reference clock signal f REF The signal currents are subtracted and converted into a voltage signal, which outputs a voltage signal proportional to the frequency difference between the two. This voltage signal is then converted via an analog-to-digital converter into a frequency control word for the VCO, which controls the VCO frequency up or down. Ultimately, after stabilization, the frequency divider output frequency is near the reference frequency. Compared to traditional methods, this invention significantly reduces the time required for automatic frequency band selection, thereby significantly reducing the stabilization time of the phase-locked loop frequency switching. This facilitates rapid frequency switching in electronic systems, particularly those requiring rapid scanning across a wide frequency range, such as detection systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a typical architecture diagram of a phase-locked loop in the prior art;

[0039] Figure 2 This is a typical VCO structure diagram;

[0040] Figure 3 Schematic diagram of VCO frequency band control for a typical VCO structure;

[0041] Figure 4 Schematic diagram of the automatic frequency calibration circuit of the present invention in a phase-locked loop;

[0042] Figure 5 is a circuit diagram of a frequency discriminator in an automatic frequency calibration circuit of the present invention;

[0043] Figure 6 This is a schematic diagram of the simulation results of the automatic calibration loop bandwidth;

[0044] Figure 7 Schematic diagram of the simulation results of the automatic calibration loop frequency stabilization time. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0046] An embodiment of the present invention provides an automatic frequency calibration circuit, comprising:

[0047] A frequency discriminator having a frequency division signal input terminal, a reference clock signal input terminal and a voltage signal output terminal;

[0048] The frequency discriminator includes a signal comparison circuit and an integration circuit. The signal comparison circuit is configured to perform a signal current difference between the frequency-divided signal transmitted from the frequency-divided signal input terminal and the reference clock signal transmitted from the reference clock signal input terminal. The integration circuit is configured to convert the current difference into an output voltage and output it through the voltage signal output terminal.

[0049] The frequency-divided signal is configured as a first frequency-divided signal obtained by dividing the first frequency signal output by the voltage-controlled oscillator by an N-frequency divider;

[0050] an analog-to-digital converter having a voltage signal input terminal and a control signal output terminal;

[0051] The analog-to-digital converter receives the voltage signal output by the frequency discriminator through the voltage signal input terminal, converts the voltage signal into a digital signal and outputs it as a frequency control word through the control signal output terminal;

[0052] The frequency control word is configured to be transmitted to the voltage-controlled oscillator to control the voltage-controlled oscillator to generate a second frequency signal, driving the frequency of the second frequency-divided signal obtained after the second frequency signal is divided by the N divider to gradually approach the reference clock signal.

[0053] Specifically, if Figure 4 As shown, the automatic frequency calibration circuit of this embodiment is composed of a frequency discriminator circuit and an analog-to-digital converter (ADC) circuit. When the automatic frequency calibration circuit is working, the VCO output signal enters the frequency discriminator through the N divider, and the frequency discriminator compares the divided signal. f div With reference clock signal f REF The frequency of the two frequencies is proportional to the output voltage signal V FD , which is converted into the frequency control word of VCO through the analog-to-digital converter.

[0054] like Figure 5 As shown in the frequency discriminator circuit, the reference clock signal and the divided frequency signal are respectively coupled through two coupling capacitors C C To the middle node of the two series diodes, both series diodes are connected to the common mode voltage V on one side. CM , one side connected to V MID , but the two sets of series diodes are in opposite directions. V MID After passing through the integration circuit to V AMP , where the integration circuit is composed of the operational amplifier AMP and the integration capacitor C0. AMP After being filtered by capacitors R and C1, the output VFD Assume that the diode in the figure is an ideal diode, that is, the forward conduction voltage is 0 and there is no reverse leakage current (the actual non-ideal diode analysis process is similar and the same results can be obtained). If the reference clock signal and the divided frequency signal swing are both V A , then each reference cycle is injected by the reference clock signal into V MID The charge at the node is C C *V A , similarly, each frequency division signal cycle, from V MID The charge drawn from the node is also C C *V A , converted into current:

[0055]

[0056] Due to the clamping effect of the operational amplifier in the integrator, V MID The potential is always clamped to V CM , then the current flowing through the integrating capacitor C0 is equal to I REF with I div The difference, that is,

[0057]

[0058] Integrator output voltage V AMP Depends on the amount of charge accumulated across the capacitor C0, which is proportional to the current I AMP The integral over time,

[0059]

[0060] V AMP The voltage value after filtering by the filter composed of resistor R and capacitor C1 is the output voltage of the frequency detector V FD .

[0061] From the above description, it can be seen that when the divider frequency is lower than the reference frequency, the current I AMP is positive, V AMP The terminal voltage gradually decreases with time accumulation, V FD The discriminator output voltage V FD After the ADC converts the signal into a digital signal, it generates the VCO frequency control word, which controls the VCO frequency to increase. Conversely, when the divider frequency is higher than the reference frequency, the discriminator output voltage rises. After the ADC converts the signal into the VCO frequency control word, it controls the VCO frequency to decrease. Finally, after stabilization, the divider output frequency is near the reference frequency, which means that the VCO frequency is at the desired output frequency. The stabilization time of the entire automatic calibration depends on the bandwidth of the entire loop. From the above analysis, the open-loop transfer function of the loop is:

[0062]

[0063] Among them, M VCO is the frequency discriminator output voltage V FD After being converted into a frequency control word by the ADC, it controls the gain of the VCO output frequency change. The loop bandwidth is,

[0064]

[0065] By properly designing the above parameter values, the bandwidth of the AFC loop can be set, thereby determining the settling time of the AFC loop. For example, setting V A =1V,N=100,C C =C0=10pF, M VCO =1GHz / V, the AFC loop bandwidth is approximately 1.5MHz, and the AFC loop has a settling time constant of 0.1us. After ten times the settling time constant, or 1us, the AFC loop reaches sufficient stability to obtain the appropriate VCO frequency band control word. Compared to traditional methods, the method described in this invention significantly reduces the time required for automatic frequency band selection, thereby significantly reducing the stabilization time of the phase-locked loop frequency switching. This facilitates rapid frequency switching in electronic systems, particularly those requiring rapid scanning across a wide frequency range, such as detection systems.

[0066] In order to more clearly demonstrate the performance superiority of the automatic frequency calibration circuit proposed in the present invention, simulation result data of the automatic frequency calibration circuit of the present invention are provided below.

[0067] like Figure 6 As shown, Figure 6 The following is the simulation result of automatic calibration loop bandwidth. As can be seen from the figure, the AFC loop bandwidth is set to about 1.6MHz. Figure 7 As shown, Figure 7 This is the simulation result of the automatic calibration loop frequency stabilization time. As can be seen from the figure, when the AFC loop bandwidth is set to 1.6MHz and the reference frequency is 100MHz, after 1us, the frequency of the VCO output signal after division stabilizes to around 100MHz.

[0068] In another embodiment, the present invention further provides a phase-locked loop, comprising: a voltage-controlled oscillator, an N-frequency divider, and the automatic frequency calibration circuit as described in any one of the above.

[0069] Other embodiments or specific implementations of the phase-locked loop of the present invention can refer to the above-mentioned automatic frequency calibration circuit embodiments, which will not be described in detail here.

[0070] It should be understood that, in the description of this specification, reference to terms such as "one embodiment," "another embodiment," "other embodiments," or "first to Nth embodiments" means that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any appropriate manner in any one or more embodiments or examples.

[0071] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0072] The above are only preferred embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An automatic frequency calibration circuit, characterized in that: include: A frequency discriminator having a frequency division signal input terminal, a reference clock signal input terminal and a voltage signal output terminal; The frequency discriminator includes a signal comparison circuit and an integration circuit. The signal comparison circuit is configured to perform a signal current difference between the frequency-divided signal transmitted from the frequency-divided signal input terminal and the reference clock signal transmitted from the reference clock signal input terminal. The integration circuit is configured to convert the current difference into an output voltage and output it through the voltage signal output terminal. The signal comparison circuit includes: a first comparison branch circuit and a second comparison branch circuit, wherein the first ends of the first comparison branch circuit and the second comparison branch circuit are configured to be connected to a common mode level, and the second ends of the first comparison branch circuit and the second comparison branch circuit are configured to be connected to an intermediate node; Wherein, the first comparison branch circuit includes a first diode, a second diode and a first coupling capacitor, and the second comparison branch circuit includes a third diode, a fourth diode and a second coupling capacitor; The anode of the first diode is connected to the middle node, the anode of the second diode is connected to the cathode of the first diode, the cathode of the second diode is connected to the common mode level, the first end of the first coupling capacitor is connected between the first diode and the second diode, and the second end of the first coupling capacitor is connected to the reference clock signal input terminal; The anode of the third diode is connected to the common mode level, the anode of the fourth diode is connected to the cathode of the third diode, the cathode of the fourth diode is connected to the intermediate node, the first end of the second coupling capacitor is connected between the third diode and the fourth diode, and the second end of the second coupling capacitor is connected to the frequency division signal input terminal; The frequency-divided signal is configured as a first frequency-divided signal obtained by dividing the first frequency signal output by the voltage-controlled oscillator by an N-frequency divider; an analog-to-digital converter having a voltage signal input terminal and a control signal output terminal; The analog-to-digital converter receives the voltage signal output by the frequency discriminator through the voltage signal input terminal, converts the voltage signal into a digital signal and outputs it as a frequency control word through the control signal output terminal; The frequency control word is configured to be transmitted to the voltage-controlled oscillator to control the voltage-controlled oscillator to generate a second frequency signal, driving the frequency of the second frequency-divided signal obtained after the second frequency signal is divided by the N divider to gradually approach the reference clock signal.

2. The automatic frequency calibration circuit according to claim 1, wherein: The integration circuit includes an operational amplifier and an integration capacitor; Wherein, the non-inverting input terminal of the operational amplifier is connected to the output terminal of the signal comparison circuit, and the inverting input terminal of the operational amplifier is connected to the common mode level; The first end of the integrating capacitor is connected to the non-inverting input end of the operational amplifier, and the second end of the integrating capacitor is connected to the output end of the operational amplifier.

3. The automatic frequency calibration circuit according to claim 2, wherein: The potential of the output terminal of the signal comparison circuit is clamped to a common mode level by the operational amplifier, and the current flowing through the integrating capacitor is a current difference value obtained by subtracting the signal current of the frequency-divided signal from the reference clock signal; The expression of the current difference is specifically: I AMP =I REF -I div I REF =C C V A f REF I div =C C V A f div Where, I AMP is the current flowing through the integrating capacitor, I REF is the current value of the reference clock signal flowing into the middle node, I div is the current value of the reference clock signal flowing out of the middle node, C C V A C is the charge injected into the middle node by the reference clock signal for each reference cycle and the charge drawn from the middle node for each frequency division signal cycle. C is the value of the coupling capacitor, V A is the swing of the reference clock signal and the divided frequency signal.

4. The automatic frequency calibration circuit according to claim 3, wherein: The output voltage of the voltage signal output terminal of the integration circuit is related to the charge accumulation amount at both ends of the integration capacitor and is proportional to the current difference I AMP The expression of the output voltage for the integral of time is specifically: Where C0 is the capacitance of the integrating capacitor, V AMP (t) is the output voltage that changes with time t.

5. The automatic frequency calibration circuit according to claim 1, wherein: The frequency discriminator further includes a filter circuit arranged between the integration circuit and the voltage signal output terminal, the filter circuit including a filter resistor connected in series between the frequency discriminator and the analog-to-digital converter and a filter capacitor connected in parallel between the filter resistor and the analog-to-digital converter.

6. The automatic frequency calibration circuit according to claim 5, wherein: The automatic frequency calibration circuit controls the voltage-controlled oscillator to generate the second frequency signal, and drives the frequency of the second divided signal obtained after the second frequency signal is divided by the N frequency divider to gradually approach the reference clock signal. The expression of the open-loop transfer function is specifically: Where MVCO is the gain of the voltage controlled oscillator output frequency after the voltage signal output by the frequency discriminator is converted into a frequency control word through the analog-to-digital converter, and V A is the swing of the reference clock signal and the frequency-divided signal, C C is the value of the coupling capacitor, C0 is the capacitance of the integrating capacitor, R is the filter resistor, C1 is the filter capacitor, and s is a complex frequency domain variable.

7. The automatic frequency calibration circuit according to claim 6, wherein: The automatic frequency calibration circuit controls the voltage-controlled oscillator to generate the second frequency signal, and drives the frequency of the second divided signal obtained after the second frequency signal is divided by the N frequency divider to gradually approach the reference clock signal. The expression of the loop bandwidth is specifically: Where MVCO is the gain of the voltage controlled oscillator output frequency after the voltage signal output by the frequency discriminator is converted into a frequency control word through the analog-to-digital converter, and V A is the swing of the reference clock signal and the frequency-divided signal, C C is the value of the coupling capacitor, and C0 is the capacitance value of the integrating capacitor.

8. A phase-locked loop, characterized in that: include: A voltage-controlled oscillator, an N-frequency divider, and an automatic frequency calibration circuit as claimed in any one of claims 1 to 7.

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