An integer order differential analog-to-digital conversion device for intracranial neural field potential acquisition

Abstract

This invention proposes an integer-order differential analog-to-digital converter (ADC) for intracranial neural potential acquisition. First, an integer-order differential operator is designed to calculate arbitrary integer-order incremental codes, which more effectively utilizes the sparsity of intracranial neural potentials, significantly improving the compression rate of intracranial neural potentials. It also offers greater flexibility, with adjustable differential order, adapting to a wider range of intracranial neural potential acquisition applications. Second, a multi-level buffer matrix module is designed to generate arbitrary integer-order incremental code values ​​in a concise and efficient manner. Finally, a serialized bitstream generator is designed to serialize and package integer-order incremental data acquired from multiple parallel channels. This not only offers high scalability but also allows for reliable interfacing with subsequent synchronous clock wireless transmission systems, avoiding the overhead and latency of synchronous-asynchronous interface coordination, further improving signal acquisition efficiency.

Description

Technical Field

[0001] This invention belongs to the field of brain-computer interfaces, and in particular relates to an integer-order differential analog-to-digital converter for acquiring intracranial neural field potentials. Background Technology

[0002] As a disruptive technology at the intersection of neuroscience and engineering, invasive brain-computer interfaces (BCIs) are reshaping the paradigm of rehabilitation for paralyzed patients and treatment for neurological diseases by directly capturing electrical activity in the cerebral cortex through implanted electrode arrays. This technology can not only interpret motor intention signals, helping spinal cord injury patients control robotic arms to perform grasping actions, but also intervene in abnormal brain electrical rhythms through closed-loop electrical stimulation, providing precise treatment options for tremor control in Parkinson's disease. Its high spatiotemporal resolution signal decoding capabilities enable researchers to explore the neural circuit mechanisms of cognitive function with single-neuron precision, accelerating the deep integration of brain-computer interface theory and clinical translational research.

[0003] In invasive systems, intracranial neural field potentials, as core bioelectrical signals reflecting the synchronous firing of neuronal clusters, directly determine the performance boundaries of brain-computer interfaces through their acquisition quality. These signals are formed by the superposition of postsynaptic potentials from cortical pyramidal cells, exhibiting microvolt-level amplitudes and kilohertz-level dynamic ranges. To accurately capture their millisecond-level transient fluctuations, implanted electrodes must penetrate the pia mater to contact the cortical surface, and low-noise amplifiers and high-precision filtering circuits must be used to eliminate electromyographic artifacts. However, this invasive acquisition method presents multiple engineering challenges regarding biocompatibility, long-term electrode stability, and signal fidelity; even the introduction of minute noise can distort the spatiotemporal characteristics of neural coding.

[0004] Traditional acquisition architectures typically employ Nyquist analog-to-digital converters (ADCs) for uniform sampling of intracranial neural field potentials across the entire frequency band. This design suffers from severe energy efficiency bottlenecks when dealing with large-scale parallel acquisition across multiple channels. Since the energy of neural electrical signals is primarily concentrated below 300Hz, and there is strong correlation between adjacent sampling points, the forced high-frequency sampling strategy results in over 70% of the data being redundant. This not only leads to inefficient use of wireless transmission bandwidth but also causes a dramatic increase in the power density of implanted devices. When the number of channels exceeds 128, the system's static power consumption may exceed the 10mW threshold, causing local tissue temperature rise and accelerating the aging of electrode encapsulation materials, seriously threatening the long-term implantation safety of the device.

[0005] To overcome energy efficiency barriers, event-driven incremental coding analog-to-digital conversion technologies (such as Delta-ADC) have emerged. This solution innovatively introduces a dynamic threshold comparison mechanism, triggering quantization only when the signal amplitude exceeds a preset threshold. This adaptive sampling strategy fully utilizes the sparsity of neural signals in the time dimension, intelligently distinguishing the spike waves during epileptic seizures from background noise. This results in data throughput reductions of over 82% in scenarios such as Parkinson's disease monitoring and rhythm acquisition. By constructing a multi-level differential coding tree, the system can simultaneously extract signal amplitude abrupt changes and slope variations, significantly reducing single-channel power consumption and extending the battery life of implanted devices while maintaining action potential waveform details.

[0006] However, despite the theoretically significant improvement in acquisition efficiency offered by Delta-ADCs, current implementations still face several key challenges. First, the incremental coding method used in Delta-ADCs is not always superior to traditional Nyquist-based analog-to-digital converters (ADCs). In certain applications, especially those with frequent or complex signal changes, Delta-ADCs may actually outperform traditional successive approximation ADCs. Furthermore, existing Delta-ADCs generally employ first-order differential computation to generate first-order incremental codes. However, first-order incremental coding does not fully utilize the sparsity of intracranial neural field potentials, resulting in limited compression and insufficient acquisition efficiency. Finally, most existing Delta-ADC systems use asynchronous sampling, while wireless brain-computer interface systems typically employ synchronous digital processing. This leads to significant overhead and latency in coordination between system interfaces, further impacting overall performance and energy efficiency.

[0007] Therefore, to meet the demands of modern brain-computer interfaces for efficient acquisition, low-power transmission, and high-quality signal recovery, it is crucial to design a novel analog-to-digital converter (ADC) capable of effectively compressing intracranial neural potential signals, improving acquisition efficiency, and adapting to wireless transmission requirements. This design not only needs to fully exploit the sparsity characteristics of intracranial neural potentials but also consider the system's power consumption, sampling efficiency, and compatibility with subsequent processing modules. Summary of the Invention

[0008] To overcome the low efficiency of intracranial neural field potential acquisition in existing technologies, this invention provides an integer-order difference analog-to-digital converter (IOD-ADC) for intracranial neural field potential acquisition, which comprehensively improves signal acquisition efficiency while maintaining the simplicity of the circuit topology. First, an integer-order differential operator is designed to calculate arbitrary integer-order incremental codes. Compared to existing first-order incremental codes, this not only more effectively utilizes the sparsity of intracranial neural field potentials and significantly improves the compression ratio, but also offers greater flexibility, with adjustable differential order to adapt to more intracranial neural field potential acquisition application scenarios. Second, a multi-level buffer matrix module is designed to generate arbitrary integer-order incremental code values ​​in a concise and efficient manner. Finally, a serialized bitstream generator is designed to serialize and package integer-order incremental data acquired from multiple parallel channels. This not only has high scalability, applicable to multiple channel acquisitions, but also reliably interfaces with subsequent synchronous clock wireless transmission systems, avoiding the overhead and latency of synchronous-asynchronous interface coordination, further improving signal acquisition efficiency.

[0009] This invention relates to an integer-order differential analog-to-digital converter (ADC) for intracranial neural field potential acquisition. The circuit comprises a multiplexer, a multi-level buffer matrix module, a DAC controller, a DAC, a comparator, an increment counter, and a serialized bitstream generator. The multiplexer is controlled by the global clock CLK of the IOD-ADC. ADC The system controls the switching of acquisition channels every clock cycle and stabilizes the current acquisition signal to support multi-channel parallel acquisition.

[0010] Furthermore, the multi-level buffer matrix module is controlled by the global clock CLK of the IOD-ADC. ADC The control unit is responsible for storing and outputting the last acquired value for each channel to support the calculation of incremental codes of arbitrary integer order.

[0011] Furthermore, the DAC controller is used to read the previous acquisition value from the multi-level buffer matrix module and, in conjunction with the output of the incremental counter, generate DAC control codes.

[0012] Furthermore, the DAC reads the DAC control code output by the DAC controller, converts it into a signal to be compared, and after multiple comparisons, stores the final DAC output as the current acquisition value of the current channel in the multi-level buffer matrix module.

[0013] Furthermore, the comparator is used to compare the signal to be acquired output from the multiplexer with the signal to be compared output from the DAC, and inputs the comparison result into the increment counter for increment counting.

[0014] Furthermore, the increment counter is controlled by the global clock CLK of the IOD-ADC. ADC The control system reads the comparator's output in each clock cycle, calculates the integer increment between the current acquired signal and the previous acquired value, and transmits the increment to the DAC controller and the serialized bit stream generator.

[0015] Furthermore, the serialized bitstream generator is controlled by the global clock CLK of the IOD-ADC. ADC The control system stores and converts the signal increment output by the increment counter into a bit stream in each clock cycle, compresses the data, and serializes and packages it to ensure the synchronization of data transmission, generating the final bit stream output by the IOD-ADC.

[0016] This invention first designs an integer-order differential operator to calculate arbitrary integer-order incremental codes. Compared to existing first-order incremental codes, this not only more effectively utilizes the sparsity of intracranial neural potentials and significantly improves the compression rate of intracranial neural potentials, but also offers greater flexibility, with an adjustable differential order to adapt to more intracranial neural potential acquisition application scenarios. Secondly, a multi-level buffer matrix module is designed to generate arbitrary integer-order incremental code values ​​in a concise and efficient manner. Finally, a serialized bitstream generator is designed to serialize and package integer-order incremental data acquired from multiple parallel channels. This not only has high scalability, applicable to multiple channel acquisitions, but also reliably interfaces with subsequent synchronous clock wireless transmission systems, avoiding the overhead and latency of synchronous-asynchronous interface coordination, further improving signal acquisition efficiency. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This invention presents the overall architecture of an integer-order differential analog-to-digital converter for intracranial neural field potential acquisition.

[0019] Figure 2 This is a schematic diagram of a multi-level buffer matrix module;

[0020] Figure 3 This is a flowchart illustrating the execution process of the multi-level buffer matrix module.

[0021] Figure 4 This is a schematic diagram of the DAC controller.

[0022] Figure 5 Here is a diagram of the DAC structure;

[0023] Figure 6 Here is a diagram of the comparator structure;

[0024] Figure 7 This is a schematic diagram of the working principle of an incremental counter.

[0025] Figure 8 Here is an example timing diagram for an increment counter;

[0026] Figure 9 This is a schematic diagram of the working principle of a serialized bit stream generator.

[0027] Figure 10 Data results acquired by two different ADCs;

[0028] Figure 11 The result of normalizing the data acquired by the two ADCs;

[0029] Figure 12 This is the result of converting the data acquired by the two ADCs into a bitstream;

[0030] Figure 13 To count the number of 0s and 1s in the bit stream and the total number of binary values. Detailed Implementation

[0031] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0032] For a time series signal X = [x1, x2, ..., xn] with N points, N ] T Its r-th order difference operator is defined as:

[0033]

[0034] Where x i It is the i-th element in signal X, where r is a positive integer. Let represent the number of combinations of r choosing j, and Y be the increment of signal X after r-order difference calculation. r It is an r-order difference operator, which can be represented in matrix form as follows:

[0035]

[0036] As can be seen from the above formula, when calculating the r-th order increment of the current data point, it is necessary to obtain the values ​​of the previous r data points.

[0037] Taking the second-order difference operator as an example, its matrix form is:

[0038]

[0039] To calculate the second-order difference increment value of the current data point, it is first necessary to obtain the values ​​of the previous two data points. The second-order minuend y is then calculated. i =(2x i-1 -x i-2 Then use the currently collected data point x i Subtract y i The second-order difference increment value z is obtained. i =x i -y i =x i -(2x i-1 -x i-2 ).

[0040] Taking the third-order difference operator as an example, its matrix form is:

[0041]

[0042] To calculate the third-order difference increment value of the current data point, it is first necessary to obtain the values ​​of the previous three data points. The third-order minuend y is then calculated. i =(-3x i-1 +3x i-2 -x i-3 Then use the currently collected data point x i Subtract y i The third-order difference increment value z is obtained. i =x i -y i =x i -(-3x i-1 +3x i-2 -x i-3 ).

[0043] To achieve r-order incremental acquisition, this invention proposes an integer-order differential analog-to-digital converter for intracranial neural field potential acquisition, the overall architecture of which is as follows: Figure 1 As shown, this device consists of a multiplexer, a multi-level buffer matrix module, a DAC controller, a DAC, a comparator, an increment counter, and a serialized bitstream generator.

[0044] The multiplexer is powered by the global clock CLK of the IOD-ADC. ADCThe control switches the acquisition channel every clock cycle and stabilizes the current acquisition signal after the channel switch, thus supporting multi-channel parallel acquisition. The multiplexer in this circuit adopts a standard time-division multiplexing structure, allowing L channels of signals to share a single physical channel for transmission, and stabilizing the signal at different clock cycles (CLK). ADC The channel is occupied sequentially within the cycle to achieve efficient data acquisition.

[0045] In this invention, the time-division multiplexing structure is implemented through a multiplexer circuit. The switch position changes once per clock cycle to select different acquisition channels. After the multiplexer, the signal enters the sample-and-hold circuit, where a switched capacitor circuit physically holds the signal, ensuring signal stability during acquisition and guaranteeing the accuracy and reliability of subsequent acquisitions.

[0046] like Figure 2 As shown, the multi-level buffer matrix module is controlled by the global clock CLK of the IOD-ADC. ADC The control module is responsible for storing and outputting the values ​​of the previous r data points for each channel to support the calculation of the r-th order minuend, while avoiding the complexity of the traditional first-in-first-out buffer structure.

[0047] Specifically, the module comprises a storage matrix and a computation matrix. The storage matrix has r rows and L columns. In each clock cycle, data from the DAC input is fed into the left side of the r-th row. Data from the rightmost edge of each row is shifted out of the storage matrix and input into the computation matrix for calculation. Simultaneously, the data in the storage matrix moves in a circular fashion; data shifted out of the lower row is simultaneously shifted into the left side of the upper row. Except for the r-th row, which can receive data from the DAC, data in other rows can only be shifted in from the corresponding row below it and cannot receive input data from outside the module. Therefore, the storage matrix forms a 1-input, r-output structure. This structure is designed to work in conjunction with the computation matrix to read data in a fixed manner, thereby avoiding increased circuit complexity and power consumption due to frequent switching of read ports.

[0048] The computation matrix consists of a series of computation units, including shift units, addition units, and inversion units. The shift units can shift the input data bit-wise to the left or right to perform multiplication or division operations. The addition units are used to perform addition operations on the input data. The inversion unit is used to invert the sign bit of the input data to obtain the inverted value. By combining these computation units, the calculation of an r-order minuend can be realized, and the difference increment value can be output to the DAC controller, thus completing the task of the multi-level buffer matrix module.

[0049] The multi-level buffer matrix module is controlled by the global clock CLK of the IOD-ADC. ADCThe control process involves receiving one data point, reading from the storage matrix, and performing one calculation per cycle. Taking a 3rd-order IOD-ADC as an example, assuming the current cycle is i, and the first channel needs to be sampled to obtain the sampled value... At this point, the third-order difference increment is... The execution process is as follows Figure 3 As shown, the details are as follows:

[0050] Assume the data stored in the current storage matrix is:

[0051]

[0052] Step 1: Extract the first 3 acquisition values ​​of the first channel from the 3 output terminals of the storage matrix. and The three collected values ​​were input into the calculation matrix and the calculations were performed respectively.

[0053] Step 2: Activate an inverted cell in the computation matrix, and... Input the inverted element of the computation matrix to obtain

[0054] The third step is to activate a shift unit and an adder unit in the computation matrix, and then... Shift the input to the shift unit left by 1 bit to obtain... Then input the result into the addition unit and Add them together to get

[0055] The fourth step is to activate one shift unit, one addition unit, and one inversion unit in the computation matrix, and then... Shift the input to the shift unit left by 1 bit to obtain... Then input the result into the addition unit and Add them together to get Finally, input the result into the inverting unit to obtain...

[0056] Fifth step: Activate an addition unit in the computation matrix, and input the three results obtained from steps two through four into the addition unit to obtain... This is the output third-order minuend.

[0057] like Figure 4 As shown, the DAC controller is used to read the r-th order minuend output by the multi-level buffer matrix module and, in combination with the output of the increment counter, generate DAC control code.

[0058] Specifically, affected by the global clock CLK ADCUnder control, the IOD-ADC will sequentially acquire data from L channels, one channel per clock cycle. Assuming we are currently acquiring data from the first channel, we will obtain the acquired value... The DAC controller's workflow is as follows:

[0059] The first step is to calculate the r-th order minuend y using a multi-level buffer matrix module. i .

[0060] Step 2: Input the increment value kΔ into the increment counter, and the r-order minuend y i Add them together to get the value y to be compared. i +kΔ, where Δ is the smallest quantization unit of the IOD-ADC. The initial value of the increment is 0Δ.

[0061] Step 3: Compare the value y to be compared i +kΔ is used as the DAC control code, input to the DAC, and converted into the corresponding signal to be compared.

[0062] Step 4: Input the signal to be compared into the comparator and compare it with the signal to be acquired. If the signal to be acquired is greater than the signal to be compared, the increment counter is incremented by 1Δ, and the increment value becomes (k+1)Δ; otherwise, it is decremented by 1Δ, and the increment value becomes (k-1)Δ.

[0063] Step 5: Repeat steps 2 through 4 until the difference between the signal to be acquired and the signal to be compared is less than 1Δ. At this point, stop the loop and use the DAC output as the acquired value.

[0064] Step 6: Store back into the multilevel buffer matrix module and update the value of each row in the multilevel buffer matrix module.

[0065] The process described above can then be repeated to acquire data from channels 2 to L. After acquiring data from channel L, return to acquiring data from channel 1.

[0066] like Figure 5 As shown, the DAC reads the DAC control code output by the DAC controller, converts it into a signal to be compared, and after multiple comparisons, stores the final DAC output as the current acquisition value of the current channel in the multi-level buffer matrix module.

[0067] Specifically, the DAC employs an 8-bit capacitor divider structure, consisting of an array of eight weighted capacitors with sizes C, 2C, 4C, 8C, C, 2C, 4C, and 8C respectively. Before conversion begins, the Reset switch is closed, grounding the upper plates of all capacitors and discharging the capacitor array. During conversion, the Reset switch is opened, and the lower plates of the eight binary weighted capacitors are connected to V according to the control code.ref Alternatively, a 1.067C attenuation capacitor is added to divide the capacitor array into two parts, thereby reducing the variety of capacitors. The rightmost part of the DAC forms a voltage follower structure through an operational amplifier with negative feedback, isolating the capacitor array from the DAC output to reduce output impedance and enhance load-driving capability.

[0068] like Figure 6 As shown, the comparator compares the signal to be acquired from the multiplexer output with the signal to be compared from the DAC output, and inputs the comparison result into the increment counter for increment counting. To reduce power consumption, the IOD-ADC uses a dynamic comparator. The signal to be acquired is generated by Vi. np The input signal to be compared is V. inn The input is V, and the comparison result is given by V. out Terminal output.

[0069] like Figure 7 As shown, the increment counter is controlled by the global clock CLK of the IOD-ADC. ADC The control system reads the comparator's output in each clock cycle, calculates the integer increment between the current acquired signal and the previous acquired value, and transmits the increment to the DAC controller and the serialized bit stream generator.

[0070] Specifically, the increment counter contains two modules: a sign register consisting of a 1-bit register circuit to store the sign of the increment value, and an 8-bit binary counter consisting of 8 D flip-flops to store the magnitude of the increment value.

[0071] The increment counter operates as follows: The initial increment value is 0Δ. When the comparator output is positive, it is determined that the signal to be acquired is greater than the signal to be compared, so the increment counter is incremented by 1Δ, the sign register is positive, and the increment value becomes (0+1)Δ. When the comparator output is negative, it is determined that the signal to be acquired is less than the signal to be compared, so the increment counter is decremented by 1Δ, the sign register is negative, and the increment value becomes (0-1)Δ. After each judgment, the increment value is output to the DAC controller to generate DAC control code. The above judgment steps are repeated until the difference between the signal to be acquired and the signal to be compared is less than 1Δ. At this point, the loop stops, and the sign in the sign register is concatenated with the value in the 8-bit binary counter to obtain the final integer increment value.

[0072] like Figure 8 The image shows an example timing diagram for an increment counter. At each global clock CLK... ADC One channel is sampled at a time within each clock cycle. The output of the multiplexer remains stable within each clock cycle, allowing the incremental counter to perform analog-to-digital conversion.

[0073] During the first cycle, the increment counter performs analog-to-digital conversion on channel CH1. In CLK... ADC During the low-level period of CLK, both the signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the signal to be compared from channel CH1. ADC During the high-level period, the increment counter begins analog-to-digital conversion. The first comparison finds that the signal to be compared is less than the signal to be acquired, so the increment is increased by 1Δ, and the comparison continues. After six increments of 1Δ, the difference between the signal to be compared and the signal to be acquired is less than 1Δ, at which point the conversion is complete. In the next CLK... ADC At the start of the cycle, the increment counter outputs the increment value of channel CH1, which is +6Δ.

[0074] During the second cycle, the increment counter performs analog-to-digital conversion on the CH2 channel. (CLK) ADC During the low-level period of CLK, both the signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the signal to be compared from channel CH2. ADC During the high-level period, the increment counter begins analog-to-digital conversion. The first comparison finds that the difference between the signal to be compared and the signal to be acquired is less than 1Δ, at which point the conversion is complete. In the next CLK... ADC At the start of the cycle, the increment counter outputs the increment value of the CH2 channel, which is 0Δ. At this point, it is assumed that there is no increment between the current acquisition and the previous acquisition of the CH2 channel.

[0075] During the third cycle, the increment counter performs analog-to-digital conversion on channel CH3. In CLK... ADC During the low-level period, both the signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the signal to be compared from channel CH3. In CLK... ADC During the high-level period, the increment counter begins analog-to-digital conversion. The first comparison finds that the signal to be compared is greater than the signal to be acquired, so the increment is decreased by 1Δ, and the comparison continues. After four decrements of 1Δ, the difference between the signal to be compared and the signal to be acquired is less than 1Δ, at which point the conversion is complete. In the next CLK... ADC At the start of the cycle, the increment counter outputs the increment value of channel CH3, which is -4Δ.

[0076] Other channels will undergo analog-to-digital conversion cycle by cycle, following the above conversion rules.

[0077] like Figure 9 As shown, the serialized bitstream generator is controlled by the global clock CLK of the IOD-ADC. ADC The control system stores and converts the signal increment output by the increment counter into a bit stream in each clock cycle, compresses the data, and serializes and packages it to ensure the synchronization of data transmission, generating the final bit stream output by the IOD-ADC.

[0078] Specifically, in each global clock CLK ADC On the rising edge of the signal, the event detector reads the increment value from the increment counter and determines whether the increment value constitutes an integer-order increment event. When the increment value is not 0Δ, it indicates that the currently acquired signal is different from the signal to be compared, and it can be determined as an integer-order increment event. At this time, the increment value is stored in the event register.

[0079] Each integer-order increment event requires 9 + log2L bits of storage space, where log2L bits are used for numbering the L channels, 1 bit is used for the increment value sign, and 8 bits are used to store the increment value magnitude. In addition, the system is equipped with a 9 + log2L bit replica memory for parallel data caching and processing to improve data throughput efficiency.

[0080] After all L channels have completed one acquisition cycle, a complete data acquisition frame is formed. Upon completion of each acquisition frame, the finite state machine generates an enable signal ENA and inputs it to the bitstream clock generator. This clock generator has a built-in ring oscillator specifically designed to provide the clock CLK for bitstream packetization. BIT .

[0081] Subsequently, the finite state machine scans the data in the event register and, based on CLK... BIT The clock is packaged into a bit stream, which is then used to generate the IOD-ADC data bit stream.

[0082] This invention compares the proposed IOD-ADC with the state-of-the-art Nyquist ADC. The experimental setup is as follows: Animals were anesthetized and held still in their cages. Electrodes were implanted in the head, leading to two electrode channels. Each electrode channel possessed the same neural field potential. Channel 1 was acquired using a Nyquist ADC, and channel 2 was acquired using an IOD-ADC. The IOD-ADC differential orders were selected as 1, 2, and 3 for comprehensive comparison. The acquired data were transmitted to a computer via wired connection for analysis.

[0083] Data acquired by the two ADCs, such as Figure 10 As shown, the data acquired by the Nyquist ADC has large fluctuations and large amplitudes, while the data acquired by the IOD-ADC has smaller fluctuations, with most acquired values ​​being very close to 0 and only a few acquired values ​​being relatively large, showing high sparsity.

[0084] The data acquired by the two ADCs were sorted in descending order and then normalized. The data is as follows: Figure 11 As shown, the data collected by the IOD-ADC is significantly more sparsity than that collected by the Nyquist ADC.

[0085] Convert the data acquired by the two ADCs into a bitstream, such as Figure 12 As shown, the bitstream of the IOD-ADC is much sparser than that of the Nyquist ADC.

[0086] The data acquired by the two ADCs is converted into a bitstream, and the number of 0s and 1s in the bitstream and the total number of binary values ​​are counted, such as... Figure 13 As shown, the data volume of the first-order IOD-ADC bitstream is 47.3% of that of the Nyquist ADC bitstream, the second-order IOD-ADC bitstream is 43.2% of that of the Nyquist ADC bitstream, and the third-order IOD-ADC bitstream is 41.4% of that of the Nyquist ADC bitstream.

[0087] The above demonstrates that the amount of data that an IOD-ADC needs to transmit is significantly less than that required by a Nyquist ADC, thus resulting in higher energy efficiency.

[0088] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0089] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0090] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0091] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0092] In the embodiments provided by this invention, it should be understood that the disclosed apparatus / terminal devices and methods can be implemented in other ways. For example, the apparatus / terminal device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0093] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0094] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0095] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0096] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. An integer-order differential analog-to-digital converter (IOD-ADC) for acquiring intracranial neural field potentials, the device comprising a multiplexer, a multi-level buffer matrix module, a DAC controller, a DAC, a comparator, an increment counter, and a serialized bit stream generator, for acquiring intracranial neural field potential signals; The multiplexer, multi-level buffer matrix module, increment counter, and serialized bitstream generator are all affected by the global clock CLK of the IOD-ADC. ADC control; The multiplexer switches the acquisition channel in each clock cycle and stabilizes the current acquisition signal to support multi-channel parallel acquisition; The multi-level buffer matrix module is responsible for storing and outputting the previous acquisition value of each channel to support the calculation of incremental encoding of arbitrary integer order; The DAC controller is used to read the previous acquisition value from the multi-level buffer matrix module and, in conjunction with the output of the incremental counter, generate DAC control code. The DAC reads the DAC control code output by the DAC controller, converts it into a signal to be compared, and after multiple comparisons, stores the final DAC output as the current acquisition value of the current channel into the multi-level buffer matrix module. The comparator is used to compare the signal to be acquired output from the multiplexer with the signal to be compared output from the DAC, and input the comparison result into the increment counter for increment counting; In each clock cycle, the increment counter reads the output of the comparator, calculates the integer increment between the current acquired signal and the previous acquired value, and transmits the increment to the DAC controller and the serialized bit stream generator. The serialized bitstream generator stores and converts the signal increment output by the increment counter into a bitstream in each clock cycle, generating the final bitstream output by the IOD-ADC.

2. An integer-order differential analog-to-digital converter according to claim 1, wherein the multiplexer adopts a standard time-division multiplexing structure, the time-division multiplexing structure is implemented by a multiplexer circuit, and the switch position is switched once in each clock cycle to select different acquisition channels.

3. An integer-order differential analog-to-digital converter according to claim 1, wherein the multi-level buffer matrix module comprises a storage matrix and a computation matrix; The storage matrix contains OK Columns, reading data in a fixed format; The computation matrix consists of shift units, addition units, and inversion units. The shift units shift the input data bit-wise to the left or right to perform multiplication or division operations. The addition units perform addition operations on the input data. The inversion unit inverts the sign bit of the input data to obtain its inverted value. By combining these computation units, it is possible to achieve... The minuend is calculated, and the differential increment value is output to the DAC controller, thus completing the task of the multi-level buffer matrix module.

4. An integer-order differential analog-to-digital converter according to claim 3, wherein the storage matrix, in each clock cycle, inputs data from the DAC input to the... To the left of each row, the rightmost data in each row is moved out of the storage matrix and input into the calculation matrix for computation; simultaneously, the data in the storage matrix is ​​shifted in a circular motion, meaning that data moved out of the lower row is simultaneously moved into the left side of the upper row; except for the first row... Data from lines other than the DAC input data can only be moved in from the corresponding line below it, and cannot receive input data from outside the module.

5. An integer-order differential analog-to-digital converter according to claim 1, wherein the DAC controller is used to read the output of the multi-level buffer matrix module. The minuend is used, and combined with the output of the increment counter, to generate the DAC control code.

6. An integer-order differential analog-to-digital converter according to claim 1, wherein the DAC controller operates as follows: The first step is to calculate using a multi-level buffer matrix module. minuend ; Step 2: The increment counter increments the value. enter, minuend Add them together to get the value to be compared. ,in This is the smallest quantization unit for the IOD-ADC, where the initial value of the increment is... ; Step 3: Compare the values ​​to be compared As the DAC control code, it is input into the DAC and converted into the corresponding signal to be compared; Step 4: Input the signal to be compared into the comparator and compare it with the signal to be acquired; If the signal to be acquired is greater than the signal to be compared, the increment counter increments. The increment value becomes Otherwise reduce The increment value becomes ; Step 5: Repeat steps 2 through 4 until the difference between the signal to be acquired and the signal to be compared is less than 1. At this point, the loop stops, and the output of the DAC at this moment is used as the sampled value. ; Step 6: Store back into the multilevel buffer matrix module and update the value of each row in the multilevel buffer matrix module.

7. An integer-order differential analog-to-digital converter according to claim 1, wherein the DAC is implemented using an 8-bit capacitor voltage divider structure; and the comparator is a dynamic comparator.

8. An integer-order differential analog-to-digital converter according to claim 1, wherein the increment counter comprises a sign register and an 8-bit binary counter, the sign register being composed of a 1-bit register circuit for storing the sign of the increment value, and the 8-bit binary counter being composed of 8 D flip-flops for storing the magnitude of the increment value.

9. An integer-order differential analog-to-digital converter according to claim 8, wherein the operation of the increment counter is as follows: the initial value of the increment is... When the comparator output is positive, it is determined that the signal to be acquired is greater than the signal to be compared, and the increment counter is incremented. The sign register is positive, and the increment value becomes... When the comparator output is negative, it indicates that the signal to be acquired is less than the signal to be compared, and the increment counter is decremented. The sign register is negative, and the increment value becomes... After each judgment, the incremental value is output to the DAC controller to generate DAC control code; the above judgment steps are repeated until the difference between the signal to be acquired and the signal to be compared is less than 1. At this point, the loop stops, and the sign in the sign register and the value in the 8-bit binary counter are concatenated to obtain the final integer increment value. in, It is the smallest quantization unit of the IOD-ADC.

10. An integer-order differential analog-to-digital converter according to claim 1, wherein the serialized bitstream generator comprises an event judge, an event register, a finite state machine, a bitstream clock generator, and a bitstream packer.

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