Fault Injection and Fault Tolerance Test Device Based on Network Time Synchronization Protocol

Abstract

This invention discloses a fault injection and fault tolerance testing device based on a network time synchronization protocol, comprising: a first data interface, a traffic splitting module, a test configuration module, a fault injection module, a time synchronization module, a synchronization status monitoring module, and a second data interface. The fault injection module injects faults into synchronization frames according to fault injection configuration information to obtain fault-injected synchronization frames. The time synchronization module implements the network time synchronization protocol function based on the fault-injected synchronization frames and outputs response synchronization frames. The fault injection module injects faults into the received response synchronization frames to obtain fault-injected response synchronization frames. The synchronization status monitoring module monitors the working status of the time synchronization module, obtains status monitoring information, and evaluates the fault tolerance of the time synchronization function based on the status monitoring information. This invention implements fault tolerance testing of devices with time synchronization functions through hardware logic, making the fault tolerance testing results more reliable.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of communication, and particularly relates to a fault injection fault-tolerant test device based on a network time synchronization protocol. BACKGROUND

[0002] With the wide application of Ethernet data transmission technology, the continuous improvement of data transmission rate and the proposal and development of time deterministic network, higher requirements are put forward for the synchronization accuracy, fault tolerance and synchronization overhead of network time synchronization technology. In practice, in order to avoid the uncertain time delay and jitter caused by software processing operation, the time synchronization algorithm is usually implemented in the data link layer of the network.

[0003] When designing a device with a time synchronization function, it is necessary to test the fault tolerance of the time synchronization module in the device that implements the network time synchronization function to ensure that it meets the fault tolerance requirements. In the prior art, when performing fault tolerance testing, the basic function testing and fault tolerance testing of the time synchronization algorithm are usually realized by first building a network topology through software simulation. However, there are often differences between the simulation environment and the real environment, so that the simulation results and the real performance also have certain differences. In addition, when testing a device with a time synchronization function in a network that needs to run a time synchronization algorithm (such as a time-triggered Ethernet), the prior art focuses more on testing the protocol consistency of the device, and ignores the influence of the internal state change of the device on the fault tolerance.

[0004] Therefore, there is an urgent need for a scheme that can test the fault tolerance of the time synchronization function in a real environment, so that the test results are more reliable. SUMMARY

[0005] In order to solve the above problems existing in the prior art, the present application provides a fault injection fault-tolerant test device based on a network time synchronization protocol.

[0006] The technical problem to be solved by the present application is solved by the following technical scheme:

[0007] A fault injection fault-tolerant test device based on a network time synchronization protocol, comprising: a first data interface, a shunt module, a test configuration module, a fault injection module, a time synchronization module, a synchronization state monitoring module and a second data interface;

[0008] The first data interface is used to receive network data; the network data includes service frames and synchronization frames;

[0009] The shunt module is used to perform frame shunting on the network data, so that the synchronization frames enter the fault injection module;

[0010] The test configuration module is used to obtain fault injection configuration information and generate fault injection instructions based on the fault injection configuration information and send them to the fault injection module.

[0011] The fault injection module is used to inject faults into the received synchronization frame according to the fault injection instruction, and output the fault injection synchronization frame to the time synchronization module.

[0012] The time synchronization module is used to implement the network time synchronization protocol function according to the fault injection synchronization frame, and to output a response synchronization frame to the fault injection module according to the fault injection synchronization frame.

[0013] The fault injection module is further configured to inject faults into the received response synchronization frame according to the fault injection instruction, so as to obtain a fault injection response synchronization frame.

[0014] The second data interface is used to output the fault injection response synchronization frame;

[0015] The synchronization status monitoring module is used to monitor the working status of the time synchronization module, obtain status monitoring information, and evaluate the fault tolerance of the time synchronization function based on the status monitoring information.

[0016] Optionally, the device further includes: a synchronization logic hardening module;

[0017] The synchronization logic hardening module is used for:

[0018] The fault injection synchronization frame output by the fault injection module is reinforced with synchronization logic, so that the time synchronization module can implement the network time synchronization protocol function based on the fault injection synchronization frame reinforced with synchronization logic.

[0019] The response synchronization frame output by the time synchronization module is reinforced with synchronization logic, so that the fault injection module can inject faults into the received response synchronization frame after the synchronization logic is reinforced.

[0020] Optionally, the device further includes: a status reporting module;

[0021] The status reporting module is used to convert the status monitoring information into a format and report it to the host computer so as to realize the fault tolerance assessment of the time synchronization function in the host computer.

[0022] Optionally, the device further includes: a storage module;

[0023] The storage module is used to store the status monitoring information;

[0024] The status reporting module is specifically used to read status monitoring information from the storage module, convert the format, and then report it to the host computer.

[0025] Optionally, the synchronization status monitoring module is specifically used for:

[0026] By monitoring the execution status, transmission time, and frame content of the fault injection synchronization frame in the time synchronization module, it is determined whether the time synchronization module is in an abnormal state, and status monitoring information is obtained.

[0027] Optionally, the synchronization logic hardening includes: executing a central guard inspection mechanism (CGIM) and learning and predicting synchronization frames.

[0028] Optionally, the fault injection configuration information includes: fault type, fault frequency, number of faults, fault input port, and fault output port.

[0029] Optionally, the device is applied to an FPGA.

[0030] Optionally, the FPGA is applied to a network interface card (NIC) device, a switch device, or a bridge device.

[0031] The fault injection and fault tolerance testing device based on a network time synchronization protocol provided by this invention includes a first data interface, a traffic splitting module, a test configuration module, a fault injection module, a time synchronization module, a synchronization status monitoring module, and a second data interface. The fault injection module injects faults into synchronization frames according to fault injection configuration information, simulating possible fault types during data transmission, thereby testing the fault tolerance of the time synchronization function. The synchronization status monitoring module monitors the functional status of the time synchronization module in real time, thereby determining whether the time synchronization module functions abnormally under fault injection conditions, and assessing the fault tolerance of the time synchronization function accordingly.

[0032] This invention implements synchronous logic hardening function through a synchronous logic hardening module, so that when the fault tolerance does not meet the requirements, the fault tolerance can be further improved through synchronous logic hardening.

[0033] This invention implements fault tolerance testing for devices with time synchronization functions through hardware logic, making up for the limitations of the original theoretical analysis and software simulation, making the fault tolerance test results more reliable, and providing a more reliable reference for the design of devices with time synchronization functions.

[0034] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0035] Figure 1 This is a structural diagram of a fault injection and fault tolerance testing device based on a network time synchronization protocol provided in an embodiment of the present invention;

[0036] Figure 2This is a structural diagram of another fault injection and fault tolerance testing device based on a network time synchronization protocol provided in an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of a fault injection configuration information format for a fault injection fault-tolerant testing device based on a network time synchronization protocol provided in an embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram of the status monitoring information format of the fault injection fault-tolerant testing device based on the network time synchronization protocol provided in this embodiment of the invention. Detailed Implementation

[0039] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0040] To enable time synchronization fault tolerance testing of devices with time synchronization capabilities in a real-world environment, thereby obtaining more reliable fault tolerance test results and providing a reliable reference for the design of such devices, this invention proposes a fault injection fault tolerance testing device based on a network time synchronization protocol, such as... Figure 1 and Figure 2 As shown, the device includes: a first data interface, a traffic splitting module, a test configuration module, a fault injection module, a time synchronization module, a synchronization status monitoring module, and a second data interface.

[0041] The first data interface is used to receive network data, which includes service frames and synchronization frames.

[0042] Specifically, the first data interface may include a physical layer and a MAC generic IP core. The first data interface receives network data, specifically by converting the received network physical signals into network data frames at the data link layer.

[0043] For example, in a TTE network, the first data interface is specifically used to convert the network's physical signals into standard TTE format data at the data link layer, resulting in a TTE network data frame. TTE (Time-Triggered Ethernet) is a time-deterministic network protocol widely used in aerospace, automotive (e.g., in-vehicle networks), industrial control, and other scenarios with stringent timing requirements. A TTE data frame extends the standard Ethernet frame by adding time-triggered fields to support time synchronization and deterministic scheduling. A TTE data frame typically includes: a standard Ethernet header, TTE-specific fields, a data payload, and a frame check sequence.

[0044] The splitting module is used to split network data into frames, allowing synchronization frames to enter the fault injection module.

[0045] Specifically, the traffic splitting module identifies synchronization frames based on the frame type field and then distributes them to the fault injection module. Furthermore, different service frame processing methods can be selected depending on the test scenario. When only the device's time synchronization function is being tested, service frames can be discarded without processing. When both service and time synchronization functions need to be tested simultaneously, the traffic splitting module can distribute service frames to other processing modules or transmission paths within the test device to complete the corresponding service functions. In this case, a data selection output module can be introduced to sort and select the service frames and response synchronization frames to be output, and then output them separately through the second data interface.

[0046] The test configuration module is used to obtain fault injection configuration information and generate fault injection commands based on the fault injection configuration information and send them to the fault injection module.

[0047] In one implementation, the host computer generates fault injection configuration information, and the test configuration module obtains this information via the Peripheral Component Interconnect Express (PCIE) interface. For example... Figure 3 As shown, the fault injection configuration information includes: fault type, fault frequency, number of faults, fault input port, and fault output port. It can be understood that the fault input port and fault output port are ports of the test equipment.

[0048] The test configuration module generates fault injection instructions based on the fault injection configuration information. This means parsing the fault injection configuration information according to pre-agreed rules and translating it into fault injection instructions that can be executed by the fault injection module.

[0049] The fault injection module is used to inject faults into the received synchronization frames according to the fault injection instructions, and output the fault injection synchronization frames to the time synchronization module.

[0050] Here, by injecting faults into the synchronization frames, abnormal scenarios that may occur during data transmission (such as frame loss, delay, and tampering) can be simulated. This allows testing whether the behavior of the time synchronization function under fault conditions meets design expectations, thereby evaluating its fault tolerance. Fault injection types can include: modifying the frame type field, extending the frame dwell time, modifying the synchronization information field, and changing the frame length.

[0051] Specifically, this will be illustrated by taking the example of tampering with the content of synchronization frames in a TTE network based on the AS6802 time synchronization protocol to simulate a transparent clock anomaly. In a stable TTE network, synchronization frames are exchanged every basic cycle. When the transparent clock in the synchronization frame field sent by the synchronization host to the compression host changes abnormally, it will cause two effects:

[0052] The first scenario involves an abnormal change exceeding the maximum transmission delay. In this case, the time point calculated by the fixed function within the time synchronization logic becomes a negative number, thus exceeding the limit and reaching an absolutely unreachable time point. Consequently, the time synchronization function cannot be completed normally, and the synchronization state machine may even freeze.

[0053] The second scenario involves an abnormal change to a time delay less than or equal to the maximum transmission delay. In this case, the calculated fixed time point will be offset. However, since the AS6802 time synchronization protocol has a fault tolerance window, the fixed time point within the fault tolerance window will participate in the time synchronization process, thus affecting the time synchronization accuracy of the TTE network. The fixed time point outside the fault tolerance window will be received through a new observation window, and the number of observation windows will be determined according to the windowing principle. The compressed time point obtained after calculation will then be filtered according to the optimal frame selection principle.

[0054] The time synchronization module is used to implement the network time synchronization protocol function based on the fault injection synchronization frame, and outputs a response synchronization frame to the fault injection module based on the fault injection synchronization frame.

[0055] The primary function of a network time synchronization protocol is to ensure that all devices in a network maintain time consistency, guaranteeing the time consistency and coordination of operations between different nodes in a distributed system. In this embodiment, the network time synchronization protocol can be either the AS6802 time synchronization protocol or the Precision Time Protocol (PTP). The Precision Time Protocol employs a master-slave clock architecture, utilizing hardware timestamp technology and precise clock synchronization algorithms to achieve high-precision time synchronization within a local area network. It can maintain a high degree of synchronization between the slave clock and the master clock through precise measurement and compensation of network latency. The AS6802 time synchronization protocol improves and extends upon the Precision Time Protocol by introducing a global time base, adding fault tolerance mechanisms, and employing a fully distributed clock synchronization algorithm. Through functional components such as message solidification, compression, and cluster detection, it achieves high-precision, high-fault-tolerant time synchronization, enabling nodes in the network to maintain time consistency within microsecond-level precision. The AS6802 time synchronization protocol plays a crucial role in aerospace flight control systems, avionics equipment, industrial automated production lines, industrial robot control, and automotive autonomous driving systems and power control systems.

[0056] It is understandable that the operation of the time synchronization module in implementing the network time synchronization protocol function based on the fault-injected synchronization frame is the same as that of the time synchronization module in implementing the network time synchronization protocol function based on the normal synchronization frame. Compared to the normal synchronization frame, because the fault-injected synchronization frame is injected with a pre-configured fault, the time synchronization function may malfunction due to this fault when the time synchronization module implements the network time synchronization protocol function based on the fault-injected synchronization frame. Therefore, fault injection can be used to verify the fault tolerance of the time synchronization function for this fault.

[0057] Similarly, the time synchronization module outputs a response synchronization frame based on the fault-injected synchronization frame, which is actually the same as the time synchronization module outputting a response synchronization frame after implementing the network time synchronization protocol function based on the normal synchronization frame.

[0058] In other words, the focus of the implementation of the time synchronization module in this invention is on the consistency between the time synchronization behavior and the function of the network time synchronization protocol, and whether the network time synchronization function can be implemented normally, rather than implementing the fault tolerance enhancement function not designed in the network time synchronization protocol.

[0059] In practice, the time synchronization module can be implemented using an IP core or a Register Transfer Level (RTL).

[0060] The fault injection module is also used to inject faults into the received response synchronization frame according to the fault injection instruction, so as to obtain a fault injection response synchronization frame.

[0061] Here, the response synchronization frame received by the fault injection module is output by the time synchronization module. The fault injection module performs fault injection on the received response synchronization frame in a similar way to it performs fault injection on the synchronization frame output by the splitter module, so it will not be described in detail here.

[0062] It is understandable that when the fault injection configuration information does not specify fault injection for the response synchronization frame, the fault injection module will not perform fault injection on the response synchronization frame, but will directly output it to the second data interface.

[0063] The second data interface is used to output fault injection response synchronization frames.

[0064] Specifically, the second data interface converts the fault injection response synchronization frame into a physical signal and outputs it to other nodes in the network.

[0065] The synchronization status monitoring module is used to monitor the working status of the time synchronization module, obtain status monitoring information, and evaluate the fault tolerance of the time synchronization function based on the status monitoring information.

[0066] This synchronization status monitoring module is specifically used for:

[0067] By monitoring the execution status, transmission and reception times, and frame content of the fault-injected synchronization frames in the time synchronization module, it is determined whether the time synchronization module is in an abnormal state, thus obtaining status monitoring information. Here, the format of the status monitoring information is as follows: Figure 4 As shown, it includes the synchronization frame content, behavior, time point, status, and abnormal events. Among them, behavior refers to the sending or receiving behavior of the synchronization frame; status is the status information of the time synchronization module during the time synchronization process; and abnormal events are the categories of abnormal events that occur during the time synchronization process.

[0068] For example, consider monitoring the operating status of the time synchronization module within a TTE network. When the time synchronization module receives a fault-injected synchronization frame, it first determines whether an anomaly has occurred based on the frame's reception time. If the arrival time of the received fault-injected synchronization frame deviates from the reception window, a first-state anomaly event is identified. Second, it checks the frame content of the fault-injected synchronization frame to determine if there are any anomalies. If the received frame content does not match expectations, a second-state anomaly event is considered to have occurred. Finally, if an abnormal transition occurs in the processing state machine during the time synchronization module's processing of the fault-injected synchronization frame, a third-state anomaly event is identified. The synchronization status monitoring module collects and records the frame content and anomaly information from each interaction to obtain status monitoring information.

[0069] In this embodiment of the invention, the fault tolerance of the time synchronization function is evaluated based on the status monitoring information. The specific evaluation criteria may include whether the behavior of the time synchronization function under fault conditions meets the design expectations, that is, whether the time synchronization function can identify the abnormality in the fault injection synchronization frame, thereby converting it into a missed fault, not performing the time synchronization function according to the fault injection synchronization frame, and the output response synchronization frame is normal, but it is not limited to this.

[0070] In one embodiment, such as Figure 2 As shown, the above-mentioned device may further include: a synchronization logic hardening module;

[0071] Synchronous logic hardening module, used for:

[0072] The fault injection synchronization frame output by the fault injection module is reinforced with synchronization logic, so that the time synchronization module can implement the network time synchronization protocol function based on the fault injection synchronization frame with reinforced synchronization logic.

[0073] The synchronization logic of the response synchronization frame output by the time synchronization module is strengthened, so that the fault injection module can inject faults into the received response synchronization frame after the synchronization logic is strengthened.

[0074] In one implementation, the synchronization logic hardening includes: executing a Center Guardian Inspection Mechanism (CGIM) and learning and predicting synchronization frames. Executing the CGIM includes: performing CRC check and secondary encryption verification on the fault injection synchronization frames output by the fault injection module; and performing secondary encryption on the response synchronization frames output by the time synchronization module, using an asymmetric hash encryption algorithm. Learning and predicting synchronization frames includes performing timing analysis and prediction on the response synchronization frames output by the time synchronization module; when the response synchronization frame does not match the expected response synchronization frame, the output of the response synchronization frame is truncated, thereby converting time synchronization faults in the network into missed faults, achieving a self-detection mechanism.

[0075] Understandably, when the fault tolerance of the time synchronization function cannot meet the requirements, the time synchronization logic can be strengthened on the basis of the time synchronization module through the synchronization logic reinforcement module, thereby improving the fault tolerance of the time synchronization function.

[0076] Meanwhile, this solution decouples the synchronization logic hardening module from the time synchronization module by independently designing the synchronization logic hardening module, thereby making the solution more flexible. It allows for the selection of whether to apply the synchronization logic hardening module and the selection of a suitable synchronization logic hardening method.

[0077] In one embodiment, such as Figure 2 As shown, the above-mentioned device may further include: a status reporting module;

[0078] The status reporting module is used to convert the status monitoring information into a new format and report it to the host computer so that the host computer can evaluate the fault tolerance of the time synchronization function.

[0079] Specifically, the status reporting module converts the status monitoring information into a format compatible with the PCIe interface and reports it to the host computer periodically or non-periodically. The host computer performs a fault tolerance assessment of the time synchronization function based on the status monitoring information. The specific assessment criteria are: whether the behavior of the time synchronization function under fault conditions meets the design expectations, that is, whether the time synchronization function can convert the fault-injected synchronization frame into a missed fault and output a normal synchronization frame.

[0080] Understandably, reporting status monitoring information to the host computer via the status reporting module, and having the host computer perform fault tolerance assessment for time synchronization, makes the fault tolerance testing process and results more transparent and intuitive, making it easier to identify problems in the design and make corresponding analysis and modifications.

[0081] In one embodiment, such as Figure 2 As shown, the above-mentioned device may further include: a storage module;

[0082] The storage module is used to store status monitoring information;

[0083] The status reporting module is specifically used to read status monitoring information from the storage module, convert the format, and then report it to the host computer.

[0084] Specifically, the storage module may include: a memory controller submodule and a memory submodule.

[0085] The memory controller submodule is used to write status monitoring information to or read status monitoring information from the memory submodule according to partitions. The memory submodule is used to partition and store status monitoring information. The memory controller submodule divides the storage space for different behaviors and states of status monitoring information into different address spaces. When a partition's storage space is full and not read in time, it falls back to the first address in the partition's address space to start writing, and simultaneously reports an information overwrite signal to the host computer.

[0086] Understandably, the storage module stores the status monitoring information generated by the synchronous status monitoring module first, and then the status reporting module reports it to the host computer. This implementation method enables offline analysis of fault-tolerant test data, reduces the real-time requirements of the device, and enhances the traceability of the test process.

[0087] In one embodiment, the above-described device is applied to an FPGA.

[0088] For details, see Figure 1 and Figure 2 All of these modules can be implemented by defining corresponding functional modules in the FPGA. For specific definition methods, please refer to the relevant prior art for the specific implementation of custom modules in the FPGA (such as instantiating existing modules to build more complex modules, using IP cores, or using hardware description languages ​​for design, etc.). This invention will not elaborate on these methods.

[0089] In one embodiment, the FPGA described above is applied to a network interface card (NIC) device, a switch device, or a bridge device. That is, the fault injection and fault-tolerant testing device based on the network time synchronization protocol provided in this embodiment of the invention can be applied to NIC devices, switch devices, or bridge devices, but is not limited thereto.

[0090] It is understandable that when the above-mentioned device is applied to network interface card (NIC) devices, switch devices, or bridge devices, the time synchronization module is the time synchronization module in the NIC device, switch device, or bridge device.

[0091] The fault injection and fault tolerance testing device based on a network time synchronization protocol provided by this invention includes a first data interface, a traffic splitting module, a test configuration module, a fault injection module, a time synchronization module, a synchronization status monitoring module, and a second data interface. The fault injection module injects faults into synchronization frames according to fault injection configuration information, simulating possible fault types during data transmission, thereby testing the fault tolerance of the time synchronization function. The synchronization status monitoring module monitors the functional status of the time synchronization module in real time, thereby determining whether the time synchronization module functions abnormally under fault injection conditions, and assessing the fault tolerance of the time synchronization function accordingly.

[0092] This invention implements synchronous logic hardening function through a synchronous logic hardening module, so that when the fault tolerance does not meet the requirements, the fault tolerance can be further improved through synchronous logic hardening.

[0093] This invention implements fault tolerance testing for devices with time synchronization functions through hardware logic, making up for the limitations of the original theoretical analysis and software simulation, making the fault tolerance test results more reliable, and providing a more reliable reference for the design of devices with time synchronization functions.

[0094] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0095] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0096] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0097] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A network time protocol based fault injection fault tolerance testing apparatus, characterized in that, The device comprises: a first data interface, a shunt module, a test configuration module, a fault injection module, a time synchronization module, a synchronous state monitoring module and a second data interface; the first data interface is configured to receive network data; the network data comprises service frames and synchronization frames; the shunt module is configured to perform frame shunting on the network data, so that the synchronization frames enter the fault injection module; the test configuration module is configured to obtain fault injection configuration information and generate a fault injection instruction according to the fault injection configuration information and send the fault injection instruction to the fault injection module; the fault injection module is configured to perform fault injection on the received synchronization frames according to the fault injection instruction and output fault injection synchronization frames to the time synchronization module; the time synchronization module is configured to implement a network time synchronization protocol function according to the fault injection synchronization frames and output a response synchronization frame to the fault injection module according to the fault injection synchronization frames; the fault injection module is further configured to perform fault injection on the received response synchronization frame according to the fault injection instruction to obtain a fault injection response synchronization frame; the second data interface is configured to output the fault injection response synchronization frame; the synchronous state monitoring module is configured to monitor the working state of the time synchronization module to obtain state monitoring information and evaluate the fault tolerance of the time synchronization function according to the state monitoring information.

2. The network time protocol based fault injection fault-tolerant testing apparatus according to claim 1, wherein, The device further comprises a synchronous logic reinforcement module; the synchronous logic reinforcement module is configured to: perform synchronous logic reinforcement on the fault injection synchronization frames output by the fault injection module, so that the time synchronization module implements a network time synchronization protocol function according to the synchronous logic reinforced fault injection synchronization frames; and perform synchronous logic reinforcement on the response synchronization frames output by the time synchronization module, so that the fault injection module performs fault injection on the received synchronous logic reinforced response synchronization frames.

3. The network time protocol based fault injection fault-tolerant testing apparatus of claim 1, wherein, The device further comprises a state reporting module; the state reporting module is configured to report the state monitoring information to an upper computer after format conversion, so as to evaluate the fault tolerance of the time synchronization function in the upper computer.

4. The network time protocol based fault injection fault-tolerant testing apparatus according to claim 3, wherein, The device further comprises a storage module; the storage module is configured to store the state monitoring information; the state reporting module is specifically configured to read the state monitoring information from the storage module and report it to the upper computer after format conversion.

5. The network time protocol based fault injection fault-tolerant testing apparatus of claim 1, wherein, The synchronous state monitoring module is specifically configured to: judge whether the time synchronization module is in an abnormal state by monitoring the execution state, time point and frame content of the receiving and sending behavior of the fault injection synchronization frames in the time synchronization module, and obtain state monitoring information.

6. The network time protocol based fault injection fault-tolerant testing apparatus of claim 2, wherein, The synchronous logic reinforcement comprises a central guard inspection mechanism (CGIM) and learning prediction on the synchronization frames.

7. The network time protocol based fault injection fault-tolerant testing apparatus of claim 1, wherein, The fault injection configuration information comprises fault types, fault frequencies, fault times, fault input ports and fault output ports.

8. The network time protocol based fault injection fault-tolerant testing apparatus according to any one of claims 1 to 7, characterized in that, The device is applied to an FPGA.

9. The network time protocol based fault injection fault-tolerant testing apparatus according to claim 8, wherein, The FPGA is applied to a network card device, a switch device or a network bridge device.

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