Semiconductor structure

Abstract

The invention provides a semiconductor structure which is applied to the technical field of semiconductors. In the invention, the plug in the semiconductor structure can be bent, and the contact pad on the plug can have different inclination angles with the top surface of the plug, so that a new structure is provided, and the efficiency and the reliability of the semiconductor structure are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor structure. Background Art

[0002] Dynamic random access memory (DRAM) belongs to a type of volatile memory, including an array area composed of multiple memory cells and a peripheral area composed of control circuits. Each memory cell is composed of a transistor and a capacitor electrically connected to the transistor. The transistor controls the storage or release of charge in the capacitor to achieve the purpose of storing data. The control circuit can address each memory cell to control the access of data in each memory cell through word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell. However, due to process technology limitations, there are still many defects in existing dynamic random access memories, and further improvement and effective enhancement of the performance and reliability of related memory components are awaited. Summary of the Invention

[0003] The purpose of the present invention is to provide a semiconductor structure to propose a new structure of the semiconductor structure and improve the reliability and performance of the semiconductor structure.

[0004] To solve the above technical problems, the present invention provides a semiconductor structure, including:

[0005] A substrate;

[0006] Multiple plugs, extending along a first direction and arranged on the substrate at intervals in a second direction perpendicular to the first direction;

[0007] Multiple contact pads, respectively arranged on the multiple plugs, wherein at least one top surface of the multiple contact pads is a horizontal plane extending parallel to the second direction, and at least two top surfaces of the multiple contact pads have different inclination angles relative to the horizontal plane.

[0008] Optionally, at least one of the multiple plugs has a curved side surface, and the side surface has a depression.

[0009] Optionally, the semiconductor structure may further include:

[0010] A plurality of auxiliary lines are defined by straight lines connecting the vertex and the bottom point of the side surface of the plurality of plugs respectively, and the maximum distance from the depression on the side surface of the plug to the corresponding auxiliary line in the second direction is the first offset.

[0011] Optionally, the first offset between the plurality of plugs and the corresponding auxiliary lines increases from the middle position to the edge position.

[0012] Optionally, at least one side surface of the plug further has a protrusion, and the maximum distance from the protrusion to the corresponding auxiliary line in the second direction is the second offset.

[0013] Optionally, the first offset in the same plug is greater than its corresponding second offset.

[0014] Optionally, the plurality of plugs include a first plug, a second plug, and a third plug arranged in sequence from the middle position to the edge position in the second direction, and the first plug, the second plug, and the third plug are physically in contact with a first contact pad, a second contact pad, and a third contact pad respectively, and the first offset and / or the second offset of the first plug, the second plug, and the third plug show an increasing trend.

[0015] Optionally, the top surface of the first contact pad is a horizontal plane extending parallel in the second direction, the top surface of the second contact pad has a first inclination angle relative to the horizontal plane, the top surface of the third contact pad has a second inclination angle relative to the horizontal plane, the second contact pad is located between the first contact pad and the third contact pad, and the first inclination angle is less than the second inclination angle.

[0016] Optionally, for the plurality of contact pads, from the middle position to the edge position in the second direction, the inclination angle of the top surface relative to the horizontal plane shows an increasing trend.

[0017] Optionally, the ratio of the height of the plug in the first direction to the width in the second direction is greater than 10.

[0018] Optionally, the semiconductor structure may further include:

[0019] A dielectric layer, which is located between adjacent contact pads and plugs.

[0020] Optionally, there are no other plugs provided in the dielectric layer on the side of the contact pad located at the edge position of the plurality of contact pads that is far from other contact pads.

[0021] Optionally, the semiconductor structure may further include:

[0022] A plurality of vertical lines are defined by lines that respectively pass through the bottom points of the side surfaces of the plug and extend parallel in the first direction. The plug at least includes a first part and a second part that are respectively located on both sides of the corresponding vertical line.

[0023] To solve the above problems, the present invention also provides a semiconductor structure, including:

[0024] A substrate;

[0025] A plurality of plugs extending in a first direction and arranged on the substrate at intervals in a second direction perpendicular to the first direction;

[0026] A plurality of auxiliary lines are defined by lines connecting the vertex and the bottom point of the single-side surface of the plug. The single-side surface of at least one plug includes a first part and a second part that are respectively bent toward both sides of the auxiliary line.

[0027] Optionally, the semiconductor structure may further include:

[0028] A plurality of contact pads are arranged on the substrate at intervals in the second direction, and each contact pad is physically in contact with each plug; wherein, the inclination angle of the contact pad located at the edge position among the plurality of contact pads with respect to the horizontal plane extending in the second direction is greater than the inclination angle of other contact pads with respect to the horizontal plane.

[0029] Optionally, the first part of the single-side surface of the plug is located in the upper half of the plug and is a recessed part. The maximum distance from the first part to the corresponding auxiliary line in the second direction is a first offset. The first offset between the plurality of plugs and the corresponding auxiliary line shows an increasing trend from the middle position to the edge position.

[0030] Optionally, the second part of the single-side surface of the plug is located in the lower half of the plug and is a protruding part. The maximum distance from the second part to the corresponding auxiliary line in the second direction is a second offset.

[0031] Optionally, the first offset in the same plug is greater than its corresponding second offset.

[0032] Optionally, from the middle position to the edge position of the plurality of contact pads, the inclination angle of the top surface with respect to the horizontal plane shows an increasing trend.

[0033] Optionally, the ratio of the height of the plug in the first direction to the width in the second direction is greater than 10.

[0034] In the present invention, a semiconductor structure includes a plurality of plugs and a plurality of contact pads, wherein the plurality of contact pads are respectively disposed on the plurality of plugs, and the top surface of at least one contact pad is a horizontal plane extending parallel in a first direction, so that the top surfaces of at least two contact pads have different inclination angles relative to the horizontal plane, in order to propose a new structure of the semiconductor structure and simultaneously achieve the purpose of improving the performance and reliability of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings are used to provide a further understanding of the present application and constitute a part of the specification, and are used to explain the present application together with the following specific embodiments, but do not constitute a limitation to the present application. In the drawings:

[0036] Figure 1 is a schematic diagram of the semiconductor structure in the first embodiment of the present invention.

[0037] Figure 2 In the embodiment of the present invention, for Figure 1 the enlarged schematic diagram of the semiconductor structure corresponding to the black dashed box shown after adding auxiliary lines.

[0038] Figure 3 is a schematic diagram of the semiconductor structure in the second embodiment of the present invention.

[0039] Figure 4 In the embodiment of the present invention, for Figure 3 the enlarged schematic diagram of the semiconductor structure corresponding to the black dashed box shown after adding auxiliary lines.

[0040] Among them, the reference numerals are:

[0041] 100 - Substrate, R1 - First region, R2 - Second region, R3 - Third region, 110 - First dielectric layer, 120 - Plug (first - layer plug), 121 - First plug, 122 - Second plug, 123 - Third plug, 130 - Second dielectric layer, 140 - Contact pad, 141 - First contact pad, 142 - Second contact pad, 143 - Third contact pad, 150 - Third dielectric layer, 160 - Next - layer plug (second - layer plug), 170 - Fourth dielectric layer, 141HP - Horizontal plane (the angle between the first contact pad and the first direction, 0), ∠1 - First inclination angle (the first contact pad and the horizontal plane, 0), ∠2 - Second inclination angle (the second contact pad and the horizontal plane, greater than 0), ∠3 - Third inclination angle (the third contact pad and the horizontal plane, greater than 0 and greater than the second inclination angle), AL - Auxiliary line, VL - Vertical line, W1 - First offset, W2 - Second offset.

[0042] In the drawings, the same components are denoted by the same reference numerals, and the drawings are not drawn to actual scale. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further elaborated in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present invention and to be able to fully convey the scope of the present invention to those skilled in the art.

[0044] The present invention will be described more specifically by way of example with reference to the accompanying drawings in the following paragraphs. The advantages and features of the present invention will be clearer according to the following description and the claims. It should be noted that the drawings are all in very simplified forms and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention. It can be understood that the meanings of "on...", "above...", and "overhead..." in the present invention should be interpreted in the broadest manner, so that "on..." not only means "on" something "without any intervening features or layers (i.e., directly on something)", but also includes the meaning of being "on" something with intervening features or layers.

[0045] In addition, for the sake of convenience of description, spatial relative terms such as "on...", "above...", "overhead...", "upper", "upper part", etc. may be used herein to describe the relationship between one element or feature and another element or feature as shown in the drawings. Except for the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive words used herein can be interpreted accordingly.

[0046] In the embodiments of the present invention, terms such as "first", "second", etc. are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

[0047] For the convenience of understanding, the first direction, the second direction, and the horizontal plane are defined below. The first direction is the direction perpendicular to the surface of the substrate 100 and corresponds to D1 in the drawings. The second direction is the direction parallel to the surface of the substrate 100 and corresponds to D2 in the drawings. The horizontal plane is the top surface of the contact pad 140 extending parallel along the second direction and corresponds to 141HP in the drawings. The first direction D1 and the second direction D2 are perpendicular to each other.

[0048] Please refer to Figure 1 and Figure 2 , Figure 1This is a partial cross-sectional schematic diagram of the semiconductor structure in the first embodiment of the present invention. Figure 2 It is a magnified schematic diagram of the semiconductor structure corresponding to the black dashed box shown in Figure 1 after adding auxiliary lines. The semiconductor structure of the present invention can be used to manufacture dynamic random access memory (DRAM). Without departing from the spirit of the present invention, the present invention can also be applied to other types of memories. As Figure 1 and Figure 2 shown, the semiconductor structure in the first embodiment of the present invention includes a substrate 100, a plurality of plugs 120, and a plurality of contact pads 140. The substrate 100 can be divided into at least one first region R1 arranged along the second direction D2, a plurality of second regions R2, and a plurality of third regions R3 according to the different inclination angles between the top surfaces of the plurality of contact pads 140 and the horizontal plane 141HP. The first region R1 can be located in the middle region of the substrate 100, the plurality of second regions R2 can be located in partial regions of the substrate 100 on both sides of the first region R1, and the plurality of third regions R3 can be located in partial regions of the substrate 100 on both sides of the second regions R2. Thus, in the second direction D2, when observing from the first region R1 from left to right or from right to left, the substrate 100 includes the first region R1, the second region R2, and the third region R3 arranged adjacent to each other in sequence, but not limited thereto. A first dielectric layer 110 can also be provided on the substrate 100. The thickness of the first dielectric layer 110 along the first direction D1 is greater than or equal to the extension length of the plurality of plugs 120 in the first direction D1, so that the plurality of plugs 120 are all wrapped by the first dielectric layer 110 to achieve the function of insulating different plugs 120. Exemplarily, the substrate 100 is any suitable substrate material well-known in the art. For example, it can be a silicon substrate, a silicon-containing substrate, a silicon-on-insulator substrate, or a substrate composed of other suitable materials, but not limited thereto; the material of the first dielectric layer 110 can include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), nitrogen-doped silicon carbide (NDC), low dielectric constant (low-k) dielectric materials such as fluorinated silica glass (FSG), silicon carbon oxide (SiCOH), spin-on glass, porous low dielectric constant dielectric materials, organic polymer dielectric materials, or a combination of the above materials, but not limited thereto.

[0049] The multiple plugs 120 can be disposed in different dielectric layers of the substrate 100 along the first direction D1. For example, they can be disposed in the first dielectric layer 110 and the third dielectric layer 150. The multiple plugs 120 located in different dielectric layers can also be disposed on different regions of the substrate 100 at intervals along the second direction D2, that is, on the first region R1, the second region R2, and the third region R3. The number of plugs 120 in different dielectric layers of different regions can be the same or different. Exemplarily, in this embodiment, the plugs 120 located in the first dielectric layer 110 are referred to as the first-layer plugs, and the plugs 120 located in the third dielectric layer 150 are referred to as the second-layer plugs 160. Hereinafter, the characteristics such as the positions and connection relationships of the multiple plugs 120 in the same dielectric layer will be introduced by taking the multiple plugs 120 (the first-layer plugs) located in the first dielectric layer 110 as an example. Those skilled in the art can easily understand the relevant characteristics of the multiple plugs 120 located in other dielectric layers, such as the third dielectric layer 150, based on the above introduction of the multiple plugs 120 in the first dielectric layer 110.

[0050] Specifically, the side surfaces of some of the multiple plugs 120 are not curved and do not have depressions. For example, Figure 1 or Figure 2 the plug identified by the reference numeral "121" in the figure. Some of the side surfaces of the plugs 120 can also be curved and have depressions along the second direction D2. For example, Figure 1 or Figure 2 the plugs identified by the reference numerals "122 or 123" in the figure. And the degrees of curvature of these plugs 120 with curved and depressed side surfaces along the second direction D2 are different. For the convenience of description, in this embodiment, the multiple plugs 120 are divided into the first plug 121, the second plug 122, and the third plug 123. The degrees of curvature of the first plug 121, the second plug 122, and the third plug 123 along the second direction D2 are identified by the first offset amount of the depression of the side surface of each plug 120 to the corresponding auxiliary line in the second direction D2. Among them, the auxiliary line is a straight line connecting the vertex and the bottom point of the side surface of the multiple plugs 120. For example, Figure 2 the straight line identified by the reference numeral "AL" in the figure. The first offset amount is the maximum distance from the depression of the side surface of each plug 120 to the corresponding auxiliary line AL in the second direction D2. For example, Figure 2The distance indicated by the reference numeral "W1" in the figure, but not limited thereto. Exemplarily, the material of the plug 120 may be metal tungsten, and the ratio of its height in the first direction D1 to its width in the second direction D2 may be greater than 10, that is, it is in the shape of a long strip, but not limited thereto. In this embodiment, the first plug 121 may be arranged in the first dielectric layer 110 of the first region R1, the second plug 122 may be arranged in the first dielectric layer 110 of the second region R2, and the third plug 123 may be arranged in the first dielectric layer 110 of the third region R3; under this arrangement, the first offset W1 from the first plug 121 to the third plug 123 (from the middle position to the edge position) increases from the first region R1 to the third region R3, that is, the first offset W1 of the first plug 121 is smaller than the first offset W1 of the second plug 122, and the first offset W1 of the second plug 122 is smaller than the first offset W1 of the third plug 123.

[0051] It should be understood that if the depression of the side surface (also referred to as the single-side surface) of each plug 120 is located to the left or right of the corresponding auxiliary line AL, or the depression is bent toward the corresponding auxiliary line AL, the first offset W1 of the plug 120 can also be understood or referred to as the first part or the depression of the single-side surface of the plug 120. Obviously, the first part or the depression is located in the upper half of the corresponding plug 120, so that the corresponding plug 120 is C-shaped.

[0052] Further, a second dielectric layer 130 is further disposed on the first dielectric layer 110 in which the plurality of plugs 120 are formed. The material of the second dielectric layer 130 may be the same as that of the first dielectric layer 110. For example, both are silicon oxide. The plurality of contact pads 140 may be disposed in the second dielectric layer 130 at intervals along the second direction D2, and the bottoms are respectively in physical contact with one of the plugs 120. Based on the division method of the plugs 120, in this embodiment, the contact pads 140 respectively disposed on the first plug 121, the second plug 122, and the third plug 123 and physically connected thereto are divided into a first contact pad 141, a second contact pad 142, and a third contact pad 143. Among the plurality of contact pads 140, the contact pads located at the edge position (i.e., the third contact pad 143) do not have other contact pads 140 and the corresponding plugs 120 disposed in the first dielectric layer 110 on one side away from other contact pads (the second contact pad 142 or the first contact pad 141). It should be understood that the top surfaces of the first plug 121, the second plug 122, and the third plug 123 will have different angles with the horizontal plane 141HP due to different bending degrees of their side surfaces, so that the top surfaces of the respective contact pads 140 formed on and physically contacting the top surfaces of the respective plugs 120 have different inclination angles with respect to the horizontal plane 141HP. Preferably, the inclination angles of the top surfaces of the plurality of contact pads 140 with respect to the horizontal plane 141HP show an increasing trend along the second direction D2 from the middle position to the edge position (for example, from the first region R1 to the third region R3). For example Figure 2 As shown, the top surface of the first contact pad 141 is parallel to the horizontal plane 141HP, that is, the first inclination angle ∠1 with respect to the horizontal plane 141HP is 0, and is less than the second inclination angle ∠2 of the top surface of the second contact pad 142 with respect to the horizontal plane 141HP; the second inclination angle ∠2 of the top surface of the second contact pad 142 with respect to the horizontal plane 141HP is less than the third inclination angle ∠3 of the top surface of the third contact pad 143 with respect to the horizontal plane 141HP, that is, 0 = ∠1 < ∠2 < ∠3, but not limited thereto. Exemplarily, the material of the contact pad 140 may be a conductive material, such as aluminum, titanium, tantalum, tungsten, copper, titanium nitride, titanium carbide, tantalum nitride, titanium tungsten, titanium nitride, polysilicon, doped silicon, metal silicide and other metal or non-metal conductive materials or any combination thereof, but not limited thereto.

[0053] In addition, a third dielectric layer 150 and a fourth dielectric layer 170 are further disposed on the second dielectric layer 130 in this embodiment from bottom to top. The materials of the third dielectric layer 150 and the fourth dielectric layer 170 can be the same as that of the first dielectric layer 110, such as silicon oxide. Also, similar to the first dielectric layer 110 and the second dielectric layer 130, corresponding first plugs 121, second plugs 122, third plugs 123 and first contact pads 141, second contact pads 142 and third contact pads 143 in physical contact therewith can be disposed in the third dielectric layer 150 and the fourth dielectric layer 170. Among them, the bottoms of the first plug 121, the second plug 122 and the third plug 123 located in the third dielectric layer 150 should be physically connected to the first contact pad 141, the second contact pad 142 and the third contact pad 143 located below and aligned therewith respectively.

[0054] It should be understood that "conformal" in the present invention refers to constructing a continuous structural shape by utilizing the similarity and correlation in the morphology between two or more shapes.

[0055] Those of ordinary skill in the art to which the present invention pertains should easily understand that, on the premise of meeting the requirements of actual products, the semiconductor structure of the present invention may have other forms and is not limited to the foregoing. Further embodiments or variations of the semiconductor structure of the present invention will be described below. And for simplicity of description, the following description mainly details the differences of each embodiment and will not repeat the same parts. In addition, the same components in each embodiment of the present invention are labeled with the same reference numerals for easy comparison between embodiments.

[0056] Please refer to Figure 3 and Figure 4 , Figure 3 which is a partial cross-sectional schematic diagram of the semiconductor structure in the second embodiment of the present invention, Figure 4 is a magnified schematic diagram of the semiconductor structure corresponding to the black dashed box shown in Figure 3 after adding auxiliary lines. As shown in Figure 3 and 4As shown, the semiconductor structure in the second embodiment of the present invention is substantially the same as that in the foregoing first embodiment, and also includes a substrate 100, a plurality of plugs 120, a plurality of contact pads 140, a first dielectric layer 110 (with a first layer of plugs disposed therein), a second dielectric layer 130, a third dielectric layer 150 (with a second layer of plugs 160 disposed therein), and a fourth dielectric layer 170. Among them, the plurality of plugs 120 located in the same dielectric layer can also be divided into a first plug 121, a second plug 122, and a third plug 123 arranged from the middle position to the edge position. Moreover, in the third dielectric layer 130 on the top surfaces of the first plug 121, the second plug 122, and the third plug 123, there are also provided a first contact pad 141, a second contact pad 142, and a third contact pad 143 that are physically in contact with the top surfaces of the respective plugs 120 and have an inclination angle. The same parts will not be elaborated here; the main difference between the semiconductor structure of the second embodiment of the present invention and the foregoing first embodiment lies in that: some of the plurality of plugs 120 not only have a first part or a recess, but also have a second part or a protrusion located in the lower half of the corresponding plug 120, so as to be in an S shape. For the sake of easy distinction, in this embodiment, the straight line connecting the vertex and the bottom point of the single-side surface of each plug 120 can be called a vertical line VL. Obviously, in this embodiment, among the plurality of plugs 120 located in the same dielectric layer, such as the first dielectric layer 110, some can be in an S shape, some can be in a C shape (the same as the first embodiment above), and some can also be in a straight line shape. Among them, the recess of the third plug 123 in the S-shaped plug, for example Figure 4 is located in its upper half or on the left side of the corresponding vertical line VL, and has a first offset W1 from the vertical line VL, while the protrusion of the third plug 123 is located in its lower half or on the right side of the corresponding vertical line VL, and has a second offset W2 (the second distance between the protrusion and the vertical line VL) from the vertical line VL; preferably, for the same plug 120, the first offset W1 in the same plug 120 is greater than its corresponding second offset W2. And for different plugs 120, from the middle position to the edge position, for example, from the first plug 121 to the third plug 123, their corresponding first offset W1 or second offset W2 both show an increasing trend from the first region R1 to the third region R3. For example, the first offset W1 of the first plug 121 is less than the first offset W1 of the second plug 122, the first offset W1 of the second plug 122 is less than the first offset W1 of the third plug 123, and, the second offset W2 of the first plug 121 is less than the second offset W2 of the second plug 122, the second offset W2 of the second plug 122 is less than the second offset W2 of the third plug 123, but not limited thereto.

[0057] In summary, the semiconductor structure includes a plurality of plugs and a plurality of contact pads, wherein the plurality of contact pads are respectively disposed on the plurality of plugs, and the top surface of at least one contact pad is a horizontal plane extending parallel in a first direction. Furthermore, the top surfaces of at least two contact pads have different inclination angles relative to the horizontal plane, so as to propose a new structure of the semiconductor structure and simultaneously achieve the purpose of improving the performance and reliability of the semiconductor device.

[0058] The foregoing is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A plurality of plugs, extending in a first direction and disposed on the substrate at intervals from each other in a second direction perpendicular to the first direction; A plurality of contact pads, respectively disposed on the plurality of plugs, wherein at least one of the top surfaces of the plurality of contact pads is a horizontal plane extending parallel to the second direction, and at least two of the top surfaces of the plurality of contact pads have different inclination angles relative to the horizontal plane.

2. The semiconductor structure according to claim 1, wherein, At least one of the plurality of plugs has a curved side surface, and the side surface has a recess.

3. The semiconductor structure according to claim 2, wherein Further comprising: A plurality of auxiliary lines, respectively defined by straight lines connecting the apex and the bottom point of the side surface of the plurality of plugs, and the maximum distance from the recess of the side surface of the plug to the corresponding auxiliary line in the second direction is a first offset.

4. The semiconductor structure according to claim 3, wherein, The first offset between the plurality of plugs and the corresponding auxiliary lines increases from the middle position to the edge position.

5. The semiconductor structure according to claim 4, characterized in that, The side surface of at least one of the plugs further has a protrusion, and the maximum distance from the protrusion to the corresponding auxiliary line in the second direction is a second offset.

6. The semiconductor structure according to claim 5, characterized in that, The first offset in the same plug is greater than its corresponding second offset.

7. The semiconductor structure according to claim 5, wherein The plurality of plugs include a first plug, a second plug, and a third plug arranged in sequence from the middle position to the edge position in the second direction, and the first plug, the second plug, and the third plug are respectively in physical contact with a first contact pad, a second contact pad, and a third contact pad, and the first offset and / or the second offset of the first plug, the second plug, and the third plug show an increasing trend.

8. The semiconductor structure according to claim 7, wherein, The top surface of the first contact pad is a horizontal plane extending parallel to the second direction, the top surface of the second contact pad has a first inclination angle relative to the horizontal plane, the top surface of the third contact pad has a second inclination angle relative to the horizontal plane, the second contact pad is located between the first contact pad and the third contact pad, and the first inclination angle is less than the second inclination angle.

9. The semiconductor structure according to claim 1, characterized in that, The inclination angles of the top surfaces of the plurality of contact pads relative to the horizontal plane increase from the middle position to the edge position in the second direction.

10. The semiconductor structure according to claim 1, wherein The ratio of the height of the plug in the first direction to the width in the second direction is greater than 10.

11. The semiconductor structure according to claim 1, wherein Further comprising: A dielectric layer, interposed between adjacent contact pads and plugs.

12. The semiconductor structure according to claim 11, wherein No other plugs are provided in the dielectric layer on the side of the contact pad located at the edge position away from other contact pads.

13. The semiconductor structure according to claim 2, wherein Further comprising: A plurality of vertical lines, respectively defined by straight lines passing through the bottom points of the side surfaces of the plugs and extending parallel to the first direction, and the plug at least includes a first part and a second part located on both sides of the corresponding vertical line respectively.

14. A semiconductor structure, characterized in that, Comprising: A substrate; A plurality of plugs, extending in a first direction and disposed on the substrate at intervals from each other in a second direction perpendicular to the first direction; Multiple auxiliary lines are defined by straight lines connecting the vertex and the bottom point of the single-sided surface of the plug, wherein the single-sided surface of at least one of the plugs includes a first part and a second part that are respectively bent toward both sides of the auxiliary line.

15. The semiconductor structure according to claim 14, wherein Further included are: A plurality of contact pads are arranged on the substrate at intervals in the second direction, and each of the contact pads is physically in contact with each of the plugs; wherein, the inclination angle of the contact pads located at the edge position among the plurality of contact pads with respect to the horizontal plane extending in the second direction is greater than the inclination angle of the other contact pads with respect to the horizontal plane.

16. The semiconductor structure according to claim 14, wherein The first part of the single-sided surface of the plug is located in the upper half of the plug and is a concave part, and the maximum distance from the first part to the corresponding auxiliary line in the second direction is a first offset. The first offset between the plurality of plugs and the corresponding auxiliary lines increases from the middle position to the edge position.

17. The semiconductor structure according to claim 16, wherein The second part of the single-sided surface of the plug is located in the lower half of the plug and is a protruding part, and the maximum distance from the second part to the corresponding auxiliary line in the second direction is a second offset.

18. The semiconductor structure according to claim 17, wherein The first offset in the same plug is greater than its corresponding second offset.

19. The semiconductor structure according to claim 14, wherein, From the middle position to the edge position of the plurality of contact pads, the inclination angle of the top surface with respect to the horizontal plane increases.

20. The semiconductor structure according to claim 14, wherein, The ratio of the height of the plug in the first direction to the width in the second direction is greater than 10.

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