Semiconductor device, memory system, and method of manufacturing semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a memory system and a manufacturing method of the semiconductor device. The semiconductor device includes: a stacking structure having a stacking direction; the grid line gap isolation structure penetrates through the stacking structure and comprises a first isolation part and a second isolation part which are arranged in the first direction, and the first isolation part and the second isolation part extend in the first direction; the supporting structure extends in at least part of the stacking structure in the stacking direction, is located between the first isolation part and the second isolation part and is connected with the first isolation part and the second isolation part in the first direction; in the second direction, the size of the supporting structure is larger than the size of the first isolation part and larger than the size of the second isolation part, and the first direction, the second direction and the stacking direction intersect with one another.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a memory system, and a method for manufacturing a semiconductor device. Background Art

[0002] In order to improve the integration of semiconductor devices, the size of semiconductor devices in the vertical direction has been continuously increasing, which will affect the structural stability and yield of semiconductor devices. Summary of the Invention

[0003] The present application provides a semiconductor device, a memory system, and a method for manufacturing a semiconductor device that can at least partially solve the above problems or other problems in the art.

[0004] In a first aspect, some embodiments of the present application provide a semiconductor device. The semiconductor device includes: a stacked structure having a stacking direction; a gate line gap isolation structure that penetrates the stacked structure and includes a first isolation portion and a second isolation portion arranged in a first direction, both the first isolation portion and the second isolation portion extending in the first direction; and a support structure that extends in the stacking direction in at least a part of the stacked structure, is located between the first isolation portion and the second isolation portion, and is connected to the first isolation portion and the second isolation portion in the first direction; wherein, in a second direction, the size of the support structure is greater than the size of the first isolation portion and greater than the size of the second isolation portion, and the first direction, the second direction, and the stacking direction intersect with each other.

[0005] In an exemplary embodiment, the gate line gap isolation structure further includes at least one third isolation portion that penetrates the support structure.

[0006] In an exemplary embodiment, the support structure penetrates the stacked structure, and the first isolation portion and the second isolation portion are disconnected.

[0007] In an exemplary embodiment, the stacked structure includes a first stacked portion and a second stacked portion in the stacking direction, the support structure penetrates the first stacked portion, and both the first isolation portion and the second isolation portion penetrate the first stacked portion and the second stacked portion; wherein, the portions of the first isolation portion that penetrate the second stacked portion and the portions of the second isolation portion that penetrate the second stacked portion extend in the first direction and are connected to each other.

[0008] In an exemplary embodiment, the material of the portion of the support structure in contact with the stacked structure is an insulating material.

[0009] In an exemplary embodiment, the support structure includes a support main body portion and an insulating layer at least partially covering the outer surface of the support main body portion, and the insulating layer is in contact with the stacked structure.

[0010] In an exemplary embodiment, the material of the insulating layer includes silicon oxide, and the material of the support main body portion includes polysilicon.

[0011] In an exemplary embodiment, on a plane perpendicular to the stacking direction, the gate line gap isolation structure has a concave-convex shape.

[0012] In an exemplary embodiment, the stacking structure includes alternately stacked dielectric layers and gate layers.

[0013] In an exemplary embodiment, the semiconductor device further includes a plurality of channel structures that penetrate the stacking structure.

[0014] In a second aspect, some embodiments of the present application provide a memory system. The memory system includes: a memory including a semiconductor device as mentioned in any of the above embodiments; and a controller coupled to the memory for controlling the memory to store data.

[0015] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes: forming a support structure extending along the stacking direction of the initial stacking structure in at least a part of the initial stacking structure; and forming a gate line gap penetrating the initial stacking structure, the gate line gap including a first gap portion and a second gap portion located on both sides of the support structure along a first direction, the first gap portion and the second gap portion exposing the support structure and both extending along the first direction; wherein, in a second direction, the size of the support structure is greater than the size of the first gap portion and greater than the size of the second gap portion, and the first direction, the second direction, and the stacking direction intersect each other.

[0016] In an exemplary embodiment, the initial stacking structure includes alternately stacked dielectric layers and sacrificial layers, and the manufacturing method further includes: removing the sacrificial layers in the initial stacking structure by using the first gap portion and the second gap portion; forming a gate layer in the gap formed after removing the sacrificial layers; and forming a first isolation portion and a second isolation portion in the first gap portion and the second gap portion respectively.

[0017] In an exemplary embodiment, forming a gate line gap penetrating the initial stacking structure includes: forming a plurality of first holes and a plurality of second holes penetrating the initial stacking structure, the plurality of first holes and the plurality of second holes being arranged along the first direction and arranged on both sides of the support structure; and etching the initial stacking structure by using the plurality of first holes and the plurality of second holes to connect the plurality of first holes into the first gap portion and connect the plurality of second holes into the second gap portion.

[0018] In an exemplary embodiment, the initial stack structure includes an initial first stack portion and an initial second stack portion in a stack direction, a support structure penetrates the initial first stack portion, and both a first gap portion and a second gap portion penetrate the initial first stack portion and the initial second stack portion; wherein, forming a gate line gap penetrating the initial stack structure further includes: forming at least one third hole penetrating the support structure and the initial second stack portion, and the at least one third hole is arranged between a plurality of first holes and a plurality of second holes; wherein, etching the initial stack structure using the plurality of first holes and the plurality of second holes includes: connecting a portion of the first gap portion penetrating the initial second stack portion and a portion of the second gap portion penetrating the initial second stack portion to each other.

[0019] In an exemplary embodiment, forming a support structure extending in the stack direction of at least a part of the initial stack structure includes: forming an opening extending in the stack direction in at least a part of the initial stack structure; and forming a support structure in the opening.

[0020] In an exemplary embodiment, forming a support structure in the opening includes: forming an insulating layer on the inner wall of the opening; and forming a support main body portion on the inner side of the insulating layer, wherein the material of the support main body portion is different from the material of the dielectric layer and different from the material of the sacrificial layer.

[0021] In an exemplary embodiment, the material of the insulating layer includes silicon oxide, and the material of the support main body portion includes polysilicon.

[0022] In an exemplary embodiment, the manufacturing method further includes: forming a plurality of channel holes penetrating the initial stack structure, wherein the plurality of channel holes, the plurality of first holes, and the plurality of second holes are formed using the same mask. Description of the Drawings

[0023] Other features, objects, and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Among them:

[0024] Figure 1A is a top view schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0025] Figure 1B is Figure 1A a partial enlarged schematic diagram of the area A shown;

[0026] Figure 1C is along Figure 1B a cross-sectional schematic diagram of the semiconductor device taken along the line I-I' shown;

[0027] Figure 1D is along Figure 1B a cross-sectional schematic diagram of the semiconductor device taken along the line II-II' shown;

[0028] Figure 1E is taken along Figure 1B a schematic cross-sectional view of a semiconductor device taken along the line III-III' shown;

[0029] Figure 1F is taken along Figure 1C a schematic cross-sectional view of a semiconductor device taken along the line IV-IV' shown;

[0030] Figure 2 is a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0031] Figures 3A to 9D is a schematic structural view of a semiconductor device during manufacturing provided by an embodiment of the present application;

[0032] Figure 10 is a block diagram of a system having a memory system provided by an embodiment of the present application; and

[0033] Figure 11A and Figure 11B is a schematic view of a memory system provided by an embodiment of the present application; Detailed Description of the Invention

[0034] To better understand the present application, more detailed descriptions of various aspects of the present application will be made with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] It should be noted that in this specification, the expressions such as first, second, and third are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order. Therefore, without departing from the teachings of the present application, the first isolation portion discussed in the present application may also be referred to as the second isolation portion, and vice versa.

[0036] In the drawings, for ease of illustration, the thickness, dimensions, and shapes of the components have been slightly adjusted. The drawings are only examples and are not drawn to an exact scale. As used herein, the terms "substantially", "about", and similar terms are used as terms indicating approximation, rather than terms indicating degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0037] It should also be understood that expressions such as "comprising", "including", "having", "containing" and / or "including" are open rather than closed expressions in this specification, which means the presence of the stated features, elements and / or components is indicated, but the presence of one or more other features, elements, components and / or combinations thereof is not excluded. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features rather than just individual elements in the list. In addition, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0038] Unless otherwise defined, all terms used herein (including engineering terms and scientific and technical terms) have the same meaning as commonly understood by those of ordinary skill in the art to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0039] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. In addition, unless clearly defined or conflicting with the context, the specific steps included in the methods described in this application do not have to be limited to the recited order and can be executed in any order or in parallel.

[0040] In addition, when using "connected" or "coupled" in this application, it may indicate direct contact or indirect contact between the corresponding components, unless there are clear other limitations or can be deduced from the context.

[0041] The present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0042] Some embodiments of the present application provide a semiconductor device. Figure 1A is a top view schematic diagram of the semiconductor device provided by the embodiment of the present application. Figure 1B is Figure 1A a partial enlarged schematic diagram of the area A shown. Figure 1C is along Figure 1B a cross-sectional schematic diagram of the semiconductor device taken along the line I-I' shown. Figure 1D is along Figure 1B a cross-sectional schematic diagram of the semiconductor device taken along the line II-II' shown. Figure 1E is along Figure 1B a cross-sectional schematic diagram of the semiconductor device taken along the line III-III' shown. Figure 1F is along Figure 1CSchematic cross-sectional view of a semiconductor device taken along line IV-IV'. For example, Figures 1A to 1F The illustrated semiconductor device 100 may be part of a 3D NAND memory.

[0043] It should be noted that hereinafter, the x-direction, y-direction, and z-direction in each of the drawings show the spatial relationship of the components in the semiconductor device. For example, the z-direction is the stacking direction of the stacked structure (or initial stacked structure), and the x-direction and y-direction are two directions that intersect (e.g., are perpendicular) to each other in a plane intersecting (e.g., perpendicular) to the stacking direction. For example, the x-direction is the extending direction of the first isolation portion and the second isolation portion. The same concept will be adopted throughout this application to describe the spatial relationship of the components in the semiconductor device.

[0044] As Figures 1A to 1F shown, the semiconductor device 100 includes a stacked structure 111, a gate line gap isolation structure 112, and a support structure 113.

[0045] In some embodiments, the stacked structure 111 may include dielectric layers 1111 and gate layers 1112 stacked alternately. For example, each dielectric layer 1111 and each gate layer 1112 can extend laterally in the x-direction and y-direction. The material of the dielectric layer 1111 may include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the material of the dielectric layer 1111 may be silicon oxide (SiO2). In some examples, the gate layer 1112 may include a high-k layer 11121, a bonding layer 11122, and a conductive layer 11123 arranged in sequence from outside to inside. The material of the high-k layer 11121 may include but is not limited to aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O3), and hafnium oxide (HfO2). The material of the bonding layer 11122 may include but is not limited to titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN). The material of the conductive layer 11123 may include but is not limited to polycrystalline silicon (poly-Si), amorphous silicon (α-Si), tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru). In some other examples, at least one of the high-k layer 11121 and the bonding layer 11122 may not be present in the gate layer 1112 (not shown). For example, the gate layer may be composed of a single conductive material.

[0046] The gate line gap isolation structure 112 can penetrate the stacked structure 111 and includes a first isolation portion 1121 and a second isolation portion 1122 arranged along the x direction. Among them, both the first isolation portion 1121 and the second isolation portion 1122 extend along the x direction (for example, continuously extend). In some embodiments, in a plane perpendicular to the z direction, the gate line gap isolation structure 112 has a concave-convex shape. For example, in a plane perpendicular to the z direction, both the first isolation portion 1121 and the second isolation portion 1122 have a concave-convex shape. The gate line gap isolation structure 112 with the above shape helps to improve the structural stability and yield of the semiconductor device 100, especially for the semiconductor device 100 with a stacked structure 111 having a large number of stacked layers.

[0047] In some embodiments, the material of the portion of the gate line gap isolation structure 112 in contact with the stacked structure 111 can be an insulating material to electrically isolate the stacked structures 111 (for example, the gate layer 1112) on both sides of the gate line gap isolation structure 112. For example, the material of the portions of the first isolation portion 1121 and the second isolation structure 1122 in contact with the stacked structure 111 can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. In some examples, the gate line gap isolation structure 112 can include polysilicon bodies 11211, 11221 and silicon oxide layers 11212, 11222 covering at least a portion of the outer surfaces of the polysilicon bodies 11211, 11221. Adopting this material combination helps to optimize the structural stress distribution of the semiconductor device 100. For example, the first isolation portion 1121 can include a polysilicon body 11211 and a silicon oxide layer 11212 covering the sidewalls and bottom of the polysilicon body 11211. The second isolation portion 1122 can include a polysilicon body 11221 and a silicon oxide layer 11222 covering the sidewalls and bottom of the polysilicon body 11221.

[0048] As Figure 1F shown, the support structure 113 extends along the z direction in at least a portion of the stacked structure 111, is located between the first isolation portion 1121 and the second isolation portion 1122, and is connected (for example, in contact) with the first isolation portion 1121 and the second isolation portion 1122 along the x direction. For example, in a plane perpendicular to the z direction, the outer contour of the support structure 113 is generally rectangular. In other examples, the outer contour of the support structure 113 in a plane perpendicular to the z direction can include a circle, an ellipse, or other irregular rings, and the present application does not make specific limitations thereto. In the semiconductor device 100, in the y direction, the dimension d1 of the support structure 113 is greater than the dimension d2 of the first isolation portion 1121 and greater than the dimension d3 of the second isolation portion 1122.

[0049] It should be noted that in the case where both the first isolation portion 1121 and the second isolation portion 1122 are concave-convex in a plane perpendicular to the z direction, the dimension d2 of the first isolation portion 1121 in the y direction and the dimension d3 of the second isolation portion 1122 in the y direction may be the maximum dimensions of the two in the y direction. Optionally, the dimension d2 of the first isolation portion 1121 in the y direction and the dimension d3 of the second isolation portion 1122 in the y direction may be the same.

[0050] According to the semiconductor device 100 provided by the embodiment of the present application, the support structure 113 extends in the x direction in at least a part of the stacked structure 111, is located between the first isolation portion 1121 and the second isolation portion 1122, and is connected to the first isolation portion 1121 and the second isolation portion 1122 in the x direction. In the y direction, the dimension d1 of the support structure 113 is greater than the dimension d2 of the first isolation portion 1121 and greater than the dimension d2 of the second isolation portion 1122, which can reinforce the stacked structure 111 on both sides of the first isolation portion 1121 and the second isolation portion 1122, and helps to improve the structural stability and yield of the semiconductor device 100.

[0051] In some embodiments, continuing to refer to Figures 1A to 1F , the material of the portion of the support structure 113 in contact with the stacked structure 111 is an insulating material to electrically isolate the stacked structures 111 (e.g., the gate layer 1112) on both sides of the support structure 113. Exemplarily, the support structure 113 includes a support main body portion 1131 and an insulating layer 1132 at least partially covering the outer surface of the support main body portion 1131. Among them, the insulating layer 1132 is in contact with the stacked structure 111. For example, the material of the insulating layer 1132 includes silicon oxide (SiO2), and the material of the support main body portion 1131 includes polysilicon (poly-Si).

[0052] In some embodiments, the gate line gap isolation structure 112 may further include at least one third isolation portion 1123. The third isolation portion 1123 penetrates the support structure 113. In some examples, the number of the third isolation portions 1123 is one, and the third isolation portion 1123 has a spacing distance from the outer contour of the support structure 113. In other examples, the number of the third isolation portions 1123 is greater than one (not shown), these third isolation portions 1123 are arranged in the x direction and spaced from each other, and at the same time, they all have a spacing distance from the outer contour of the support structure 113. The material composition of the third isolation portion 1123 may be the same as that of the first isolation portion 1121 and the second isolation portion 1122. For example, the third isolation portion 1123 may include a polysilicon main body 11231 and a silicon oxide layer 11232 covering the side wall of the polysilicon main body 11231.

[0053] In some embodiments, the stacked structure 111 may include a first stacked portion 1113 and second stacked portions 1114-1, 1114-2 in the z direction. For example, in the z direction, the first stacked portion 1113 is located between the two second stacked portions 1114-1, 1114-2. Both the first stacked portion 1113 and the second stacked portions 1114-1, 1114-2 include at least a pair of dielectric layers 1111 and gate layers 1112. Among them, the support structure 113 penetrates the first stacked portion 1113. In other words, the support structure 113 does not extend into the second stacked portions 1114-1, 1114-2 in the z direction. The first isolation portion 1121 and the second isolation portion 1122 penetrate the first stacked portion 1113 and the second stacked portions 1114-1, 1114-2, and the portions of the first isolation portion 1121 that penetrate the second stacked portions 1141-1, 1114-2 and the portions of the second isolation portion 1122 that penetrate the second stacked portions 1114-1, 1114-2 extend in the x direction and are connected to each other. For example, the portions of the first isolation portion 1121 and the second isolation portion 1122 that penetrate the second stacked portions 1114-1, 1114-2 cover the surfaces of the support structure 113 and the third isolation portion 1123 in the z direction. For example, the polysilicon bodies 11211 in the first isolation portion 1121, the polysilicon bodies 11221 in the second isolation portion 1122, and the polysilicon bodies 11231 in the third isolation portion 1123 are an integral structure. The silicon oxide layers 11212 in the first isolation portion 1121, the silicon oxide layers 11222 in the second isolation portion 1122, and the silicon oxide layers 11232 in the third isolation portion 1123 are an integral structure.

[0054] It should be noted that Figures 1A to 1F The number and relative positions of the illustrated first stacked portion 1113 and second stacked portions 1114-1, 1114-2 are only examples. In other examples, the stacked structure 111 may include one first stacked portion and one second stacked portion (not shown) arranged in the z direction. The portion of the first isolation portion that penetrates one second stacked portion and the portion of the second isolation portion that penetrates one second stacked portion extend in the x direction and are connected to each other.

[0055] In the present application, it is illustrated above that the support structure 113 extends in the z direction in a part of the stacked structure 111, which helps to reduce the process difficulty (such as an etching process) of forming the third isolation portion 1123. In other embodiments, the support structure may penetrate the stacked structure, whereby the first isolation portion and the second isolation portion are disconnected (not shown). For example, the first isolation portion and the second isolation portion are spaced apart by the support structure in the x direction.

[0056] In some embodiments, the semiconductor device 100 further includes a plurality of channel structures 114. The channel structures 114 penetrate the stacked structure 111. For example, in a plane perpendicular to the z-direction, the plurality of channel structures 114 may be arranged at intervals along the x-direction and the y-direction. Exemplarily, the channel structure 114 may include a blocking layer 1141, a charge trapping layer 1142, a tunneling layer 1143, and a channel layer 1144 arranged in sequence from the outside to the inside. For example, the blocking layer 1141, the charge trapping layer 1142, the tunneling layer 1143, and the channel layer 1144 all penetrate the stacked structure 111, and the channel layer 1144 protrudes from the stacked structure 111. Among them, the blocking layer 1141, the charge trapping layer 1142, and the tunneling layer 1143 may be referred to as functional layers. For example, the materials of the blocking layer 1141, the charge trapping layer 1142, and the tunneling layer 1143 may include silicon oxide (SiO2), silicon nitride (Si3O4), and silicon oxide (SiO2) in sequence. The material of the channel layer 1144 may include amorphous silicon (α-Si), polysilicon (poly-Si), or any other suitable semiconductor material.

[0057] In some embodiments, a portion of the channel structure 114 surrounded by a gate layer 1112 and a portion of the gate layer 1112 form a memory cell. A plurality of memory cells are arranged in series along the extending direction of the channel structure 114 (e.g., the z-direction) to form a memory string and share the channel layer 1144.

[0058] In some embodiments, the semiconductor device 100 may further include a semiconductor layer 115. The semiconductor layer 115 may be located on one side (e.g., the surface) of the stacked structure 111 in the z-direction. For example, the semiconductor layer 115 may extend laterally along the x-direction and the y-direction. The portion of the channel layer 1144 protruding from the stacked structure 111 may be located in the semiconductor layer 115. For example, each of the channel layers 1144 in the plurality of channel structures 114 may be located in the semiconductor layer 115. The material of the semiconductor layer 115 may include single-crystalline silicon (s-Si), polysilicon (poly-Si), amorphous silicon (α-Si), or any other suitable semiconductor material. When the material of the semiconductor layer 115 is the same as that of the channel layer 1144, there is no obvious interface between the portion of the channel layer 1144 located in the semiconductor layer 115 and the semiconductor layer 115.

[0059] In some embodiments, the first isolation portion 1121 and the second isolation portion 1122 in the gate line gap isolation structure 112 extend in the z-direction into the semiconductor layer 115. The portions of the first isolation portion 1121 and the second isolation portion 1122 in the gate line gap isolation structure 112 extending into the semiconductor layer 115 are a plurality of protrusions arranged at intervals along the x-direction.

[0060] In some embodiments, such as Figure 1AAs shown, a plurality of gate line gap isolation structures 112 are arranged at intervals in the y direction. Adjacent gate line gap isolation structures 112 divide the stacked structure 111 into memory blocks 101. In addition, the semiconductor device 100 can also be divided into a memory area 102 and a connection area 103 in the x direction. For example, a plurality of channel structures 114 are located in the memory area 102. In some embodiments, the semiconductor device 100 may further include a top select gate cut line structure 116 and a contact structure 117. The top select gate cut line structure 116 can extend in the z direction in part of the stacked structure 111, and also extend in the x direction in the memory area 102 and the connection area 103. The material of the top select gate cut line structure 116 may include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. The contact structure 117 can be located in the connection area 103 and extend in the z direction in part of the stacked structure 111. For example, the contact structure 117 can be used to lead out the gate layer 1112 in the z direction. The material of the contact structure 117 may include one or more of polysilicon (poly-Si), amorphous silicon (α-Si), tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru) or any other suitable conductive material.

[0061] Some embodiments of the present application also provide a method for manufacturing a semiconductor device. Figure 2 It is a schematic flow chart of the method for manufacturing a semiconductor device provided by an embodiment of the present application. As Figure 2 shown, the method 200 for manufacturing a semiconductor device (hereinafter simply referred to as the manufacturing method 200) may include the following steps.

[0062] S210, forming a support structure extending in the stacking direction of the initial stacked structure in at least part of the initial stacked structure.

[0063] S220, forming a gate line gap penetrating the initial stacked structure, the gate line gap including a first gap portion and a second gap portion located on both sides of the support structure in the first direction, the first gap portion and the second gap portion exposing the support structure and both extending in the first direction.

[0064] Wherein, in the second direction, the size of the support structure is larger than the size of the first gap portion and larger than the size of the second gap portion, and the first direction, the second direction and the stacking direction intersect each other

[0065] Figures 3A to 9D It is a schematic structural diagram of the semiconductor device provided by an embodiment of the present application during the manufacturing process. For example, Figures 3A to 9D can be used to form Figures 1A to 1F the semiconductor device 100 shown. Wherein, Figure 3AIt is a top view schematic diagram of the intermediate structure 300a after forming the initial second stacked portion 3114-2'. Figure 3B It is along Figure 3A A cross-sectional schematic diagram of the intermediate structure 300a taken along the line I-I' shown. Figure 3C It is along Figure 3A A cross-sectional schematic diagram of the intermediate structure 300a taken along the line II-II' shown. Figure 3D It is along Figure 3A A cross-sectional schematic diagram of the intermediate structure 300a taken along the line III-III' shown.

[0066] Figure 4A It is a top view schematic diagram of the intermediate structure 300b after forming the support structure 313. Figure 4B It is along Figure 4A A cross-sectional schematic diagram of the intermediate structure 300b taken along the line I-I' shown. Figure 4C It is along Figure 4A A cross-sectional schematic diagram of the intermediate structure 300b taken along the line II-II' shown. Figure 4D It is along Figure 4A A cross-sectional schematic diagram of the intermediate structure 300b taken along the line III-III' shown.

[0067] Figure 5A It is a top view schematic diagram of the intermediate structure 300c after forming a plurality of first holes 322, a plurality of second holes 323, and at least one third hole 324. Figure 5B Along Figure 5A A cross-sectional schematic diagram of the intermediate structure 300c taken along the line I-I' shown. Figure 5C It is along Figure 5A A cross-sectional schematic diagram of the intermediate structure 300c taken along the line II-II' shown. Figure 5D It is along Figure 5A A cross-sectional schematic diagram of the intermediate structure 300c taken along the line III-III' shown.

[0068] Figure 6A It is a top view schematic diagram of the intermediate structure 300d after forming a mask layer 328 that exposes a plurality of first holes 322, a plurality of second holes 323, and at least one third hole 324. Figure 6B Along Figure 6A A cross-sectional schematic diagram of the intermediate structure 300d taken along the line I-I' shown. Figure 6C It is along Figure 6A A cross-sectional schematic diagram of the intermediate structure 300d taken along the line II-II' shown. Figure 6D It is along Figure 6A A cross-sectional schematic diagram of the intermediate structure 300d taken along the line III-III' shown.

[0069] Figure 7A It is a top view schematic diagram of the intermediate structure 300e after the formation of the first gap portion 330 and the second gap portion 331. Figure 7B Along Figure 7A A cross-sectional schematic diagram of the intermediate structure 300e taken along the line I-I' shown. Figure 7C It is along Figure 7A A cross-sectional schematic diagram of the intermediate structure 300e taken along the line II-II' shown. Figure 7D It is along Figure 7A A cross-sectional schematic diagram of the intermediate structure 300e taken along the line III-III' shown.

[0070] Figure 8A It is a top view schematic diagram of the intermediate structure 300f after the formation of the channel structure 314. Figure 8B Along Figure 8A A cross-sectional schematic diagram of the intermediate structure 300f taken along the line I-I' shown. Figure 8C It is along Figure 8A A cross-sectional schematic diagram of the intermediate structure 300f taken along the line II-II' shown. Figure 8D It is along Figure 8A A cross-sectional schematic diagram of the intermediate structure 300f taken along the line III-III' shown.

[0071] Figure 9A It is a top view schematic diagram of the intermediate structure 300g after the formation of the gate layer 3112, the first isolation portion 3121, and the second isolation portion 3122. Figure 9B Along Figure 9A A cross-sectional schematic diagram of the intermediate structure 300g taken along the line I-I' shown. Figure 9C It is along Figure 9A A cross-sectional schematic diagram of the intermediate structure 300g taken along the line II-II' shown. Figure 9D It is along Figure 9A A cross-sectional schematic diagram of the intermediate structure 300g taken along the line III-III' shown.

[0072] Next, in conjunction with Figures 3A to 9D An exemplary description of the manufacturing method 200 including steps S210 and S220 will be given.

[0073] S210

[0074] As Figures 5A to 5D shown, a support structure 313 extending in the z direction can be formed in at least a part of the initial stack structure 311'. Next, in conjunction with Figures 3A to 5D An example of the process method for forming the support structure 313 will be given. In some embodiments, as Figures 3A to 3DAs shown, an initial second stack portion 3114-2' can be formed on one side of a substrate 321. The substrate 321 can include a semiconductor substrate. For example, the material of the semiconductor substrate can include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). As another example, the semiconductor substrate can include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate, etc. For example, during the manufacturing process, the substrate 321 can serve as a support and can be at least partially removed in subsequent processes. Exemplarily, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to alternately form a dielectric layer 3111 and a sacrificial layer 3113 to form the initial second stack portion 3114-2'. The materials of the dielectric layer 3111 and the sacrificial layer 3115 are different, so that the two have different etching selectivity ratios with respect to the same etching material. For example, the material of the dielectric layer 3111 can include silicon dioxide (SiO2), and the material of the sacrificial layer 3115 can include silicon nitride (Si3N4).

[0075] As Figures 4A to 4D shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used again to alternately form a dielectric layer 3111 and a sacrificial layer 3115 to form an initial first stack portion 3113'. For example, the number of pairs of the dielectric layer 3111 and the sacrificial layer 3115 in the initial first stack portion 3113' can be less than the number of pairs of the dielectric layer 3111 and the sacrificial layer 3115 in the initial second stack portion 3114-2'. Further, an etching process (e.g., dry etching and / or wet etching) can be used to form an opening (corresponding to the outer contour of the support structure 313) through the initial first stack portion 3113'. Then, a support structure 313 can be formed in the opening by using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The support structure 313 has a dimension d1 in the y direction.

[0076] As Figures 5A to 5D shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used again to alternately form a dielectric layer 3111 and a sacrificial layer 3115 to form another initial second stack portion 3114-1'. The other initial second stack portion 3114-2' can cover the surfaces of the support structure 313 and the initial first stack portion 3113'.

[0077] In some embodiments, as Figure 4A and Figure 5DAs shown, the step of forming the support structure 313 in the opening may include: First, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form an insulating layer 3132 on the inner wall of the above-mentioned opening. The material of the insulating layer 3132 may include silicon oxide (SiO2). Then, a support main body portion 3131 may be formed inside the insulating layer 3132. The material of the support main body portion 3131 is different from that of the dielectric layer 3111 and different from that of the sacrificial layer 3115. For example, when the material of the dielectric layer 3111 is silicon oxide (SiO2) and the material of the sacrificial layer 3115 is silicon nitride (Si3N4), the material of the support main body portion 3131 may include polysilicon (poly-Si).

[0078] It should be noted that in this step, the support structure may also be formed by the following process methods. For example, after forming the initial stacked structure 311', a support structure penetrating the initial stacked structure 311' may be formed. Another example is that first, a part of the initial stacked structure (for example, this part of the initial stacked structure may be called the initial first stacked part) is formed, then a support structure penetrating the initial first stacked part is formed, and then another part of the initial stacked structure (for example, this part of the initial stacked structure may be called the initial second stacked part) covering the initial first stacked part and the support structure is formed. Another example is that after forming the initial stacked structure 311', a support structure extending in a part of the initial stacked structure 311' (for example, this part of the initial stacked structure may be called the initial first stacked part) is formed from one side of the initial stacked structure 311' in the z direction, where the other part of the initial stacked structure 311' may be called the initial second stacked part.

[0079] S220

[0080] As Figures 7A to 7D shown, a gate line gap 312' penetrating the initial stacked structure 311' is formed. In some embodiments, step S220 may be performed by the following process methods. As Figures 3A to 3DAs shown, after forming the initial second stacked portion 3114-2', an etching process (e.g., dry etching and / or wet etching) can be employed to form a plurality of initial first holes 322' and a plurality of initial second holes 323' that penetrate the initial second stacked portion 3114-2'. The plurality of initial first holes 322' and the plurality of initial second holes 323' are arranged in the x direction (e.g., spaced apart). For example, the spacing distance of each initial first hole 322' in the x direction is the same, and the spacing distance of each initial second hole 323' in the x direction is the same. Further, each initial first hole 322' and each initial second hole 323' extend into the substrate 321. Optionally, during the formation of the plurality of initial first holes 322' and the plurality of initial second holes 323', the same mask can be used to form at least one (e.g., one) initial third hole 324' that penetrates the initial second stacked portion 3114-2' in the same etching process (e.g., dry etching and / or wet etching). For example, in the x direction, the spacing distance between the initial third hole 324' and the nearest initial first hole 322' is the same as the spacing distance between the initial third hole 324' and the nearest initial second hole 323'. In this case, the plurality of initial first holes 322', the initial third hole 324', and the plurality of initial second holes 323' can be arranged in the x direction at substantially equal spacing distances to be compatible with a uniformly arranged pattern design, which helps to simplify the process and reduce costs. Optionally, during the formation of the plurality of initial first holes 322' and the plurality of initial second holes 323', the same mask can be used to form a plurality of initial channel holes 325' that penetrate the initial second stacked portion 3114-2' in the same etching process (e.g., dry etching and / or wet etching). For example, the plurality of initial channel holes 325' can be spaced apart in the x direction and the y direction. Further, each initial channel hole 325' can extend into the substrate 321.

[0081] Furthermore, as Figures 3A to 4D shown, a first sacrificial material layer 326 can be formed in the plurality of initial first holes 322' and the plurality of initial second holes 323' by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Optionally, in the case where the initial third hole 324' and / or the plurality of initial channel holes 325' are formed, the first sacrificial material layer 326 can also be formed in the initial third hole 324' and / or the plurality of initial channel holes 325' by a thin film deposition process.

[0082] Furthermore, as Figures 5A to 5DAs shown, after forming the initial first stacked portion 3113' and another initial second stacked portion 3114-1', an etching process (e.g., wet etching and / or dry etching) can be used to etch a part of the initial second stacked portion 3114-1' to form a plurality of first holes 322 and a plurality of second holes 323 that penetrate the initial second stacked portion 3114-1', the initial first stacked portion 3113', and the initial second stacked portion 3114-2'. In other words, a plurality of first holes 322 and a plurality of second holes 323 can be formed that penetrate the initial stacked structure 311'. Among them, the first holes 322 include the initial first holes 322', and the second holes 323 include the initial second holes 323'. The plurality of first holes 322 and the plurality of second holes 323 are arranged in the x direction and are arranged on both sides of the support structure 313. Optionally, during the formation of the plurality of first holes 322 and the plurality of second holes 323, the same mask can be used to form a third hole 324 that penetrates the initial stacked structure 311' in the same etching process (e.g., dry etching and / or wet etching). It should be noted that in some embodiments, the material of the support main body 3131 in the support structure 313 is different from both the dielectric layer 3111 and the sacrificial layer 3115. When the support structure 313 extends in the z direction in a part of the initial stacked structure 311', the process difficulty of etching to form the third hole 324 can be reduced. Optionally, during the formation of the plurality of first holes 322 and the plurality of second holes 323, the same mask can be used to form a plurality of channel holes 325 that penetrate the initial stacked structure 311' in the same etching process (e.g., dry etching and / or wet etching). For example, a first oxide layer 333 can be formed on the surface of the substrate 321 exposed to the plurality of first holes 322, the plurality of second holes 323, the third hole 324, and the plurality of channel holes 325. Another example is that in the case where the material of the support portion main body 3132 is polysilicon (poly-Si), a second oxide layer 327 can be formed on the side wall of the support main body 3231 exposed to the third hole 324.

[0083] It should be noted that in the present application, an exemplary multi-step etching process for forming the plurality of first holes 322 and the plurality of second holes 323 is described. Using this process method can reduce the etching difficulty of forming the plurality of first holes 322 and the plurality of second holes 323. In other embodiments, after forming the initial stacked structure 311', a one-step etching can be performed to form the plurality of first holes 322 and the plurality of second holes 323 that penetrate the initial stacked structure 311' to improve efficiency. The present application does not make specific limitations on this.

[0084] In some embodiments, such as Figures 5A to 6DAs shown, a thin film deposition process of CVD, PVD, ALD or any combination thereof may be used to form a second sacrificial material layer 329 in the plurality of first holes 322 and the plurality of second holes 323. Optionally, in the case where a third hole 324 and / or a plurality of channel holes 325 are formed, a thin film deposition process may be used to form a second sacrificial material layer 329 in the third hole 324 and / or the plurality of channel holes 325. The material of the second sacrificial material layer 329 may include polycrystalline silicon (poly-Si).

[0085] In some embodiments, Figures 6A to 6D As shown, a mask layer 328 may be formed on a side (eg, a surface) of the initial stacked structure 311' away from the substrate 321. The mask layer 328 may cover a plurality of channel holes 325 (see Figures 5A to 5D ) in the second sacrificial material layer 329, and exposing a plurality of first holes 322 and a plurality of second holes 323 (reference Figures 5A to 5D ) in the second sacrificial material layer 329. Optionally, the mask layer 328 may expose the second sacrificial material layer 329 in the third hole 324. For example, the mask layer 328 may have an opening 3281 extending continuously along the x direction. The opening 3281 may expose the plurality of first holes 322 and the plurality of second holes 323 (refer to Figures 5A to 5D ) in the second sacrificial material layer 329. Optionally, the opening 3281 may also expose the second sacrificial material layer 329 in the third hole 324. The material of the mask layer 328 may be different from the material of the dielectric layer 3111 and different from the material of the sacrificial layer 3115. For example, the material of the mask layer 328 may include photoresist.

[0086] In some embodiments, Figures 6A to 7D As shown, the plurality of first holes 322 and the plurality of second holes 323 (see Figures 5A to 5D ) in the second sacrificial material layer 329. Optionally, the third hole 324 (reference Figures 5A to 5D ) is also removed. Next, an etching process (eg, wet etching) may be used to form the plurality of first holes 322 and the plurality of second holes 323 (see Figures 5A to 5D ) to etch the initial stack structure 311', so that a plurality of first holes 322 (reference Figures 5A to 5D ) is connected to form a first slit portion 330, and a plurality of second holes 323 (reference Figures 5A to 5D ) are connected to form a second slit portion 331, thereby forming a gate line slit 312' that penetrates the initial stacked structure 311'. For example, a plurality of first holes 322 and a plurality of second holes 323 (refer to Figures 5A to 5D ) extending into the substrate 321 is not connected.

[0087] After the above-mentioned process treatment, the gate line gap 312' may include a first gap portion 330 and a second gap portion 331 located on both sides of the support structure 313 along the x direction, and the first gap portion 330 and the second gap portion 331 expose the support structure 313 (for example, the support main body portion 3131). Among them, both the first gap portion 330 and the second gap portion 331 extend along the x direction. For example, in a plane perpendicular to the z direction, the first gap portion 330 and the second gap portion 331 are in a concave-convex shape.

[0088] As described above, during the formation of the support structure 313, the support structure 313 (for example, the insulating layer 3132) has a dimension d1 in the y direction, and this dimension d1 is greater than the dimension d2 of the first gap portion 330 in the y direction and greater than the dimension d3 of the second gap portion 331 in the y direction. Thus, after the gate line gap 312' is formed, the support structure 313 extends into the initial stacked structure 311' along the y direction, thereby playing a role in strengthening the initial stacked structure 311'.

[0089] In some embodiments, when the material of the insulating layer 3132 in the support structure 313 is silicon oxide (SiO2) and the material of the support main body portion 3131 is polysilicon (poly-Si), during the formation of the first gap portion 330 and the second gap portion 331, a part of the insulating layer 3132 located on both sides of the support main body portion 3131 along the x direction can be etched, and a part of the insulating layer 3132 located on both sides of the support main body portion 3131 along the y direction is retained, so that the first gap portion 330 and the second gap portion 331 expose the support main body portion 3131. For example, the support main body portion 3131 can be used as a stop layer.

[0090] In some embodiments, when the third hole 324 is formed, during the formation of the first gap portion 330 and the second gap portion 331, the etching material (for example, the etchant) passes through the part of the support structure 313 that the third hole 324 does not penetrate (that is, the part where the third hole 324 penetrates the initial second stacked parts 3114-1', 3114-2'), so that the parts of the first gap portion 330 and the second gap portion 331 that penetrate the initial second stacked parts 3114-1', 3114-2' are communicated with each other. Optionally, the etching material (for example, the etchant) can remove the second oxide layer 327 (refer to Figures 6A to 6D ) through the part of the support structure 313 that the third hole 324 penetrates, and stops at the support main body portion 3131. In this embodiment, by first forming a plurality of first holes and a plurality of second holes arranged along the x direction, and then forming the first gap portion and the second gap portion extending along the x direction, not only can the etching stress be relieved, but also the structural stability of the initial stacked structure can be improved.

[0091] In some embodiments, the manufacturing method 200 may further include the following steps. As Figures 7A to 8D shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form a third sacrificial material layer 332 in the first gap portion 330 and the second gap portion 331. Optionally, the third sacrificial material layer 332 is also formed in the portion of the third hole 324 that penetrates the support structure 313. Next, the mask layer 328 may be removed, and the second sacrificial material layer 329 in the plurality of channel holes 325 (refer to Figures 5A to 5D ) may be removed. Further, a plurality of channel structures 314 are formed in the plurality of channel holes 325 (refer to Figures 5A to 5D ). For example, the step of forming the channel structures 314 may include: using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof to sequentially form a blocking layer 3141, a charge trapping layer 3142, a tunneling layer 3143, and a channel layer 3144 on the inner wall of the channel hole 325 (refer to Figures 5A to 5D ). For example, the channel structures 314 may extend into the substrate 321.

[0092] In some embodiments, as Figures 8A to 9D shown, an etching (e.g., wet etching) process may be used to remove the third sacrificial material layer 332 in the first gap portion 330 and the second gap portion 331 (refer to Figures 7A to 7D ). Optionally, the third sacrificial material layer 332 in the portion of the third hole 324 that penetrates the support structure 313 is also removed. Thereby, the first gap portion 330 and the second gap portion 331 (refer to Figures 7A to 7D ) are exposed. Optionally, the portion of the third hole 324 that penetrates the support structure 313 is also exposed and communicates with the first gap portion 330 and the second gap portion 331 in the z direction. Then, an etching (e.g., wet etching) process may be used, and the sacrificial layer 3115 in the initial stack structure 331' may be removed using the first gap portion 330 and the second gap portion 331. Then, a gate layer 3112 is formed in the gap formed after removing the sacrificial layer 3115. For example, a high-k layer 31121, an adhesion layer 31122, and a conductive layer 31123 may be sequentially formed on the inner wall of the above gap using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof to form the gate layer 3112. The initial stack structure 311' after the above process is called the stack structure 311.

[0093] In some embodiments, continuing to refer to FIGS. 8A to Figure 9D , a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form, in the first gap portion 330 and the second gap portion 331 (refer to Figures 7A to 7D)The first isolation portion 3121 and the second isolation portion 3122 are respectively formed therein. For example, in the space formed by the portions of the first gap portion 330, the second gap portion 331, and the third hole 324 passing through the support structure 313, silicon oxide layers 31212, 31222, 31232 and polysilicon bodies 31211, 31221, 31231 are sequentially formed. Among them, the silicon oxide layer 31212 and the polysilicon body 31211 formed in the first gap portion 330 (refer to Figures 7A to 7D ) can constitute the first isolation portion 3121, and the silicon oxide layer 31222 and the polysilicon body 31221 formed in the second gap portion 331 (refer to Figures 7A to 7D ) can constitute the second isolation portion 3122. The silicon oxide layer 31232 and the polysilicon body 31231 formed in the portion where the third hole 324 passes through the support structure 313 can constitute the third isolation portion 3123.

[0094] In some embodiments, at least part of the substrate 321 may also be removed, and a part of the barrier layer 3141, the charge trapping layer 3142, and the tunneling layer 3143 protruding from the stacked structure 311 may be removed to expose the channel layer 3144. Next, a semiconductor layer 115 (refer to Figures 1A to 1F ) connected (e.g., in contact) to the channel layer 3144 may be formed by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0095] The embodiment of the present application also provides a memory system. Figure 10 is a block diagram of a system having the memory system provided by the embodiment of the present application. Figure 11A and Figure 11B is a schematic diagram of the memory system provided by the embodiment of the present application.

[0096] As Figure 10 shown, the system 11 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having the memory system 12 therein). As Figure 10As shown, the system 11 may include a host 18 and a memory system 12 having one or more memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the memory 14.

[0097] The memory 14 may include semiconductor devices described in any embodiment of the present application. For example, Figures 1A to 1FThe semiconductor device 100 shown. According to some embodiments, the controller 16 is coupled to the memory 14 and the host 18, and is configured to control the memory 14. The controller 16 can manage the data stored in the memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multi-media-card (eMMC) used as a data storage device for a mobile device, and an enterprise storage array, where the mobile device is such as a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operations of the memory 14, such as read, erase, and program operations. The controller 16 can also be configured to manage various functions related to the data stored in or to be stored in the memory 14, and the various functions include but are not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the controller 16 is further configured to process an error correction code (ECC) related to the data read from or written to the memory 14. Any other suitable functions can also be performed by the controller 16, for example, formatting the memory 14. The controller 16 can communicate with external devices (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0098] The controller 16 and one or more memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of end electronic products. In as Figure 11AIn one example shown, the controller 16 and the single memory 14 may be integrated into the memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 22 may further include a memory card connector 24 that couples the memory card 22 to a host (e.g., Figure 10 the host 18 in). In another example as shown in Figure 11B , the controller 16 and multiple memories 14 may be integrated into the SSD 26. The SSD 26 may further include an SSD connector 28 that couples the SSD 26 to a host (e.g., Figure 10 the host 18 in). In some embodiments, the storage capacity and / or the operating speed of the SSD 26 are higher than those of the memory card 22.

[0099] The above description is only for the embodiments of the present application and the explanation of the applied technical principles. Those skilled in the art should understand that the protection scope involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the technical solutions formed by mutually replacing the above features with the (but not limited to) technical features having similar functions disclosed in the present application.

Claims

1. A semiconductor device, characterized in that, Comprising: A stacked structure having a stacking direction; A gate line gap isolation structure that penetrates the stacked structure and includes a first isolation portion and a second isolation portion arranged along a first direction, both the first isolation portion and the second isolation portion extending along the first direction; And A support structure that extends along the stacking direction in at least a part of the stacked structure, is located between the first isolation portion and the second isolation portion, and is connected to the first isolation portion and the second isolation portion along the first direction; Wherein, in a second direction, the size of the support structure is larger than the size of the first isolation portion and larger than the size of the second isolation portion, The first direction, the second direction, and the stacking direction intersect with each other.

2. The semiconductor device according to claim 1, wherein, The gate line gap isolation structure further includes at least one third isolation portion that penetrates the support structure.

3. The semiconductor device according to claim 2, wherein, The support structure penetrates the stacked structure, and the first isolation portion and the second isolation portion are disconnected.

4. The semiconductor device according to claim 2, wherein, The stacked structure includes a first stacked portion and a second stacked portion in the stacking direction, the support structure penetrates the first stacked portion, and both the first isolation portion and the second isolation portion penetrate the first stacked portion and the second stacked portion; Wherein, the portion of the first isolation portion that penetrates the second stacked portion and the portion of the second isolation portion that penetrates the second stacked portion extend along the first direction and are connected to each other.

5. The semiconductor device according to claim 1, wherein, The material of the portion of the support structure in contact with the stacked structure is an insulating material.

6. The semiconductor device according to claim 5, wherein, The support structure includes a support main body portion and an insulating layer that at least partially covers the outer surface of the support main body portion, and the insulating layer is in contact with the stacked structure.

7. The semiconductor device according to claim 6, wherein, The material of the insulating layer includes silicon oxide, and the material of the support main body portion includes polysilicon.

8. The semiconductor device according to any one of claims 1 to 7, wherein, In a plane perpendicular to the stacking direction, the gate line gap isolation structure has a concave-convex shape.

9. The semiconductor device according to any one of claims 1 to 7, wherein, The stacked structure includes alternately stacked dielectric layers and gate layers.

10. The semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device further includes a plurality of channel structures that penetrate the stacked structure.

11. A memory system, characterized in that, Comprising: A memory including the semiconductor device according to any one of claims 1 to 10; And A controller coupled to the memory and configured to control the memory to store data.

12. A method for manufacturing a semiconductor device, characterized in that, Comprising: A support structure formed to extend along the stacking direction of at least a part of an initial stacked structure; And Forming a gate line gap that penetrates the initial stacked structure, the gate line gap including a first gap portion and a second gap portion located on both sides of the support structure along a first direction, the first gap portion and the second gap portion exposing the support structure and both extending along the first direction; Wherein, in a second direction, the size of the support structure is larger than the size of the first gap portion and larger than the size of the second gap portion, and the first direction, the second direction, and the stacking direction intersect with each other.

13. The manufacturing method according to claim 12, wherein, The initial stacked structure includes alternately stacked dielectric layers and sacrificial layers, and the manufacturing method further includes: Remove the sacrificial layer in the initial stacked structure by using the first gap portion and the second gap portion; Form a gate layer in the gap formed after removing the sacrificial layer; and Form a first isolation portion and a second isolation portion in the first gap portion and the second gap portion respectively.

14. The manufacturing method according to claim 13, wherein, Forming a gate line gap penetrating the initial stacked structure includes: Forming a plurality of first holes and a plurality of second holes penetrating the initial stacked structure, the plurality of first holes and the plurality of second holes are arranged along the first direction and are arranged on both sides of the support structure; and Etch the initial stacked structure by using the plurality of first holes and the plurality of second holes, so that the plurality of first holes are connected to form the first gap portion, and the plurality of second holes are connected to form the second gap portion.

15. The manufacturing method according to claim 14, wherein, The initial stacked structure includes an initial first stacked portion and an initial second stacked portion in the stacking direction, the support structure penetrates the initial first stacked portion, and both the first gap portion and the second gap portion penetrate the initial first stacked portion and the initial second stacked portion; Wherein, forming a gate line gap penetrating the initial stacked structure further includes: Forming at least one third hole penetrating the support structure and the initial second stacked portion, the at least one third hole is arranged between the plurality of first holes and the plurality of second holes; Wherein, etching the initial stacked structure by using the plurality of first holes and the plurality of second holes includes: Connect the part of the first gap portion penetrating the initial second stacked portion and the part of the second gap portion penetrating the initial second stacked portion to each other.

16. The manufacturing method according to any one of claims 13 to 15, wherein Forming a support structure extending along the stacking direction of the initial stacked structure in at least part of the initial stacked structure includes: Forming an opening extending along the stacking direction in at least part of the initial stacked structure; and Form the support structure in the opening.

17. The manufacturing method according to claim 16, wherein, Forming the support structure in the opening includes: Forming an insulating layer on the inner wall of the opening; and Forming a support main body portion inside the insulating layer, wherein the material of the support main body portion is different from the material of the dielectric layer and different from the material of the sacrificial layer.

18. The manufacturing method according to claim 17, wherein The material of the insulating layer includes silicon oxide, and the material of the support main body portion includes polysilicon.

19. The manufacturing method according to claim 12, wherein, The manufacturing method further includes: Forming a plurality of channel holes penetrating the initial stacked structure, wherein the plurality of channel holes, the plurality of first holes, and the plurality of second holes are formed by using the same mask.

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