Semiconductor device, preparation method thereof and storage system
By designing a two-stage connection structure, the problem of difficulty in etching process in three-dimensional memory is solved, and more efficient connection structure formation is achieved, reducing etching offset and structural design complexity.
Patent Information
- Application Number
- CN202410110725.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-24
- Publication Date
- 2025-07-25
AI Technical Summary
In three-dimensional memory, the etching process of the connection structure is difficult, which affects the connection efficiency of the control circuit and the storage structure.
The connection structure of the semiconductor device is designed as a two-stage structure. The end surface sizes of the first connection structure and the second connection structure are different. It is formed by segmented etching to reduce the etching depth and difficulty.
It reduces the difficulty of the etching process, improves the reliability and efficiency of the connecting structure, reduces the etching offset, and optimizes the structure design area.
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Figure CN120379273A_ABST
Abstract
Description
Technical Field
[0001] This application generally relates to the field of electronic devices, and more specifically, to a semiconductor device, a manufacturing method thereof, and a storage system. Background Art
[0002] In three-dimensional memories, a control circuit is combined with a storage structure to control read and write operations of the storage structure. In order to lead out the control circuit and connect it to an external circuit, the configuration of the connection structure often causes difficulties in various processes. Therefore, how to design a better connection structure has always been a problem in the industry.
[0003] Summary of the Application
[0004] The purpose of this application is to provide a semiconductor device, a manufacturing method thereof, and a storage system, aiming to reduce the etching process difficulty of the connection structure.
[0005] In a first aspect, this application provides a semiconductor device, which includes:
[0006] A transistor array;
[0007] A storage array located on one side of the transistor array along a first direction;
[0008] A connection structure located at the periphery of the storage array and the transistor array and extending along the first direction;
[0009] Wherein, the connection structure includes a first connection structure and a second connection structure connected along the first direction; the first connection structure includes a first end face close to the second connection structure and a second end face far from the second connection structure, and the size of the first end face is smaller than that of the second end face; the second connection structure includes a third end face close to the first connection structure and a fourth end face far from the first connection structure, and the size of the third end face is smaller than that of the fourth end face.
[0010] In some embodiments, the semiconductor device further includes:
[0011] Internal lead-out contacts connected to the side of the transistor array far from the storage array;
[0012] Wherein, the second connection structure is located at one end of the first connection structure close to the internal lead-out contacts; and one end of the second connection structure far from the first connection structure is flush with one end of the internal lead-out contacts far from the transistor array.
[0013] In some embodiments, the connection structure further includes along the first direction:
[0014] The third connection structure is connected to one end of the first connection structure away from the second connection structure.
[0015] In some embodiments, the semiconductor device further includes:
[0016] External lead contacts, connected to a side of the memory array away from the transistor array;
[0017] Wherein, one end of the third connection structure away from the first connection structure is flush with one end of the external lead contact away from the memory array.
[0018] In some embodiments, the transistor array includes:
[0019] Semiconductor columns, arranged in an array between the internal lead contacts and the memory array, the semiconductor columns are arranged in multiple rows along a second direction, and the second direction is perpendicular to the first direction;
[0020] Gate line structures, located between adjacent rows of the semiconductor columns and extending along the second direction;
[0021] Wherein, the internal lead contacts include gate line lead contacts and bit line lead contacts, the gate line lead contacts are connected to the ends of the gate line structures along the second direction, and the bit line lead contacts are connected to one end of the semiconductor columns away from the memory array.
[0022] In some embodiments, the dimension of the second connection structure along the first direction is greater than or equal to the dimension of the bit line lead contact along the first direction.
[0023] In some embodiments, the dimension of the gate line lead contact along the first direction is greater than the dimension of the bit line lead contact along the first direction.
[0024] In some embodiments, the dimension of the second connection structure along the first direction is equal to the dimension of the gate line lead contact along the first direction.
[0025] In some embodiments, the dimension of the first end face is smaller than the dimension of the third end face.
[0026] In some embodiments, the third connection structure includes a fifth end face close to the first connection structure and a sixth end face away from the first connection structure, and the dimension of the fifth end face is smaller than the dimension of the sixth end face.
[0027] In some embodiments, the semiconductor device further includes:
[0028] Virtual semiconductor columns, spaced apart from the periphery of the semiconductor columns;
[0029] Wherein, one end of the first connection structure close to the second connection structure is located in the gap between the virtual semiconductor columns.
[0030] In some embodiments, the size of the external lead contact along the first direction is greater than the size of the third connection structure along the first direction.
[0031] In some embodiments, the size of the first connection structure along the first direction is greater than the size of the second connection structure along the first direction; the size of the second connection structure along the first direction is greater than the size of the third connection structure along the first direction.
[0032] In some embodiments, along the direction away from the second connection structure, the cross-sectional area of the first connection structure in the plane direction perpendicular to the first direction gradually increases; along the direction away from the first connection structure, the cross-sectional area of the second connection structure in the plane direction gradually increases.
[0033] In some embodiments, the semiconductor device further includes:
[0034] A first pad connected to one end of the external lead contact away from the memory array;
[0035] A second pad connected to one end of the third connection structure away from the first connection structure.
[0036] In some embodiments, the semiconductor device further includes:
[0037] A control circuit bonded to the side of the transistor array away from the memory array and connected to the connection structure.
[0038] In some embodiments, the semiconductor device further includes:
[0039] A first bonding metal layer connected to the side of the second connection structure away from the transistor array;
[0040] A second bonding metal layer bonded to the side of the first bonding metal layer away from the second connection structure.
[0041] In some embodiments, the memory array includes:
[0042] Capacitor structures arranged in an array;
[0043] A conductive layer covering the surface of the capacitor structure, and the conductive layer is connected to the external lead contact.
[0044] In some embodiments, the capacitor structure includes:
[0045] A stacked layer, including a first dielectric layer and a second dielectric layer alternately stacked along the first direction, wherein the thickness of the first dielectric layer along the first direction is greater than that of the second dielectric layer along the first direction;
[0046] A first electrode structure, penetrating the stacked layer along the first direction, and one end of the first electrode structure close to the transistor array is connected to the semiconductor column;
[0047] A second electrode structure, located between the first electrode structure and the stacked layer, and one end of the second electrode structure far from the transistor array is connected to the conductive layer;
[0048] A dielectric layer, located between the first electrode structure and the second electrode structure.
[0049] In a second aspect, the present application provides a method for manufacturing a semiconductor device, and the method for manufacturing the semiconductor device includes:
[0050] Forming a first substrate;
[0051] Forming a transistor array in the first substrate;
[0052] Forming a memory array on one side of the transistor array along a first direction;
[0053] Forming a first connection structure around the memory array and the transistor array, and the first connection structure extends along the first direction;
[0054] Thinning the first substrate to expose the transistor array;
[0055] Forming a second connection structure on one side of the transistor array and the first connection structure far from the memory array, and the second connection structure connects the first connection structure;
[0056] Wherein, the first connection structure includes a first end face close to the second connection structure and a second end face far from the second connection structure, and the size of the first end face is smaller than that of the second end face; the second connection structure includes a third end face close to the first connection structure and a fourth end face far from the first connection structure, and the size of the third end face is smaller than that of the fourth end face.
[0057] In some embodiments, the step of forming the second connection structure on one side of the transistor array and the first connection structure far from the memory array includes:
[0058] On a side of the transistor array and the first connection structure away from the storage array, an internal lead contact and a second connection structure are formed. The internal lead contact is connected to the transistor array, and the second connection structure is connected to the first connection structure.
[0059] In some embodiments, the method for manufacturing the semiconductor device further includes:
[0060] Connecting the control circuit to the internal lead contact and the second connection structure through a bonding metal layer;
[0061] On a side of the storage array and the first connection structure away from the transistor array, an external lead contact and a third connection structure are formed. The external lead contact is connected to the storage array, and the third connection structure is connected to the first connection structure.
[0062] In some embodiments, the step of forming a transistor array in the first substrate includes:
[0063] Etching the first substrate to form array - arranged semiconductor columns and dummy semiconductor columns. The dummy semiconductor columns are located on the periphery of the semiconductor columns. The semiconductor columns are arranged in multiple rows along a second direction, and the second direction is perpendicular to the first direction;
[0064] Forming a gate line structure between adjacent two rows of the semiconductor columns. The gate line structure extends along the second direction, and a dimension of the gate line structure along the first direction is smaller than a dimension of the semiconductor column along the first direction;
[0065] Wherein, the internal lead contact includes a gate line lead contact and a bit line lead contact. The gate line lead contact is connected to an end of the gate line structure along the second direction, and the bit line lead contact is connected to an end of the semiconductor column away from the storage array.
[0066] In some embodiments, the step of forming a first connection structure on the peripheries of the storage array and the transistor array includes:
[0067] Forming an insulating layer covering the surface of the storage array;
[0068] Etching the insulating layer on the periphery of the storage array to form a through - hole extending along the first direction. A bottom of the through - hole is located in a space between the dummy semiconductor columns;
[0069] Filling a conductive material in the through - hole to form a first connection structure.
[0070] In some embodiments, the method for manufacturing the semiconductor device further includes:
[0071] A first pad is formed at one end of the external lead contact away from the storage array;
[0072] A second pad is formed at one end of the third connection structure away from the first connection structure.
[0073] In some embodiments, the step of forming a storage array on one side of the transistor array along a first direction includes:
[0074] Capacitor structures arranged in an array are formed on one side of the transistor array along the first direction;
[0075] A conductive layer is covered on the surface of the capacitor structure, and the conductive layer is connected to the external lead contact.
[0076] In some embodiments, the step of forming capacitor structures arranged in an array on one side of the transistor array along the first direction includes:
[0077] A stacked layer is formed on one side of the transistor array along the first direction. The stacked layer includes a first dielectric layer and a second dielectric layer that are alternately stacked along the first direction, and the thickness of the first dielectric layer along the first direction is greater than the thickness of the second dielectric layer along the first direction;
[0078] A first electrode structure is formed to penetrate the stacked layer along the first direction. One end of the first electrode structure close to the transistor array is connected to the semiconductor pillar;
[0079] A second electrode structure is formed between the first electrode structure and the stacked layer. One end of the second electrode structure away from the transistor array is connected to the conductive layer;
[0080] A dielectric layer is formed between the first electrode structure and the second electrode structure.
[0081] In some embodiments, before the step of forming an internal lead contact and a second connection structure on one side of the transistor array and the first connection structure away from the storage array, the method for manufacturing the semiconductor device further includes:
[0082] A bit line is formed at one end of the semiconductor pillar away from the storage array. The bit line extends along a third direction, and the third direction is perpendicular to the first direction and the second direction;
[0083] Wherein, the bit line lead contact is connected to the bit line.
[0084] In a third aspect, the present application provides a storage system, including:
[0085] The semiconductor device in any of the above embodiments;
[0086] A controller, which is connected to the semiconductor device and is used to control the semiconductor device to store data.
[0087] This application provides a semiconductor device, a manufacturing method thereof, and a storage system. The semiconductor device includes a transistor array, a storage array, and a connection structure. The storage array is located on one side of the transistor array along a first direction. The connection structure is located at the periphery of the storage array and the transistor array and extends along the first direction. Wherein, the connection structure includes a first connection structure and a second connection structure connected to each other along the first direction; the first connection structure includes a first end face close to the second connection structure and a second end face far from the second connection structure, and the size of the first end face is smaller than that of the second end face; the second connection structure includes a third end face close to the first connection structure and a fourth end face far from the first connection structure, and the size of the third end face is smaller than that of the fourth end face. The connection structure in this application is formed in two segments, and the first connection structure and the second connection structure can be etched in opposite directions respectively, so the depth of one etching can be reduced and the difficulty of the etching process can be reduced. Description of the Drawings
[0088] The technical solutions and other beneficial effects of this application will become obvious by describing the specific embodiments of this application in detail with reference to the accompanying drawings.
[0089] Figure 1 is a schematic structural diagram of a semiconductor device provided by some embodiments of this application;
[0090] Figure 2 is a schematic structural diagram of a storage array provided by some embodiments of this application;
[0091] Figure 3 is a schematic flowchart of a method for manufacturing a semiconductor device provided by some embodiments of this application;
[0092] Figures 4a - 4h is a schematic structural diagram of a semiconductor device during the manufacturing process provided by some embodiments of this application;
[0093] Figure 5 is a schematic structural diagram of a storage system provided by some embodiments of this application. Detailed Description of the Embodiments
[0094] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only some of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of this application.
[0095] It should be understood that although terms such as first and second may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component, without departing from the scope of the present application.
[0096] It should be understood that when a component is said to be "on" another component or "connected" to another component, it may be directly on the other component or connected to the other component, or there may also be intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner.
[0097] As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a scope smaller than the scope of the underlying or overlying structure. In addition, the layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer may extend horizontally, vertically, and / or along a tapered surface. The substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. The layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnect lines, and / or vertical interconnect access (VIA) are formed) and one or more dielectric layers.
[0098] It should be noted that the diagrams provided in the embodiments of the present application only illustrate the basic concept of the present application in a schematic manner. Although only the components related to the present application are shown in the diagrams and are not drawn according to the number, shape, and size of the components in actual implementation, the type, quantity, and ratio of each component in actual implementation may be arbitrarily changed, and the component layout type may also be more complex.
[0099] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a semiconductor device provided in some embodiments of the present application.
[0100] The semiconductor device 100 may be a wafer or a 3D memory, or a part of a 3D memory. The 3D memory may be applied to communication products, consumer electronic products, automotive products, aerospace products, artificial intelligence products, or big data, etc. Among them, consumer electronic products include but are not limited to mobile phones, computers, tablets, cameras, smart glasses, or gaming products, etc.
[0101] The semiconductor device 100 includes a transistor array 10, a memory array 20, and a connection structure 30. The memory array 20 is located on one side of the transistor array 10 along the first direction (X). The connection structure 30 is located on the periphery of the memory array 20 and the transistor array 10 and extends along the first direction (X). Among them, the connection structure 30 includes a first connection structure 31 and a second connection structure 32 connected along the first direction (X). The first connection structure 31 includes a first end face 311 (bottom face) close to the second connection structure 32 and a second end face 312 (top face) far from the second connection structure 32, and the size of the first end face 311 is smaller than the size of the second end face 312. The second connection structure 32 includes a third end face 321 (top face) close to the first connection structure 31 and a fourth end face 322 (bottom face) far from the first connection structure 31, and the size of the third end face 321 is smaller than the size of the fourth end face 322.
[0102] It can be understood that the "size of the end face" herein may refer to the surface area of the end face.
[0103] It can be understood that due to the influence of the etching process, the size of the first end face 311 is smaller than the size of the second end face 312, which means that the first connection structure 31 can be formed by an etching process from the second end face 312 to the first end face 311; the size of the third end face 321 is smaller than the size of the fourth end face 322, which means that the second connection structure 32 can be formed by an etching process from the fourth end face 322 to the third end face 321.
[0104] In some embodiments, the second connection structure 32 can be etched and formed first, and then the first connection structure 31 can be etched and formed, and the size of the first end face 311 is smaller than the size of the third end face 321. In this way, the size of the third end face 321 is larger, and the first connection structure 31 is easy to connect with the third end face 321 of the second connection structure 32, increasing the etching process window of the first connection structure 31.
[0105] In some embodiments, along the direction away from the second connection structure 32, the cross-sectional area of the first connection structure 31 in the plane (YZ) direction perpendicular to the first direction (X) gradually increases; along the direction away from the first connection structure 31, the cross-sectional area of the second connection structure 32 in the plane (YZ) direction gradually increases. That is to say, in Figure 1 the cross-sectional area of the first connection structure 31 gradually increases from bottom to top, and the cross-sectional area of the second connection structure 32 gradually increases from top to bottom.
[0106] The semiconductor device 100 may further include an internal lead contact 40, which is located on a side of the transistor array 10 away from the storage array 20. Among them, the second connection structure 32 is located at an end of the first connection structure 31 close to the internal lead contact 40, that is Figure 1 in Figure 1 , the second connection structure 32 is located below the first connection structure 31.
[0107] In some embodiments, an end of the second connection structure 32 away from the first connection structure 31 (the fourth end face 322) is flush with an end of the internal lead contact 40 away from the transistor array 10. It should be noted that in the case where the internal lead contact 40 and the second connection structure 32 are formed together and planarized, an end of the second connection structure 32 away from the first connection structure 31 may be flush with an end of the internal lead contact 40 away from the transistor array 10. Due to process influences, the above two ends may not be flush, and the present application does not limit this.
[0108] In some embodiments, the connection structure 30 further includes a third connection structure 33 along the first direction (X). The third connection structure 33 is connected to an end of the first connection structure 31 away from the second connection structure 32. That is, the connection structure 30 is formed by connecting the first connection structure 31, the second connection structure 32, and the third connection structure 33, and the first connection structure 31 is located between the second connection structure 32 and the third connection structure 33.
[0109] In some of these embodiments, the third connection structure 33 includes a fifth end face close to the first connection structure 31 and a sixth end face away from the first connection structure 31, and the size of the fifth end face is smaller than the size of the sixth end face.
[0110] Specifically, along the direction away from the first connection structure 31 (from the fifth end face to the sixth end face), the cross-sectional area of the first connection structure 31 gradually increases; along the direction away from the first connection structure 31 (from the sixth end face to the fifth end face), the cross-sectional area of the second connection structure 32 gradually increases. Among them, the "cross-sectional area" refers to the area of the cross-section in the plane (YZ) direction perpendicular to the first direction (X).
[0111] It can be understood that due to the influence of the etching process, the size of the fifth end face is smaller than the size of the sixth end face, which means that the third connection structure 33 can be formed by performing an etching process from the sixth end face to the fifth end face direction.
[0112] The semiconductor device 100 may further include an external lead contact 60, which is connected to the side of the memory array 20 away from the transistor array 10 and is used to lead out the memory array 20. Wherein, one end of the third connection structure 33 away from the first connection structure 31 is flush with one end of the external lead contact 60 away from the memory array 20.
[0113] It should be noted that when the external lead contact 60 and the first connection structure 31 are formed together and planarized, one end of the first connection structure 31 away from the second connection structure 32 may be flush with one end of the external lead contact 60 away from the memory array 20. Due to process influence, the above two ends in the semiconductor device 100 may not be flush, and the present application does not limit this.
[0114] In some embodiments, the dimension of the external lead contact 60 along the first direction (X) is greater than the dimension of the third connection structure 33 along the first direction (X).
[0115] In some embodiments, in the connection structure 30, the dimension of the first connection structure 31 along the first direction (X) is greater than the dimension of the second connection structure 32 along the first direction (X); the dimension of the second connection structure 32 along the first direction (X) is greater than the dimension of the third connection structure 33 along the first direction (X).
[0116] The semiconductor device 100 may further include a first pad 91 and a second pad 92. The first pad 91 is connected to one end of the external lead contact 60 away from the memory array 20, and the second pad 92 is connected to one end of the third connection structure 33 away from the first connection structure 31. The first pad 91 can connect the external lead contact 60 to an external circuit, and the second pad 92 can connect the third connection structure 33 to an external circuit, that is, connect the control circuit 70 to the external circuit.
[0117] The semiconductor device 100 may further include a control circuit 70, which is bonded to the side of the transistor array 10 away from the memory array 20 and is connected to the connection structure 30.
[0118] Specifically, the semiconductor device 100 further includes a first bonding metal layer 81 and a second bonding metal layer 82. The first bonding metal layer 81 is connected to the side of the second connection structure 32 away from the transistor array 10, and the second bonding metal layer 82 is bonded to the side of the first bonding metal layer 81 away from the second connection structure 32. Therefore, the second connection structure 32 is connected to the control circuit 70 through the first bonding metal layer 81 and the second bonding metal layer 82.
[0119] The transistor array 10 may include semiconductor pillars 11 and a gate line structure 12. The array of semiconductor pillars 11 is disposed between the internal lead contact 40 and the memory array 20. The semiconductor pillars 11 extend along a first direction (X) and are arranged in multiple rows along a second direction (Y), where the second direction (Y) is perpendicular to the first direction (X). Specifically, the semiconductor pillars 11 are arranged in an array along the second direction (Y) and a third direction (Z), and the third direction (Z) is perpendicular to the first direction (X) and the second direction (Y). Among them, multiple semiconductor pillars 11 are arranged in rows along the second direction (Y), and multiple semiconductor pillars 11 are arranged in columns along the third direction (Z).
[0120] The gate line structure 12 is located between two adjacent rows of the semiconductor pillars 11 in the third direction (Z) and extends along the second direction (Y). Since Figure 1 it is a cross-sectional view, the position of the gate line structure 12 is represented by a dashed line.
[0121] Among them, the material of the semiconductor pillars 11 may include silicon or polysilicon. The gate line structure 12 may include a gate and a gate insulating layer, and the gate insulating layer is located between the semiconductor pillar 11 and the gate.
[0122] In some embodiments, the internal lead contact 40 may include a gate line lead contact 41 and a bit line lead contact 42. The gate line lead contact 41 is connected to an end of the gate line structure 12 along the second direction (Y), and the bit line lead contact 42 is connected to an end of the semiconductor pillar 11 away from the memory array 20.
[0123] In some embodiments, an end of the gate line lead contact 41 away from the transistor array 10 may be flush with an end of the bit line lead contact 42 away from the transistor array 10. Similarly, the present application does not limit this.
[0124] In some embodiments, the dimension of the gate line structure 12 along the first direction (X) is smaller than the dimension of the semiconductor pillar 11 along the first direction (X), and the dimension of the gate line lead contact 41 along the first direction (X) is larger than the dimension of the bit line lead contact 42 along the first direction (X).
[0125] In some embodiments, the size of the second connection structure 32 in the first direction (X) is greater than or equal to the size of the bit line lead-out contact in the first direction (X). In some of these embodiments, the size of the second connection structure 32 in the first direction (X) is equal to the size of the gate line lead-out contact in the first direction (X). Since the second connection structure 32 and the gate line lead-out contact 41 and the bit line lead-out contact 42 can be formed in the same etching process, the bit line lead-out contact 42 can stop on the semiconductor pillar 11, and the gate line lead-out contact 41 can stop on the gate line structure 12. By designing the sizes of the second connection structure 32 and the gate line lead-out contact 41 to be equal, the etching times of the second connection structure 32 and the gate line lead-out contact 41 can be made equal, so that the etching process of the second connection structure 32 stops, and the size of the second connection structure 32 is increased as much as possible to reduce the etching depth required for the subsequent first connection structure 31.
[0126] The semiconductor device 100 may further include a virtual semiconductor pillar 13, which is disposed at intervals around the transistor array 10 or the semiconductor pillar 11 and has the same material as the semiconductor pillar 11. The difference between the semiconductor pillar 11 and the virtual semiconductor pillar 13 is that the semiconductor pillar 11 has electrical connections, while the virtual semiconductor pillar 13 has no electrical connections.
[0127] Among them, the second connection structure 32 may be located in the interval between the virtual semiconductor pillars 13. Specifically, the third end face 321 of the second connection structure 32 close to the first connection structure 31 (that is, the junction of the second connection structure 32 and the first connection structure 31) is located between adjacent virtual semiconductor pillars 13.
[0128] The storage array 20 may include a capacitor structure 21 and a conductive layer 22 arranged in an array. The conductive layer 22 covers the surface of the capacitor structure 21 and is connected to the external lead-out contact 60. Among them, the material of the conductive layer 22 may include tungsten.
[0129] Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of a storage array provided by some embodiments of the present application.
[0130] The capacitor structure 21 may include a stacked layer 211, a first electrode structure 212, a second electrode structure 213, and a dielectric layer 214. In some embodiments, the stacked layer 211 includes a first dielectric layer 2111 and a second dielectric layer 2112 alternately stacked in the first direction (X), and the thickness of the first dielectric layer 2111 in the first direction (X) is greater than the thickness of the second dielectric layer 2112 in the first direction (X). Among them, the first dielectric layer 2111 may be silicon oxide, and the second dielectric layer 2112 may be silicon nitride.
[0131] In some embodiments, in some regions, the stacked layer 211 may include only the first dielectric layer 2111. In other regions, the stacked layer 211 is formed by alternating the first dielectric layer 2111 and the second dielectric layer 2112. The second dielectric layer 2112 may act as a framework to provide support during the manufacturing process in the stacked layer 211.
[0132] The first electrode structure 212 penetrates through the stacked layer 211 along the first direction (X). One end (the lower end) of the first electrode structure 212 close to the transistor array 10 is connected to the semiconductor pillar 11. The second electrode structure 213 is located between the first electrode structure 212 and the stacked layer 211. One end (the upper end) of the second electrode structure 213 away from the transistor array 10 is connected to the conductive layer. The dielectric layer 214 is located between the first electrode structure 212 and the second electrode structure 213 to provide insulation. Therefore, the first electrode structure 212 and the second electrode structure 213 form two plates of a capacitor.
[0133] In some embodiments, the first electrode structure 212 may include a first filling layer 2121 and a first electrode 2122 surrounding the first filling layer 2121. The first filling layer 2121 may include polysilicon, and the first electrode 2122 may include tantalum carbide. The second electrode structure 213 may include a second electrode 2131. The second electrode 2131 may include tantalum carbide, and the dielectric layer 214 surrounds the second electrode 2131. The dielectric layer 214 may include a high-K dielectric layer (such as aluminum oxide). Among them, the first electrode 2122 is connected to the semiconductor pillar 11, and the second electrode 2131 is connected to the conductive layer 22.
[0134] In the embodiment of the present application, the connection structure 30 in the semiconductor device 100 can be divided into at least two segments. Among them, the first connection structure 31 can be formed separately, the second connection structure 32 can be formed together with the internal lead contact 40, and the third connection structure 33 can be formed together with the external lead contact 60. Therefore, the depth of a single etching can be reduced, the difficulty of the etching process can be decreased, and no new manufacturing process needs to be added. Since the thickness of the etched film layer is reduced during a single etching, the recognition degree of the etching mark increases, which is beneficial to increasing the etching process window. In addition, since the first connection structure 31 is formed between the virtual semiconductor pillars 13, in order to prevent the first connection structure 31 from contacting the virtual semiconductor pillars 13, a certain space needs to be reserved between the virtual semiconductor pillars 13. If the depth of a single etching is greater and the offset is larger, then a larger space needs to be reserved. By segmenting the connection structure 30 in the present application, the etching depth of the first connection structure 31 can be reduced, the offset can be decreased, so that the space that needs to be reserved between the virtual semiconductor pillars 13 can be reduced, thereby reducing the area of the structural design.
[0135] Please refer toFigure 3 , Figure 3 is a schematic flow chart of a method for manufacturing a semiconductor device provided by some embodiments of the present application. Please refer to Figures 4a - 4h , Figures 4a - 4h which is a schematic structural diagram of a semiconductor device during manufacturing provided by some embodiments of the present application. In this embodiment, taking the manufacturing of the above-mentioned semiconductor device 100 as an example, the method for manufacturing the semiconductor device will be described. Therefore, please refer to Figure 1 and Figure 2 , and the method for manufacturing the semiconductor device includes the following steps S1 - S7.
[0136] Step S1: Provide a first substrate 101.
[0137] As Figure 4a shown, the first substrate 101 can be silicon or polysilicon, and the first substrate 101 has the same material as the subsequent formed semiconductor column 11.
[0138] Step S2: Form a transistor array 10 in the first substrate 101.
[0139] Specifically, step S2 may include the following steps.
[0140] 1) As Figure 4a shown, etch the first substrate 101 to form an array of semiconductor columns 11 and dummy semiconductor columns 13 arranged in an array. The dummy semiconductor columns 13 are located on the periphery of the semiconductor columns 11. The semiconductor columns 11 are arranged in multiple rows along a second direction (Y), and the second direction (Y) is perpendicular to the first direction (X). Among them, the second direction (Y) is the row direction.
[0141] 2) As Figure 4b shown, form a gate line structure 12 between two adjacent rows of the semiconductor columns 11. The gate line structure 12 extends along the second direction (Y), and the dimension of the gate line structure 12 along the first direction (X) is smaller than the dimension of the semiconductor column 11 along the first direction (X).
[0142] Among them, an insulating layer is filled between the semiconductor columns 11, between the dummy semiconductor columns 13, and between the semiconductor columns 11 and the dummy semiconductor columns 13.
[0143] Step S3: Form a memory array 20 on one side of the transistor array 10 along the first direction (X).
[0144] Specifically, step S3 may include the following steps.
[0145] 1) As Figure 4c shown, form an array of capacitor structures 21 on one side of the transistor array 10 along the first direction (X).
[0146] In some embodiments, it may be combined with Figure 2 , first, a stacked layer 211 is formed on one side of the transistor array 10 along the first direction (X). The stacked layer 211 includes a first dielectric layer 2111 and a second dielectric layer 2112 that are alternately stacked along the first direction (X). The thickness of the first dielectric layer 2111 along the first direction (X) is greater than the thickness of the second dielectric layer 2112 along the first direction (X). Then, a first electrode structure 212 is formed that penetrates the stacked layer 211 along the first direction (X). One end of the first electrode structure 212 close to the transistor array 10 is connected to the semiconductor pillar 11. Next, a second electrode structure 213 is formed between the first electrode structure 212 and the stacked layer 211. Finally, a dielectric layer 214 is formed between the first electrode structure 212 and the second electrode structure 213.
[0147] Specifically, after the stacked layer 211 is formed, a first electrode hole 2122T can be formed first by an etching process, and a first electrode structure 212 (such as tantalum carbide and polysilicon are deposited in sequence) is formed in the first electrode hole 2122T, and the bottom of the first electrode structure 212 is exposed for connection to the semiconductor pillar 11. Then, the part of the stacked layer 211 other than the first electrode structure 212 is removed to form a cavity around the first electrode structure 212, and a dielectric layer 214 and a second electrode structure 213 (such as a high-K dielectric layer and tantalum carbide are deposited in sequence) are formed in the cavity.
[0148] In some embodiments, in the process of removing the part of the stacked layer 211 other than the first electrode structure 212, the second dielectric layer 2112 can be spaced and punched so that the etching solution can contact the first dielectric layer 2111 to remove the first dielectric layer 2111, and the second dielectric layer 2112 is retained at the unpunched positions, so as to play a role in supporting the overall structure when the first dielectric layer 2111 is removed. After the second electrode structure 213 is formed, the first dielectric layer 2111 (such as silicon oxide) can be filled again, so in Figure 2 the displayed capacitance structure 21, the second electrode structure 213 can also be completely filled with the first dielectric layer 2111. That is to say, in the finally formed capacitance structure 21, there is no second dielectric layer 2112 in the area of the stacked layer 211 corresponding to the punched holes, only the first dielectric layer 2111 is included, and the area of the stacked layer 211 corresponding to the unpunched holes has the first dielectric layer 2111 and the second dielectric layer 2112.
[0149] In some embodiments, in the process of forming the first electrode structure 212, an insulating layer can be formed on the top of the first electrode structure 212 so that the subsequent formed conductive layer 22 will not be connected to the first electrode structure 212.
[0150] 2) Cover a conductive layer 22 on the surface of the capacitor structure 21.
[0151] Specifically, as Figure 4c shown, an initial conductive layer (such as tungsten) can be deposited on the surface of the capacitor structure 21 and on the side of the virtual semiconductor pillar 13 close to the capacitor structure 21 first, and then the initial conductive layer is patterned to form the conductive layer 22. Wherein, one end of the second electrode structure 213 away from the transistor array 10 is connected to the conductive layer 22.
[0152] In some embodiments, the manufacturing method of the semiconductor device 100 may include: forming a dielectric layer 50 between the transistor array 10 and the memory array 20.
[0153] Specifically, as Figure 4c shown, an initial dielectric layer is formed on one side of the transistor array 10 first, and then the capacitor structure 21 is formed on the initial dielectric layer. During the patterning of the initial conductive layer, the initial dielectric layer can be patterned to form the dielectric layer 50 between the memory array 20 and the transistor array 10.
[0154] Step S4: Form a first connection structure 31 around the memory array 20 and the transistor array 10, and the first connection structure 31 extends along the first direction (X).
[0155] Specifically, as Figure 4d shown, step S4 includes: 1) After forming the dielectric layer 50 and the memory array 20, cover an insulating layer on the memory array 20; 2) Etch the insulating layer around the memory array 20 to form a through hole extending along the first direction (X), and the bottom of the through hole is located in the gap between the virtual semiconductor pillars 13; 3) Fill the through hole with a conductive material to form the first connection structure 31.
[0156] Step S5: Thin the first substrate 101 to expose the transistor array 10.
[0157] Specifically, as Figure 4e shown, a second substrate 102 can be formed on the side of the memory array 20 away from the transistor array 10 first, and then the second substrate 102 is placed below and the first substrate 101 is placed above, and then the first substrate 101 is thinned to expose the transistor array 10.
[0158] In some embodiments, as Figure 4f shown, after exposing the semiconductor pillar 11, a bit line BL is formed at one end of the semiconductor pillar 11 away from the memory array 20, and the bit line BL extends along the third direction (Z), and the third direction (Z) is perpendicular to the first direction (X) and the second direction (Y).
[0159] Step S6: Form a second connection structure 32 on a side of the transistor array 10 and the first connection structure 31 away from the storage array 20, and the second connection structure 32 connects the first connection structure 31.
[0160] In some embodiments, as Figure 4g shown, form an internal lead contact 40 and a second connection structure 32 on a side of the transistor array 10 and the first connection structure 31 away from the storage array 20, the internal lead contact 40 connects the transistor array 10, and the second connection structure 32 connects the first connection structure 31.
[0161] Specifically, first form an insulating layer on the bit line BL and the virtual semiconductor column 13, and then perform an etching process and a filling process on the insulating layer to form the internal lead contact 40 and the second connection structure 32. The etching depth of the second connection structure 32 is greater than the etching depth of the internal lead contact 40, and the second connection structure 32 lands on the first connection structure 31, and the internal lead contact 40 lands on the bit line BL and the gate line structure 12.
[0162] Wherein, the internal lead contact 40 includes a gate line lead contact 41 and a bit line lead contact 42, the gate line lead contact 41 connects an end of the gate line structure 12 along the second direction (Y), and the bit line lead contact 42 connects an end of the semiconductor column 11 away from the storage array 20.
[0163] Wherein, the first connection structure 31 includes a first end face 311 close to the second connection structure 32 and a second end face 312 away from the second connection structure 32, and the second connection structure 32 includes a third end face 321 close to the first connection structure 31 and a fourth end face 322 away from the first connection structure 31. Since the first connection structure 31 is etched and formed on the front side (the side close to the storage array 20) first, and then the second connection structure 32 is etched and formed on the back side (the side close to the transistor array 10), due to the influence of the etching process, the size of the first end face 311 is smaller than the size of the second end face 312, and the size of the third end face 321 is smaller than the size of the fourth end face 322.
[0164] In some embodiments, the etching depth of the first connection structure 31 is greater than the etching depth of the second connection structure 32, and the size of the first end face 311 of the first connection structure 31 is smaller than the size of the third end face 321 of the second connection structure 32.
[0165] Step S7: Form an external lead contact 60 and a third connection structure 33 on a side of the storage array 20 and the first connection structure 31 away from the transistor array 10. The external lead contact 60 is connected to the storage array 20, and the third connection structure 33 is connected to the first connection structure 31.
[0166] Before step S7, as Figure 4h shown, the method for manufacturing the semiconductor device 100 may further include: connecting the control circuit 70 to the internal lead contact 40 and the second connection structure 32 through a bonding metal layer.
[0167] Specifically, after bonding the control circuit 70, place the control circuit 70 below and the storage array 20 above. Then, etch the insulating layer covering the storage array 20 and the first connection structure 31 to form the external lead contact 60 and the third connection structure 33. Among them, the etching depth of the third connection structure 33 is less than that of the external lead contact 60, and the third connection structure 33 lands on the first connection structure 31, and the external lead contact 60 lands on the conductive layer 22.
[0168] The method for manufacturing the semiconductor device 100 further includes: as Figure 1 shown, form a first pad 91 at an end of the external lead contact 60 away from the storage array 20; form a second pad 92 at an end of the third connection structure 33 away from the first connection structure 31. Among them, the first pad 91 and the second pad 92 are respectively connected to different external circuits.
[0169] In the method for manufacturing the semiconductor device 100 provided by the embodiments of the present application, the connection structure 30 is formed by at least two etching processes, which can reduce the depth of one etching, thereby reducing the process difficulty and increasing the process window. Moreover, the thickness of the film layer etched at one time is reduced, which can increase the recognizability of the etching mark. In addition, the etching depth of the first connection structure 31 is reduced, the offset is reduced, and the distance between the first connection structure 31 and the virtual semiconductor pillar 13 that needs to be reserved is reduced, so that the area of the structure can be reduced and the integration degree can be improved.
[0170] Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of a storage system provided by some embodiments of the present application. The storage system 200 includes a semiconductor device 201 and a controller 202. The semiconductor device 201 may be the semiconductor device in any of the above embodiments, and the semiconductor device 201 may be manufactured by the method for manufacturing the semiconductor device in the above embodiments. The controller 202 is connected to the semiconductor device 201 and is used to control the semiconductor device 201 to store data, and the semiconductor device 201 can perform the operation of storing data based on the control of the controller 202.
[0171] In some embodiments, the storage system may be implemented as, for example, a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of an MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of an SD, mini SD, and micro SD, a storage device of a personal computer memory card international association (PCMCIA) card type, a storage device of a peripheral component interconnect (PCI) type, a storage device of a high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card, or a memory stick, etc.
[0172] The semiconductor device 201 includes: a transistor array; a storage array located on one side of the transistor array along a first direction; a connection structure located at the periphery of the storage array and the transistor array and extending along the first direction; wherein the connection structure includes a first connection structure and a second connection structure connected to each other along the first direction; the first connection structure includes a first end face close to the second connection structure and a second end face far from the second connection structure, and the size of the first end face is smaller than the size of the second end face; the second connection structure includes a third end face close to the first connection structure and a fourth end face far from the first connection structure, and the size of the third end face is smaller than the size of the fourth end face.
[0173] The description of the above embodiments is only used to help understand the technical solutions and their core ideas of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A semiconductor device, characterized in that, The semiconductor device includes: A transistor array; A memory array located on one side of the transistor array along a first direction; A connection structure located at the periphery of the memory array and the transistor array and extending along the first direction; Wherein, the connection structure includes a first connection structure and a second connection structure connected along the first direction; the first connection structure includes a first end face close to the second connection structure and a second end face far from the second connection structure, and the size of the first end face is smaller than that of the second end face; the second connection structure includes a third end face close to the first connection structure and a fourth end face far from the first connection structure, and the size of the third end face is smaller than that of the fourth end face.
2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: Internal lead contacts connected to the side of the transistor array far from the memory array; Wherein, the second connection structure is located at one end of the first connection structure close to the internal lead contacts; and one end of the second connection structure far from the first connection structure is flush with one end of the internal lead contacts far from the transistor array.
3. The semiconductor device according to claim 2, wherein, The connection structure further includes along the first direction: A third connection structure connected to one end of the first connection structure far from the second connection structure.
4. The semiconductor device according to claim 3, wherein, The semiconductor device further includes: External lead contacts connected to the side of the memory array far from the transistor array; Wherein, one end of the third connection structure far from the first connection structure is flush with one end of the external lead contacts far from the memory array.
5. The semiconductor device according to claim 4, characterized in that, The transistor array includes: Semiconductor columns arranged in an array between the internal lead contacts and the memory array, and the semiconductor columns are arranged in multiple rows along a second direction perpendicular to the first direction; A gate line structure located between adjacent rows of the semiconductor columns and extending along the second direction; Wherein, the internal lead contacts include gate line lead contacts and bit line lead contacts, the gate line lead contacts are connected to the ends of the gate line structure along the second direction, and the bit line lead contacts are connected to one end of the semiconductor columns far from the memory array.
6. The semiconductor device according to claim 5, characterized in that, The size of the second connection structure along the first direction is greater than or equal to the size of the bit line lead contacts along the first direction.
7. The semiconductor device according to claim 6, characterized in that, The size of the gate line lead contacts along the first direction is greater than the size of the bit line lead contacts along the first direction.
8. The semiconductor device according to claim 7, wherein, The size of the second connection structure along the first direction is equal to the size of the gate line lead contacts along the first direction.
9. The semiconductor device according to claim 1, wherein The size of the first end face is smaller than the size of the third end face.
10. The semiconductor device according to claim 3, wherein The third connection structure includes a fifth end face close to the first connection structure and a sixth end face far from the first connection structure, and the size of the fifth end face is smaller than that of the sixth end face.
11. The semiconductor device according to claim 5, characterized in that, The semiconductor device further includes: Virtual semiconductor columns arranged at intervals around the semiconductor columns; Wherein, one end of the first connection structure close to the second connection structure is located in the interval between the virtual semiconductor columns.
12. The semiconductor device according to claim 4, wherein, The dimension of the external lead contact along the first direction is greater than the dimension of the third connection structure along the first direction.
13. The semiconductor device according to claim 3, wherein The dimension of the first connection structure along the first direction is greater than the dimension of the second connection structure along the first direction; the dimension of the second connection structure along the first direction is greater than the dimension of the third connection structure along the first direction.
14. The semiconductor device according to claim 1, wherein Along the direction away from the second connection structure, the cross-sectional area of the first connection structure in the plane direction perpendicular to the first direction gradually increases; along the direction away from the first connection structure, the cross-sectional area of the second connection structure in the plane direction gradually increases.
15. The semiconductor device according to claim 4, wherein, The semiconductor device further includes: A first pad connected to one end of the external lead contact away from the memory array. A second pad connected to one end of the third connection structure away from the first connection structure.
16. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: A control circuit bonded to the side of the transistor array away from the memory array and connected to the connection structure.
17. The semiconductor device according to claim 16, wherein, The semiconductor device further includes: A first bonding metal layer connected to the side of the second connection structure away from the transistor array. A second bonding metal layer bonded to the side of the first bonding metal layer away from the second connection structure.
18. The semiconductor device according to claim 5, wherein, The memory array includes: Capacitor structures arranged in an array. A conductive layer covering the surface of the capacitor structure, and the conductive layer is connected to the external lead contact.
19. The semiconductor device according to claim 18, wherein, The capacitor structure includes: A stacked layer including a first dielectric layer and a second dielectric layer alternately stacked along the first direction, and the thickness of the first dielectric layer along the first direction is greater than the thickness of the second dielectric layer along the first direction. A first electrode structure penetrating the stacked layer along the first direction, and one end of the first electrode structure close to the transistor array is connected to the semiconductor column. A second electrode structure located between the first electrode structure and the stacked layer, and one end of the second electrode structure away from the transistor array is connected to the conductive layer. A dielectric layer located between the first electrode structure and the second electrode structure.
20. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method of the semiconductor device includes: Forming a first substrate. Forming a transistor array in the first substrate. Forming a memory array on one side of the transistor array along the first direction. Forming a first connection structure around the memory array and the transistor array, and the first connection structure extends along the first direction. Thinning the first substrate to expose the transistor array. Forming a second connection structure on the side of the transistor array and the first connection structure away from the memory array, and the second connection structure connects the first connection structure. Wherein, the first connection structure includes a first end face close to the second connection structure and a second end face away from the second connection structure, and the size of the first end face is smaller than the size of the second end face; the second connection structure includes a third end face close to the first connection structure and a fourth end face away from the first connection structure, and the size of the third end face is smaller than the size of the fourth end face.
21. The method for manufacturing a semiconductor device according to claim 20, characterized in that, The step of forming a second connection structure on a side of the transistor array and the first connection structure away from the memory array includes: Forming an internal lead contact and a second connection structure on a side of the transistor array and the first connection structure away from the memory array, where the internal lead contact is connected to the transistor array and the second connection structure is connected to the first connection structure.
22. The method for manufacturing a semiconductor device according to claim 21, wherein, The method for manufacturing the semiconductor device further includes: Connecting a control circuit to the internal lead contact and the second connection structure through a bonding metal layer; Forming an external lead contact and a third connection structure on a side of the memory array and the first connection structure away from the transistor array, where the external lead contact is connected to the memory array and the third connection structure is connected to the first connection structure.
23. The method for manufacturing a semiconductor device according to claim 22, characterized in that, The step of forming a transistor array in the first substrate includes: Etching the first substrate to form array - arranged semiconductor pillars and dummy semiconductor pillars, where the dummy semiconductor pillars are located on the periphery of the semiconductor pillars, the semiconductor pillars are arranged in multiple rows along a second direction, and the second direction is perpendicular to the first direction; Forming a gate line structure between adjacent two rows of the semiconductor pillars, where the gate line structure extends along the second direction, and a dimension of the gate line structure along the first direction is smaller than a dimension of the semiconductor pillar along the first direction; Wherein, the internal lead contact includes a gate line lead contact and a bit line lead contact, the gate line lead contact is connected to an end of the gate line structure along the second direction, and the bit line lead contact is connected to an end of the semiconductor pillar away from the memory array.
24. The method for manufacturing a semiconductor device according to claim 23, wherein, The step of forming a first connection structure on the peripheries of the memory array and the transistor array includes: Forming an insulating layer covering the surface of the memory array; Etching the insulating layer on the periphery of the memory array to form a through - hole extending along the first direction, and a bottom of the through - hole is located in a gap between the dummy semiconductor pillars; Filling a conductive material in the through - hole to form a first connection structure.
25. The method for manufacturing a semiconductor device according to claim 22, wherein, The method for manufacturing the semiconductor device further includes: Forming a first pad at an end of the external lead contact away from the memory array; Forming a second pad at an end of the third connection structure away from the first connection structure.
26. The method for manufacturing a semiconductor device according to claim 23, wherein, The step of forming a memory array on a side of the transistor array along a first direction includes: Forming array - arranged capacitor structures on a side of the transistor array along the first direction; Covering a conductive layer on the surface of the capacitor structures, and the conductive layer is connected to the external lead contact.
27. The method for manufacturing a semiconductor device according to claim 26, wherein, The step of forming array - arranged capacitor structures on a side of the transistor array along the first direction includes: Forming a stacked layer on a side of the transistor array along the first direction, where the stacked layer includes a first dielectric layer and a second dielectric layer alternately stacked along the first direction, and a thickness of the first dielectric layer along the first direction is greater than a thickness of the second dielectric layer along the first direction; Forming a first electrode structure penetrating the stacked layer along the first direction, and an end of the first electrode structure close to the transistor array is connected to the semiconductor pillar; A second electrode structure is formed between the first electrode structure and the stacked layer, and one end of the second electrode structure away from the transistor array is connected to the conductive layer; A dielectric layer is formed between the first electrode structure and the second electrode structure.
28. The manufacturing method of the semiconductor device according to claim 23, wherein, Before the step of forming the internal lead contact and the second connection structure on a side of the transistor array and the first connection structure away from the storage array, the method for manufacturing the semiconductor device further includes: A bit line is formed at one end of the semiconductor column away from the storage array, and the bit line extends in a third direction perpendicular to the first direction and the second direction; Wherein, the bit line lead contact is connected to the bit line.
29. A storage system, characterized in that, Comprising: The semiconductor device according to any one of claims 1-19; A controller connected to the semiconductor device for controlling the semiconductor device to store data.